Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11239

1

T1

5

T2

6

T4

7

auto[Attestation]

7910

1

T1

3

T2

7

T4

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2835	1			T1	2		T2	1		T5	2
auto[Aes]	3485	1			T1	2		T5	1		T15	6
auto[Kmac]	3378	1			T2	3		T5	4		T15	1
auto[Otbn]	3364	1			T2	3		T4	12		T5	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7776	1			T1	8		T2	8		T3	1
auto[OpGenId]	6087	1			T1	4		T2	6		T5	9
auto[OpGenSwOut]	6031	1			T1	4		T2	4		T5	3
auto[OpGenHwOut]	7031	1			T2	3		T4	12		T5	9
auto[OpDisable]	143	1			T49	1		T50	1		T51	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10749

1

T1

8

T2

10

T3

1

auto[OpDoneFail]

16319

1

T1

8

T2

11

T4

12

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6491	1			T1	1		T2	1		T3	1
auto[StInit]	3839	1			T1	2		T2	2		T4	2
auto[StCreatorRootKey]	3196	1			T1	2		T2	3		T4	2
auto[StOwnerIntKey]	2854	1			T1	2		T2	4		T4	2
auto[StOwnerKey]	2482	1			T1	2		T2	1		T4	2
auto[StDisabled]	8206	1			T1	7		T2	10		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	340	1			T16	1		T17	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T1	1		T26	2		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	86	1			T51	1		T42	1		T57	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T2	1		T124	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T87	1		T109	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	233	1			T1	1		T50	2		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	339	1			T36	1		T30	3		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	117	1			T38	1		T109	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	81	1			T15	1		T56	2		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	75	1			T36	1		T50	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T1	1		T50	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	208	1			T15	1		T36	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	327	1			T16	6		T17	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	93	1			T22	1		T56	2		T23	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T38	1		T26	2		T56	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	76	1			T15	1		T36	1		T56	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	48	1			T50	1		T26	1		T123	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	216	1			T5	1		T124	1		T56	6
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	299	1			T16	2		T30	2		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	112	1			T49	1		T50	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T50	1		T26	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	68	1			T17	1		T50	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	60	1			T187	1		T47	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	225	1			T2	1		T5	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	75	1			T50	1		T26	4		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	134	1			T17	1		T34	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T38	1		T188	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	83	1			T26	4		T82	1		T56	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T26	1		T56	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	238	1			T15	1		T49	1		T26	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	83	1			T26	2		T56	10		T57	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	109	1			T26	1		T22	1		T56	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	94	1			T15	1		T17	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T26	1		T100	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	64	1			T56	2		T190	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	224	1			T1	1		T15	1		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	88	1			T26	2		T56	4		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	105	1			T2	1		T36	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	86	1			T26	1		T191	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	65	1			T2	1		T26	1		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	65	1			T123	1		T56	2		T191	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	228	1			T5	1		T109	1		T26	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	79	1			T50	1		T26	3		T56	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	108	1			T15	1		T50	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T56	1		T57	1		T191	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T17	1		T26	2		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	61	1			T56	2		T187	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	207	1			T15	2		T50	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	291	1			T16	1		T17	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	85	1			T26	1		T124	1		T22	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	63	1			T50	2		T42	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	71	1			T15	1		T189	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	47	1			T50	2		T123	1		T56	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	170	1			T36	1		T50	1		T109	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	480	1			T16	1		T35	8		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	130	1			T15	1		T26	1		T122	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	96	1			T50	1		T124	1		T56	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	91	1			T193	1		T194	1		T62	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	90	1			T35	1		T36	1		T109	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	300	1			T35	2		T50	1		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	420	1			T16	2		T17	2		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	114	1			T36	1		T26	2		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T123	1		T195	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T81	1		T82	2		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	80	1			T123	1		T81	1		T56	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	294	1			T5	1		T50	3		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	458	1			T4	4		T16	2		T36	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	128	1			T4	1		T36	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	119	1			T5	1		T50	1		T123	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	98	1			T4	1		T86	1		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	78	1			T5	1		T17	2		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	318	1			T4	1		T15	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T50	2		T26	1		T56	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	95	1			T50	1		T22	2		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	71	1			T5	1		T26	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	68	1			T15	1		T50	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	40	1			T5	1		T50	1		T109	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	219	1			T15	2		T50	1		T109	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	55	1			T26	2		T56	3		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	130	1			T35	1		T26	1		T22	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	114	1			T35	1		T26	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	95	1			T5	1		T35	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	90	1			T17	3		T36	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	287	1			T15	1		T35	2		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T26	4		T56	3		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	123	1			T50	1		T37	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T5	1		T17	1		T123	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	103	1			T195	1		T57	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	87	1			T17	1		T26	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	310	1			T2	1		T50	1		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	51	1			T50	3		T26	1		T56	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	104	1			T50	2		T109	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T2	1		T4	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T26	1		T82	1		T56	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	92	1			T4	1		T26	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	253	1			T2	1		T4	3		T5	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	196	1			T2	1		T87	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	700	1			T1	2		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	203	1			T1	1		T15	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	679	1			T15	1		T36	2		T30	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	197	1			T15	1		T36	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	647	1			T5	1		T16	6		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	198	1			T17	1		T50	2		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	654	1			T2	1		T5	1		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	203	1			T38	1		T26	3		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	457	1			T15	1		T17	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	213	1			T17	1		T50	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	432	1			T1	1		T15	2		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	196	1			T2	1		T26	2		T123	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	441	1			T2	1		T5	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	198	1			T17	1		T26	2		T56	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	417	1			T15	3		T50	4		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	169	1			T15	1		T50	4		T123	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	558	1			T16	1		T17	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	254	1			T35	1		T36	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	933	1			T15	1		T16	1		T35	10
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	266	1			T123	2		T81	2		T82	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	840	1			T5	1		T16	2		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	279	1			T4	1		T5	2		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	920	1			T4	6		T15	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	169	1			T5	2		T15	1		T50	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	383	1			T15	2		T50	4		T109	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	279	1			T5	1		T17	3		T35	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	492	1			T15	1		T35	3		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	278	1			T17	2		T26	1		T123	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	513	1			T2	1		T5	1		T50	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T2	1		T4	2		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	425	1			T2	1		T4	3		T5	2