Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33262

1

T1

23

T2

27

T3

29

auto[1]

283

1

T36

1

T109

4

T140

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33278	1			T1	23		T2	27		T3	29
auto[134217728:268435455]	9	1			T109	1		T335	1		T329	1
auto[268435456:402653183]	8	1			T359	1		T274	1		T332	2
auto[402653184:536870911]	5	1			T359	1		T274	1		T337	1
auto[536870912:671088639]	6	1			T332	1		T254	1		T260	1
auto[671088640:805306367]	9	1			T140	1		T359	1		T281	1
auto[805306368:939524095]	9	1			T109	1		T314	1		T274	1
auto[939524096:1073741823]	15	1			T131	1		T359	1		T388	1
auto[1073741824:1207959551]	10	1			T388	1		T335	1		T330	1
auto[1207959552:1342177279]	6	1			T274	1		T389	1		T238	1
auto[1342177280:1476395007]	9	1			T36	1		T240	1		T354	1
auto[1476395008:1610612735]	8	1			T240	1		T389	1		T282	1
auto[1610612736:1744830463]	5	1			T140	1		T281	1		T314	1
auto[1744830464:1879048191]	17	1			T109	1		T130	1		T359	3
auto[1879048192:2013265919]	8	1			T373	1		T390	1		T391	1
auto[2013265920:2147483647]	9	1			T129	1		T335	1		T274	1
auto[2147483648:2281701375]	7	1			T335	2		T281	1		T354	1
auto[2281701376:2415919103]	10	1			T359	1		T330	1		T314	1
auto[2415919104:2550136831]	5	1			T314	1		T373	1		T390	1
auto[2550136832:2684354559]	10	1			T330	1		T354	1		T371	1
auto[2684354560:2818572287]	13	1			T129	1		T130	1		T354	1
auto[2818572288:2952790015]	7	1			T332	1		T373	1		T389	1
auto[2952790016:3087007743]	6	1			T359	2		T240	1		T279	1
auto[3087007744:3221225471]	5	1			T359	1		T314	1		T354	1
auto[3221225472:3355443199]	9	1			T359	1		T228	1		T240	1
auto[3355443200:3489660927]	5	1			T140	1		T131	1		T335	1
auto[3489660928:3623878655]	10	1			T335	1		T314	1		T337	1
auto[3623878656:3758096383]	10	1			T140	1		T330	1		T389	1
auto[3758096384:3892314111]	9	1			T129	1		T335	3		T330	1
auto[3892314112:4026531839]	7	1			T335	1		T254	1		T261	1
auto[4026531840:4160749567]	11	1			T109	1		T140	1		T359	1
auto[4160749568:4294967295]	10	1			T274	1		T332	1		T254	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33262	1			T1	23		T2	27		T3	29
auto[0:134217727]	auto[1]	16	1			T130	1		T131	1		T332	1
auto[134217728:268435455]	auto[1]	9	1			T109	1		T335	1		T329	1
auto[268435456:402653183]	auto[1]	8	1			T359	1		T274	1		T332	2
auto[402653184:536870911]	auto[1]	5	1			T359	1		T274	1		T337	1
auto[536870912:671088639]	auto[1]	6	1			T332	1		T254	1		T260	1
auto[671088640:805306367]	auto[1]	9	1			T140	1		T359	1		T281	1
auto[805306368:939524095]	auto[1]	9	1			T109	1		T314	1		T274	1
auto[939524096:1073741823]	auto[1]	15	1			T131	1		T359	1		T388	1
auto[1073741824:1207959551]	auto[1]	10	1			T388	1		T335	1		T330	1
auto[1207959552:1342177279]	auto[1]	6	1			T274	1		T389	1		T238	1
auto[1342177280:1476395007]	auto[1]	9	1			T36	1		T240	1		T354	1
auto[1476395008:1610612735]	auto[1]	8	1			T240	1		T389	1		T282	1
auto[1610612736:1744830463]	auto[1]	5	1			T140	1		T281	1		T314	1
auto[1744830464:1879048191]	auto[1]	17	1			T109	1		T130	1		T359	3
auto[1879048192:2013265919]	auto[1]	8	1			T373	1		T390	1		T391	1
auto[2013265920:2147483647]	auto[1]	9	1			T129	1		T335	1		T274	1
auto[2147483648:2281701375]	auto[1]	7	1			T335	2		T281	1		T354	1
auto[2281701376:2415919103]	auto[1]	10	1			T359	1		T330	1		T314	1
auto[2415919104:2550136831]	auto[1]	5	1			T314	1		T373	1		T390	1
auto[2550136832:2684354559]	auto[1]	10	1			T330	1		T354	1		T371	1
auto[2684354560:2818572287]	auto[1]	13	1			T129	1		T130	1		T354	1
auto[2818572288:2952790015]	auto[1]	7	1			T332	1		T373	1		T389	1
auto[2952790016:3087007743]	auto[1]	6	1			T359	2		T240	1		T279	1
auto[3087007744:3221225471]	auto[1]	5	1			T359	1		T314	1		T354	1
auto[3221225472:3355443199]	auto[1]	9	1			T359	1		T228	1		T240	1
auto[3355443200:3489660927]	auto[1]	5	1			T140	1		T131	1		T335	1
auto[3489660928:3623878655]	auto[1]	10	1			T335	1		T314	1		T337	1
auto[3623878656:3758096383]	auto[1]	10	1			T140	1		T330	1		T389	1
auto[3758096384:3892314111]	auto[1]	9	1			T129	1		T335	3		T330	1
auto[3892314112:4026531839]	auto[1]	7	1			T335	1		T254	1		T261	1
auto[4026531840:4160749567]	auto[1]	11	1			T109	1		T140	1		T359	1
auto[4160749568:4294967295]	auto[1]	10	1			T274	1		T332	1		T254	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1690

1

T2

4

T3

5

T6

2

auto[1]

1780

1

T2

1

T6

1

T5

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T50	1		T26	1		T56	3
auto[134217728:268435455]	118	1			T3	1		T5	1		T17	1
auto[268435456:402653183]	107	1			T50	1		T26	2		T46	1
auto[402653184:536870911]	102	1			T34	1		T36	1		T26	1
auto[536870912:671088639]	118	1			T16	1		T50	1		T26	1
auto[671088640:805306367]	124	1			T51	1		T56	1		T57	3
auto[805306368:939524095]	92	1			T3	1		T5	1		T15	1
auto[939524096:1073741823]	113	1			T2	1		T30	1		T50	1
auto[1073741824:1207959551]	114	1			T2	1		T6	1		T50	3
auto[1207959552:1342177279]	109	1			T16	1		T123	1		T56	2
auto[1342177280:1476395007]	97	1			T15	1		T30	1		T124	1
auto[1476395008:1610612735]	109	1			T5	1		T109	1		T100	1
auto[1610612736:1744830463]	114	1			T51	1		T56	4		T57	1
auto[1744830464:1879048191]	119	1			T50	1		T56	1		T196	1
auto[1879048192:2013265919]	93	1			T2	1		T3	1		T56	2
auto[2013265920:2147483647]	117	1			T3	1		T50	2		T39	1
auto[2147483648:2281701375]	121	1			T37	1		T39	1		T26	1
auto[2281701376:2415919103]	104	1			T17	1		T50	1		T26	2
auto[2415919104:2550136831]	93	1			T39	1		T46	2		T22	1
auto[2550136832:2684354559]	101	1			T36	1		T37	2		T52	1
auto[2684354560:2818572287]	109	1			T2	1		T34	1		T49	1
auto[2818572288:2952790015]	110	1			T16	2		T50	1		T26	1
auto[2952790016:3087007743]	103	1			T6	1		T50	1		T37	1
auto[3087007744:3221225471]	93	1			T26	1		T83	1		T56	2
auto[3221225472:3355443199]	121	1			T5	2		T15	1		T109	1
auto[3355443200:3489660927]	106	1			T2	1		T37	1		T26	3
auto[3489660928:3623878655]	96	1			T37	1		T52	1		T57	1
auto[3623878656:3758096383]	95	1			T56	2		T57	2		T58	1
auto[3758096384:3892314111]	108	1			T6	1		T50	1		T100	1
auto[3892314112:4026531839]	105	1			T26	3		T22	2		T51	2
auto[4026531840:4160749567]	138	1			T3	1		T15	1		T50	1
auto[4160749568:4294967295]	113	1			T50	1		T37	1		T80	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T56	1		T57	1		T58	1
auto[0:134217727]	auto[1]	49	1			T50	1		T26	1		T56	2
auto[134217728:268435455]	auto[0]	65	1			T3	1		T17	1		T123	1
auto[134217728:268435455]	auto[1]	53	1			T5	1		T26	2		T123	1
auto[268435456:402653183]	auto[0]	48	1			T46	1		T392	1		T140	1
auto[268435456:402653183]	auto[1]	59	1			T50	1		T26	2		T124	1
auto[402653184:536870911]	auto[0]	53	1			T36	1		T26	1		T56	1
auto[402653184:536870911]	auto[1]	49	1			T34	1		T22	1		T47	2
auto[536870912:671088639]	auto[0]	58	1			T16	1		T26	1		T46	2
auto[536870912:671088639]	auto[1]	60	1			T50	1		T57	1		T47	2
auto[671088640:805306367]	auto[0]	63	1			T56	1		T57	2		T58	1
auto[671088640:805306367]	auto[1]	61	1			T51	1		T57	1		T58	1
auto[805306368:939524095]	auto[0]	44	1			T3	1		T5	1		T16	1
auto[805306368:939524095]	auto[1]	48	1			T15	1		T26	1		T56	1
auto[939524096:1073741823]	auto[0]	54	1			T2	1		T50	1		T26	1
auto[939524096:1073741823]	auto[1]	59	1			T30	1		T100	1		T56	1
auto[1073741824:1207959551]	auto[0]	55	1			T2	1		T6	1		T50	1
auto[1073741824:1207959551]	auto[1]	59	1			T50	2		T124	1		T47	3
auto[1207959552:1342177279]	auto[0]	48	1			T16	1		T56	1		T74	1
auto[1207959552:1342177279]	auto[1]	61	1			T123	1		T56	1		T191	1
auto[1342177280:1476395007]	auto[0]	47	1			T22	1		T56	1		T233	1
auto[1342177280:1476395007]	auto[1]	50	1			T15	1		T30	1		T124	1
auto[1476395008:1610612735]	auto[0]	51	1			T109	1		T100	1		T56	1
auto[1476395008:1610612735]	auto[1]	58	1			T5	1		T57	1		T189	1
auto[1610612736:1744830463]	auto[0]	53	1			T56	3		T384	1		T47	1
auto[1610612736:1744830463]	auto[1]	61	1			T51	1		T56	1		T57	1
auto[1744830464:1879048191]	auto[0]	61	1			T50	1		T57	1		T384	1
auto[1744830464:1879048191]	auto[1]	58	1			T56	1		T196	1		T227	2
auto[1879048192:2013265919]	auto[0]	48	1			T2	1		T3	1		T56	2
auto[1879048192:2013265919]	auto[1]	45	1			T73	1		T59	1		T48	1
auto[2013265920:2147483647]	auto[0]	42	1			T3	1		T39	1		T124	1
auto[2013265920:2147483647]	auto[1]	75	1			T50	2		T26	1		T56	1
auto[2147483648:2281701375]	auto[0]	56	1			T37	1		T56	1		T57	2
auto[2147483648:2281701375]	auto[1]	65	1			T39	1		T26	1		T47	1
auto[2281701376:2415919103]	auto[0]	43	1			T26	1		T58	2		T47	1
auto[2281701376:2415919103]	auto[1]	61	1			T17	1		T50	1		T26	1
auto[2415919104:2550136831]	auto[0]	51	1			T39	1		T46	2		T22	1
auto[2415919104:2550136831]	auto[1]	42	1			T57	1		T198	1		T55	1
auto[2550136832:2684354559]	auto[0]	49	1			T37	2		T56	2		T57	1
auto[2550136832:2684354559]	auto[1]	52	1			T36	1		T52	1		T187	1
auto[2684354560:2818572287]	auto[0]	48	1			T49	1		T26	1		T22	1
auto[2684354560:2818572287]	auto[1]	61	1			T2	1		T34	1		T30	1
auto[2818572288:2952790015]	auto[0]	54	1			T50	1		T26	1		T56	1
auto[2818572288:2952790015]	auto[1]	56	1			T16	2		T124	1		T56	3
auto[2952790016:3087007743]	auto[0]	48	1			T39	1		T52	1		T384	1
auto[2952790016:3087007743]	auto[1]	55	1			T6	1		T50	1		T37	1
auto[3087007744:3221225471]	auto[0]	53	1			T26	1		T83	1		T56	1
auto[3087007744:3221225471]	auto[1]	40	1			T56	1		T69	1		T47	1
auto[3221225472:3355443199]	auto[0]	64	1			T39	1		T56	1		T23	1
auto[3221225472:3355443199]	auto[1]	57	1			T5	2		T15	1		T109	1
auto[3355443200:3489660927]	auto[0]	51	1			T2	1		T37	1		T124	1
auto[3355443200:3489660927]	auto[1]	55	1			T26	3		T123	1		T56	1
auto[3489660928:3623878655]	auto[0]	50	1			T37	1		T52	1		T384	1
auto[3489660928:3623878655]	auto[1]	46	1			T57	1		T47	3		T59	1
auto[3623878656:3758096383]	auto[0]	45	1			T56	2		T59	1		T140	1
auto[3623878656:3758096383]	auto[1]	50	1			T57	2		T58	1		T47	3
auto[3758096384:3892314111]	auto[0]	53	1			T6	1		T50	1		T100	1
auto[3758096384:3892314111]	auto[1]	55	1			T56	1		T57	2		T189	1
auto[3892314112:4026531839]	auto[0]	65	1			T26	2		T22	2		T51	2
auto[3892314112:4026531839]	auto[1]	40	1			T26	1		T247	1		T69	1
auto[4026531840:4160749567]	auto[0]	58	1			T3	1		T50	1		T26	1
auto[4026531840:4160749567]	auto[1]	80	1			T15	1		T80	1		T82	1
auto[4160749568:4294967295]	auto[0]	53	1			T50	1		T37	1		T80	1
auto[4160749568:4294967295]	auto[1]	60	1			T82	1		T56	1		T191	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1675

1

T2

5

T3

4

T6

2

auto[1]

1794

1

T3

1

T6

1

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T52	1		T51	1		T56	3
auto[134217728:268435455]	115	1			T16	1		T17	1		T37	1
auto[268435456:402653183]	103	1			T30	1		T50	1		T26	1
auto[402653184:536870911]	112	1			T36	1		T50	1		T37	1
auto[536870912:671088639]	129	1			T36	1		T50	1		T26	2
auto[671088640:805306367]	107	1			T5	2		T26	2		T52	1
auto[805306368:939524095]	81	1			T50	1		T26	2		T124	1
auto[939524096:1073741823]	123	1			T5	1		T123	1		T51	1
auto[1073741824:1207959551]	110	1			T3	1		T50	1		T39	1
auto[1207959552:1342177279]	104	1			T17	1		T30	1		T39	1
auto[1342177280:1476395007]	112	1			T2	1		T50	2		T26	1
auto[1476395008:1610612735]	128	1			T2	1		T50	1		T26	1
auto[1610612736:1744830463]	110	1			T6	1		T16	1		T34	1
auto[1744830464:1879048191]	114	1			T3	1		T6	1		T5	1
auto[1879048192:2013265919]	100	1			T15	1		T124	1		T22	1
auto[2013265920:2147483647]	86	1			T2	1		T3	1		T26	1
auto[2147483648:2281701375]	109	1			T3	1		T6	1		T50	1
auto[2281701376:2415919103]	108	1			T30	1		T37	2		T123	1
auto[2415919104:2550136831]	99	1			T2	1		T37	1		T26	1
auto[2550136832:2684354559]	131	1			T15	1		T26	2		T123	1
auto[2684354560:2818572287]	100	1			T17	1		T46	1		T124	1
auto[2818572288:2952790015]	104	1			T56	1		T57	1		T384	1
auto[2952790016:3087007743]	108	1			T50	1		T37	2		T39	1
auto[3087007744:3221225471]	122	1			T100	1		T227	1		T59	2
auto[3221225472:3355443199]	91	1			T3	1		T15	1		T50	1
auto[3355443200:3489660927]	120	1			T5	1		T50	1		T26	1
auto[3489660928:3623878655]	103	1			T26	1		T46	1		T56	2
auto[3623878656:3758096383]	99	1			T2	1		T50	2		T26	1
auto[3758096384:3892314111]	104	1			T16	2		T109	1		T26	1
auto[3892314112:4026531839]	112	1			T49	1		T123	1		T82	1
auto[4026531840:4160749567]	119	1			T50	1		T56	1		T23	1
auto[4160749568:4294967295]	105	1			T15	1		T123	1		T22	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T51	1		T56	1		T128	1
auto[0:134217727]	auto[1]	57	1			T52	1		T56	2		T58	1
auto[134217728:268435455]	auto[0]	51	1			T17	1		T37	1		T124	1
auto[134217728:268435455]	auto[1]	64	1			T16	1		T124	1		T82	1
auto[268435456:402653183]	auto[0]	52	1			T26	1		T56	1		T57	1
auto[268435456:402653183]	auto[1]	51	1			T30	1		T50	1		T56	1
auto[402653184:536870911]	auto[0]	57	1			T36	1		T50	1		T37	1
auto[402653184:536870911]	auto[1]	55	1			T57	1		T47	1		T59	1
auto[536870912:671088639]	auto[0]	64	1			T26	1		T56	1		T233	1
auto[536870912:671088639]	auto[1]	65	1			T36	1		T50	1		T26	1
auto[671088640:805306367]	auto[0]	57	1			T5	1		T52	1		T56	1
auto[671088640:805306367]	auto[1]	50	1			T5	1		T26	2		T56	1
auto[805306368:939524095]	auto[0]	38	1			T50	1		T26	2		T124	1
auto[805306368:939524095]	auto[1]	43	1			T52	1		T56	1		T57	1
auto[939524096:1073741823]	auto[0]	57	1			T123	1		T233	2		T191	1
auto[939524096:1073741823]	auto[1]	66	1			T5	1		T51	1		T82	1
auto[1073741824:1207959551]	auto[0]	57	1			T3	1		T50	1		T39	1
auto[1073741824:1207959551]	auto[1]	53	1			T56	2		T57	1		T58	1
auto[1207959552:1342177279]	auto[0]	44	1			T17	1		T82	1		T69	1
auto[1207959552:1342177279]	auto[1]	60	1			T30	1		T39	1		T22	1
auto[1342177280:1476395007]	auto[0]	46	1			T2	1		T50	1		T46	2
auto[1342177280:1476395007]	auto[1]	66	1			T50	1		T26	1		T57	1
auto[1476395008:1610612735]	auto[0]	64	1			T2	1		T56	1		T23	1
auto[1476395008:1610612735]	auto[1]	64	1			T50	1		T26	1		T56	2
auto[1610612736:1744830463]	auto[0]	55	1			T39	1		T22	1		T128	1
auto[1610612736:1744830463]	auto[1]	55	1			T6	1		T16	1		T34	1
auto[1744830464:1879048191]	auto[0]	50	1			T6	1		T5	1		T16	1
auto[1744830464:1879048191]	auto[1]	64	1			T3	1		T50	1		T26	2
auto[1879048192:2013265919]	auto[0]	45	1			T124	1		T22	1		T56	2
auto[1879048192:2013265919]	auto[1]	55	1			T15	1		T187	1		T58	2
auto[2013265920:2147483647]	auto[0]	43	1			T2	1		T3	1		T22	1
auto[2013265920:2147483647]	auto[1]	43	1			T26	1		T83	1		T56	1
auto[2147483648:2281701375]	auto[0]	53	1			T3	1		T6	1		T26	1
auto[2147483648:2281701375]	auto[1]	56	1			T50	1		T26	1		T46	1
auto[2281701376:2415919103]	auto[0]	54	1			T37	2		T124	1		T56	5
auto[2281701376:2415919103]	auto[1]	54	1			T30	1		T123	1		T57	1
auto[2415919104:2550136831]	auto[0]	54	1			T2	1		T26	1		T52	1
auto[2415919104:2550136831]	auto[1]	45	1			T37	1		T56	1		T58	2
auto[2550136832:2684354559]	auto[0]	56	1			T123	1		T51	1		T80	1
auto[2550136832:2684354559]	auto[1]	75	1			T15	1		T26	2		T56	1
auto[2684354560:2818572287]	auto[0]	50	1			T46	1		T124	1		T56	1
auto[2684354560:2818572287]	auto[1]	50	1			T17	1		T48	2		T55	1
auto[2818572288:2952790015]	auto[0]	54	1			T56	1		T384	1		T47	1
auto[2818572288:2952790015]	auto[1]	50	1			T57	1		T61	1		T47	1
auto[2952790016:3087007743]	auto[0]	56	1			T50	1		T37	1		T26	1
auto[2952790016:3087007743]	auto[1]	52	1			T37	1		T39	1		T57	1
auto[3087007744:3221225471]	auto[0]	54	1			T100	1		T342	1		T48	2
auto[3087007744:3221225471]	auto[1]	68	1			T227	1		T59	2		T48	2
auto[3221225472:3355443199]	auto[0]	39	1			T3	1		T15	1		T50	1
auto[3221225472:3355443199]	auto[1]	52	1			T26	1		T189	1		T190	1
auto[3355443200:3489660927]	auto[0]	68	1			T5	1		T100	1		T51	1
auto[3355443200:3489660927]	auto[1]	52	1			T50	1		T26	1		T57	1
auto[3489660928:3623878655]	auto[0]	52	1			T46	1		T56	1		T128	1
auto[3489660928:3623878655]	auto[1]	51	1			T26	1		T56	1		T27	1
auto[3623878656:3758096383]	auto[0]	46	1			T2	1		T50	1		T26	1
auto[3623878656:3758096383]	auto[1]	53	1			T50	1		T57	1		T190	1
auto[3758096384:3892314111]	auto[0]	55	1			T16	2		T123	1		T233	2
auto[3758096384:3892314111]	auto[1]	49	1			T109	1		T26	1		T57	1
auto[3892314112:4026531839]	auto[0]	54	1			T49	1		T123	1		T82	1
auto[3892314112:4026531839]	auto[1]	58	1			T196	2		T57	1		T227	1
auto[4026531840:4160749567]	auto[0]	53	1			T50	1		T187	1		T47	1
auto[4026531840:4160749567]	auto[1]	66	1			T56	1		T23	1		T58	1
auto[4160749568:4294967295]	auto[0]	53	1			T15	1		T22	1		T83	1
auto[4160749568:4294967295]	auto[1]	52	1			T123	1		T56	1		T57	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1682

1

T2

4

T3

4

T6

2

auto[1]

1788

1

T2

1

T3

1

T6

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	124	1			T49	1		T39	1		T22	1
auto[134217728:268435455]	118	1			T2	2		T46	1		T56	2
auto[268435456:402653183]	108	1			T50	1		T26	3		T57	3
auto[402653184:536870911]	103	1			T123	1		T46	1		T124	1
auto[536870912:671088639]	100	1			T16	1		T34	1		T26	1
auto[671088640:805306367]	97	1			T37	1		T52	1		T80	1
auto[805306368:939524095]	118	1			T26	5		T123	1		T124	1
auto[939524096:1073741823]	109	1			T3	1		T16	1		T109	1
auto[1073741824:1207959551]	97	1			T2	1		T16	1		T56	1
auto[1207959552:1342177279]	96	1			T5	1		T15	1		T39	1
auto[1342177280:1476395007]	105	1			T5	1		T50	1		T26	2
auto[1476395008:1610612735]	118	1			T3	1		T5	1		T30	1
auto[1610612736:1744830463]	105	1			T2	1		T26	1		T100	2
auto[1744830464:1879048191]	99	1			T26	2		T80	1		T57	1
auto[1879048192:2013265919]	100	1			T37	1		T26	1		T82	1
auto[2013265920:2147483647]	100	1			T50	2		T37	1		T109	1
auto[2147483648:2281701375]	113	1			T15	1		T37	1		T26	1
auto[2281701376:2415919103]	101	1			T6	1		T37	1		T56	2
auto[2415919104:2550136831]	96	1			T37	1		T82	1		T56	2
auto[2550136832:2684354559]	124	1			T3	1		T15	1		T17	1
auto[2684354560:2818572287]	119	1			T37	1		T39	1		T26	1
auto[2818572288:2952790015]	113	1			T100	1		T52	1		T56	3
auto[2952790016:3087007743]	97	1			T39	1		T123	1		T57	1
auto[3087007744:3221225471]	124	1			T16	1		T17	1		T50	2
auto[3221225472:3355443199]	101	1			T34	1		T30	1		T50	3
auto[3355443200:3489660927]	114	1			T22	1		T83	1		T56	4
auto[3489660928:3623878655]	115	1			T17	1		T50	2		T26	1
auto[3623878656:3758096383]	111	1			T2	1		T6	1		T36	1
auto[3758096384:3892314111]	114	1			T5	1		T50	1		T52	1
auto[3892314112:4026531839]	118	1			T3	2		T5	1		T15	1
auto[4026531840:4160749567]	108	1			T16	1		T50	2		T26	1
auto[4160749568:4294967295]	105	1			T6	1		T26	2		T56	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	66	1			T39	1		T52	1		T56	1
auto[0:134217727]	auto[1]	58	1			T49	1		T22	1		T56	2
auto[134217728:268435455]	auto[0]	64	1			T2	2		T56	1		T233	1
auto[134217728:268435455]	auto[1]	54	1			T46	1		T56	1		T57	1
auto[268435456:402653183]	auto[0]	54	1			T50	1		T26	2		T57	2
auto[268435456:402653183]	auto[1]	54	1			T26	1		T57	1		T227	1
auto[402653184:536870911]	auto[0]	52	1			T123	1		T46	1		T83	1
auto[402653184:536870911]	auto[1]	51	1			T124	1		T82	1		T190	1
auto[536870912:671088639]	auto[0]	52	1			T56	3		T57	1		T189	1
auto[536870912:671088639]	auto[1]	48	1			T16	1		T34	1		T26	1
auto[671088640:805306367]	auto[0]	35	1			T52	1		T80	1		T56	1
auto[671088640:805306367]	auto[1]	62	1			T37	1		T56	1		T196	1
auto[805306368:939524095]	auto[0]	59	1			T26	4		T56	2		T57	1
auto[805306368:939524095]	auto[1]	59	1			T26	1		T123	1		T124	1
auto[939524096:1073741823]	auto[0]	51	1			T3	1		T16	1		T109	1
auto[939524096:1073741823]	auto[1]	58	1			T51	1		T227	1		T47	2
auto[1073741824:1207959551]	auto[0]	46	1			T2	1		T16	1		T233	1
auto[1073741824:1207959551]	auto[1]	51	1			T56	1		T196	1		T57	1
auto[1207959552:1342177279]	auto[0]	43	1			T15	1		T39	1		T26	1
auto[1207959552:1342177279]	auto[1]	53	1			T5	1		T191	1		T190	1
auto[1342177280:1476395007]	auto[0]	60	1			T5	1		T50	1		T26	1
auto[1342177280:1476395007]	auto[1]	45	1			T26	1		T123	1		T227	1
auto[1476395008:1610612735]	auto[0]	53	1			T3	1		T46	1		T124	1
auto[1476395008:1610612735]	auto[1]	65	1			T5	1		T30	1		T50	1
auto[1610612736:1744830463]	auto[0]	46	1			T2	1		T100	2		T56	1
auto[1610612736:1744830463]	auto[1]	59	1			T26	1		T56	1		T58	1
auto[1744830464:1879048191]	auto[0]	49	1			T80	1		T57	1		T227	1
auto[1744830464:1879048191]	auto[1]	50	1			T26	2		T191	1		T58	1
auto[1879048192:2013265919]	auto[0]	47	1			T56	2		T69	1		T59	1
auto[1879048192:2013265919]	auto[1]	53	1			T37	1		T26	1		T82	1
auto[2013265920:2147483647]	auto[0]	55	1			T50	1		T37	1		T46	1
auto[2013265920:2147483647]	auto[1]	45	1			T50	1		T109	1		T57	3
auto[2147483648:2281701375]	auto[0]	52	1			T37	1		T191	1		T48	1
auto[2147483648:2281701375]	auto[1]	61	1			T15	1		T26	1		T57	2
auto[2281701376:2415919103]	auto[0]	52	1			T6	1		T37	1		T56	1
auto[2281701376:2415919103]	auto[1]	49	1			T56	1		T47	2		T242	1
auto[2415919104:2550136831]	auto[0]	50	1			T37	1		T82	1		T191	1
auto[2415919104:2550136831]	auto[1]	46	1			T56	2		T57	1		T190	1
auto[2550136832:2684354559]	auto[0]	65	1			T3	1		T17	1		T124	1
auto[2550136832:2684354559]	auto[1]	59	1			T15	1		T50	1		T39	1
auto[2684354560:2818572287]	auto[0]	63	1			T37	1		T39	1		T22	1
auto[2684354560:2818572287]	auto[1]	56	1			T26	1		T187	1		T58	1
auto[2818572288:2952790015]	auto[0]	54	1			T100	1		T52	1		T56	2
auto[2818572288:2952790015]	auto[1]	59	1			T56	1		T58	1		T47	2
auto[2952790016:3087007743]	auto[0]	43	1			T39	1		T57	1		T59	3
auto[2952790016:3087007743]	auto[1]	54	1			T123	1		T58	1		T60	1
auto[3087007744:3221225471]	auto[0]	47	1			T17	1		T50	1		T52	1
auto[3087007744:3221225471]	auto[1]	77	1			T16	1		T50	1		T56	2
auto[3221225472:3355443199]	auto[0]	42	1			T34	1		T50	2		T124	1
auto[3221225472:3355443199]	auto[1]	59	1			T30	1		T50	1		T56	1
auto[3355443200:3489660927]	auto[0]	59	1			T22	1		T83	1		T56	3
auto[3355443200:3489660927]	auto[1]	55	1			T56	1		T47	1		T59	1
auto[3489660928:3623878655]	auto[0]	53	1			T17	1		T50	1		T22	2
auto[3489660928:3623878655]	auto[1]	62	1			T50	1		T26	1		T56	1
auto[3623878656:3758096383]	auto[0]	48	1			T6	1		T124	1		T51	1
auto[3623878656:3758096383]	auto[1]	63	1			T2	1		T36	1		T30	1
auto[3758096384:3892314111]	auto[0]	55	1			T51	1		T56	1		T58	1
auto[3758096384:3892314111]	auto[1]	59	1			T5	1		T50	1		T52	1
auto[3892314112:4026531839]	auto[0]	66	1			T3	1		T5	1		T15	1
auto[3892314112:4026531839]	auto[1]	52	1			T3	1		T36	1		T26	1
auto[4026531840:4160749567]	auto[0]	45	1			T16	1		T50	2		T124	1
auto[4026531840:4160749567]	auto[1]	63	1			T26	1		T56	2		T57	1
auto[4160749568:4294967295]	auto[0]	56	1			T26	1		T56	2		T57	1
auto[4160749568:4294967295]	auto[1]	49	1			T6	1		T26	1		T187	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1651

1

T2

3

T3

4

T6

2

auto[1]

1818

1

T2

2

T3

1

T6

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	119	1			T5	1		T16	1		T51	1
auto[134217728:268435455]	120	1			T2	1		T3	1		T6	1
auto[268435456:402653183]	115	1			T17	1		T50	1		T26	1
auto[402653184:536870911]	105	1			T50	1		T26	2		T46	1
auto[536870912:671088639]	115	1			T2	1		T50	1		T37	1
auto[671088640:805306367]	111	1			T109	1		T39	1		T123	1
auto[805306368:939524095]	106	1			T50	1		T37	1		T39	1
auto[939524096:1073741823]	101	1			T2	1		T37	1		T26	2
auto[1073741824:1207959551]	115	1			T16	1		T50	1		T37	1
auto[1207959552:1342177279]	112	1			T15	1		T39	1		T52	1
auto[1342177280:1476395007]	117	1			T50	1		T39	1		T26	1
auto[1476395008:1610612735]	111	1			T50	1		T26	2		T22	1
auto[1610612736:1744830463]	101	1			T3	1		T34	1		T50	2
auto[1744830464:1879048191]	101	1			T2	1		T6	1		T36	1
auto[1879048192:2013265919]	91	1			T2	1		T50	1		T26	1
auto[2013265920:2147483647]	107	1			T26	1		T52	1		T233	1
auto[2147483648:2281701375]	101	1			T15	1		T46	1		T56	3
auto[2281701376:2415919103]	128	1			T5	1		T26	1		T56	1
auto[2415919104:2550136831]	111	1			T17	1		T34	1		T30	1
auto[2550136832:2684354559]	103	1			T26	2		T123	2		T56	2
auto[2684354560:2818572287]	106	1			T5	1		T15	1		T37	1
auto[2818572288:2952790015]	102	1			T3	1		T30	1		T50	1
auto[2952790016:3087007743]	102	1			T16	1		T50	1		T26	2
auto[3087007744:3221225471]	104	1			T6	1		T5	1		T15	1
auto[3221225472:3355443199]	111	1			T3	1		T49	1		T26	2
auto[3355443200:3489660927]	108	1			T5	1		T17	1		T50	1
auto[3489660928:3623878655]	109	1			T50	1		T26	1		T56	1
auto[3623878656:3758096383]	101	1			T3	1		T16	1		T36	1
auto[3758096384:3892314111]	98	1			T124	2		T51	1		T56	3
auto[3892314112:4026531839]	124	1			T30	1		T50	2		T37	1
auto[4026531840:4160749567]	107	1			T123	1		T100	1		T58	1
auto[4160749568:4294967295]	107	1			T100	1		T83	1		T57	1