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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4680 1 T2 8 T3 6 T6 6
auto[1] 2260 1 T2 2 T3 4 T5 6


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 254 1 T5 2 T109 2 T196 2
auto[134217728:268435455] 238 1 T2 4 T34 2 T49 2
auto[268435456:402653183] 214 1 T50 2 T39 2 T26 2
auto[402653184:536870911] 198 1 T6 2 T22 4 T57 2
auto[536870912:671088639] 212 1 T37 2 T26 4 T56 8
auto[671088640:805306367] 230 1 T2 2 T16 2 T39 2
auto[805306368:939524095] 226 1 T15 2 T50 4 T123 2
auto[939524096:1073741823] 238 1 T5 2 T50 2 T37 4
auto[1073741824:1207959551] 228 1 T17 2 T50 2 T109 2
auto[1207959552:1342177279] 200 1 T3 2 T39 2 T123 2
auto[1342177280:1476395007] 180 1 T16 2 T34 2 T26 4
auto[1476395008:1610612735] 226 1 T5 2 T50 2 T26 2
auto[1610612736:1744830463] 198 1 T5 2 T36 2 T50 4
auto[1744830464:1879048191] 216 1 T17 2 T26 4 T124 4
auto[1879048192:2013265919] 208 1 T26 2 T124 2 T56 2
auto[2013265920:2147483647] 204 1 T30 2 T26 2 T52 2
auto[2147483648:2281701375] 242 1 T26 4 T100 2 T82 2
auto[2281701376:2415919103] 248 1 T100 2 T51 2 T23 2
auto[2415919104:2550136831] 198 1 T2 2 T6 2 T123 2
auto[2550136832:2684354559] 220 1 T2 2 T50 6 T26 2
auto[2684354560:2818572287] 216 1 T16 4 T46 2 T51 2
auto[2818572288:2952790015] 176 1 T16 2 T39 2 T82 2
auto[2952790016:3087007743] 232 1 T3 4 T15 2 T30 2
auto[3087007744:3221225471] 238 1 T124 2 T56 4 T227 2
auto[3221225472:3355443199] 222 1 T5 2 T56 2 T58 2
auto[3355443200:3489660927] 240 1 T3 2 T17 2 T36 2
auto[3489660928:3623878655] 198 1 T15 2 T56 4 T57 2
auto[3623878656:3758096383] 228 1 T30 2 T22 2 T56 6
auto[3758096384:3892314111] 188 1 T3 2 T50 2 T37 2
auto[3892314112:4026531839] 204 1 T50 4 T39 2 T26 4
auto[4026531840:4160749567] 192 1 T15 2 T26 2 T46 2
auto[4160749568:4294967295] 228 1 T6 2 T50 2 T37 4


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 174 1 T109 2 T196 2 T57 2
auto[0:134217727] auto[1] 80 1 T5 2 T57 2 T189 2
auto[134217728:268435455] auto[0] 164 1 T2 4 T34 2 T49 2
auto[134217728:268435455] auto[1] 74 1 T37 2 T83 2 T56 2
auto[268435456:402653183] auto[0] 148 1 T39 2 T46 2 T80 2
auto[268435456:402653183] auto[1] 66 1 T50 2 T26 2 T100 2
auto[402653184:536870911] auto[0] 124 1 T6 2 T22 4 T57 2
auto[402653184:536870911] auto[1] 74 1 T47 2 T28 2 T7 4
auto[536870912:671088639] auto[0] 150 1 T37 2 T56 8 T57 2
auto[536870912:671088639] auto[1] 62 1 T26 4 T59 4 T28 2
auto[671088640:805306367] auto[0] 164 1 T2 2 T16 2 T57 2
auto[671088640:805306367] auto[1] 66 1 T39 2 T26 2 T52 2
auto[805306368:939524095] auto[0] 144 1 T50 4 T56 4 T57 4
auto[805306368:939524095] auto[1] 82 1 T15 2 T123 2 T198 2
auto[939524096:1073741823] auto[0] 152 1 T5 2 T50 2 T37 2
auto[939524096:1073741823] auto[1] 86 1 T37 2 T100 4 T233 2
auto[1073741824:1207959551] auto[0] 156 1 T17 2 T50 2 T26 2
auto[1073741824:1207959551] auto[1] 72 1 T109 2 T26 2 T56 2
auto[1207959552:1342177279] auto[0] 128 1 T3 2 T39 2 T123 2
auto[1207959552:1342177279] auto[1] 72 1 T59 2 T28 2 T396 2
auto[1342177280:1476395007] auto[0] 120 1 T16 2 T34 2 T26 2
auto[1342177280:1476395007] auto[1] 60 1 T26 2 T123 2 T57 2
auto[1476395008:1610612735] auto[0] 144 1 T50 2 T26 2 T57 4
auto[1476395008:1610612735] auto[1] 82 1 T5 2 T56 2 T128 2
auto[1610612736:1744830463] auto[0] 146 1 T5 2 T50 4 T26 2
auto[1610612736:1744830463] auto[1] 52 1 T36 2 T56 4 T198 2
auto[1744830464:1879048191] auto[0] 168 1 T17 2 T26 2 T124 2
auto[1744830464:1879048191] auto[1] 48 1 T26 2 T124 2 T59 2
auto[1879048192:2013265919] auto[0] 146 1 T124 2 T56 2 T227 2
auto[1879048192:2013265919] auto[1] 62 1 T26 2 T242 2 T90 2
auto[2013265920:2147483647] auto[0] 136 1 T26 2 T57 6 T247 2
auto[2013265920:2147483647] auto[1] 68 1 T30 2 T52 2 T56 4
auto[2147483648:2281701375] auto[0] 164 1 T26 4 T82 2 T56 4
auto[2147483648:2281701375] auto[1] 78 1 T100 2 T198 2 T47 4
auto[2281701376:2415919103] auto[0] 164 1 T57 2 T187 2 T190 2
auto[2281701376:2415919103] auto[1] 84 1 T100 2 T51 2 T23 2
auto[2415919104:2550136831] auto[0] 148 1 T6 2 T124 2 T80 2
auto[2415919104:2550136831] auto[1] 50 1 T2 2 T123 2 T56 4
auto[2550136832:2684354559] auto[0] 158 1 T2 2 T50 6 T123 2
auto[2550136832:2684354559] auto[1] 62 1 T26 2 T47 2 T73 2
auto[2684354560:2818572287] auto[0] 122 1 T16 4 T46 2 T51 2
auto[2684354560:2818572287] auto[1] 94 1 T56 2 T23 2 T128 2
auto[2818572288:2952790015] auto[0] 108 1 T16 2 T39 2 T82 2
auto[2818572288:2952790015] auto[1] 68 1 T56 4 T47 2 T18 4
auto[2952790016:3087007743] auto[0] 144 1 T3 2 T15 2 T50 2
auto[2952790016:3087007743] auto[1] 88 1 T3 2 T30 2 T26 2
auto[3087007744:3221225471] auto[0] 162 1 T124 2 T56 4 T227 2
auto[3087007744:3221225471] auto[1] 76 1 T40 2 T61 2 T47 2
auto[3221225472:3355443199] auto[0] 154 1 T56 2 T47 2 T59 2
auto[3221225472:3355443199] auto[1] 68 1 T5 2 T58 2 T59 2
auto[3355443200:3489660927] auto[0] 146 1 T36 2 T26 2 T56 2
auto[3355443200:3489660927] auto[1] 94 1 T3 2 T17 2 T50 2
auto[3489660928:3623878655] auto[0] 140 1 T15 2 T56 2 T247 2
auto[3489660928:3623878655] auto[1] 58 1 T56 2 T57 2 T31 2
auto[3623878656:3758096383] auto[0] 162 1 T30 2 T56 6 T57 4
auto[3623878656:3758096383] auto[1] 66 1 T22 2 T187 2 T58 2
auto[3758096384:3892314111] auto[0] 134 1 T3 2 T50 2 T37 2
auto[3758096384:3892314111] auto[1] 54 1 T124 2 T22 2 T80 2
auto[3892314112:4026531839] auto[0] 148 1 T26 2 T46 2 T51 4
auto[3892314112:4026531839] auto[1] 56 1 T50 4 T39 2 T26 2
auto[4026531840:4160749567] auto[0] 116 1 T15 2 T46 2 T83 2
auto[4026531840:4160749567] auto[1] 76 1 T26 2 T189 2 T47 2
auto[4160749568:4294967295] auto[0] 146 1 T6 2 T50 2 T37 2
auto[4160749568:4294967295] auto[1] 82 1 T37 2 T52 2 T56 2

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