Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.46 99.04 98.19 98.72 97.67 99.02 98.41 91.14


Total test records in report: 1082
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T1007 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3130122529 Jun 02 02:43:00 PM PDT 24 Jun 02 02:43:16 PM PDT 24 4199560396 ps
T179 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3068264768 Jun 02 02:44:38 PM PDT 24 Jun 02 02:44:42 PM PDT 24 814610823 ps
T1008 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2791253364 Jun 02 02:44:18 PM PDT 24 Jun 02 02:44:21 PM PDT 24 11038976 ps
T1009 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2506839479 Jun 02 02:43:28 PM PDT 24 Jun 02 02:43:30 PM PDT 24 178984352 ps
T1010 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1959162991 Jun 02 02:43:25 PM PDT 24 Jun 02 02:43:36 PM PDT 24 357978432 ps
T1011 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.801506438 Jun 02 02:43:28 PM PDT 24 Jun 02 02:43:30 PM PDT 24 59406562 ps
T1012 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1093728307 Jun 02 02:43:06 PM PDT 24 Jun 02 02:43:21 PM PDT 24 6302501287 ps
T1013 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.134073929 Jun 02 02:43:26 PM PDT 24 Jun 02 02:43:31 PM PDT 24 1724333658 ps
T1014 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1282797683 Jun 02 02:43:31 PM PDT 24 Jun 02 02:43:32 PM PDT 24 46204697 ps
T1015 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2093348565 Jun 02 02:43:08 PM PDT 24 Jun 02 02:43:11 PM PDT 24 235972530 ps
T1016 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1328745675 Jun 02 02:43:18 PM PDT 24 Jun 02 02:43:23 PM PDT 24 103132687 ps
T1017 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.590285866 Jun 02 02:43:21 PM PDT 24 Jun 02 02:43:25 PM PDT 24 304865604 ps
T1018 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3076287015 Jun 02 02:43:35 PM PDT 24 Jun 02 02:43:36 PM PDT 24 50201160 ps
T170 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.4256242969 Jun 02 02:43:11 PM PDT 24 Jun 02 02:43:14 PM PDT 24 176199175 ps
T1019 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2706905910 Jun 02 02:43:23 PM PDT 24 Jun 02 02:43:25 PM PDT 24 11397171 ps
T1020 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3887531846 Jun 02 02:43:25 PM PDT 24 Jun 02 02:43:29 PM PDT 24 103271092 ps
T1021 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2270801317 Jun 02 02:43:34 PM PDT 24 Jun 02 02:43:36 PM PDT 24 33690304 ps
T1022 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1344328104 Jun 02 02:44:18 PM PDT 24 Jun 02 02:44:21 PM PDT 24 85934069 ps
T1023 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3957683322 Jun 02 02:45:03 PM PDT 24 Jun 02 02:45:07 PM PDT 24 388024770 ps
T165 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3453451627 Jun 02 02:43:26 PM PDT 24 Jun 02 02:43:34 PM PDT 24 505451530 ps
T1024 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1629000541 Jun 02 02:43:10 PM PDT 24 Jun 02 02:43:17 PM PDT 24 3946299986 ps
T1025 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3988475747 Jun 02 02:43:00 PM PDT 24 Jun 02 02:43:05 PM PDT 24 526046768 ps
T1026 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3777780948 Jun 02 02:43:26 PM PDT 24 Jun 02 02:43:31 PM PDT 24 189771701 ps
T1027 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3876300759 Jun 02 02:43:08 PM PDT 24 Jun 02 02:43:11 PM PDT 24 287918771 ps
T1028 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2620541868 Jun 02 02:43:04 PM PDT 24 Jun 02 02:43:05 PM PDT 24 49507100 ps
T1029 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3930392537 Jun 02 02:43:35 PM PDT 24 Jun 02 02:43:44 PM PDT 24 3265420307 ps
T174 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.4032067094 Jun 02 02:43:26 PM PDT 24 Jun 02 02:43:30 PM PDT 24 183721168 ps
T1030 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.4294809273 Jun 02 02:43:01 PM PDT 24 Jun 02 02:43:03 PM PDT 24 36034269 ps
T1031 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.134722978 Jun 02 02:43:39 PM PDT 24 Jun 02 02:43:40 PM PDT 24 17637365 ps
T1032 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4147961390 Jun 02 02:43:23 PM PDT 24 Jun 02 02:43:24 PM PDT 24 102631731 ps
T1033 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2497585114 Jun 02 02:43:27 PM PDT 24 Jun 02 02:43:29 PM PDT 24 10121763 ps
T1034 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4292396932 Jun 02 02:44:37 PM PDT 24 Jun 02 02:44:39 PM PDT 24 49309466 ps
T1035 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3647813161 Jun 02 02:43:03 PM PDT 24 Jun 02 02:43:05 PM PDT 24 85001931 ps
T1036 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.277007005 Jun 02 02:43:08 PM PDT 24 Jun 02 02:43:15 PM PDT 24 222381231 ps
T1037 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.4060420984 Jun 02 02:43:23 PM PDT 24 Jun 02 02:43:26 PM PDT 24 401604138 ps
T1038 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2644597197 Jun 02 02:44:19 PM PDT 24 Jun 02 02:44:23 PM PDT 24 282097889 ps
T1039 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1564396737 Jun 02 02:43:29 PM PDT 24 Jun 02 02:43:32 PM PDT 24 34826709 ps
T1040 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3650355135 Jun 02 02:43:10 PM PDT 24 Jun 02 02:43:12 PM PDT 24 170440054 ps
T1041 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3343110802 Jun 02 02:43:42 PM PDT 24 Jun 02 02:43:43 PM PDT 24 35980961 ps
T1042 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2596285699 Jun 02 02:43:05 PM PDT 24 Jun 02 02:43:09 PM PDT 24 112573621 ps
T1043 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2457530559 Jun 02 02:43:19 PM PDT 24 Jun 02 02:43:29 PM PDT 24 1583033520 ps
T166 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3117131466 Jun 02 02:43:15 PM PDT 24 Jun 02 02:43:18 PM PDT 24 233434198 ps
T1044 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3885759363 Jun 02 02:43:10 PM PDT 24 Jun 02 02:43:24 PM PDT 24 964234285 ps
T1045 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1023008924 Jun 02 02:43:06 PM PDT 24 Jun 02 02:43:10 PM PDT 24 277321152 ps
T1046 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2021158596 Jun 02 02:43:26 PM PDT 24 Jun 02 02:43:28 PM PDT 24 12193113 ps
T1047 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.167317558 Jun 02 02:43:19 PM PDT 24 Jun 02 02:43:21 PM PDT 24 17724857 ps
T1048 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1886740730 Jun 02 02:43:07 PM PDT 24 Jun 02 02:43:11 PM PDT 24 143968347 ps
T1049 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3333678578 Jun 02 02:43:34 PM PDT 24 Jun 02 02:43:40 PM PDT 24 18807311 ps
T1050 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1862214525 Jun 02 02:43:10 PM PDT 24 Jun 02 02:43:12 PM PDT 24 87351882 ps
T1051 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1409829189 Jun 02 02:43:16 PM PDT 24 Jun 02 02:43:18 PM PDT 24 74466156 ps
T1052 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1223023578 Jun 02 02:43:14 PM PDT 24 Jun 02 02:43:15 PM PDT 24 29476400 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.851365532 Jun 02 02:43:04 PM PDT 24 Jun 02 02:43:08 PM PDT 24 88861988 ps
T1054 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2943432371 Jun 02 02:43:05 PM PDT 24 Jun 02 02:43:06 PM PDT 24 16365217 ps
T1055 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1307134090 Jun 02 02:43:05 PM PDT 24 Jun 02 02:43:10 PM PDT 24 536959987 ps
T1056 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2610748636 Jun 02 02:43:28 PM PDT 24 Jun 02 02:43:32 PM PDT 24 89657705 ps
T1057 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4118445548 Jun 02 02:43:07 PM PDT 24 Jun 02 02:43:11 PM PDT 24 248851025 ps
T1058 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2688083415 Jun 02 02:43:02 PM PDT 24 Jun 02 02:43:04 PM PDT 24 40406200 ps
T1059 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4162570148 Jun 02 02:43:22 PM PDT 24 Jun 02 02:43:25 PM PDT 24 145473271 ps
T1060 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2799248617 Jun 02 02:43:00 PM PDT 24 Jun 02 02:43:02 PM PDT 24 46087337 ps
T1061 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1984741239 Jun 02 02:43:28 PM PDT 24 Jun 02 02:43:30 PM PDT 24 42063198 ps
T1062 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.930937995 Jun 02 02:43:46 PM PDT 24 Jun 02 02:43:48 PM PDT 24 46790902 ps
T1063 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2127120256 Jun 02 02:43:11 PM PDT 24 Jun 02 02:43:13 PM PDT 24 57068362 ps
T181 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1869936331 Jun 02 02:43:05 PM PDT 24 Jun 02 02:43:15 PM PDT 24 215264477 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1309854186 Jun 02 02:43:18 PM PDT 24 Jun 02 02:43:22 PM PDT 24 243138303 ps
T1065 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.64105151 Jun 02 02:43:21 PM PDT 24 Jun 02 02:43:24 PM PDT 24 499428285 ps
T1066 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.531194272 Jun 02 02:43:27 PM PDT 24 Jun 02 02:43:31 PM PDT 24 163049871 ps
T1067 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3609953485 Jun 02 02:44:18 PM PDT 24 Jun 02 02:44:21 PM PDT 24 15806968 ps
T1068 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2958718393 Jun 02 02:42:58 PM PDT 24 Jun 02 02:43:12 PM PDT 24 609913070 ps
T1069 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3071034229 Jun 02 02:42:57 PM PDT 24 Jun 02 02:42:59 PM PDT 24 72461054 ps
T1070 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2317348336 Jun 02 02:43:25 PM PDT 24 Jun 02 02:43:27 PM PDT 24 69786322 ps
T1071 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2851234831 Jun 02 02:43:15 PM PDT 24 Jun 02 02:43:18 PM PDT 24 416301982 ps
T1072 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1694968633 Jun 02 02:43:26 PM PDT 24 Jun 02 02:43:27 PM PDT 24 40600116 ps
T1073 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.684999877 Jun 02 02:43:25 PM PDT 24 Jun 02 02:43:32 PM PDT 24 650257964 ps
T1074 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1148712109 Jun 02 02:43:06 PM PDT 24 Jun 02 02:43:08 PM PDT 24 12075329 ps
T1075 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3126448857 Jun 02 02:43:06 PM PDT 24 Jun 02 02:43:08 PM PDT 24 74163209 ps
T1076 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2252630740 Jun 02 02:43:05 PM PDT 24 Jun 02 02:43:07 PM PDT 24 11420275 ps
T1077 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3218340467 Jun 02 02:43:27 PM PDT 24 Jun 02 02:43:30 PM PDT 24 26988852 ps
T1078 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1950686821 Jun 02 02:43:25 PM PDT 24 Jun 02 02:43:27 PM PDT 24 32495600 ps
T1079 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2652478826 Jun 02 02:43:08 PM PDT 24 Jun 02 02:43:13 PM PDT 24 95232464 ps
T1080 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2886458436 Jun 02 02:43:02 PM PDT 24 Jun 02 02:43:11 PM PDT 24 148930003 ps
T1081 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1823060661 Jun 02 02:43:27 PM PDT 24 Jun 02 02:43:29 PM PDT 24 22937761 ps
T1082 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.693448929 Jun 02 02:43:25 PM PDT 24 Jun 02 02:43:27 PM PDT 24 74311011 ps

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1362140071
Short name T5
Test name
Test status
Simulation time 159804138 ps
CPU time 4.2 seconds
Started Jun 02 02:59:39 PM PDT 24
Finished Jun 02 02:59:43 PM PDT 24
Peak memory 209428 kb
Host smart-e87f4b7f-1ff3-4e1e-a24f-81c6391218d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362140071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1362140071
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4236542801
Short name T56
Test name
Test status
Simulation time 5155944232 ps
CPU time 46.62 seconds
Started Jun 02 03:03:53 PM PDT 24
Finished Jun 02 03:04:40 PM PDT 24
Peak memory 216400 kb
Host smart-6ffbfb44-f9d0-495a-b313-d116d14a5230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236542801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4236542801
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2520767200
Short name T26
Test name
Test status
Simulation time 316829595 ps
CPU time 16.1 seconds
Started Jun 02 03:02:21 PM PDT 24
Finished Jun 02 03:02:37 PM PDT 24
Peak memory 220184 kb
Host smart-23afeb53-3219-4b39-a2b9-05a60ff961a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520767200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2520767200
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1577149508
Short name T58
Test name
Test status
Simulation time 2597443800 ps
CPU time 24.23 seconds
Started Jun 02 02:59:26 PM PDT 24
Finished Jun 02 02:59:51 PM PDT 24
Peak memory 221548 kb
Host smart-7b053c28-9804-43c8-b59e-2e5853cacb99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577149508 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1577149508
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3252609462
Short name T11
Test name
Test status
Simulation time 506930758 ps
CPU time 12.42 seconds
Started Jun 02 02:59:25 PM PDT 24
Finished Jun 02 02:59:38 PM PDT 24
Peak memory 234612 kb
Host smart-fe89daef-6dc1-4787-9902-f46a7b9b34c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252609462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3252609462
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3988674637
Short name T47
Test name
Test status
Simulation time 8790575099 ps
CPU time 46.44 seconds
Started Jun 02 03:04:29 PM PDT 24
Finished Jun 02 03:05:16 PM PDT 24
Peak memory 222544 kb
Host smart-3c08ee1c-7d13-4894-b530-39351354b6ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988674637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3988674637
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.945008453
Short name T34
Test name
Test status
Simulation time 200108480 ps
CPU time 2.18 seconds
Started Jun 02 03:02:52 PM PDT 24
Finished Jun 02 03:02:55 PM PDT 24
Peak memory 208924 kb
Host smart-242cc1e6-85eb-41a6-bd0d-e8a3a37de0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945008453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.945008453
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1500783543
Short name T57
Test name
Test status
Simulation time 2819889414 ps
CPU time 29.06 seconds
Started Jun 02 03:01:17 PM PDT 24
Finished Jun 02 03:01:46 PM PDT 24
Peak memory 216952 kb
Host smart-786269fd-d367-4ff9-91f2-ed99694f6723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500783543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1500783543
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.474273838
Short name T7
Test name
Test status
Simulation time 9521943330 ps
CPU time 47.11 seconds
Started Jun 02 03:03:59 PM PDT 24
Finished Jun 02 03:04:47 PM PDT 24
Peak memory 217048 kb
Host smart-fdc14dbf-2c21-40fd-a883-40c519f62277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474273838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.474273838
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.587852866
Short name T359
Test name
Test status
Simulation time 1411208951 ps
CPU time 62.12 seconds
Started Jun 02 03:00:52 PM PDT 24
Finished Jun 02 03:01:56 PM PDT 24
Peak memory 214652 kb
Host smart-ae4a0256-7589-4535-a590-693673e379bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587852866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.587852866
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3301399809
Short name T106
Test name
Test status
Simulation time 88644655 ps
CPU time 3.42 seconds
Started Jun 02 02:43:00 PM PDT 24
Finished Jun 02 02:43:04 PM PDT 24
Peak memory 219828 kb
Host smart-c5540a77-4063-4826-9eba-f132cc8aca44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301399809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3301399809
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.10666534
Short name T238
Test name
Test status
Simulation time 510849493 ps
CPU time 15.44 seconds
Started Jun 02 03:01:22 PM PDT 24
Finished Jun 02 03:01:38 PM PDT 24
Peak memory 215120 kb
Host smart-47028983-ecdc-48c3-ac2c-6ab4c1ba73fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10666534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.10666534
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3341290160
Short name T37
Test name
Test status
Simulation time 324564329 ps
CPU time 4.48 seconds
Started Jun 02 03:03:06 PM PDT 24
Finished Jun 02 03:03:11 PM PDT 24
Peak memory 221468 kb
Host smart-bef6ebe6-3ac8-4631-8f95-99d0348af782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341290160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3341290160
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3668201044
Short name T332
Test name
Test status
Simulation time 8123666803 ps
CPU time 107.17 seconds
Started Jun 02 03:04:22 PM PDT 24
Finished Jun 02 03:06:10 PM PDT 24
Peak memory 214412 kb
Host smart-dd1846e9-9703-4bc9-9f5c-e33c4ab08204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668201044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3668201044
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3901306586
Short name T23
Test name
Test status
Simulation time 304233856 ps
CPU time 5.72 seconds
Started Jun 02 03:02:14 PM PDT 24
Finished Jun 02 03:02:20 PM PDT 24
Peak memory 209344 kb
Host smart-9a06ea9b-e29c-4d5d-ab87-f7d39904bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901306586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3901306586
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3212719182
Short name T10
Test name
Test status
Simulation time 98276824 ps
CPU time 4.46 seconds
Started Jun 02 03:00:23 PM PDT 24
Finished Jun 02 03:00:28 PM PDT 24
Peak memory 214160 kb
Host smart-b7e624a0-22b7-4bd2-b569-344d8b93a4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212719182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3212719182
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2258292897
Short name T397
Test name
Test status
Simulation time 1614355357 ps
CPU time 15.12 seconds
Started Jun 02 03:00:23 PM PDT 24
Finished Jun 02 03:00:39 PM PDT 24
Peak memory 214608 kb
Host smart-e34a71d7-d0f1-4f61-b008-76ff12f39374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2258292897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2258292897
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3504303136
Short name T16
Test name
Test status
Simulation time 389488286 ps
CPU time 3.12 seconds
Started Jun 02 03:02:38 PM PDT 24
Finished Jun 02 03:02:41 PM PDT 24
Peak memory 214164 kb
Host smart-b29196b0-89fc-4ed6-a2b8-234942c9213c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504303136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3504303136
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1794262559
Short name T111
Test name
Test status
Simulation time 100287862 ps
CPU time 3.17 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:09 PM PDT 24
Peak memory 214060 kb
Host smart-e2523902-65f6-48c2-8b38-235f0b8ccfd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794262559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1794262559
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2225560258
Short name T230
Test name
Test status
Simulation time 11834867994 ps
CPU time 55.19 seconds
Started Jun 02 03:03:25 PM PDT 24
Finished Jun 02 03:04:21 PM PDT 24
Peak memory 222664 kb
Host smart-06e50902-3462-4171-87a9-c35196900e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225560258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2225560258
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1475694116
Short name T54
Test name
Test status
Simulation time 184073201 ps
CPU time 10.63 seconds
Started Jun 02 03:03:35 PM PDT 24
Finished Jun 02 03:03:47 PM PDT 24
Peak memory 222636 kb
Host smart-c19359de-7249-40f9-8ceb-a8d203fd58c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475694116 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1475694116
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2206813088
Short name T314
Test name
Test status
Simulation time 3034048701 ps
CPU time 14.5 seconds
Started Jun 02 03:04:32 PM PDT 24
Finished Jun 02 03:04:47 PM PDT 24
Peak memory 214956 kb
Host smart-3a1b9082-2488-486a-9c57-a38f9a18d16c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206813088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2206813088
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3673824086
Short name T69
Test name
Test status
Simulation time 68081604 ps
CPU time 3.39 seconds
Started Jun 02 03:02:13 PM PDT 24
Finished Jun 02 03:02:17 PM PDT 24
Peak memory 222556 kb
Host smart-1a617d95-ea5f-4332-8d2a-d0afc560b7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673824086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3673824086
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.4112853605
Short name T25
Test name
Test status
Simulation time 319755665 ps
CPU time 2.51 seconds
Started Jun 02 03:01:16 PM PDT 24
Finished Jun 02 03:01:19 PM PDT 24
Peak memory 216016 kb
Host smart-ba67f5a2-2445-4b4a-931e-0949bda127a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112853605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.4112853605
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3715218771
Short name T335
Test name
Test status
Simulation time 2401295654 ps
CPU time 15.68 seconds
Started Jun 02 03:01:00 PM PDT 24
Finished Jun 02 03:01:17 PM PDT 24
Peak memory 215352 kb
Host smart-6c7fe6bd-d8ea-4f70-8217-c31cfddae1de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3715218771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3715218771
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2757558349
Short name T48
Test name
Test status
Simulation time 2177721824 ps
CPU time 52.75 seconds
Started Jun 02 03:04:39 PM PDT 24
Finished Jun 02 03:05:33 PM PDT 24
Peak memory 214496 kb
Host smart-8dc7d731-a0b3-4e1d-bd75-84b2a9c94708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757558349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2757558349
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2365693136
Short name T21
Test name
Test status
Simulation time 46176676 ps
CPU time 2.88 seconds
Started Jun 02 03:02:31 PM PDT 24
Finished Jun 02 03:02:34 PM PDT 24
Peak memory 208704 kb
Host smart-fefe8b60-dede-46cf-8ae1-c6451beef8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365693136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2365693136
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2247915619
Short name T6
Test name
Test status
Simulation time 237217031 ps
CPU time 2.22 seconds
Started Jun 02 03:03:36 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 214308 kb
Host smart-fae02ae1-c6d8-404f-b04f-6ed3254ed066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247915619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2247915619
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.600242078
Short name T31
Test name
Test status
Simulation time 85757216 ps
CPU time 2.73 seconds
Started Jun 02 03:00:29 PM PDT 24
Finished Jun 02 03:00:32 PM PDT 24
Peak memory 214212 kb
Host smart-89f9a815-df9a-4a64-bf39-ae9fad1c50fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600242078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.600242078
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1316276492
Short name T167
Test name
Test status
Simulation time 273675772 ps
CPU time 6.17 seconds
Started Jun 02 02:43:28 PM PDT 24
Finished Jun 02 02:43:35 PM PDT 24
Peak memory 213828 kb
Host smart-562e92ac-0fdb-4a69-bc69-efa8b2f59690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316276492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1316276492
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.917574739
Short name T354
Test name
Test status
Simulation time 109759649 ps
CPU time 3.94 seconds
Started Jun 02 03:01:37 PM PDT 24
Finished Jun 02 03:01:41 PM PDT 24
Peak memory 215100 kb
Host smart-cc78974b-3d00-49ee-ac24-979244aa4fda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917574739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.917574739
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2435429889
Short name T38
Test name
Test status
Simulation time 483075111 ps
CPU time 3.95 seconds
Started Jun 02 03:03:54 PM PDT 24
Finished Jun 02 03:03:59 PM PDT 24
Peak memory 210060 kb
Host smart-8711be19-6cad-45d8-b422-518fdcef0e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435429889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2435429889
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3263545625
Short name T297
Test name
Test status
Simulation time 1338607947 ps
CPU time 18.06 seconds
Started Jun 02 03:01:57 PM PDT 24
Finished Jun 02 03:02:15 PM PDT 24
Peak memory 214560 kb
Host smart-322c49d8-8f20-4eb2-ab55-4f30b22d8423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263545625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3263545625
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.681113907
Short name T411
Test name
Test status
Simulation time 19621167 ps
CPU time 0.93 seconds
Started Jun 02 03:01:28 PM PDT 24
Finished Jun 02 03:01:29 PM PDT 24
Peak memory 205948 kb
Host smart-3f8af5e2-586d-44ba-a187-19552b700cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681113907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.681113907
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1816076164
Short name T172
Test name
Test status
Simulation time 2009294334 ps
CPU time 8.99 seconds
Started Jun 02 02:43:01 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 205640 kb
Host smart-3b72da23-8bb8-4856-b7b4-b611c7d90d95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816076164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1816076164
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4127806511
Short name T203
Test name
Test status
Simulation time 14762020720 ps
CPU time 59.22 seconds
Started Jun 02 03:02:37 PM PDT 24
Finished Jun 02 03:03:37 PM PDT 24
Peak memory 215908 kb
Host smart-ca4d83df-88c7-4289-a841-b326628b5611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127806511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4127806511
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.890771457
Short name T281
Test name
Test status
Simulation time 1321198125 ps
CPU time 10.01 seconds
Started Jun 02 03:04:33 PM PDT 24
Finished Jun 02 03:04:44 PM PDT 24
Peak memory 214288 kb
Host smart-4ce3e5bc-e9fd-40b9-ba14-bf72e39ad659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890771457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.890771457
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3475977325
Short name T112
Test name
Test status
Simulation time 426829100 ps
CPU time 1.68 seconds
Started Jun 02 02:43:31 PM PDT 24
Finished Jun 02 02:43:33 PM PDT 24
Peak memory 214124 kb
Host smart-5b68d568-2f78-4932-ba1b-b143ace174d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475977325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3475977325
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2617934823
Short name T248
Test name
Test status
Simulation time 98517726 ps
CPU time 3.27 seconds
Started Jun 02 03:01:57 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 214276 kb
Host smart-7dd4ef0d-ea11-4c97-920f-46793fe24f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617934823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2617934823
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4264223015
Short name T200
Test name
Test status
Simulation time 1429408797 ps
CPU time 48.51 seconds
Started Jun 02 03:02:31 PM PDT 24
Finished Jun 02 03:03:20 PM PDT 24
Peak memory 216376 kb
Host smart-6f4a3672-595d-4fcb-8a2f-fb0755dc1a4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264223015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4264223015
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2100512145
Short name T117
Test name
Test status
Simulation time 245765604 ps
CPU time 15.57 seconds
Started Jun 02 03:00:50 PM PDT 24
Finished Jun 02 03:01:06 PM PDT 24
Peak memory 222596 kb
Host smart-14e26541-7474-4f7f-8a40-253dabe8acf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100512145 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2100512145
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1869936331
Short name T181
Test name
Test status
Simulation time 215264477 ps
CPU time 9.1 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:15 PM PDT 24
Peak memory 213712 kb
Host smart-3ecca742-db00-4936-8619-79019b84bdca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869936331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1869936331
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.731812768
Short name T3
Test name
Test status
Simulation time 121995845 ps
CPU time 3.1 seconds
Started Jun 02 03:02:20 PM PDT 24
Finished Jun 02 03:02:23 PM PDT 24
Peak memory 214372 kb
Host smart-d6ce1f9f-9d3e-4971-88b7-2a39f26fd05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731812768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.731812768
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3696233334
Short name T148
Test name
Test status
Simulation time 80666536 ps
CPU time 2.04 seconds
Started Jun 02 03:03:54 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 216968 kb
Host smart-caf4553f-ec35-4b68-866b-ce54973bb3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696233334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3696233334
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2403150958
Short name T145
Test name
Test status
Simulation time 101439774 ps
CPU time 3.82 seconds
Started Jun 02 03:02:01 PM PDT 24
Finished Jun 02 03:02:06 PM PDT 24
Peak memory 222560 kb
Host smart-e7b9ebd5-7927-471a-80e4-cb9059c0707d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403150958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2403150958
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1836928594
Short name T233
Test name
Test status
Simulation time 336135067 ps
CPU time 3 seconds
Started Jun 02 03:01:11 PM PDT 24
Finished Jun 02 03:01:14 PM PDT 24
Peak memory 214284 kb
Host smart-338fe918-d490-4146-a135-25757baafa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836928594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1836928594
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2230021957
Short name T53
Test name
Test status
Simulation time 5310396697 ps
CPU time 94.24 seconds
Started Jun 02 03:04:07 PM PDT 24
Finished Jun 02 03:05:42 PM PDT 24
Peak memory 215520 kb
Host smart-8031470c-10df-473a-a8ef-08b79d3cf43a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230021957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2230021957
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3653980216
Short name T44
Test name
Test status
Simulation time 1356957383 ps
CPU time 29.54 seconds
Started Jun 02 02:59:44 PM PDT 24
Finished Jun 02 03:00:14 PM PDT 24
Peak memory 235880 kb
Host smart-60842e08-fd9c-455d-953f-bbe582edaf69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653980216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3653980216
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3209768995
Short name T185
Test name
Test status
Simulation time 463576793 ps
CPU time 2.68 seconds
Started Jun 02 03:02:01 PM PDT 24
Finished Jun 02 03:02:05 PM PDT 24
Peak memory 210156 kb
Host smart-27c6b169-d736-4845-ad3f-77063fa73a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209768995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3209768995
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.794428328
Short name T128
Test name
Test status
Simulation time 533424294 ps
CPU time 3.93 seconds
Started Jun 02 03:04:48 PM PDT 24
Finished Jun 02 03:04:53 PM PDT 24
Peak memory 217832 kb
Host smart-9b0cfd2b-40fd-4055-88fc-a5c462679666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794428328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.794428328
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3723434961
Short name T55
Test name
Test status
Simulation time 420408737 ps
CPU time 4.46 seconds
Started Jun 02 03:02:00 PM PDT 24
Finished Jun 02 03:02:06 PM PDT 24
Peak memory 214576 kb
Host smart-1331ede5-832e-4b09-a944-4129e3a048f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723434961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3723434961
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2782858310
Short name T251
Test name
Test status
Simulation time 603093725 ps
CPU time 4.83 seconds
Started Jun 02 03:02:53 PM PDT 24
Finished Jun 02 03:02:58 PM PDT 24
Peak memory 222420 kb
Host smart-03a0c636-dd93-452a-9756-7e126c96f6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782858310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2782858310
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.425761334
Short name T129
Test name
Test status
Simulation time 50250388 ps
CPU time 3.72 seconds
Started Jun 02 03:03:24 PM PDT 24
Finished Jun 02 03:03:29 PM PDT 24
Peak memory 215380 kb
Host smart-fb7b525a-d2e8-49c5-837c-78b026ecff7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=425761334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.425761334
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.446765536
Short name T902
Test name
Test status
Simulation time 799384009 ps
CPU time 19.11 seconds
Started Jun 02 03:04:01 PM PDT 24
Finished Jun 02 03:04:21 PM PDT 24
Peak memory 214840 kb
Host smart-d9c3eacb-6f72-402e-8d3a-edf4a35d3ea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446765536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.446765536
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1580264966
Short name T223
Test name
Test status
Simulation time 691293449 ps
CPU time 4.99 seconds
Started Jun 02 03:03:07 PM PDT 24
Finished Jun 02 03:03:12 PM PDT 24
Peak memory 209608 kb
Host smart-6b34c964-b826-408e-ae9b-1042e2b27e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580264966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1580264966
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3935096983
Short name T176
Test name
Test status
Simulation time 1409193219 ps
CPU time 9.44 seconds
Started Jun 02 02:43:27 PM PDT 24
Finished Jun 02 02:43:38 PM PDT 24
Peak memory 214100 kb
Host smart-ca6023ac-a61f-4a11-96f3-836342c6c7b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935096983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3935096983
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1108164005
Short name T175
Test name
Test status
Simulation time 146681097 ps
CPU time 5.73 seconds
Started Jun 02 02:43:02 PM PDT 24
Finished Jun 02 02:43:09 PM PDT 24
Peak memory 213836 kb
Host smart-f5d4f31b-08d2-4295-8846-c8624632e370
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108164005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1108164005
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.94226459
Short name T147
Test name
Test status
Simulation time 58293427 ps
CPU time 2.7 seconds
Started Jun 02 03:02:00 PM PDT 24
Finished Jun 02 03:02:04 PM PDT 24
Peak memory 218204 kb
Host smart-15592936-62e1-4269-bcbf-5fb21f30ddf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94226459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.94226459
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.58538328
Short name T141
Test name
Test status
Simulation time 139396409 ps
CPU time 5.51 seconds
Started Jun 02 03:02:31 PM PDT 24
Finished Jun 02 03:02:37 PM PDT 24
Peak memory 218420 kb
Host smart-449f81e2-d039-4f32-b641-c6de8e6d0e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58538328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.58538328
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3739487496
Short name T146
Test name
Test status
Simulation time 155863578 ps
CPU time 5.99 seconds
Started Jun 02 03:00:48 PM PDT 24
Finished Jun 02 03:00:54 PM PDT 24
Peak memory 218468 kb
Host smart-af00baec-c7d2-4d67-a6c4-cb583da042a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739487496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3739487496
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.855178542
Short name T678
Test name
Test status
Simulation time 68953516 ps
CPU time 2.31 seconds
Started Jun 02 03:01:26 PM PDT 24
Finished Jun 02 03:01:29 PM PDT 24
Peak memory 214320 kb
Host smart-7fc8e895-c62f-48f7-aa10-026c557f6206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855178542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.855178542
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2828991561
Short name T308
Test name
Test status
Simulation time 2333822236 ps
CPU time 78.25 seconds
Started Jun 02 03:01:56 PM PDT 24
Finished Jun 02 03:03:15 PM PDT 24
Peak memory 216904 kb
Host smart-187b07fc-802f-4ec0-b3a7-ede2f2564954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828991561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2828991561
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1610259752
Short name T245
Test name
Test status
Simulation time 701439458 ps
CPU time 7.18 seconds
Started Jun 02 03:02:10 PM PDT 24
Finished Jun 02 03:02:18 PM PDT 24
Peak memory 222484 kb
Host smart-aecdddbf-440d-4e05-af58-367ff11af19c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610259752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1610259752
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3470277128
Short name T222
Test name
Test status
Simulation time 134034188 ps
CPU time 4.55 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:46 PM PDT 24
Peak memory 214296 kb
Host smart-eac2f3ed-ad53-48f0-a50a-2c40fb8fc840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470277128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3470277128
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.803113406
Short name T218
Test name
Test status
Simulation time 447931927 ps
CPU time 18.07 seconds
Started Jun 02 03:03:56 PM PDT 24
Finished Jun 02 03:04:15 PM PDT 24
Peak memory 222564 kb
Host smart-a4760fa4-20f7-405f-a4a4-7a7804d929e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803113406 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.803113406
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.326876933
Short name T62
Test name
Test status
Simulation time 94593914 ps
CPU time 2.61 seconds
Started Jun 02 03:02:30 PM PDT 24
Finished Jun 02 03:02:33 PM PDT 24
Peak memory 209912 kb
Host smart-84320024-5cfd-4d5f-81d4-483919576538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326876933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.326876933
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1277518156
Short name T132
Test name
Test status
Simulation time 96131607 ps
CPU time 3.28 seconds
Started Jun 02 03:03:24 PM PDT 24
Finished Jun 02 03:03:28 PM PDT 24
Peak memory 218524 kb
Host smart-83143356-38ed-4ce6-9464-ab7c80b14be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277518156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1277518156
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3931416402
Short name T142
Test name
Test status
Simulation time 250823681 ps
CPU time 3.75 seconds
Started Jun 02 03:03:13 PM PDT 24
Finished Jun 02 03:03:18 PM PDT 24
Peak memory 221380 kb
Host smart-c1e10ab8-bff7-4110-8fba-572d209c30f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931416402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3931416402
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1080245377
Short name T144
Test name
Test status
Simulation time 150202346 ps
CPU time 3.31 seconds
Started Jun 02 03:04:33 PM PDT 24
Finished Jun 02 03:04:37 PM PDT 24
Peak memory 218216 kb
Host smart-ff105cbd-8878-48b5-b1c2-5786451136b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080245377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1080245377
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2825217284
Short name T249
Test name
Test status
Simulation time 235202240 ps
CPU time 4.68 seconds
Started Jun 02 03:01:53 PM PDT 24
Finished Jun 02 03:01:58 PM PDT 24
Peak memory 214580 kb
Host smart-fd28ab44-81d3-4fa1-8758-dd3e1b609293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825217284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2825217284
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3646260651
Short name T353
Test name
Test status
Simulation time 1709325033 ps
CPU time 18.01 seconds
Started Jun 02 03:02:00 PM PDT 24
Finished Jun 02 03:02:19 PM PDT 24
Peak memory 214220 kb
Host smart-807d20f4-e61e-4ce2-bf8f-d86af53b16ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646260651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3646260651
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.448113939
Short name T214
Test name
Test status
Simulation time 912860157 ps
CPU time 12.07 seconds
Started Jun 02 03:02:53 PM PDT 24
Finished Jun 02 03:03:06 PM PDT 24
Peak memory 219648 kb
Host smart-f26d5a0f-f1b9-4b93-8ab9-c1c6f8535ea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448113939 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.448113939
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2220703679
Short name T344
Test name
Test status
Simulation time 3028763318 ps
CPU time 40.38 seconds
Started Jun 02 03:02:58 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 208928 kb
Host smart-76679739-458b-4745-8738-fbc5c72f986b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220703679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2220703679
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.165271694
Short name T239
Test name
Test status
Simulation time 123944918 ps
CPU time 6.66 seconds
Started Jun 02 03:04:25 PM PDT 24
Finished Jun 02 03:04:33 PM PDT 24
Peak memory 214228 kb
Host smart-5ea1a312-6c02-441f-9df4-307a095ef400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165271694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.165271694
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_random.3339392830
Short name T82
Test name
Test status
Simulation time 2604331368 ps
CPU time 20.07 seconds
Started Jun 02 03:04:48 PM PDT 24
Finished Jun 02 03:05:09 PM PDT 24
Peak memory 216224 kb
Host smart-49f8f4b4-1261-447d-9710-28eda0673ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339392830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3339392830
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.878061041
Short name T373
Test name
Test status
Simulation time 199795378 ps
CPU time 11.07 seconds
Started Jun 02 03:00:36 PM PDT 24
Finished Jun 02 03:00:47 PM PDT 24
Peak memory 214552 kb
Host smart-cc245b7d-08d0-4095-83c2-7b36ee1db095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=878061041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.878061041
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2155300777
Short name T220
Test name
Test status
Simulation time 245158269 ps
CPU time 3.75 seconds
Started Jun 02 03:00:49 PM PDT 24
Finished Jun 02 03:00:53 PM PDT 24
Peak memory 208988 kb
Host smart-09f7d4a7-55e5-4e0e-b545-db90222f5c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155300777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2155300777
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3930348901
Short name T184
Test name
Test status
Simulation time 145269034 ps
CPU time 3.89 seconds
Started Jun 02 02:42:54 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 213800 kb
Host smart-d87f6a15-e873-4053-a38f-57524a53000a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930348901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3930348901
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.4032067094
Short name T174
Test name
Test status
Simulation time 183721168 ps
CPU time 2.87 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 205916 kb
Host smart-3e44a573-58ff-4ee8-9aa7-81bce65aeaf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032067094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.4032067094
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.803703683
Short name T182
Test name
Test status
Simulation time 313076907 ps
CPU time 9.56 seconds
Started Jun 02 02:43:21 PM PDT 24
Finished Jun 02 02:43:31 PM PDT 24
Peak memory 215336 kb
Host smart-970378b0-4001-4aea-b6a3-c45deada58d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803703683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.803703683
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.4256242969
Short name T170
Test name
Test status
Simulation time 176199175 ps
CPU time 2.72 seconds
Started Jun 02 02:43:11 PM PDT 24
Finished Jun 02 02:43:14 PM PDT 24
Peak memory 213820 kb
Host smart-7cec876c-e137-4cc0-8a59-8a037a201ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256242969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.4256242969
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1848538955
Short name T152
Test name
Test status
Simulation time 513816957 ps
CPU time 10.01 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:02:06 PM PDT 24
Peak memory 222480 kb
Host smart-00af2943-facb-45c4-81ab-7765a5cf9334
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848538955 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1848538955
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.235090375
Short name T33
Test name
Test status
Simulation time 206796333 ps
CPU time 4 seconds
Started Jun 02 03:03:04 PM PDT 24
Finished Jun 02 03:03:08 PM PDT 24
Peak memory 210060 kb
Host smart-1d3f4dd2-d247-4300-aabf-29c236ffd66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235090375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.235090375
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3801296668
Short name T149
Test name
Test status
Simulation time 620749384 ps
CPU time 4.63 seconds
Started Jun 02 03:02:47 PM PDT 24
Finished Jun 02 03:02:52 PM PDT 24
Peak memory 217808 kb
Host smart-fa3d5427-48a2-4f02-9a1e-5cef8f05461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801296668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3801296668
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3730948545
Short name T143
Test name
Test status
Simulation time 372961653 ps
CPU time 2.56 seconds
Started Jun 02 03:04:44 PM PDT 24
Finished Jun 02 03:04:48 PM PDT 24
Peak memory 217512 kb
Host smart-45cc1294-6576-46b8-8588-28d51cd1b1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730948545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3730948545
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3064900528
Short name T868
Test name
Test status
Simulation time 36694726 ps
CPU time 2.28 seconds
Started Jun 02 02:59:14 PM PDT 24
Finished Jun 02 02:59:17 PM PDT 24
Peak memory 214308 kb
Host smart-4e138234-8275-4189-bbaa-e09b34602a41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064900528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3064900528
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.179307406
Short name T309
Test name
Test status
Simulation time 211664833 ps
CPU time 4.64 seconds
Started Jun 02 02:59:22 PM PDT 24
Finished Jun 02 02:59:27 PM PDT 24
Peak memory 222580 kb
Host smart-403b6f0e-b92a-4d80-97f2-33251de0b225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179307406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.179307406
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.959348147
Short name T41
Test name
Test status
Simulation time 718455648 ps
CPU time 7.36 seconds
Started Jun 02 02:59:38 PM PDT 24
Finished Jun 02 02:59:46 PM PDT 24
Peak memory 209464 kb
Host smart-56d85da0-c49f-4855-9fd3-a8dd5b0206b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959348147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.959348147
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.932542344
Short name T347
Test name
Test status
Simulation time 33217202 ps
CPU time 1.74 seconds
Started Jun 02 02:59:31 PM PDT 24
Finished Jun 02 02:59:33 PM PDT 24
Peak memory 206888 kb
Host smart-bf07b769-2046-41bc-87e6-e22747c6bba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932542344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.932542344
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2385882851
Short name T160
Test name
Test status
Simulation time 2915518309 ps
CPU time 31.02 seconds
Started Jun 02 03:01:11 PM PDT 24
Finished Jun 02 03:01:42 PM PDT 24
Peak memory 222596 kb
Host smart-9d652258-e576-4c13-a361-6d3c21e837b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385882851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2385882851
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3066799802
Short name T621
Test name
Test status
Simulation time 228094508 ps
CPU time 4.04 seconds
Started Jun 02 03:01:16 PM PDT 24
Finished Jun 02 03:01:20 PM PDT 24
Peak memory 214516 kb
Host smart-2442df09-f51f-440a-8f69-efb99171dd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066799802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3066799802
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.606874232
Short name T481
Test name
Test status
Simulation time 36500257 ps
CPU time 1.94 seconds
Started Jun 02 03:01:16 PM PDT 24
Finished Jun 02 03:01:19 PM PDT 24
Peak memory 209384 kb
Host smart-44f60ba0-3140-47c7-9999-1568a1f880ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606874232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.606874232
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.224064445
Short name T201
Test name
Test status
Simulation time 90085616 ps
CPU time 3.61 seconds
Started Jun 02 03:01:24 PM PDT 24
Finished Jun 02 03:01:29 PM PDT 24
Peak memory 221548 kb
Host smart-ef791a62-5e21-40e4-897a-c1dcf0bdca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224064445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.224064445
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.730876944
Short name T216
Test name
Test status
Simulation time 454448601 ps
CPU time 4.72 seconds
Started Jun 02 03:01:37 PM PDT 24
Finished Jun 02 03:01:42 PM PDT 24
Peak memory 220488 kb
Host smart-786ee2f5-5b98-4346-b1ae-fdbaba36469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730876944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.730876944
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.546735968
Short name T211
Test name
Test status
Simulation time 182800446 ps
CPU time 5.54 seconds
Started Jun 02 03:01:58 PM PDT 24
Finished Jun 02 03:02:05 PM PDT 24
Peak memory 222360 kb
Host smart-77d29461-79b3-46a5-a40c-d52a0ca6a172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546735968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.546735968
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3766427480
Short name T302
Test name
Test status
Simulation time 56568332 ps
CPU time 3.09 seconds
Started Jun 02 03:02:08 PM PDT 24
Finished Jun 02 03:02:12 PM PDT 24
Peak memory 207516 kb
Host smart-b960f98d-1437-4db1-aebc-46105be7bafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766427480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3766427480
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3089825046
Short name T224
Test name
Test status
Simulation time 347865216 ps
CPU time 4.46 seconds
Started Jun 02 03:02:25 PM PDT 24
Finished Jun 02 03:02:30 PM PDT 24
Peak memory 214344 kb
Host smart-0477619a-c803-4c54-9a76-8201996c530d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089825046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3089825046
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1492229036
Short name T350
Test name
Test status
Simulation time 609652519 ps
CPU time 4.85 seconds
Started Jun 02 03:02:42 PM PDT 24
Finished Jun 02 03:02:47 PM PDT 24
Peak memory 214268 kb
Host smart-02050cea-7458-4b41-8d3f-d06d1f2ab753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492229036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1492229036
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2092470869
Short name T876
Test name
Test status
Simulation time 1582317114 ps
CPU time 39.26 seconds
Started Jun 02 03:02:46 PM PDT 24
Finished Jun 02 03:03:26 PM PDT 24
Peak memory 215788 kb
Host smart-45e78d8e-8e96-4655-8686-36092a4f8a43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092470869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2092470869
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1020742217
Short name T878
Test name
Test status
Simulation time 99324598 ps
CPU time 2.06 seconds
Started Jun 02 03:02:52 PM PDT 24
Finished Jun 02 03:02:54 PM PDT 24
Peak memory 208564 kb
Host smart-8aa36605-2a3f-4759-9505-dd443144c6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020742217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1020742217
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1278899326
Short name T329
Test name
Test status
Simulation time 215317575 ps
CPU time 11.75 seconds
Started Jun 02 03:03:11 PM PDT 24
Finished Jun 02 03:03:24 PM PDT 24
Peak memory 214252 kb
Host smart-34bf9a62-af7e-4456-88c4-00638012c447
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1278899326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1278899326
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.901164208
Short name T250
Test name
Test status
Simulation time 157097974 ps
CPU time 3.68 seconds
Started Jun 02 03:03:12 PM PDT 24
Finished Jun 02 03:03:16 PM PDT 24
Peak memory 214292 kb
Host smart-195dac5c-533f-40de-a0de-53799c67ae88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901164208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.901164208
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1064981044
Short name T316
Test name
Test status
Simulation time 42875012 ps
CPU time 2.98 seconds
Started Jun 02 03:04:17 PM PDT 24
Finished Jun 02 03:04:21 PM PDT 24
Peak memory 214320 kb
Host smart-6756f745-13f2-442c-9773-7f77d52ee9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064981044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1064981044
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2958718393
Short name T1068
Test name
Test status
Simulation time 609913070 ps
CPU time 12.95 seconds
Started Jun 02 02:42:58 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 205672 kb
Host smart-e6d3b849-934b-4cd7-b2b3-ab361601f580
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958718393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
958718393
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2269380755
Short name T983
Test name
Test status
Simulation time 2692113946 ps
CPU time 16.25 seconds
Started Jun 02 02:42:56 PM PDT 24
Finished Jun 02 02:43:13 PM PDT 24
Peak memory 205584 kb
Host smart-18013416-36dd-4e1b-affd-d8cc9a585ac9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269380755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
269380755
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3071034229
Short name T1069
Test name
Test status
Simulation time 72461054 ps
CPU time 1.62 seconds
Started Jun 02 02:42:57 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 205540 kb
Host smart-4a36cb0d-8f48-4bed-85c4-d90b88686d6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071034229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
071034229
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.933655994
Short name T1000
Test name
Test status
Simulation time 26623551 ps
CPU time 1.78 seconds
Started Jun 02 02:43:06 PM PDT 24
Finished Jun 02 02:43:09 PM PDT 24
Peak memory 222064 kb
Host smart-b64b399f-dc8c-4a56-b4ba-2a742f8fc5aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933655994 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.933655994
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1548118896
Short name T987
Test name
Test status
Simulation time 116951468 ps
CPU time 1.57 seconds
Started Jun 02 02:42:57 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 205632 kb
Host smart-7458852e-a902-44f4-8052-821089a0a174
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548118896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1548118896
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2943432371
Short name T1054
Test name
Test status
Simulation time 16365217 ps
CPU time 0.91 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:06 PM PDT 24
Peak memory 205444 kb
Host smart-a73ce191-ed14-4b89-a0ef-d164d0a290be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943432371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2943432371
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.983871785
Short name T944
Test name
Test status
Simulation time 69860551 ps
CPU time 1.5 seconds
Started Jun 02 02:42:59 PM PDT 24
Finished Jun 02 02:43:01 PM PDT 24
Peak memory 205668 kb
Host smart-3758b92f-4535-400a-8143-c0941c28a918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983871785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.983871785
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3413368013
Short name T945
Test name
Test status
Simulation time 155298022 ps
CPU time 3.55 seconds
Started Jun 02 02:42:56 PM PDT 24
Finished Jun 02 02:43:01 PM PDT 24
Peak memory 214028 kb
Host smart-d7ed5088-d39c-4664-b583-94a087c76af5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413368013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3413368013
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3215987448
Short name T1006
Test name
Test status
Simulation time 1411381998 ps
CPU time 4.98 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:10 PM PDT 24
Peak memory 213776 kb
Host smart-4d0bacfd-7f0b-47df-abed-e28c52b2fdc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215987448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3215987448
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.696313887
Short name T136
Test name
Test status
Simulation time 1821013721 ps
CPU time 10.92 seconds
Started Jun 02 02:43:01 PM PDT 24
Finished Jun 02 02:43:13 PM PDT 24
Peak memory 205744 kb
Host smart-a2be48b8-b411-4f9f-88dc-280522d61276
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696313887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.696313887
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3885759363
Short name T1044
Test name
Test status
Simulation time 964234285 ps
CPU time 13.3 seconds
Started Jun 02 02:43:10 PM PDT 24
Finished Jun 02 02:43:24 PM PDT 24
Peak memory 205576 kb
Host smart-4866af4f-132b-4094-82c9-17e3c4c7d071
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885759363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
885759363
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3234909997
Short name T989
Test name
Test status
Simulation time 36945557 ps
CPU time 1 seconds
Started Jun 02 02:42:58 PM PDT 24
Finished Jun 02 02:43:00 PM PDT 24
Peak memory 205396 kb
Host smart-573c7828-bf48-4eef-a6fb-0f27206ea5a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234909997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
234909997
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3126448857
Short name T1075
Test name
Test status
Simulation time 74163209 ps
CPU time 1.12 seconds
Started Jun 02 02:43:06 PM PDT 24
Finished Jun 02 02:43:08 PM PDT 24
Peak memory 205660 kb
Host smart-6dadbacb-9824-4351-ac8e-2784ad6a05fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126448857 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3126448857
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2913990829
Short name T990
Test name
Test status
Simulation time 158919470 ps
CPU time 1.23 seconds
Started Jun 02 02:43:01 PM PDT 24
Finished Jun 02 02:43:03 PM PDT 24
Peak memory 205656 kb
Host smart-a420c42e-87ac-4526-9c19-b6736c137e35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913990829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2913990829
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1783528073
Short name T917
Test name
Test status
Simulation time 31368026 ps
CPU time 0.74 seconds
Started Jun 02 02:43:00 PM PDT 24
Finished Jun 02 02:43:01 PM PDT 24
Peak memory 205296 kb
Host smart-93bafb07-254e-4331-ac16-5b13af415f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783528073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1783528073
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1716636245
Short name T1004
Test name
Test status
Simulation time 209642276 ps
CPU time 1.87 seconds
Started Jun 02 02:43:02 PM PDT 24
Finished Jun 02 02:43:05 PM PDT 24
Peak memory 205612 kb
Host smart-9c25ba47-091c-42a8-ba5e-0651cdf36c0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716636245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1716636245
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3165710673
Short name T116
Test name
Test status
Simulation time 578956659 ps
CPU time 1.59 seconds
Started Jun 02 02:43:02 PM PDT 24
Finished Jun 02 02:43:04 PM PDT 24
Peak memory 214192 kb
Host smart-485d2b99-73f4-4ec0-8001-4651886d72b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165710673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3165710673
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4118445548
Short name T1057
Test name
Test status
Simulation time 248851025 ps
CPU time 3.89 seconds
Started Jun 02 02:43:07 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 214124 kb
Host smart-598248ed-091a-4680-ae8a-618c60a325f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118445548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.4118445548
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1886740730
Short name T1048
Test name
Test status
Simulation time 143968347 ps
CPU time 2.31 seconds
Started Jun 02 02:43:07 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 213844 kb
Host smart-55b8ebf1-8c1c-4eac-9886-06f3d6197248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886740730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1886740730
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3153098373
Short name T958
Test name
Test status
Simulation time 110914824 ps
CPU time 4.51 seconds
Started Jun 02 02:43:03 PM PDT 24
Finished Jun 02 02:43:08 PM PDT 24
Peak memory 213736 kb
Host smart-d6693ecb-9e70-4013-a540-4adb6fea32c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153098373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3153098373
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2127120256
Short name T1063
Test name
Test status
Simulation time 57068362 ps
CPU time 1.2 seconds
Started Jun 02 02:43:11 PM PDT 24
Finished Jun 02 02:43:13 PM PDT 24
Peak memory 205556 kb
Host smart-0f03e250-37a9-41a8-ab89-2032326ae2d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127120256 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2127120256
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3809187815
Short name T938
Test name
Test status
Simulation time 33683348 ps
CPU time 1.21 seconds
Started Jun 02 02:43:09 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 205524 kb
Host smart-84a0e697-5924-4ccc-8dc8-44b9ffd6d491
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809187815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3809187815
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1457901986
Short name T952
Test name
Test status
Simulation time 25833911 ps
CPU time 0.79 seconds
Started Jun 02 02:43:30 PM PDT 24
Finished Jun 02 02:43:31 PM PDT 24
Peak memory 205312 kb
Host smart-fa353d85-a659-4c95-b91e-191790abd4eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457901986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1457901986
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.64105151
Short name T1065
Test name
Test status
Simulation time 499428285 ps
CPU time 2.71 seconds
Started Jun 02 02:43:21 PM PDT 24
Finished Jun 02 02:43:24 PM PDT 24
Peak memory 205576 kb
Host smart-332c5407-2068-41dd-af46-0e1c7fb60090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64105151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sam
e_csr_outstanding.64105151
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3694369010
Short name T962
Test name
Test status
Simulation time 275618266 ps
CPU time 1.78 seconds
Started Jun 02 02:43:20 PM PDT 24
Finished Jun 02 02:43:22 PM PDT 24
Peak memory 214108 kb
Host smart-289e98e4-c999-43bd-952b-f64000848e5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694369010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3694369010
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3980889663
Short name T108
Test name
Test status
Simulation time 214098242 ps
CPU time 5.05 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:14 PM PDT 24
Peak memory 214212 kb
Host smart-b9075086-aced-48ae-8301-0102cf0cead7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980889663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3980889663
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1598265118
Short name T960
Test name
Test status
Simulation time 326442594 ps
CPU time 6.09 seconds
Started Jun 02 02:43:23 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 215932 kb
Host smart-29fad0d1-c86c-4078-ad9c-f7d43ab2f492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598265118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1598265118
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3887531846
Short name T1020
Test name
Test status
Simulation time 103271092 ps
CPU time 3.17 seconds
Started Jun 02 02:43:25 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 213828 kb
Host smart-05a50232-4aa2-461f-81e2-85ab455a1e82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887531846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3887531846
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3876300759
Short name T1027
Test name
Test status
Simulation time 287918771 ps
CPU time 1.82 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 213856 kb
Host smart-6dd16a53-67ad-4c99-8ed5-33bdf156a016
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876300759 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3876300759
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1344328104
Short name T1022
Test name
Test status
Simulation time 85934069 ps
CPU time 1.41 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 203672 kb
Host smart-6a18c336-f2b3-4fb7-998c-24a9516f7eca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344328104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1344328104
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2791253364
Short name T1008
Test name
Test status
Simulation time 11038976 ps
CPU time 0.88 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 203128 kb
Host smart-ae494e8f-7a33-42bd-8f85-b76ad1c4d5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791253364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2791253364
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2644597197
Short name T1038
Test name
Test status
Simulation time 282097889 ps
CPU time 2.17 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 205100 kb
Host smart-b94863fc-c07f-4eb6-9c6f-beb0e111addc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644597197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2644597197
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1028586
Short name T107
Test name
Test status
Simulation time 396106807 ps
CPU time 2.42 seconds
Started Jun 02 02:43:07 PM PDT 24
Finished Jun 02 02:43:10 PM PDT 24
Peak memory 214212 kb
Host smart-b3c0aea7-cf62-4b6c-be24-758af28467ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_
reg_errors.1028586
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2652478826
Short name T1079
Test name
Test status
Simulation time 95232464 ps
CPU time 4.44 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:13 PM PDT 24
Peak memory 214268 kb
Host smart-5e15566e-e7b4-41a7-af83-61fb91feb59a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652478826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2652478826
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2610748636
Short name T1056
Test name
Test status
Simulation time 89657705 ps
CPU time 3.27 seconds
Started Jun 02 02:43:28 PM PDT 24
Finished Jun 02 02:43:32 PM PDT 24
Peak memory 216956 kb
Host smart-928c963e-3572-4774-aba4-6a44511f7fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610748636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2610748636
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1826286476
Short name T150
Test name
Test status
Simulation time 46566391 ps
CPU time 1.61 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:22 PM PDT 24
Peak memory 211076 kb
Host smart-24361394-f024-4a05-87b3-4cf2aa61797e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826286476 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1826286476
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3609953485
Short name T1067
Test name
Test status
Simulation time 15806968 ps
CPU time 0.96 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 202724 kb
Host smart-15f5f0a4-20dc-4338-851e-fce37b91a3fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609953485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3609953485
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1108543825
Short name T999
Test name
Test status
Simulation time 11975418 ps
CPU time 0.82 seconds
Started Jun 02 02:43:10 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 205308 kb
Host smart-c1457fab-a125-4b80-ad58-ab6618efca66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108543825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1108543825
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2851234831
Short name T1071
Test name
Test status
Simulation time 416301982 ps
CPU time 2.65 seconds
Started Jun 02 02:43:15 PM PDT 24
Finished Jun 02 02:43:18 PM PDT 24
Peak memory 205568 kb
Host smart-98a9c0bb-f992-44d2-82b5-0a50a84eccca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851234831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2851234831
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2048130848
Short name T949
Test name
Test status
Simulation time 290344592 ps
CPU time 2.84 seconds
Started Jun 02 02:43:07 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 214240 kb
Host smart-cd8efd34-7b3c-476f-b016-45eeec5a98eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048130848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2048130848
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.819850785
Short name T948
Test name
Test status
Simulation time 318774444 ps
CPU time 4.05 seconds
Started Jun 02 02:43:07 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 220524 kb
Host smart-f74fa5c6-1c57-4de2-abc6-3f72da3ef8c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819850785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.819850785
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2228559321
Short name T929
Test name
Test status
Simulation time 419327436 ps
CPU time 3.97 seconds
Started Jun 02 02:43:11 PM PDT 24
Finished Jun 02 02:43:15 PM PDT 24
Peak memory 213860 kb
Host smart-7a7b042a-b395-4b74-9daf-62a54380bc60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228559321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2228559321
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3117131466
Short name T166
Test name
Test status
Simulation time 233434198 ps
CPU time 2.8 seconds
Started Jun 02 02:43:15 PM PDT 24
Finished Jun 02 02:43:18 PM PDT 24
Peak memory 213780 kb
Host smart-668f7897-571f-455a-8c3d-11e0901b2294
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117131466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3117131466
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4147961390
Short name T1032
Test name
Test status
Simulation time 102631731 ps
CPU time 1.21 seconds
Started Jun 02 02:43:23 PM PDT 24
Finished Jun 02 02:43:24 PM PDT 24
Peak memory 213948 kb
Host smart-df6a1932-37a9-401e-81fa-5dfae21edb7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147961390 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4147961390
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.204810822
Short name T975
Test name
Test status
Simulation time 81981193 ps
CPU time 0.91 seconds
Started Jun 02 02:43:23 PM PDT 24
Finished Jun 02 02:43:24 PM PDT 24
Peak memory 205388 kb
Host smart-eedb3334-272a-4137-ba9a-d31a60520157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204810822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.204810822
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.929410438
Short name T979
Test name
Test status
Simulation time 10285479 ps
CPU time 0.72 seconds
Started Jun 02 02:43:23 PM PDT 24
Finished Jun 02 02:43:25 PM PDT 24
Peak memory 205236 kb
Host smart-00a9f4d4-667b-4be2-b7ca-048bf8090ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929410438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.929410438
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1234739940
Short name T138
Test name
Test status
Simulation time 64741724 ps
CPU time 1.58 seconds
Started Jun 02 02:43:23 PM PDT 24
Finished Jun 02 02:43:25 PM PDT 24
Peak memory 205588 kb
Host smart-b2ecc375-e09f-4c11-b62d-eec5ec4b3f10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234739940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1234739940
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.590285866
Short name T1017
Test name
Test status
Simulation time 304865604 ps
CPU time 3.13 seconds
Started Jun 02 02:43:21 PM PDT 24
Finished Jun 02 02:43:25 PM PDT 24
Peak memory 214188 kb
Host smart-ba69cfb6-1615-471d-bbd4-1290cdf85b80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590285866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.590285866
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2179191338
Short name T965
Test name
Test status
Simulation time 883538714 ps
CPU time 8.15 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:36 PM PDT 24
Peak memory 213956 kb
Host smart-83e3aa7d-b5fe-4e52-b13f-48d71015d8c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179191338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2179191338
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.864210638
Short name T972
Test name
Test status
Simulation time 378564038 ps
CPU time 3.04 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 213788 kb
Host smart-c45c50ac-975b-4fdf-8028-d26ed42271db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864210638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.864210638
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.359221689
Short name T163
Test name
Test status
Simulation time 91160527 ps
CPU time 1.65 seconds
Started Jun 02 02:43:31 PM PDT 24
Finished Jun 02 02:43:33 PM PDT 24
Peak memory 213868 kb
Host smart-7d4fa924-4300-4b1f-98fe-71c59c4aab66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359221689 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.359221689
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3888147776
Short name T135
Test name
Test status
Simulation time 25442157 ps
CPU time 1.29 seconds
Started Jun 02 02:43:32 PM PDT 24
Finished Jun 02 02:43:34 PM PDT 24
Peak memory 205560 kb
Host smart-facba4ba-7f59-4c7b-b42a-53743c9551b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888147776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3888147776
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1950686821
Short name T1078
Test name
Test status
Simulation time 32495600 ps
CPU time 0.82 seconds
Started Jun 02 02:43:25 PM PDT 24
Finished Jun 02 02:43:27 PM PDT 24
Peak memory 205260 kb
Host smart-e3f7167b-d184-43b2-afa7-9f6014d3350f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950686821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1950686821
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1564396737
Short name T1039
Test name
Test status
Simulation time 34826709 ps
CPU time 1.93 seconds
Started Jun 02 02:43:29 PM PDT 24
Finished Jun 02 02:43:32 PM PDT 24
Peak memory 205524 kb
Host smart-2c2f5439-4d78-440c-abe2-45a666308a5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564396737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1564396737
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.684999877
Short name T1073
Test name
Test status
Simulation time 650257964 ps
CPU time 4.97 seconds
Started Jun 02 02:43:25 PM PDT 24
Finished Jun 02 02:43:32 PM PDT 24
Peak memory 214112 kb
Host smart-dfd76580-c4de-423f-88c7-928c61804897
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684999877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.684999877
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3930392537
Short name T1029
Test name
Test status
Simulation time 3265420307 ps
CPU time 7.52 seconds
Started Jun 02 02:43:35 PM PDT 24
Finished Jun 02 02:43:44 PM PDT 24
Peak memory 214396 kb
Host smart-70c135f0-dbc1-4e30-a98a-ee1af18c3bb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930392537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3930392537
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1328745675
Short name T1016
Test name
Test status
Simulation time 103132687 ps
CPU time 3.9 seconds
Started Jun 02 02:43:18 PM PDT 24
Finished Jun 02 02:43:23 PM PDT 24
Peak memory 213764 kb
Host smart-2cab9191-2bc4-42f2-a560-1300eb82e0ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328745675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1328745675
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.4060420984
Short name T1037
Test name
Test status
Simulation time 401604138 ps
CPU time 1.87 seconds
Started Jun 02 02:43:23 PM PDT 24
Finished Jun 02 02:43:26 PM PDT 24
Peak memory 213836 kb
Host smart-3ad86875-ee01-4c36-b4f2-4bbab2685cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060420984 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.4060420984
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3771480994
Short name T137
Test name
Test status
Simulation time 34666780 ps
CPU time 1.18 seconds
Started Jun 02 02:43:27 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 205576 kb
Host smart-880199a1-5ac4-44c7-9c60-ebefe28f4b72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771480994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3771480994
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2021158596
Short name T1046
Test name
Test status
Simulation time 12193113 ps
CPU time 0.89 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:28 PM PDT 24
Peak memory 205316 kb
Host smart-c600b937-0fb4-4d6b-8f43-f020d75a5c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021158596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2021158596
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.531194272
Short name T1066
Test name
Test status
Simulation time 163049871 ps
CPU time 2.62 seconds
Started Jun 02 02:43:27 PM PDT 24
Finished Jun 02 02:43:31 PM PDT 24
Peak memory 205644 kb
Host smart-fc88c8c5-d43e-4753-9cf6-2ec8c4e893d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531194272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.531194272
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2457530559
Short name T1043
Test name
Test status
Simulation time 1583033520 ps
CPU time 10.04 seconds
Started Jun 02 02:43:19 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 214132 kb
Host smart-e2d0bd17-b804-4c04-836f-c71e8b67a8fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457530559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2457530559
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2721917487
Short name T157
Test name
Test status
Simulation time 200322488 ps
CPU time 3.3 seconds
Started Jun 02 02:43:29 PM PDT 24
Finished Jun 02 02:43:33 PM PDT 24
Peak memory 212860 kb
Host smart-2b35c84f-0e90-48e1-a070-bcd7aae392e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721917487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2721917487
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2568099553
Short name T973
Test name
Test status
Simulation time 33291241 ps
CPU time 1.79 seconds
Started Jun 02 02:43:27 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 213900 kb
Host smart-ad9d4a9a-a15a-45bf-8fc1-17f74f33de0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568099553 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2568099553
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2891100611
Short name T139
Test name
Test status
Simulation time 11276910 ps
CPU time 1.02 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 205400 kb
Host smart-605d2bbd-4879-412d-8402-19c3be37c90a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891100611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2891100611
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3912754819
Short name T942
Test name
Test status
Simulation time 41756158 ps
CPU time 0.79 seconds
Started Jun 02 02:43:27 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 205276 kb
Host smart-8c256bff-b70f-40cc-b2f7-db1cf237f2c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912754819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3912754819
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1887685376
Short name T964
Test name
Test status
Simulation time 84441695 ps
CPU time 2.13 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 205496 kb
Host smart-c4197716-22ea-4d23-bc1f-5b5aee3e5e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887685376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1887685376
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3777780948
Short name T1026
Test name
Test status
Simulation time 189771701 ps
CPU time 2.87 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:31 PM PDT 24
Peak memory 214168 kb
Host smart-10e0b135-4ffa-4540-9eb6-6fa38f88e0cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777780948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3777780948
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1959162991
Short name T1010
Test name
Test status
Simulation time 357978432 ps
CPU time 9.34 seconds
Started Jun 02 02:43:25 PM PDT 24
Finished Jun 02 02:43:36 PM PDT 24
Peak memory 214164 kb
Host smart-0bb6f703-0b75-4885-a773-5c3a24eb147c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959162991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1959162991
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2894452269
Short name T993
Test name
Test status
Simulation time 96271482 ps
CPU time 2.56 seconds
Started Jun 02 02:43:30 PM PDT 24
Finished Jun 02 02:43:34 PM PDT 24
Peak memory 213772 kb
Host smart-01486714-2d4c-4496-a5b8-7b054d051005
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894452269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2894452269
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.838273709
Short name T939
Test name
Test status
Simulation time 253598692 ps
CPU time 2.79 seconds
Started Jun 02 02:43:21 PM PDT 24
Finished Jun 02 02:43:25 PM PDT 24
Peak memory 213844 kb
Host smart-e74dbfd2-6012-4896-9333-e9b60cf4184f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838273709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.838273709
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.52301498
Short name T927
Test name
Test status
Simulation time 106560323 ps
CPU time 2.47 seconds
Started Jun 02 02:43:23 PM PDT 24
Finished Jun 02 02:43:26 PM PDT 24
Peak memory 213824 kb
Host smart-7a1d5a6a-70d0-41e7-b1b8-71a1e19f80c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52301498 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.52301498
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2794004375
Short name T968
Test name
Test status
Simulation time 56481744 ps
CPU time 1.17 seconds
Started Jun 02 02:43:30 PM PDT 24
Finished Jun 02 02:43:32 PM PDT 24
Peak memory 205548 kb
Host smart-10a9d162-e079-4bbe-991e-95ca6dceb628
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794004375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2794004375
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2320870510
Short name T1003
Test name
Test status
Simulation time 10229039 ps
CPU time 0.9 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 205248 kb
Host smart-a74f9031-7acc-43ac-8840-b07f00d5193b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320870510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2320870510
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3197424107
Short name T953
Test name
Test status
Simulation time 123995981 ps
CPU time 3.16 seconds
Started Jun 02 02:43:22 PM PDT 24
Finished Jun 02 02:43:26 PM PDT 24
Peak memory 205852 kb
Host smart-3b642f9e-15ac-49a6-b8a8-778fb886de03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197424107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3197424107
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1309854186
Short name T1064
Test name
Test status
Simulation time 243138303 ps
CPU time 3.61 seconds
Started Jun 02 02:43:18 PM PDT 24
Finished Jun 02 02:43:22 PM PDT 24
Peak memory 214200 kb
Host smart-ce68cd98-dc12-40d8-8682-aa5d7337854e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309854186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1309854186
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2944903751
Short name T946
Test name
Test status
Simulation time 579757472 ps
CPU time 7.72 seconds
Started Jun 02 02:43:24 PM PDT 24
Finished Jun 02 02:43:33 PM PDT 24
Peak memory 220364 kb
Host smart-efc9bedc-1a9f-4c10-9af9-702d4a10471f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944903751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2944903751
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.395054198
Short name T981
Test name
Test status
Simulation time 92006202 ps
CPU time 1.75 seconds
Started Jun 02 02:43:25 PM PDT 24
Finished Jun 02 02:43:27 PM PDT 24
Peak memory 221540 kb
Host smart-ec882be7-0550-4835-beb6-edfbf6721198
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395054198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.395054198
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3453451627
Short name T165
Test name
Test status
Simulation time 505451530 ps
CPU time 6.65 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:34 PM PDT 24
Peak memory 213872 kb
Host smart-0616f169-e83d-4666-96f1-3ae85e0fac0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453451627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3453451627
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4292396932
Short name T1034
Test name
Test status
Simulation time 49309466 ps
CPU time 1.09 seconds
Started Jun 02 02:44:37 PM PDT 24
Finished Jun 02 02:44:39 PM PDT 24
Peak memory 213652 kb
Host smart-309278e6-9f9c-44b7-97d6-d369994a3abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292396932 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4292396932
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1138132774
Short name T970
Test name
Test status
Simulation time 18388847 ps
CPU time 1.1 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:28 PM PDT 24
Peak memory 205608 kb
Host smart-0ae163c3-ec71-4e70-bfc9-afa926d7615d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138132774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1138132774
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.95449121
Short name T941
Test name
Test status
Simulation time 13937157 ps
CPU time 0.87 seconds
Started Jun 02 02:43:21 PM PDT 24
Finished Jun 02 02:43:22 PM PDT 24
Peak memory 205332 kb
Host smart-2c668b3a-f28a-4dfb-8c4e-ef981add1563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95449121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.95449121
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.693448929
Short name T1082
Test name
Test status
Simulation time 74311011 ps
CPU time 1.26 seconds
Started Jun 02 02:43:25 PM PDT 24
Finished Jun 02 02:43:27 PM PDT 24
Peak memory 205648 kb
Host smart-47305733-7d02-4f95-aaa5-84f6fa093d48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693448929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.693448929
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1867896637
Short name T985
Test name
Test status
Simulation time 361456059 ps
CPU time 2.92 seconds
Started Jun 02 02:43:33 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 214156 kb
Host smart-6cc7e285-4efd-4c98-925e-90a62611e553
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867896637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1867896637
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1416924505
Short name T1001
Test name
Test status
Simulation time 363161761 ps
CPU time 12.92 seconds
Started Jun 02 02:43:22 PM PDT 24
Finished Jun 02 02:43:35 PM PDT 24
Peak memory 220224 kb
Host smart-2b354212-4557-4fbc-bca7-56e839fdaf7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416924505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1416924505
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.607517641
Short name T931
Test name
Test status
Simulation time 134187091 ps
CPU time 5.05 seconds
Started Jun 02 02:43:29 PM PDT 24
Finished Jun 02 02:43:35 PM PDT 24
Peak memory 215436 kb
Host smart-94425f6c-2bba-4d2c-a555-70d05c886315
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607517641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.607517641
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.752245093
Short name T168
Test name
Test status
Simulation time 802108272 ps
CPU time 6.58 seconds
Started Jun 02 02:43:18 PM PDT 24
Finished Jun 02 02:43:24 PM PDT 24
Peak memory 213840 kb
Host smart-dda76f68-1270-4021-8525-8c13f665f48d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752245093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.752245093
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3218340467
Short name T1077
Test name
Test status
Simulation time 26988852 ps
CPU time 1.58 seconds
Started Jun 02 02:43:27 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 213864 kb
Host smart-3646dc75-732e-472e-a144-981c25bd9292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218340467 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3218340467
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1465309403
Short name T963
Test name
Test status
Simulation time 22190433 ps
CPU time 0.93 seconds
Started Jun 02 02:44:37 PM PDT 24
Finished Jun 02 02:44:38 PM PDT 24
Peak memory 205268 kb
Host smart-4c35094c-9add-472b-91c0-267b2595ecc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465309403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1465309403
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3657001474
Short name T978
Test name
Test status
Simulation time 32670559 ps
CPU time 0.74 seconds
Started Jun 02 02:44:34 PM PDT 24
Finished Jun 02 02:44:36 PM PDT 24
Peak memory 205120 kb
Host smart-662301d4-e183-43ec-8e70-7231c99b18b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657001474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3657001474
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1377229487
Short name T997
Test name
Test status
Simulation time 101900380 ps
CPU time 3.75 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:31 PM PDT 24
Peak memory 205544 kb
Host smart-da229b82-cee7-4f2f-a5c7-fa05acef861c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377229487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1377229487
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.134073929
Short name T1013
Test name
Test status
Simulation time 1724333658 ps
CPU time 3.9 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:31 PM PDT 24
Peak memory 214204 kb
Host smart-731f441d-8c4c-4c66-ba9c-a4ade44f1708
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134073929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.134073929
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.456067884
Short name T992
Test name
Test status
Simulation time 89921603 ps
CPU time 3.09 seconds
Started Jun 02 02:44:34 PM PDT 24
Finished Jun 02 02:44:38 PM PDT 24
Peak memory 213916 kb
Host smart-065f7dd3-79d7-4590-86d9-aeb37b9b3c88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456067884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.456067884
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3957683322
Short name T1023
Test name
Test status
Simulation time 388024770 ps
CPU time 2.94 seconds
Started Jun 02 02:45:03 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 213616 kb
Host smart-e0df9ac2-854c-4496-a600-0e2a3522e376
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957683322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3957683322
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3068264768
Short name T179
Test name
Test status
Simulation time 814610823 ps
CPU time 3.34 seconds
Started Jun 02 02:44:38 PM PDT 24
Finished Jun 02 02:44:42 PM PDT 24
Peak memory 213664 kb
Host smart-8b5a8c44-4ad1-4387-822a-d702e9db2775
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068264768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3068264768
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1094282724
Short name T1005
Test name
Test status
Simulation time 134732392 ps
CPU time 3.85 seconds
Started Jun 02 02:43:00 PM PDT 24
Finished Jun 02 02:43:05 PM PDT 24
Peak memory 205684 kb
Host smart-e966b841-7835-423b-8902-bd4ed0f3ea29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094282724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
094282724
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.981059610
Short name T156
Test name
Test status
Simulation time 4299136742 ps
CPU time 10.43 seconds
Started Jun 02 02:43:07 PM PDT 24
Finished Jun 02 02:43:19 PM PDT 24
Peak memory 205660 kb
Host smart-603839c2-21e0-4bfd-a92a-b9d999740e47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981059610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.981059610
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1672383553
Short name T957
Test name
Test status
Simulation time 28496137 ps
CPU time 1.31 seconds
Started Jun 02 02:43:01 PM PDT 24
Finished Jun 02 02:43:03 PM PDT 24
Peak memory 205580 kb
Host smart-554a3230-4f36-4256-8ee9-856d91bbdc29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672383553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
672383553
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2799248617
Short name T1060
Test name
Test status
Simulation time 46087337 ps
CPU time 1.51 seconds
Started Jun 02 02:43:00 PM PDT 24
Finished Jun 02 02:43:02 PM PDT 24
Peak memory 213880 kb
Host smart-a1aac733-2f9b-4d87-bd6b-4f51742418d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799248617 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2799248617
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.4294809273
Short name T1030
Test name
Test status
Simulation time 36034269 ps
CPU time 0.89 seconds
Started Jun 02 02:43:01 PM PDT 24
Finished Jun 02 02:43:03 PM PDT 24
Peak memory 205340 kb
Host smart-db3a5592-e6b3-409f-be9f-fb0cac9bbb81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294809273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.4294809273
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1485597599
Short name T919
Test name
Test status
Simulation time 12260130 ps
CPU time 0.69 seconds
Started Jun 02 02:43:04 PM PDT 24
Finished Jun 02 02:43:05 PM PDT 24
Peak memory 205256 kb
Host smart-ce6bff22-03e1-4c3c-a0b7-2bc3cbe6b4c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485597599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1485597599
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.480876237
Short name T133
Test name
Test status
Simulation time 974667465 ps
CPU time 3.2 seconds
Started Jun 02 02:43:07 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 205616 kb
Host smart-35abf756-0cc8-49b1-a7a2-d705e42b1689
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480876237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.480876237
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.902475413
Short name T113
Test name
Test status
Simulation time 74088652 ps
CPU time 2.52 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:08 PM PDT 24
Peak memory 214188 kb
Host smart-738f2fc2-6faf-4993-9d1f-7dc358359255
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902475413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.902475413
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.851365532
Short name T1053
Test name
Test status
Simulation time 88861988 ps
CPU time 2.71 seconds
Started Jun 02 02:43:04 PM PDT 24
Finished Jun 02 02:43:08 PM PDT 24
Peak memory 213788 kb
Host smart-b13adb4a-55d5-4c16-8e85-9111544631a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851365532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.851365532
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.924788894
Short name T928
Test name
Test status
Simulation time 62338150 ps
CPU time 0.77 seconds
Started Jun 02 02:43:24 PM PDT 24
Finished Jun 02 02:43:25 PM PDT 24
Peak memory 205180 kb
Host smart-5c96da67-70a5-40e8-81cb-2b219f8020a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924788894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.924788894
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1823060661
Short name T1081
Test name
Test status
Simulation time 22937761 ps
CPU time 0.81 seconds
Started Jun 02 02:43:27 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 205308 kb
Host smart-a093fd5a-f742-4e46-9282-1bd6f862ec2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823060661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1823060661
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1694968633
Short name T1072
Test name
Test status
Simulation time 40600116 ps
CPU time 0.71 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:27 PM PDT 24
Peak memory 205312 kb
Host smart-aa2aaa46-40a2-42ef-95d1-c423585146ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694968633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1694968633
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.324739667
Short name T925
Test name
Test status
Simulation time 35193721 ps
CPU time 0.69 seconds
Started Jun 02 02:43:38 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 205156 kb
Host smart-51a48f53-a50b-4860-8396-7fb68a0bd209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324739667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.324739667
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.470804242
Short name T924
Test name
Test status
Simulation time 13744041 ps
CPU time 0.85 seconds
Started Jun 02 02:43:30 PM PDT 24
Finished Jun 02 02:43:32 PM PDT 24
Peak memory 205252 kb
Host smart-eb1ea546-1b35-4c31-8463-ffc62cbf38ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470804242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.470804242
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2497585114
Short name T1033
Test name
Test status
Simulation time 10121763 ps
CPU time 0.8 seconds
Started Jun 02 02:43:27 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 205328 kb
Host smart-1560b363-fb24-4ac4-b2ca-4b4261854560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497585114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2497585114
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2295801480
Short name T967
Test name
Test status
Simulation time 10619642 ps
CPU time 0.83 seconds
Started Jun 02 02:43:29 PM PDT 24
Finished Jun 02 02:43:31 PM PDT 24
Peak memory 205308 kb
Host smart-b9f8b472-6741-4be0-9508-4bc6383e07ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295801480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2295801480
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2270801317
Short name T1021
Test name
Test status
Simulation time 33690304 ps
CPU time 0.81 seconds
Started Jun 02 02:43:34 PM PDT 24
Finished Jun 02 02:43:36 PM PDT 24
Peak memory 205184 kb
Host smart-cca9c515-0d0f-44f1-9a23-1c13485aaf83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270801317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2270801317
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3343110802
Short name T1041
Test name
Test status
Simulation time 35980961 ps
CPU time 0.72 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 02:43:43 PM PDT 24
Peak memory 205260 kb
Host smart-8fad8a92-2fca-4871-a26a-c6b3e4be48cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343110802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3343110802
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1358714104
Short name T934
Test name
Test status
Simulation time 21484644 ps
CPU time 0.76 seconds
Started Jun 02 02:43:30 PM PDT 24
Finished Jun 02 02:43:32 PM PDT 24
Peak memory 205240 kb
Host smart-81c4f01e-7735-48e1-aa36-06bc5ae03b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358714104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1358714104
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1899549019
Short name T971
Test name
Test status
Simulation time 1734100807 ps
CPU time 11.46 seconds
Started Jun 02 02:43:00 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 205688 kb
Host smart-dc2ea4fe-ff12-4504-a591-605b76531c0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899549019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
899549019
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.560941303
Short name T940
Test name
Test status
Simulation time 474167981 ps
CPU time 6.81 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:16 PM PDT 24
Peak memory 205624 kb
Host smart-a0adc1d5-cd7e-4806-ac89-4b9da85ad253
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560941303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.560941303
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.286770416
Short name T923
Test name
Test status
Simulation time 65409185 ps
CPU time 1.43 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 205576 kb
Host smart-91475640-5e77-4550-8bc1-a026a849e27c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286770416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.286770416
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3058816720
Short name T155
Test name
Test status
Simulation time 168326204 ps
CPU time 2.02 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:08 PM PDT 24
Peak memory 213876 kb
Host smart-897d691b-6ca2-4aee-b824-b8a12df82b5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058816720 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3058816720
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.172113303
Short name T947
Test name
Test status
Simulation time 45543508 ps
CPU time 0.89 seconds
Started Jun 02 02:43:10 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 205236 kb
Host smart-ae49a4b9-4c8a-474b-a326-1084fc9fc23d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172113303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.172113303
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1442390293
Short name T974
Test name
Test status
Simulation time 17031582 ps
CPU time 0.69 seconds
Started Jun 02 02:43:01 PM PDT 24
Finished Jun 02 02:43:02 PM PDT 24
Peak memory 205256 kb
Host smart-d97717c6-9fed-4992-8766-c1a260dab12c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442390293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1442390293
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2688083415
Short name T1058
Test name
Test status
Simulation time 40406200 ps
CPU time 1.42 seconds
Started Jun 02 02:43:02 PM PDT 24
Finished Jun 02 02:43:04 PM PDT 24
Peak memory 205704 kb
Host smart-75b07164-8958-4fd9-a99e-8c3155366d63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688083415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2688083415
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.324562979
Short name T980
Test name
Test status
Simulation time 503144979 ps
CPU time 2.67 seconds
Started Jun 02 02:43:00 PM PDT 24
Finished Jun 02 02:43:03 PM PDT 24
Peak memory 214196 kb
Host smart-2a47b69d-73a8-4478-a872-04a95de6fd20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324562979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.324562979
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1112123397
Short name T943
Test name
Test status
Simulation time 1453478545 ps
CPU time 6.95 seconds
Started Jun 02 02:43:06 PM PDT 24
Finished Jun 02 02:43:14 PM PDT 24
Peak memory 214112 kb
Host smart-5bbdd8cd-e82e-48af-a034-09ee28db9e8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112123397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1112123397
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3988475747
Short name T1025
Test name
Test status
Simulation time 526046768 ps
CPU time 4.73 seconds
Started Jun 02 02:43:00 PM PDT 24
Finished Jun 02 02:43:05 PM PDT 24
Peak memory 216896 kb
Host smart-b575ab25-21d1-47b6-9331-5f5cd9ae8daa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988475747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3988475747
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.930937995
Short name T1062
Test name
Test status
Simulation time 46790902 ps
CPU time 0.73 seconds
Started Jun 02 02:43:46 PM PDT 24
Finished Jun 02 02:43:48 PM PDT 24
Peak memory 205320 kb
Host smart-7f259366-cd0b-4d5d-bb96-3c0e2817c1fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930937995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.930937995
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.999141581
Short name T935
Test name
Test status
Simulation time 28437916 ps
CPU time 0.72 seconds
Started Jun 02 02:43:24 PM PDT 24
Finished Jun 02 02:43:26 PM PDT 24
Peak memory 205320 kb
Host smart-c3c5edc1-7084-4ae2-b04a-d51d214e1cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999141581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.999141581
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.134722978
Short name T1031
Test name
Test status
Simulation time 17637365 ps
CPU time 0.91 seconds
Started Jun 02 02:43:39 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 205484 kb
Host smart-db87d69a-42a4-4019-b490-68c2eaeafd75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134722978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.134722978
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3333678578
Short name T1049
Test name
Test status
Simulation time 18807311 ps
CPU time 0.78 seconds
Started Jun 02 02:43:34 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 205300 kb
Host smart-ba1dda96-30dd-4201-b032-b15506b3b0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333678578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3333678578
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2706905910
Short name T1019
Test name
Test status
Simulation time 11397171 ps
CPU time 0.86 seconds
Started Jun 02 02:43:23 PM PDT 24
Finished Jun 02 02:43:25 PM PDT 24
Peak memory 205200 kb
Host smart-2ede5527-5b7c-4ebb-816a-9d2abfe57d21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706905910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2706905910
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1984741239
Short name T1061
Test name
Test status
Simulation time 42063198 ps
CPU time 0.83 seconds
Started Jun 02 02:43:28 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 205156 kb
Host smart-2646681c-7dd5-4663-aa97-82a729a53fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984741239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1984741239
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1425612563
Short name T932
Test name
Test status
Simulation time 26141492 ps
CPU time 0.76 seconds
Started Jun 02 02:43:36 PM PDT 24
Finished Jun 02 02:43:38 PM PDT 24
Peak memory 205188 kb
Host smart-4c23020e-41e9-49a8-a324-b6da2892f964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425612563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1425612563
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3837576799
Short name T994
Test name
Test status
Simulation time 49161643 ps
CPU time 0.72 seconds
Started Jun 02 02:43:35 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 205264 kb
Host smart-a9894276-a014-4acc-86be-865846192fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837576799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3837576799
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1282797683
Short name T1014
Test name
Test status
Simulation time 46204697 ps
CPU time 0.72 seconds
Started Jun 02 02:43:31 PM PDT 24
Finished Jun 02 02:43:32 PM PDT 24
Peak memory 205236 kb
Host smart-99a8488e-56ba-4df1-82c0-f87fbaed6cda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282797683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1282797683
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2317348336
Short name T1070
Test name
Test status
Simulation time 69786322 ps
CPU time 0.71 seconds
Started Jun 02 02:43:25 PM PDT 24
Finished Jun 02 02:43:27 PM PDT 24
Peak memory 205308 kb
Host smart-4167c19c-18e8-44ff-9a45-94aedeed2719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317348336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2317348336
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1955619042
Short name T959
Test name
Test status
Simulation time 757576157 ps
CPU time 14.68 seconds
Started Jun 02 02:43:07 PM PDT 24
Finished Jun 02 02:43:23 PM PDT 24
Peak memory 205508 kb
Host smart-8f4558bc-343a-4d29-b968-12ab15d7c857
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955619042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
955619042
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3130122529
Short name T1007
Test name
Test status
Simulation time 4199560396 ps
CPU time 14.94 seconds
Started Jun 02 02:43:00 PM PDT 24
Finished Jun 02 02:43:16 PM PDT 24
Peak memory 205648 kb
Host smart-50177659-a780-40d5-8435-aeb15679e831
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130122529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
130122529
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1680485426
Short name T977
Test name
Test status
Simulation time 55116120 ps
CPU time 1.44 seconds
Started Jun 02 02:43:06 PM PDT 24
Finished Jun 02 02:43:08 PM PDT 24
Peak memory 205556 kb
Host smart-a0cf8fc6-8329-4495-957c-e70004228bed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680485426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
680485426
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1977270100
Short name T955
Test name
Test status
Simulation time 19873076 ps
CPU time 1.55 seconds
Started Jun 02 02:43:00 PM PDT 24
Finished Jun 02 02:43:07 PM PDT 24
Peak memory 213800 kb
Host smart-49c82206-6784-434c-a2b0-a003bd7570c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977270100 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1977270100
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3650355135
Short name T1040
Test name
Test status
Simulation time 170440054 ps
CPU time 1.51 seconds
Started Jun 02 02:43:10 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 205564 kb
Host smart-1226ff28-000a-4ca3-8c59-22906a459233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650355135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3650355135
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.160144281
Short name T930
Test name
Test status
Simulation time 36312171 ps
CPU time 0.85 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:06 PM PDT 24
Peak memory 205308 kb
Host smart-0aa2e0ed-089e-42ab-8a92-2fbb33b57fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160144281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.160144281
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4100374994
Short name T134
Test name
Test status
Simulation time 57229636 ps
CPU time 1.6 seconds
Started Jun 02 02:43:07 PM PDT 24
Finished Jun 02 02:43:09 PM PDT 24
Peak memory 205572 kb
Host smart-c2ef971d-1536-4930-8128-0948df622dc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100374994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4100374994
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1279092629
Short name T966
Test name
Test status
Simulation time 31411584 ps
CPU time 1.69 seconds
Started Jun 02 02:43:06 PM PDT 24
Finished Jun 02 02:43:08 PM PDT 24
Peak memory 214112 kb
Host smart-b4fe0f07-25b4-42c3-b507-9c50f7fc2e86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279092629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1279092629
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2886458436
Short name T1080
Test name
Test status
Simulation time 148930003 ps
CPU time 8.32 seconds
Started Jun 02 02:43:02 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 220468 kb
Host smart-210781fd-2a1e-4227-b07a-5262618989ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886458436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2886458436
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3647813161
Short name T1035
Test name
Test status
Simulation time 85001931 ps
CPU time 1.75 seconds
Started Jun 02 02:43:03 PM PDT 24
Finished Jun 02 02:43:05 PM PDT 24
Peak memory 214008 kb
Host smart-0d3879e5-f2ad-450e-af11-fa7aaede798c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647813161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3647813161
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2345067438
Short name T951
Test name
Test status
Simulation time 23709766 ps
CPU time 0.83 seconds
Started Jun 02 02:43:27 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 205288 kb
Host smart-1815a0dd-ccd4-476d-aac1-db6adbc865c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345067438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2345067438
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.4050484639
Short name T950
Test name
Test status
Simulation time 10264512 ps
CPU time 0.77 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:28 PM PDT 24
Peak memory 205260 kb
Host smart-9fe5b57e-4c77-4fbf-9545-91673b256680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050484639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.4050484639
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3076287015
Short name T1018
Test name
Test status
Simulation time 50201160 ps
CPU time 0.72 seconds
Started Jun 02 02:43:35 PM PDT 24
Finished Jun 02 02:43:36 PM PDT 24
Peak memory 205328 kb
Host smart-99b44f49-0a00-415c-a165-74b13ee2d8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076287015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3076287015
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.293691262
Short name T986
Test name
Test status
Simulation time 45414881 ps
CPU time 0.84 seconds
Started Jun 02 02:43:28 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 205252 kb
Host smart-9187653b-914a-4a6c-b96a-57d2c0d5f0b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293691262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.293691262
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1329668509
Short name T918
Test name
Test status
Simulation time 29643004 ps
CPU time 0.71 seconds
Started Jun 02 02:43:28 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 205316 kb
Host smart-639cc298-b2ba-40b7-a8c2-4d343e4ccb44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329668509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1329668509
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1202995795
Short name T920
Test name
Test status
Simulation time 13950854 ps
CPU time 0.72 seconds
Started Jun 02 02:43:37 PM PDT 24
Finished Jun 02 02:43:39 PM PDT 24
Peak memory 205316 kb
Host smart-4e9068d8-260d-4df3-b517-69254320772f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202995795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1202995795
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1909877568
Short name T956
Test name
Test status
Simulation time 94751669 ps
CPU time 0.76 seconds
Started Jun 02 02:43:40 PM PDT 24
Finished Jun 02 02:43:41 PM PDT 24
Peak memory 205328 kb
Host smart-6fa002e5-346d-4d8e-aa53-3d10ce1f14e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909877568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1909877568
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.801506438
Short name T1011
Test name
Test status
Simulation time 59406562 ps
CPU time 0.78 seconds
Started Jun 02 02:43:28 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 205232 kb
Host smart-7e3415fa-b910-4af3-adc1-6f82aaf82a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801506438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.801506438
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2506839479
Short name T1009
Test name
Test status
Simulation time 178984352 ps
CPU time 0.85 seconds
Started Jun 02 02:43:28 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 205328 kb
Host smart-39905b2b-4593-4d1f-b5ef-2c6eea32e227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506839479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2506839479
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1163644312
Short name T991
Test name
Test status
Simulation time 78375718 ps
CPU time 0.8 seconds
Started Jun 02 02:43:29 PM PDT 24
Finished Jun 02 02:43:31 PM PDT 24
Peak memory 205248 kb
Host smart-30004943-dc57-4a22-b51a-9bdd9b2bc113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163644312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1163644312
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1862214525
Short name T1050
Test name
Test status
Simulation time 87351882 ps
CPU time 1.14 seconds
Started Jun 02 02:43:10 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 213884 kb
Host smart-7da33b1b-82be-44d6-9926-8561c3c481b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862214525 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1862214525
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2620541868
Short name T1028
Test name
Test status
Simulation time 49507100 ps
CPU time 1.09 seconds
Started Jun 02 02:43:04 PM PDT 24
Finished Jun 02 02:43:05 PM PDT 24
Peak memory 205568 kb
Host smart-b1fe8910-8008-4eae-b20e-74c6a049ee4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620541868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2620541868
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1148712109
Short name T1074
Test name
Test status
Simulation time 12075329 ps
CPU time 0.85 seconds
Started Jun 02 02:43:06 PM PDT 24
Finished Jun 02 02:43:08 PM PDT 24
Peak memory 205500 kb
Host smart-658c2a52-42e6-42d4-baf3-2b9416d0096c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148712109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1148712109
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.865377369
Short name T984
Test name
Test status
Simulation time 155588842 ps
CPU time 2.14 seconds
Started Jun 02 02:43:09 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 205592 kb
Host smart-5d7d223f-ac09-4900-a9dd-636abbcf61d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865377369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.865377369
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2606994444
Short name T115
Test name
Test status
Simulation time 114913694 ps
CPU time 2.02 seconds
Started Jun 02 02:43:06 PM PDT 24
Finished Jun 02 02:43:09 PM PDT 24
Peak memory 214036 kb
Host smart-78cee5f3-34e0-47a4-8501-b3c406d9590a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606994444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2606994444
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1093728307
Short name T1012
Test name
Test status
Simulation time 6302501287 ps
CPU time 14.4 seconds
Started Jun 02 02:43:06 PM PDT 24
Finished Jun 02 02:43:21 PM PDT 24
Peak memory 214360 kb
Host smart-c53a17b1-4963-4d28-a969-c94e252b77b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093728307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1093728307
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3457257343
Short name T922
Test name
Test status
Simulation time 666197793 ps
CPU time 3.72 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:10 PM PDT 24
Peak memory 213840 kb
Host smart-cdc10dce-cc73-4d13-b9f2-3ddab7fbf3c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457257343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3457257343
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1828851912
Short name T186
Test name
Test status
Simulation time 2520404366 ps
CPU time 6.25 seconds
Started Jun 02 02:43:22 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 215344 kb
Host smart-83a02f42-3967-4d88-be10-1df101904186
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828851912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1828851912
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.944413379
Short name T937
Test name
Test status
Simulation time 365641514 ps
CPU time 1.22 seconds
Started Jun 02 02:43:25 PM PDT 24
Finished Jun 02 02:43:27 PM PDT 24
Peak memory 205660 kb
Host smart-0d5b4343-c353-483d-8110-ea8015186910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944413379 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.944413379
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1223023578
Short name T1052
Test name
Test status
Simulation time 29476400 ps
CPU time 1.11 seconds
Started Jun 02 02:43:14 PM PDT 24
Finished Jun 02 02:43:15 PM PDT 24
Peak memory 205520 kb
Host smart-95d95968-7a87-4fe0-a34b-d5014fe9160b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223023578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1223023578
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.167317558
Short name T1047
Test name
Test status
Simulation time 17724857 ps
CPU time 0.74 seconds
Started Jun 02 02:43:19 PM PDT 24
Finished Jun 02 02:43:21 PM PDT 24
Peak memory 205148 kb
Host smart-285d4e8b-0095-4efe-aadb-240a9116c1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167317558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.167317558
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3779785770
Short name T969
Test name
Test status
Simulation time 79857529 ps
CPU time 1.74 seconds
Started Jun 02 02:43:06 PM PDT 24
Finished Jun 02 02:43:09 PM PDT 24
Peak memory 205620 kb
Host smart-82dc7c18-e344-4842-b4c6-c4a524810a5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779785770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3779785770
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1076791063
Short name T114
Test name
Test status
Simulation time 511581027 ps
CPU time 2.35 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 214140 kb
Host smart-bc747952-c421-4e6d-b69e-7da74664f8fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076791063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1076791063
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1629000541
Short name T1024
Test name
Test status
Simulation time 3946299986 ps
CPU time 5.35 seconds
Started Jun 02 02:43:10 PM PDT 24
Finished Jun 02 02:43:17 PM PDT 24
Peak memory 221164 kb
Host smart-34dbd013-28c2-4984-9d7e-5e25b6a72c45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629000541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1629000541
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2514366334
Short name T921
Test name
Test status
Simulation time 28801610 ps
CPU time 2.05 seconds
Started Jun 02 02:43:09 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 213936 kb
Host smart-4cce6031-0ba2-4825-bb4d-965cd6f9e799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514366334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2514366334
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4162570148
Short name T1059
Test name
Test status
Simulation time 145473271 ps
CPU time 2.44 seconds
Started Jun 02 02:43:22 PM PDT 24
Finished Jun 02 02:43:25 PM PDT 24
Peak memory 213896 kb
Host smart-c8cb1953-b7ff-4018-a032-210dd4c57f6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162570148 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.4162570148
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.881181120
Short name T961
Test name
Test status
Simulation time 39988597 ps
CPU time 1.39 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:10 PM PDT 24
Peak memory 205624 kb
Host smart-9c04e0e5-e388-4a84-8992-fdc16cb9658c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881181120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.881181120
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2680954790
Short name T936
Test name
Test status
Simulation time 22545742 ps
CPU time 0.84 seconds
Started Jun 02 02:43:13 PM PDT 24
Finished Jun 02 02:43:14 PM PDT 24
Peak memory 205272 kb
Host smart-ccee274b-84c6-4513-9372-51a55bfe8fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680954790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2680954790
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2093348565
Short name T1015
Test name
Test status
Simulation time 235972530 ps
CPU time 2.19 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 205528 kb
Host smart-1d10d49b-e2ba-48f7-b2f1-0074bff67083
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093348565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2093348565
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1023008924
Short name T1045
Test name
Test status
Simulation time 277321152 ps
CPU time 3.12 seconds
Started Jun 02 02:43:06 PM PDT 24
Finished Jun 02 02:43:10 PM PDT 24
Peak memory 214168 kb
Host smart-87eda1e1-c14d-445e-acdd-c02ccb747d3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023008924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1023008924
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3304494760
Short name T954
Test name
Test status
Simulation time 373306494 ps
CPU time 13.07 seconds
Started Jun 02 02:43:07 PM PDT 24
Finished Jun 02 02:43:21 PM PDT 24
Peak memory 214160 kb
Host smart-e478f735-01de-4e2e-a92f-c6ae36775ee2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304494760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3304494760
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2596285699
Short name T1042
Test name
Test status
Simulation time 112573621 ps
CPU time 3.16 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:09 PM PDT 24
Peak memory 213736 kb
Host smart-cf5747e8-67db-4f9b-b14f-4dea5fb4f890
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596285699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2596285699
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3171002217
Short name T173
Test name
Test status
Simulation time 296456765 ps
CPU time 6.4 seconds
Started Jun 02 02:43:20 PM PDT 24
Finished Jun 02 02:43:26 PM PDT 24
Peak memory 213760 kb
Host smart-39cd72c9-f25c-4235-9558-7ac977b5f69c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171002217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3171002217
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1491714451
Short name T1002
Test name
Test status
Simulation time 46718853 ps
CPU time 1.36 seconds
Started Jun 02 02:43:21 PM PDT 24
Finished Jun 02 02:43:22 PM PDT 24
Peak memory 205560 kb
Host smart-4bbc5404-c3bf-4eea-af39-881d6948cee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491714451 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1491714451
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2904044037
Short name T995
Test name
Test status
Simulation time 61035782 ps
CPU time 1.16 seconds
Started Jun 02 02:43:09 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 205524 kb
Host smart-6e413284-143b-4795-832e-444618c24b33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904044037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2904044037
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1545889991
Short name T976
Test name
Test status
Simulation time 29397607 ps
CPU time 0.78 seconds
Started Jun 02 02:43:25 PM PDT 24
Finished Jun 02 02:43:27 PM PDT 24
Peak memory 205256 kb
Host smart-38c25a00-9a73-4beb-934e-d099d13b0ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545889991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1545889991
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3606753587
Short name T982
Test name
Test status
Simulation time 243468152 ps
CPU time 2.4 seconds
Started Jun 02 02:43:09 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 205636 kb
Host smart-6f4a7948-5895-4601-ae54-6bae1c19c447
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606753587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3606753587
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.277007005
Short name T1036
Test name
Test status
Simulation time 222381231 ps
CPU time 5.78 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:15 PM PDT 24
Peak memory 218368 kb
Host smart-1b912937-be25-46ec-93d5-e8eac7adea43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277007005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.277007005
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.559930964
Short name T110
Test name
Test status
Simulation time 102780435 ps
CPU time 4.34 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:13 PM PDT 24
Peak memory 222332 kb
Host smart-d6a253d5-d90c-4287-a8d2-7bf32212c19c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559930964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.559930964
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2007357276
Short name T926
Test name
Test status
Simulation time 261616632 ps
CPU time 2.8 seconds
Started Jun 02 02:43:16 PM PDT 24
Finished Jun 02 02:43:19 PM PDT 24
Peak memory 215952 kb
Host smart-cd464d51-84c0-4c67-94de-f15117dbfbea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007357276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2007357276
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3813204395
Short name T164
Test name
Test status
Simulation time 54643835 ps
CPU time 3.09 seconds
Started Jun 02 02:43:16 PM PDT 24
Finished Jun 02 02:43:20 PM PDT 24
Peak memory 214076 kb
Host smart-c9c6b323-6878-4300-b915-984cf1ea9f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813204395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3813204395
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1409829189
Short name T1051
Test name
Test status
Simulation time 74466156 ps
CPU time 1.65 seconds
Started Jun 02 02:43:16 PM PDT 24
Finished Jun 02 02:43:18 PM PDT 24
Peak memory 213820 kb
Host smart-6e062115-9669-42d0-b262-dfa6460c5bd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409829189 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1409829189
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2252630740
Short name T1076
Test name
Test status
Simulation time 11420275 ps
CPU time 1.02 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:07 PM PDT 24
Peak memory 205428 kb
Host smart-8a675321-d53a-4daf-8c39-139c69cd4d66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252630740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2252630740
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3833205494
Short name T988
Test name
Test status
Simulation time 37026912 ps
CPU time 0.83 seconds
Started Jun 02 02:43:15 PM PDT 24
Finished Jun 02 02:43:17 PM PDT 24
Peak memory 205332 kb
Host smart-2e13c097-75b5-4d2d-8495-230acc5ab22b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833205494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3833205494
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3309314849
Short name T998
Test name
Test status
Simulation time 166498061 ps
CPU time 3.19 seconds
Started Jun 02 02:43:12 PM PDT 24
Finished Jun 02 02:43:16 PM PDT 24
Peak memory 205552 kb
Host smart-71c9698d-776f-4668-87b1-908f30519ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309314849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3309314849
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.281158392
Short name T996
Test name
Test status
Simulation time 87577647 ps
CPU time 2.02 seconds
Started Jun 02 02:43:11 PM PDT 24
Finished Jun 02 02:43:14 PM PDT 24
Peak memory 214168 kb
Host smart-34a1a705-ca07-4aca-990e-1e4c7344d0ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281158392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.281158392
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1307134090
Short name T1055
Test name
Test status
Simulation time 536959987 ps
CPU time 3.74 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:10 PM PDT 24
Peak memory 214172 kb
Host smart-6365cc02-4872-49b8-a549-a4fb808a0827
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307134090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1307134090
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3960916945
Short name T933
Test name
Test status
Simulation time 27752099 ps
CPU time 1.74 seconds
Started Jun 02 02:43:17 PM PDT 24
Finished Jun 02 02:43:19 PM PDT 24
Peak memory 213864 kb
Host smart-9a78e574-a58c-43ea-af90-00733dca52d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960916945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3960916945
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2033935031
Short name T183
Test name
Test status
Simulation time 167016956 ps
CPU time 5.95 seconds
Started Jun 02 02:43:08 PM PDT 24
Finished Jun 02 02:43:15 PM PDT 24
Peak memory 213744 kb
Host smart-1125023d-e0f7-4934-9b27-8147bf89a15e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033935031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2033935031
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2771830785
Short name T786
Test name
Test status
Simulation time 22191317 ps
CPU time 1.07 seconds
Started Jun 02 02:59:27 PM PDT 24
Finished Jun 02 02:59:29 PM PDT 24
Peak memory 206104 kb
Host smart-dca788f8-4085-4941-b698-91916a96c667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771830785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2771830785
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.921299053
Short name T788
Test name
Test status
Simulation time 177776952 ps
CPU time 3.57 seconds
Started Jun 02 02:59:22 PM PDT 24
Finished Jun 02 02:59:26 PM PDT 24
Peak memory 208312 kb
Host smart-9d169a4d-061e-4343-9563-f4e244b955f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921299053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.921299053
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2646716132
Short name T808
Test name
Test status
Simulation time 435525844 ps
CPU time 4.8 seconds
Started Jun 02 02:59:14 PM PDT 24
Finished Jun 02 02:59:19 PM PDT 24
Peak memory 209896 kb
Host smart-f19fef21-d78b-45a6-9328-8d07c6aea873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646716132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2646716132
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.55532428
Short name T589
Test name
Test status
Simulation time 152122878 ps
CPU time 2.29 seconds
Started Jun 02 02:59:23 PM PDT 24
Finished Jun 02 02:59:26 PM PDT 24
Peak memory 214664 kb
Host smart-75ade5e6-e287-459f-a490-2cd6c65ddc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55532428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.55532428
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.202279158
Short name T191
Test name
Test status
Simulation time 434626498 ps
CPU time 5.06 seconds
Started Jun 02 02:59:14 PM PDT 24
Finished Jun 02 02:59:20 PM PDT 24
Peak memory 220316 kb
Host smart-19d2c300-0df9-483e-a4db-b1639c13f516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202279158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.202279158
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2112018194
Short name T2
Test name
Test status
Simulation time 1074360544 ps
CPU time 27.42 seconds
Started Jun 02 02:59:16 PM PDT 24
Finished Jun 02 02:59:44 PM PDT 24
Peak memory 208952 kb
Host smart-68629727-ce14-47ec-97cb-ddc07eb0c9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112018194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2112018194
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1162998984
Short name T333
Test name
Test status
Simulation time 1051460933 ps
CPU time 4.11 seconds
Started Jun 02 02:59:08 PM PDT 24
Finished Jun 02 02:59:12 PM PDT 24
Peak memory 208600 kb
Host smart-ad1c1ace-9d6f-44dc-94fa-89a0ad5ac4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162998984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1162998984
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3136988426
Short name T194
Test name
Test status
Simulation time 1187426895 ps
CPU time 5.71 seconds
Started Jun 02 02:59:16 PM PDT 24
Finished Jun 02 02:59:22 PM PDT 24
Peak memory 207960 kb
Host smart-09bae89d-4455-4ad3-982b-a63ec938732c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136988426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3136988426
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3414166106
Short name T322
Test name
Test status
Simulation time 375698796 ps
CPU time 3.04 seconds
Started Jun 02 02:59:15 PM PDT 24
Finished Jun 02 02:59:19 PM PDT 24
Peak memory 207092 kb
Host smart-00897229-e029-4a86-8cb7-ff2cbc033ca2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414166106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3414166106
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2697088452
Short name T421
Test name
Test status
Simulation time 45405519 ps
CPU time 1.8 seconds
Started Jun 02 02:59:16 PM PDT 24
Finished Jun 02 02:59:19 PM PDT 24
Peak memory 207356 kb
Host smart-2690018d-97fc-497d-99a4-c5abe1a1b0b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697088452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2697088452
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2130462493
Short name T777
Test name
Test status
Simulation time 79084795 ps
CPU time 1.99 seconds
Started Jun 02 02:59:20 PM PDT 24
Finished Jun 02 02:59:22 PM PDT 24
Peak memory 209640 kb
Host smart-81d9a68d-9ba2-45f3-a8c0-a36ba41520b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130462493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2130462493
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.502019105
Short name T701
Test name
Test status
Simulation time 175357771 ps
CPU time 2.35 seconds
Started Jun 02 02:59:08 PM PDT 24
Finished Jun 02 02:59:11 PM PDT 24
Peak memory 207796 kb
Host smart-a48d32c2-4f67-428f-ae8c-024f6ba0e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502019105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.502019105
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2469448605
Short name T294
Test name
Test status
Simulation time 1891902595 ps
CPU time 50.17 seconds
Started Jun 02 02:59:29 PM PDT 24
Finished Jun 02 03:00:19 PM PDT 24
Peak memory 222416 kb
Host smart-49cad485-bbc9-45a1-8353-75bc8069ee86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469448605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2469448605
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2843659082
Short name T603
Test name
Test status
Simulation time 135638655 ps
CPU time 5.18 seconds
Started Jun 02 02:59:22 PM PDT 24
Finished Jun 02 02:59:27 PM PDT 24
Peak memory 207556 kb
Host smart-8ff49d3a-6c7d-4ed9-9c91-f109b300abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843659082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2843659082
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1690998942
Short name T366
Test name
Test status
Simulation time 106109685 ps
CPU time 1.9 seconds
Started Jun 02 02:59:21 PM PDT 24
Finished Jun 02 02:59:23 PM PDT 24
Peak memory 209936 kb
Host smart-cd9bab42-764e-45c7-9921-a8f3de88bdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690998942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1690998942
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1683691394
Short name T676
Test name
Test status
Simulation time 15160573 ps
CPU time 0.92 seconds
Started Jun 02 02:59:43 PM PDT 24
Finished Jun 02 02:59:44 PM PDT 24
Peak memory 206044 kb
Host smart-af4dc09f-9c4d-46a7-8a1f-5403d7f5a496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683691394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1683691394
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2134129651
Short name T388
Test name
Test status
Simulation time 388178962 ps
CPU time 5.86 seconds
Started Jun 02 02:59:25 PM PDT 24
Finished Jun 02 02:59:32 PM PDT 24
Peak memory 214296 kb
Host smart-d51fe17e-4dc5-4d34-8d08-e0cd91ff9a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134129651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2134129651
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3505859776
Short name T654
Test name
Test status
Simulation time 284716100 ps
CPU time 3.44 seconds
Started Jun 02 02:59:40 PM PDT 24
Finished Jun 02 02:59:44 PM PDT 24
Peak memory 214344 kb
Host smart-f3e6b5d0-430a-46bc-836f-2f4696581820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505859776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3505859776
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3256175385
Short name T286
Test name
Test status
Simulation time 160282718 ps
CPU time 2.59 seconds
Started Jun 02 02:59:40 PM PDT 24
Finished Jun 02 02:59:43 PM PDT 24
Peak memory 214352 kb
Host smart-32390059-0ee0-4a0e-b755-bc1fbc32bfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256175385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3256175385
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1355612154
Short name T667
Test name
Test status
Simulation time 295940409 ps
CPU time 2.89 seconds
Started Jun 02 02:59:30 PM PDT 24
Finished Jun 02 02:59:34 PM PDT 24
Peak memory 214312 kb
Host smart-c34e3905-d610-43c3-b458-591fe183030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355612154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1355612154
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1238395082
Short name T774
Test name
Test status
Simulation time 770890338 ps
CPU time 4.13 seconds
Started Jun 02 02:59:26 PM PDT 24
Finished Jun 02 02:59:30 PM PDT 24
Peak memory 214408 kb
Host smart-349b7c8e-5ac7-4c92-9115-d7875de16710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238395082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1238395082
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.213189911
Short name T563
Test name
Test status
Simulation time 87359502 ps
CPU time 2.79 seconds
Started Jun 02 02:59:26 PM PDT 24
Finished Jun 02 02:59:29 PM PDT 24
Peak memory 206916 kb
Host smart-3ceaed49-7870-4352-b122-878ba1d9f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213189911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.213189911
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1427205139
Short name T669
Test name
Test status
Simulation time 1906754897 ps
CPU time 46.63 seconds
Started Jun 02 02:59:28 PM PDT 24
Finished Jun 02 03:00:15 PM PDT 24
Peak memory 208500 kb
Host smart-b8afd6a2-6474-43a5-8dcc-421bb9897aba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427205139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1427205139
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1771546083
Short name T470
Test name
Test status
Simulation time 125054758 ps
CPU time 3.16 seconds
Started Jun 02 02:59:28 PM PDT 24
Finished Jun 02 02:59:31 PM PDT 24
Peak memory 206952 kb
Host smart-f2589e91-0f40-47f8-bdb8-ee3ce675852a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771546083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1771546083
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3450094048
Short name T802
Test name
Test status
Simulation time 795976303 ps
CPU time 21.3 seconds
Started Jun 02 02:59:25 PM PDT 24
Finished Jun 02 02:59:47 PM PDT 24
Peak memory 208752 kb
Host smart-92505c58-1fc5-43b9-b521-22942bdb936e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450094048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3450094048
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3263385163
Short name T198
Test name
Test status
Simulation time 547088041 ps
CPU time 2.67 seconds
Started Jun 02 02:59:39 PM PDT 24
Finished Jun 02 02:59:42 PM PDT 24
Peak memory 214344 kb
Host smart-cb6b9325-49ba-4f1b-a97b-fa716156b1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263385163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3263385163
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3463196718
Short name T1
Test name
Test status
Simulation time 11131753852 ps
CPU time 50.57 seconds
Started Jun 02 02:59:26 PM PDT 24
Finished Jun 02 03:00:17 PM PDT 24
Peak memory 208632 kb
Host smart-3efe76ab-2d89-4792-a699-cb18443571f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463196718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3463196718
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.151105442
Short name T212
Test name
Test status
Simulation time 2267825465 ps
CPU time 31.27 seconds
Started Jun 02 02:59:38 PM PDT 24
Finished Jun 02 03:00:09 PM PDT 24
Peak memory 216052 kb
Host smart-4397e9da-4585-49a8-bb9f-236f729f67ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151105442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.151105442
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2077646048
Short name T162
Test name
Test status
Simulation time 102486598 ps
CPU time 2.46 seconds
Started Jun 02 02:59:40 PM PDT 24
Finished Jun 02 02:59:43 PM PDT 24
Peak memory 209904 kb
Host smart-ad19ceea-d37d-44a7-a18d-cbb7f0b2a07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077646048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2077646048
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3613482182
Short name T637
Test name
Test status
Simulation time 53489203 ps
CPU time 0.92 seconds
Started Jun 02 03:01:11 PM PDT 24
Finished Jun 02 03:01:13 PM PDT 24
Peak memory 206028 kb
Host smart-19a31ce7-e53d-4667-9511-1fff658d8fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613482182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3613482182
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2907935002
Short name T428
Test name
Test status
Simulation time 87467216 ps
CPU time 3.6 seconds
Started Jun 02 03:01:10 PM PDT 24
Finished Jun 02 03:01:15 PM PDT 24
Peak memory 208468 kb
Host smart-4003e3c9-d6cb-485f-9dd9-b7da4c47f17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907935002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2907935002
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3774323037
Short name T49
Test name
Test status
Simulation time 540132296 ps
CPU time 2.22 seconds
Started Jun 02 03:01:04 PM PDT 24
Finished Jun 02 03:01:07 PM PDT 24
Peak memory 209760 kb
Host smart-af4953a5-2a11-43db-8d7b-dd66d59d0544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774323037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3774323037
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3846193390
Short name T89
Test name
Test status
Simulation time 35353055 ps
CPU time 2.44 seconds
Started Jun 02 03:01:11 PM PDT 24
Finished Jun 02 03:01:14 PM PDT 24
Peak memory 214324 kb
Host smart-e6a88537-34b5-47f4-b831-8a37800e438f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846193390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3846193390
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1466391158
Short name T550
Test name
Test status
Simulation time 133734410 ps
CPU time 3.39 seconds
Started Jun 02 03:01:04 PM PDT 24
Finished Jun 02 03:01:08 PM PDT 24
Peak memory 214324 kb
Host smart-e8ad5d3e-6cda-4458-ab52-a51d4d6d5751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466391158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1466391158
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.636345960
Short name T187
Test name
Test status
Simulation time 62676217 ps
CPU time 4.11 seconds
Started Jun 02 03:01:03 PM PDT 24
Finished Jun 02 03:01:08 PM PDT 24
Peak memory 218284 kb
Host smart-d4ab1cdc-65fd-4358-bbc9-3088eea763f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636345960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.636345960
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1851699829
Short name T385
Test name
Test status
Simulation time 380087388 ps
CPU time 4.72 seconds
Started Jun 02 03:01:05 PM PDT 24
Finished Jun 02 03:01:10 PM PDT 24
Peak memory 206852 kb
Host smart-3bd0d264-455e-4c52-9a43-3ea27c3857bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851699829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1851699829
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2415859944
Short name T816
Test name
Test status
Simulation time 60143257 ps
CPU time 2.96 seconds
Started Jun 02 03:01:03 PM PDT 24
Finished Jun 02 03:01:07 PM PDT 24
Peak memory 207520 kb
Host smart-f754cdfc-d6cc-4d68-92f5-732f3b2a95dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415859944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2415859944
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.246962500
Short name T387
Test name
Test status
Simulation time 55796988 ps
CPU time 3.01 seconds
Started Jun 02 03:01:04 PM PDT 24
Finished Jun 02 03:01:08 PM PDT 24
Peak memory 209080 kb
Host smart-62a5c659-edb3-4cb8-a144-c9bd505d0c8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246962500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.246962500
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3081858730
Short name T101
Test name
Test status
Simulation time 476661750 ps
CPU time 4.36 seconds
Started Jun 02 03:01:04 PM PDT 24
Finished Jun 02 03:01:10 PM PDT 24
Peak memory 207072 kb
Host smart-50e582c3-cf01-46bf-8dd9-a0812bdb1101
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081858730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3081858730
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3433030523
Short name T869
Test name
Test status
Simulation time 437412890 ps
CPU time 2.56 seconds
Started Jun 02 03:01:13 PM PDT 24
Finished Jun 02 03:01:16 PM PDT 24
Peak memory 207680 kb
Host smart-ab4adb1e-fbd5-4365-9ec4-a7e49c7532fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433030523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3433030523
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.904630329
Short name T670
Test name
Test status
Simulation time 153985809 ps
CPU time 3.88 seconds
Started Jun 02 03:01:03 PM PDT 24
Finished Jun 02 03:01:08 PM PDT 24
Peak memory 207268 kb
Host smart-fcdccf56-994c-4037-8e21-2cb7b4fc8d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904630329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.904630329
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1319031695
Short name T827
Test name
Test status
Simulation time 1599351341 ps
CPU time 9.46 seconds
Started Jun 02 03:01:10 PM PDT 24
Finished Jun 02 03:01:20 PM PDT 24
Peak memory 222560 kb
Host smart-4ea05412-16c9-43bf-9d66-411aa8b7d505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319031695 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1319031695
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1840544773
Short name T627
Test name
Test status
Simulation time 302768766 ps
CPU time 4.79 seconds
Started Jun 02 03:01:05 PM PDT 24
Finished Jun 02 03:01:10 PM PDT 24
Peak memory 209780 kb
Host smart-42b42baf-d298-4ccb-b012-6d26132a1094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840544773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1840544773
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3807809342
Short name T888
Test name
Test status
Simulation time 184564378 ps
CPU time 2.49 seconds
Started Jun 02 03:01:11 PM PDT 24
Finished Jun 02 03:01:14 PM PDT 24
Peak memory 210480 kb
Host smart-5400c15b-450f-4912-96e0-fe674c51a86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807809342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3807809342
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1743493849
Short name T596
Test name
Test status
Simulation time 15518213 ps
CPU time 0.81 seconds
Started Jun 02 03:01:19 PM PDT 24
Finished Jun 02 03:01:20 PM PDT 24
Peak memory 205912 kb
Host smart-436f0cc9-b48c-45c2-93c6-33771d5964af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743493849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1743493849
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2053793174
Short name T274
Test name
Test status
Simulation time 175726025 ps
CPU time 9.31 seconds
Started Jun 02 03:01:15 PM PDT 24
Finished Jun 02 03:01:25 PM PDT 24
Peak memory 222388 kb
Host smart-cf85f833-4e1c-432f-a8d0-b3342a61d6d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2053793174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2053793174
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.711153314
Short name T348
Test name
Test status
Simulation time 161752840 ps
CPU time 3.15 seconds
Started Jun 02 03:01:17 PM PDT 24
Finished Jun 02 03:01:21 PM PDT 24
Peak memory 208104 kb
Host smart-1b6f08e6-7d92-4f94-8a48-882ea7763224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711153314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.711153314
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2216758216
Short name T864
Test name
Test status
Simulation time 57967634 ps
CPU time 2.07 seconds
Started Jun 02 03:01:16 PM PDT 24
Finished Jun 02 03:01:18 PM PDT 24
Peak memory 214500 kb
Host smart-8ed73cba-5b90-459f-9ac0-67c9f9f60529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216758216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2216758216
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1107041977
Short name T549
Test name
Test status
Simulation time 84898594 ps
CPU time 2.41 seconds
Started Jun 02 03:01:18 PM PDT 24
Finished Jun 02 03:01:20 PM PDT 24
Peak memory 209568 kb
Host smart-d6f240af-82cb-4831-8d98-ad8ab180021c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107041977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1107041977
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.674955993
Short name T288
Test name
Test status
Simulation time 1133285055 ps
CPU time 7.59 seconds
Started Jun 02 03:01:17 PM PDT 24
Finished Jun 02 03:01:25 PM PDT 24
Peak memory 214300 kb
Host smart-a2820fcb-784f-48bc-ba39-a9df7f3500a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674955993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.674955993
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.377180784
Short name T755
Test name
Test status
Simulation time 70696672 ps
CPU time 3.29 seconds
Started Jun 02 03:01:10 PM PDT 24
Finished Jun 02 03:01:14 PM PDT 24
Peak memory 208552 kb
Host smart-c564c6ed-efe1-4aa5-8ddf-45e603c639f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377180784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.377180784
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.790606921
Short name T719
Test name
Test status
Simulation time 1302560193 ps
CPU time 6.26 seconds
Started Jun 02 03:01:18 PM PDT 24
Finished Jun 02 03:01:25 PM PDT 24
Peak memory 208132 kb
Host smart-db28a2df-ce3b-4ea9-8c01-cf646efddd9d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790606921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.790606921
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1646957534
Short name T898
Test name
Test status
Simulation time 64945362 ps
CPU time 3.25 seconds
Started Jun 02 03:01:13 PM PDT 24
Finished Jun 02 03:01:16 PM PDT 24
Peak memory 207492 kb
Host smart-afa2200b-9bc3-425b-87b4-c204fce2dbcd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646957534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1646957534
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1655382956
Short name T778
Test name
Test status
Simulation time 80925191 ps
CPU time 4.03 seconds
Started Jun 02 03:01:21 PM PDT 24
Finished Jun 02 03:01:25 PM PDT 24
Peak memory 208824 kb
Host smart-f562ffa5-2c2c-40f5-9523-60cb7aadc1c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655382956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1655382956
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.434490518
Short name T759
Test name
Test status
Simulation time 29445255 ps
CPU time 2.46 seconds
Started Jun 02 03:01:18 PM PDT 24
Finished Jun 02 03:01:21 PM PDT 24
Peak memory 209844 kb
Host smart-3366c699-7b04-471f-a4be-f9992f8b71db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434490518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.434490518
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.503148836
Short name T879
Test name
Test status
Simulation time 807542093 ps
CPU time 19.88 seconds
Started Jun 02 03:01:11 PM PDT 24
Finished Jun 02 03:01:31 PM PDT 24
Peak memory 207728 kb
Host smart-cec54efe-1673-42df-b9b4-4a8e15b027a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503148836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.503148836
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.960143673
Short name T323
Test name
Test status
Simulation time 204160793 ps
CPU time 7.56 seconds
Started Jun 02 03:01:16 PM PDT 24
Finished Jun 02 03:01:24 PM PDT 24
Peak memory 210500 kb
Host smart-2b357cb8-ed84-4650-949c-054d6ada0573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960143673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.960143673
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.942718098
Short name T850
Test name
Test status
Simulation time 104274567 ps
CPU time 2.42 seconds
Started Jun 02 03:01:22 PM PDT 24
Finished Jun 02 03:01:25 PM PDT 24
Peak memory 222572 kb
Host smart-27db70ba-dba7-4dca-90fc-625c3657bc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942718098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.942718098
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3593875734
Short name T270
Test name
Test status
Simulation time 215376249 ps
CPU time 5.03 seconds
Started Jun 02 03:01:25 PM PDT 24
Finished Jun 02 03:01:31 PM PDT 24
Peak memory 214232 kb
Host smart-cb0e39c0-a915-4f0b-b6fd-f533128d9e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593875734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3593875734
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2307828071
Short name T426
Test name
Test status
Simulation time 33284544 ps
CPU time 2.18 seconds
Started Jun 02 03:01:23 PM PDT 24
Finished Jun 02 03:01:25 PM PDT 24
Peak memory 216824 kb
Host smart-08011531-3307-4a02-9bce-6efaccbcede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307828071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2307828071
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.96982921
Short name T623
Test name
Test status
Simulation time 975718367 ps
CPU time 6 seconds
Started Jun 02 03:01:23 PM PDT 24
Finished Jun 02 03:01:29 PM PDT 24
Peak memory 209828 kb
Host smart-c6b90b18-aed3-4d28-b342-9a2ab4971cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96982921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.96982921
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.957582022
Short name T601
Test name
Test status
Simulation time 863689573 ps
CPU time 19.78 seconds
Started Jun 02 03:01:16 PM PDT 24
Finished Jun 02 03:01:37 PM PDT 24
Peak memory 208244 kb
Host smart-2f18a1be-7a7f-4698-9fc3-1e73506663cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957582022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.957582022
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2581276015
Short name T699
Test name
Test status
Simulation time 40371546 ps
CPU time 1.82 seconds
Started Jun 02 03:01:23 PM PDT 24
Finished Jun 02 03:01:26 PM PDT 24
Peak memory 206972 kb
Host smart-b48ed7c1-07ea-4e92-9aa4-4748f00e7b3a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581276015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2581276015
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.653258925
Short name T839
Test name
Test status
Simulation time 395822266 ps
CPU time 3.62 seconds
Started Jun 02 03:01:18 PM PDT 24
Finished Jun 02 03:01:22 PM PDT 24
Peak memory 206912 kb
Host smart-4f9f50f2-96e4-4e2c-9d55-69404878c7ce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653258925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.653258925
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2890233252
Short name T86
Test name
Test status
Simulation time 192133050 ps
CPU time 3.36 seconds
Started Jun 02 03:01:22 PM PDT 24
Finished Jun 02 03:01:26 PM PDT 24
Peak memory 206924 kb
Host smart-704eee22-9877-4e57-a047-00b09c78e6df
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890233252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2890233252
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.445804520
Short name T537
Test name
Test status
Simulation time 91270572 ps
CPU time 1.78 seconds
Started Jun 02 03:01:30 PM PDT 24
Finished Jun 02 03:01:32 PM PDT 24
Peak memory 206788 kb
Host smart-a05c28ea-74cd-447e-8350-78b19ddf6ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445804520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.445804520
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1743212157
Short name T484
Test name
Test status
Simulation time 210345073 ps
CPU time 2.59 seconds
Started Jun 02 03:01:18 PM PDT 24
Finished Jun 02 03:01:22 PM PDT 24
Peak memory 208312 kb
Host smart-aba8961c-9955-4c4b-a7e9-33d62c37b2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743212157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1743212157
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1392062491
Short name T326
Test name
Test status
Simulation time 1553121713 ps
CPU time 31.74 seconds
Started Jun 02 03:01:28 PM PDT 24
Finished Jun 02 03:02:00 PM PDT 24
Peak memory 217044 kb
Host smart-678989be-e435-4dd9-bcb4-9af23fc3c099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392062491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1392062491
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2734572956
Short name T768
Test name
Test status
Simulation time 495187666 ps
CPU time 5.1 seconds
Started Jun 02 03:01:25 PM PDT 24
Finished Jun 02 03:01:31 PM PDT 24
Peak memory 209696 kb
Host smart-c18da274-7a58-4dfb-bd3d-5d4e822e3cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734572956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2734572956
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.756523648
Short name T126
Test name
Test status
Simulation time 157512453 ps
CPU time 3.19 seconds
Started Jun 02 03:01:29 PM PDT 24
Finished Jun 02 03:01:32 PM PDT 24
Peak memory 210388 kb
Host smart-f8b537ae-10e4-479e-9d01-4b6cecefad75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756523648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.756523648
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2111398719
Short name T766
Test name
Test status
Simulation time 16130211 ps
CPU time 0.98 seconds
Started Jun 02 03:01:39 PM PDT 24
Finished Jun 02 03:01:40 PM PDT 24
Peak memory 206148 kb
Host smart-9bb98012-6fc3-40ce-9c62-e1fe06e57769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111398719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2111398719
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2790000674
Short name T391
Test name
Test status
Simulation time 96400478 ps
CPU time 4.74 seconds
Started Jun 02 03:01:28 PM PDT 24
Finished Jun 02 03:01:33 PM PDT 24
Peak memory 215052 kb
Host smart-86941281-8bf1-425a-9b34-15b8f29fc307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790000674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2790000674
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2321445019
Short name T865
Test name
Test status
Simulation time 86773357 ps
CPU time 3.83 seconds
Started Jun 02 03:01:41 PM PDT 24
Finished Jun 02 03:01:45 PM PDT 24
Peak memory 218504 kb
Host smart-6ea1a373-6c0e-4492-9ba2-19c9f7965fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321445019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2321445019
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.672042910
Short name T418
Test name
Test status
Simulation time 95978538 ps
CPU time 2.65 seconds
Started Jun 02 03:01:29 PM PDT 24
Finished Jun 02 03:01:32 PM PDT 24
Peak memory 218372 kb
Host smart-00815390-359d-4a68-bbf8-8e9357b3bdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672042910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.672042910
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3194783506
Short name T600
Test name
Test status
Simulation time 129091059 ps
CPU time 3.84 seconds
Started Jun 02 03:01:35 PM PDT 24
Finished Jun 02 03:01:39 PM PDT 24
Peak memory 215196 kb
Host smart-e689098b-c60c-48f9-9853-6d2dfac1b6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194783506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3194783506
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1003591766
Short name T268
Test name
Test status
Simulation time 91628632 ps
CPU time 3.77 seconds
Started Jun 02 03:01:36 PM PDT 24
Finished Jun 02 03:01:41 PM PDT 24
Peak memory 214188 kb
Host smart-f724f1f1-e386-41be-8023-ab9459aad27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003591766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1003591766
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.2322968763
Short name T494
Test name
Test status
Simulation time 1434167002 ps
CPU time 32.88 seconds
Started Jun 02 03:01:28 PM PDT 24
Finished Jun 02 03:02:02 PM PDT 24
Peak memory 208116 kb
Host smart-f8706252-863e-443f-a0f2-197c565b1c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322968763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2322968763
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2626339080
Short name T229
Test name
Test status
Simulation time 606897469 ps
CPU time 6.68 seconds
Started Jun 02 03:01:28 PM PDT 24
Finished Jun 02 03:01:36 PM PDT 24
Peak memory 206868 kb
Host smart-b5fa9e3f-8271-4b02-9ec1-7e8228f3c584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626339080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2626339080
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1415404297
Short name T630
Test name
Test status
Simulation time 118045900 ps
CPU time 3.74 seconds
Started Jun 02 03:01:28 PM PDT 24
Finished Jun 02 03:01:32 PM PDT 24
Peak memory 206916 kb
Host smart-fc6a9182-f6a7-4503-b207-2904457fdfa7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415404297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1415404297
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2467335236
Short name T612
Test name
Test status
Simulation time 321728030 ps
CPU time 4.46 seconds
Started Jun 02 03:01:29 PM PDT 24
Finished Jun 02 03:01:34 PM PDT 24
Peak memory 208028 kb
Host smart-b153d0e8-64ed-4473-b484-b5fef689d114
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467335236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2467335236
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1230513891
Short name T543
Test name
Test status
Simulation time 835851654 ps
CPU time 6.45 seconds
Started Jun 02 03:01:35 PM PDT 24
Finished Jun 02 03:01:42 PM PDT 24
Peak memory 208716 kb
Host smart-33bf7a90-bc0c-460a-9ec7-0fed4b330bab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230513891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1230513891
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.4182718547
Short name T710
Test name
Test status
Simulation time 232628140 ps
CPU time 5.44 seconds
Started Jun 02 03:01:36 PM PDT 24
Finished Jun 02 03:01:42 PM PDT 24
Peak memory 208236 kb
Host smart-f76e342c-e056-4c4c-8c08-1801f799b73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182718547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.4182718547
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.106046493
Short name T571
Test name
Test status
Simulation time 3930298693 ps
CPU time 19.53 seconds
Started Jun 02 03:01:29 PM PDT 24
Finished Jun 02 03:01:49 PM PDT 24
Peak memory 207848 kb
Host smart-6d741243-edba-44fd-a35b-a2c43e5f6a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106046493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.106046493
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1717201680
Short name T76
Test name
Test status
Simulation time 18361087545 ps
CPU time 98.1 seconds
Started Jun 02 03:01:37 PM PDT 24
Finished Jun 02 03:03:15 PM PDT 24
Peak memory 216132 kb
Host smart-cb6094c8-b070-4c15-9980-43357c835e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717201680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1717201680
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3818775594
Short name T724
Test name
Test status
Simulation time 87836236 ps
CPU time 4.03 seconds
Started Jun 02 03:01:38 PM PDT 24
Finished Jun 02 03:01:42 PM PDT 24
Peak memory 209124 kb
Host smart-b9564552-8a77-4906-a290-b50f96f0ef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818775594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3818775594
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3050754934
Short name T66
Test name
Test status
Simulation time 364337315 ps
CPU time 3.86 seconds
Started Jun 02 03:01:35 PM PDT 24
Finished Jun 02 03:01:39 PM PDT 24
Peak memory 210008 kb
Host smart-8933c9c3-6a78-45e0-99ec-d36e5645c4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050754934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3050754934
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1668663741
Short name T524
Test name
Test status
Simulation time 10397854 ps
CPU time 0.84 seconds
Started Jun 02 03:01:54 PM PDT 24
Finished Jun 02 03:01:55 PM PDT 24
Peak memory 205928 kb
Host smart-78a18a24-6df8-4427-9be6-263c6b01abf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668663741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1668663741
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3687613447
Short name T570
Test name
Test status
Simulation time 36982787 ps
CPU time 1.41 seconds
Started Jun 02 03:01:51 PM PDT 24
Finished Jun 02 03:01:53 PM PDT 24
Peak memory 208400 kb
Host smart-fa23ccb7-8c6a-40e9-a1f2-38d41c050e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687613447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3687613447
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2725721177
Short name T462
Test name
Test status
Simulation time 21441568 ps
CPU time 1.7 seconds
Started Jun 02 03:01:39 PM PDT 24
Finished Jun 02 03:01:41 PM PDT 24
Peak memory 210024 kb
Host smart-69e684de-b88f-4328-b304-d950bb57ad4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725721177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2725721177
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2006616182
Short name T221
Test name
Test status
Simulation time 2269704549 ps
CPU time 43.01 seconds
Started Jun 02 03:01:36 PM PDT 24
Finished Jun 02 03:02:19 PM PDT 24
Peak memory 214276 kb
Host smart-dfe6c2e3-9b5d-4f95-a50f-6929e2bf00dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006616182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2006616182
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_random.3617654286
Short name T666
Test name
Test status
Simulation time 136671799 ps
CPU time 3.47 seconds
Started Jun 02 03:01:38 PM PDT 24
Finished Jun 02 03:01:42 PM PDT 24
Peak memory 207364 kb
Host smart-a451f609-2518-4c59-93a5-ff215850afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617654286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3617654286
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1486746144
Short name T585
Test name
Test status
Simulation time 19689121 ps
CPU time 1.75 seconds
Started Jun 02 03:01:38 PM PDT 24
Finished Jun 02 03:01:40 PM PDT 24
Peak memory 206752 kb
Host smart-159e21c3-5064-4c34-9648-844159b51ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486746144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1486746144
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1399518515
Short name T886
Test name
Test status
Simulation time 183088445 ps
CPU time 5.99 seconds
Started Jun 02 03:01:40 PM PDT 24
Finished Jun 02 03:01:46 PM PDT 24
Peak memory 208208 kb
Host smart-0fe2e138-52f2-4a5d-9546-da402708b7a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399518515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1399518515
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.825087288
Short name T562
Test name
Test status
Simulation time 74400538 ps
CPU time 1.78 seconds
Started Jun 02 03:01:39 PM PDT 24
Finished Jun 02 03:01:41 PM PDT 24
Peak memory 206772 kb
Host smart-8ab6a233-2549-4dee-93e8-93ee32d54032
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825087288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.825087288
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2150563578
Short name T852
Test name
Test status
Simulation time 362186888 ps
CPU time 5.85 seconds
Started Jun 02 03:01:36 PM PDT 24
Finished Jun 02 03:01:42 PM PDT 24
Peak memory 208476 kb
Host smart-6c9bc8da-88d0-42fe-8651-07dbf6f010b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150563578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2150563578
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1335711860
Short name T894
Test name
Test status
Simulation time 998481121 ps
CPU time 16.49 seconds
Started Jun 02 03:01:54 PM PDT 24
Finished Jun 02 03:02:11 PM PDT 24
Peak memory 209672 kb
Host smart-77864e85-5f04-4d66-95c0-29e88a6dac8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335711860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1335711860
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3076707283
Short name T557
Test name
Test status
Simulation time 641822692 ps
CPU time 3.93 seconds
Started Jun 02 03:01:36 PM PDT 24
Finished Jun 02 03:01:41 PM PDT 24
Peak memory 206824 kb
Host smart-7b552702-1a09-48a4-bdb8-703efeaac2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076707283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3076707283
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1207820234
Short name T469
Test name
Test status
Simulation time 1544839705 ps
CPU time 15.93 seconds
Started Jun 02 03:01:53 PM PDT 24
Finished Jun 02 03:02:10 PM PDT 24
Peak memory 220868 kb
Host smart-4454266d-0ff6-4dc5-91a5-a039491a694a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207820234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1207820234
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1763388857
Short name T190
Test name
Test status
Simulation time 4041568921 ps
CPU time 27.88 seconds
Started Jun 02 03:01:37 PM PDT 24
Finished Jun 02 03:02:05 PM PDT 24
Peak memory 209688 kb
Host smart-e649b5f7-8a73-443a-80b3-56d0e113aabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763388857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1763388857
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.262045072
Short name T367
Test name
Test status
Simulation time 211088801 ps
CPU time 2.44 seconds
Started Jun 02 03:01:52 PM PDT 24
Finished Jun 02 03:01:55 PM PDT 24
Peak memory 210968 kb
Host smart-39161a69-f9b9-4b99-8654-3ba680c642fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262045072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.262045072
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2707954915
Short name T471
Test name
Test status
Simulation time 15843565 ps
CPU time 1 seconds
Started Jun 02 03:02:00 PM PDT 24
Finished Jun 02 03:02:02 PM PDT 24
Peak memory 206036 kb
Host smart-234ffeb5-0530-4b46-a155-442128ec4bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707954915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2707954915
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1017013786
Short name T330
Test name
Test status
Simulation time 185658307 ps
CPU time 5.65 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:02:02 PM PDT 24
Peak memory 214292 kb
Host smart-bb832b50-7821-4660-98bc-b197ac94d553
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017013786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1017013786
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.183207924
Short name T555
Test name
Test status
Simulation time 97069897 ps
CPU time 4.59 seconds
Started Jun 02 03:01:56 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 209188 kb
Host smart-3cc08a85-ead5-4df6-9e02-faf812396753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183207924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.183207924
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.206085600
Short name T741
Test name
Test status
Simulation time 1863522779 ps
CPU time 19.45 seconds
Started Jun 02 03:01:56 PM PDT 24
Finished Jun 02 03:02:16 PM PDT 24
Peak memory 208252 kb
Host smart-280d0d98-1a7c-415c-8a59-6ac697a95d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206085600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.206085600
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3226369302
Short name T96
Test name
Test status
Simulation time 293400840 ps
CPU time 3.83 seconds
Started Jun 02 03:01:58 PM PDT 24
Finished Jun 02 03:02:03 PM PDT 24
Peak memory 209032 kb
Host smart-de4435b5-a451-4f16-ba78-a10742b545bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226369302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3226369302
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_random.2251429222
Short name T675
Test name
Test status
Simulation time 224509770 ps
CPU time 5.12 seconds
Started Jun 02 03:01:53 PM PDT 24
Finished Jun 02 03:01:59 PM PDT 24
Peak memory 208968 kb
Host smart-cfc00c20-85c8-48e5-83c3-5489c1c8cf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251429222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2251429222
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.4136111744
Short name T360
Test name
Test status
Simulation time 103878258 ps
CPU time 2.75 seconds
Started Jun 02 03:01:54 PM PDT 24
Finished Jun 02 03:01:57 PM PDT 24
Peak memory 208688 kb
Host smart-4db9294a-7756-43d0-9e17-ebd34268c868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136111744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.4136111744
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.478016768
Short name T423
Test name
Test status
Simulation time 3845099905 ps
CPU time 6.37 seconds
Started Jun 02 03:01:51 PM PDT 24
Finished Jun 02 03:01:58 PM PDT 24
Peak memory 209056 kb
Host smart-1ff8835f-65f9-4407-a840-e2cff2214cb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478016768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.478016768
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3756706805
Short name T276
Test name
Test status
Simulation time 128776830 ps
CPU time 2.96 seconds
Started Jun 02 03:01:54 PM PDT 24
Finished Jun 02 03:01:57 PM PDT 24
Peak memory 208700 kb
Host smart-39f61f2d-078f-4b29-a7d9-595736d16e88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756706805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3756706805
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3231874935
Short name T237
Test name
Test status
Simulation time 266108627 ps
CPU time 7.9 seconds
Started Jun 02 03:01:52 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 208724 kb
Host smart-23ac6e57-0e1f-4f2e-bad2-dd8482620003
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231874935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3231874935
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_smoke.833386062
Short name T602
Test name
Test status
Simulation time 238097974 ps
CPU time 3.04 seconds
Started Jun 02 03:01:54 PM PDT 24
Finished Jun 02 03:01:58 PM PDT 24
Peak memory 208316 kb
Host smart-ca42554f-7580-49de-99c9-78d889207987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833386062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.833386062
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.863532541
Short name T210
Test name
Test status
Simulation time 4567453593 ps
CPU time 50.33 seconds
Started Jun 02 03:01:57 PM PDT 24
Finished Jun 02 03:02:49 PM PDT 24
Peak memory 217700 kb
Host smart-8283bdcb-d963-4bad-8cb5-e3a4deaa45fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863532541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.863532541
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2496069403
Short name T633
Test name
Test status
Simulation time 1425543166 ps
CPU time 39.69 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:02:35 PM PDT 24
Peak memory 210664 kb
Host smart-168484bb-fbf8-4940-91a1-30c25c2c2e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496069403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2496069403
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.482993172
Short name T826
Test name
Test status
Simulation time 57600085 ps
CPU time 1.87 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:01:57 PM PDT 24
Peak memory 209808 kb
Host smart-5a7147ad-c974-447d-9ce5-b6bed796a929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482993172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.482993172
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3271151477
Short name T828
Test name
Test status
Simulation time 26309057 ps
CPU time 0.92 seconds
Started Jun 02 03:01:56 PM PDT 24
Finished Jun 02 03:01:58 PM PDT 24
Peak memory 206084 kb
Host smart-d6294893-3c06-474c-9667-a8e525847f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271151477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3271151477
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2005469930
Short name T371
Test name
Test status
Simulation time 436223592 ps
CPU time 4.23 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:02:00 PM PDT 24
Peak memory 214236 kb
Host smart-05f21382-1808-45dc-8823-8539eabc9a8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005469930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2005469930
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3758452986
Short name T561
Test name
Test status
Simulation time 349741206 ps
CPU time 1.93 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:01:58 PM PDT 24
Peak memory 208412 kb
Host smart-c4f1142e-24db-43ae-83b5-56dab50846ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758452986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3758452986
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.181261670
Short name T679
Test name
Test status
Simulation time 226424375 ps
CPU time 2.5 seconds
Started Jun 02 03:01:56 PM PDT 24
Finished Jun 02 03:01:59 PM PDT 24
Peak memory 214264 kb
Host smart-7d219ee2-a6b1-4d36-8ac9-ca21ac4a4c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181261670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.181261670
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.4260629316
Short name T39
Test name
Test status
Simulation time 99888288 ps
CPU time 4.44 seconds
Started Jun 02 03:02:00 PM PDT 24
Finished Jun 02 03:02:06 PM PDT 24
Peak memory 222336 kb
Host smart-14b93f78-3227-479a-84b7-98c850176099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260629316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.4260629316
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3977622674
Short name T46
Test name
Test status
Simulation time 268880875 ps
CPU time 3.84 seconds
Started Jun 02 03:01:57 PM PDT 24
Finished Jun 02 03:02:02 PM PDT 24
Peak memory 209612 kb
Host smart-4531b3f1-d7dd-46e6-9797-cef263085d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977622674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3977622674
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2949840578
Short name T854
Test name
Test status
Simulation time 529823967 ps
CPU time 7.3 seconds
Started Jun 02 03:01:59 PM PDT 24
Finished Jun 02 03:02:07 PM PDT 24
Peak memory 210176 kb
Host smart-43e94f92-c9c7-43ae-a5a7-f3588c557454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949840578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2949840578
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3902432135
Short name T422
Test name
Test status
Simulation time 140332939 ps
CPU time 4.27 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 208592 kb
Host smart-f1ac8d0f-7644-4e3b-8149-9f062586ce0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902432135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3902432135
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1170290714
Short name T346
Test name
Test status
Simulation time 55437576 ps
CPU time 3.19 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:01:58 PM PDT 24
Peak memory 207236 kb
Host smart-c27e21fd-ee6e-4db9-ba39-a9b8d57630c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170290714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1170290714
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1563414898
Short name T546
Test name
Test status
Simulation time 459809613 ps
CPU time 5.07 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 208720 kb
Host smart-d5d6a906-7f38-4a2d-9b5d-bf22ad9b924e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563414898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1563414898
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.450137763
Short name T574
Test name
Test status
Simulation time 145409909 ps
CPU time 4.15 seconds
Started Jun 02 03:01:57 PM PDT 24
Finished Jun 02 03:02:02 PM PDT 24
Peak memory 208552 kb
Host smart-d406f52e-0aeb-49ba-894c-ad95fd75867e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450137763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.450137763
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2304493854
Short name T458
Test name
Test status
Simulation time 292110851 ps
CPU time 3.42 seconds
Started Jun 02 03:01:59 PM PDT 24
Finished Jun 02 03:02:03 PM PDT 24
Peak memory 209348 kb
Host smart-aa1e969a-9592-4df8-a24f-910c49ec9e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304493854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2304493854
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2581647779
Short name T740
Test name
Test status
Simulation time 25862161 ps
CPU time 1.95 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:01:57 PM PDT 24
Peak memory 207360 kb
Host smart-59b85114-6ba4-45c3-9762-8bd68eb10750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581647779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2581647779
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2631109058
Short name T910
Test name
Test status
Simulation time 387323947 ps
CPU time 4.33 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 208664 kb
Host smart-b93486c1-e66d-48fd-ad55-ddead8871ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631109058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2631109058
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1833752961
Short name T504
Test name
Test status
Simulation time 28551568 ps
CPU time 0.94 seconds
Started Jun 02 03:02:03 PM PDT 24
Finished Jun 02 03:02:04 PM PDT 24
Peak memory 205944 kb
Host smart-bf3ba118-c168-4a69-b433-398782e6d920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833752961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1833752961
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3316101472
Short name T263
Test name
Test status
Simulation time 123503957 ps
CPU time 4.28 seconds
Started Jun 02 03:02:00 PM PDT 24
Finished Jun 02 03:02:05 PM PDT 24
Peak memory 208252 kb
Host smart-c1d86383-08cb-4f62-9c24-ec989e55dcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316101472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3316101472
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2551829916
Short name T515
Test name
Test status
Simulation time 146062893 ps
CPU time 2.11 seconds
Started Jun 02 03:01:58 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 214356 kb
Host smart-812721a6-fe0d-447c-8dbe-3dd3620c3ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551829916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2551829916
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.916651889
Short name T849
Test name
Test status
Simulation time 230465379 ps
CPU time 3.51 seconds
Started Jun 02 03:01:56 PM PDT 24
Finished Jun 02 03:02:00 PM PDT 24
Peak memory 208296 kb
Host smart-290302da-2dcb-43da-bb33-315c90ddfc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916651889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.916651889
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3761153601
Short name T392
Test name
Test status
Simulation time 920040249 ps
CPU time 22.95 seconds
Started Jun 02 03:01:59 PM PDT 24
Finished Jun 02 03:02:23 PM PDT 24
Peak memory 208936 kb
Host smart-6f789e2d-e883-44e1-8ebb-2e8baa7e7c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761153601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3761153601
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3110346235
Short name T409
Test name
Test status
Simulation time 148543022 ps
CPU time 4.19 seconds
Started Jun 02 03:01:56 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 208600 kb
Host smart-3ecd0292-e720-4c3e-8f83-87b798bf2aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110346235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3110346235
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.517783406
Short name T728
Test name
Test status
Simulation time 91576859 ps
CPU time 1.97 seconds
Started Jun 02 03:01:58 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 208696 kb
Host smart-cefed0c7-122e-4c0f-9ecc-62a1d45dc7f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517783406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.517783406
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1891015901
Short name T520
Test name
Test status
Simulation time 155760973 ps
CPU time 4.32 seconds
Started Jun 02 03:01:56 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 207920 kb
Host smart-1375fa17-ccb7-460d-80e4-ed8d21ba533f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891015901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1891015901
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2528531818
Short name T287
Test name
Test status
Simulation time 500101320 ps
CPU time 5.7 seconds
Started Jun 02 03:01:54 PM PDT 24
Finished Jun 02 03:02:00 PM PDT 24
Peak memory 208800 kb
Host smart-a454287e-3358-4559-a020-e4f3fed0503a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528531818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2528531818
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3791849385
Short name T424
Test name
Test status
Simulation time 329509659 ps
CPU time 2.48 seconds
Started Jun 02 03:02:00 PM PDT 24
Finished Jun 02 03:02:04 PM PDT 24
Peak memory 208596 kb
Host smart-abf3015f-e69b-47ac-9783-be796f806fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791849385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3791849385
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1264393841
Short name T607
Test name
Test status
Simulation time 880279408 ps
CPU time 4.73 seconds
Started Jun 02 03:01:54 PM PDT 24
Finished Jun 02 03:01:59 PM PDT 24
Peak memory 208536 kb
Host smart-a4784520-7734-4f64-89f4-61624d67ea4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264393841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1264393841
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3080405912
Short name T880
Test name
Test status
Simulation time 2555517141 ps
CPU time 52.75 seconds
Started Jun 02 03:02:03 PM PDT 24
Finished Jun 02 03:02:56 PM PDT 24
Peak memory 216432 kb
Host smart-3d0f4d9d-19f4-4d4f-9cdf-9e7c5974cba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080405912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3080405912
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.563954596
Short name T331
Test name
Test status
Simulation time 291415629 ps
CPU time 4.33 seconds
Started Jun 02 03:01:55 PM PDT 24
Finished Jun 02 03:02:00 PM PDT 24
Peak memory 209640 kb
Host smart-e2c62126-ec5e-4c23-9eb3-06f84489c3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563954596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.563954596
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1526103428
Short name T736
Test name
Test status
Simulation time 53551164 ps
CPU time 2.37 seconds
Started Jun 02 03:02:02 PM PDT 24
Finished Jun 02 03:02:05 PM PDT 24
Peak memory 210008 kb
Host smart-b8f466e9-b333-487f-b0d5-4195db486803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526103428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1526103428
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3803646530
Short name T466
Test name
Test status
Simulation time 11671972 ps
CPU time 0.73 seconds
Started Jun 02 03:02:07 PM PDT 24
Finished Jun 02 03:02:08 PM PDT 24
Peak memory 205960 kb
Host smart-42f8ed58-ff24-43d1-9f1a-9c8b506291c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803646530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3803646530
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3829962839
Short name T130
Test name
Test status
Simulation time 313438120 ps
CPU time 4.06 seconds
Started Jun 02 03:02:02 PM PDT 24
Finished Jun 02 03:02:06 PM PDT 24
Peak memory 214292 kb
Host smart-8e40a7ad-d45d-411c-9c6d-4e8d7907348c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829962839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3829962839
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1277852539
Short name T40
Test name
Test status
Simulation time 197582746 ps
CPU time 4.93 seconds
Started Jun 02 03:02:08 PM PDT 24
Finished Jun 02 03:02:13 PM PDT 24
Peak memory 208448 kb
Host smart-7858fde6-23e1-4df2-93b1-ad0d654a9c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277852539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1277852539
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.61024952
Short name T490
Test name
Test status
Simulation time 86596173 ps
CPU time 3.12 seconds
Started Jun 02 03:02:02 PM PDT 24
Finished Jun 02 03:02:06 PM PDT 24
Peak memory 218272 kb
Host smart-d1b15d42-66c1-4439-8d3c-67bdb1a33dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61024952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.61024952
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.156608405
Short name T588
Test name
Test status
Simulation time 122897835 ps
CPU time 3.34 seconds
Started Jun 02 03:02:10 PM PDT 24
Finished Jun 02 03:02:14 PM PDT 24
Peak memory 214324 kb
Host smart-c8eef032-9cdf-4b50-8f92-62d78e5d835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156608405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.156608405
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2235165743
Short name T809
Test name
Test status
Simulation time 147041565 ps
CPU time 4.53 seconds
Started Jun 02 03:02:11 PM PDT 24
Finished Jun 02 03:02:16 PM PDT 24
Peak memory 222484 kb
Host smart-74158b61-63b1-490f-91bb-74b5dd0a356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235165743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2235165743
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.746165339
Short name T532
Test name
Test status
Simulation time 1212865086 ps
CPU time 9.27 seconds
Started Jun 02 03:02:04 PM PDT 24
Finished Jun 02 03:02:14 PM PDT 24
Peak memory 218428 kb
Host smart-25d5fa47-8bfe-41bf-baf1-1de4218868d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746165339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.746165339
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3407505082
Short name T442
Test name
Test status
Simulation time 85025583 ps
CPU time 3.71 seconds
Started Jun 02 03:02:01 PM PDT 24
Finished Jun 02 03:02:06 PM PDT 24
Peak memory 207976 kb
Host smart-87d73bc1-ff45-4432-97ce-542409e70567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407505082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3407505082
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1508119955
Short name T318
Test name
Test status
Simulation time 218428465 ps
CPU time 7.78 seconds
Started Jun 02 03:02:05 PM PDT 24
Finished Jun 02 03:02:13 PM PDT 24
Peak memory 208680 kb
Host smart-df4835d4-6152-4e89-bee0-c7b7a9a93763
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508119955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1508119955
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.758585100
Short name T821
Test name
Test status
Simulation time 61058973 ps
CPU time 3.2 seconds
Started Jun 02 03:02:01 PM PDT 24
Finished Jun 02 03:02:05 PM PDT 24
Peak memory 207516 kb
Host smart-9c614981-db48-4685-9855-17e251e12635
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758585100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.758585100
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2140718910
Short name T432
Test name
Test status
Simulation time 128838549 ps
CPU time 3.99 seconds
Started Jun 02 03:02:02 PM PDT 24
Finished Jun 02 03:02:06 PM PDT 24
Peak memory 206820 kb
Host smart-c11363f6-53f4-4a48-ad70-90a64bd99070
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140718910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2140718910
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2433686786
Short name T634
Test name
Test status
Simulation time 651210580 ps
CPU time 3.5 seconds
Started Jun 02 03:02:16 PM PDT 24
Finished Jun 02 03:02:20 PM PDT 24
Peak memory 209068 kb
Host smart-a017d7aa-c991-4ad7-bcc7-87efe8bcb647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433686786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2433686786
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3332385514
Short name T404
Test name
Test status
Simulation time 102223866 ps
CPU time 2.78 seconds
Started Jun 02 03:02:01 PM PDT 24
Finished Jun 02 03:02:05 PM PDT 24
Peak memory 206852 kb
Host smart-85bf4dc0-ceab-4365-9a89-1c89b59a5a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332385514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3332385514
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1604312740
Short name T75
Test name
Test status
Simulation time 1143029599 ps
CPU time 35 seconds
Started Jun 02 03:02:08 PM PDT 24
Finished Jun 02 03:02:44 PM PDT 24
Peak memory 215064 kb
Host smart-e66a320f-1347-43c4-b209-ed1bf1261f23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604312740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1604312740
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1438324973
Short name T582
Test name
Test status
Simulation time 79331827 ps
CPU time 3.52 seconds
Started Jun 02 03:02:13 PM PDT 24
Finished Jun 02 03:02:17 PM PDT 24
Peak memory 207388 kb
Host smart-d485d7ea-9ac7-4e01-892e-90aabe815c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438324973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1438324973
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2751136019
Short name T761
Test name
Test status
Simulation time 87165514 ps
CPU time 1.83 seconds
Started Jun 02 03:02:09 PM PDT 24
Finished Jun 02 03:02:11 PM PDT 24
Peak memory 209908 kb
Host smart-005f92f9-2fa5-4fcd-9def-e733db9999ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751136019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2751136019
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1321333229
Short name T845
Test name
Test status
Simulation time 69590945 ps
CPU time 0.91 seconds
Started Jun 02 03:02:16 PM PDT 24
Finished Jun 02 03:02:17 PM PDT 24
Peak memory 205896 kb
Host smart-9abc8d26-027c-4a44-bc4a-74035477e627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321333229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1321333229
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2602929286
Short name T853
Test name
Test status
Simulation time 146443096 ps
CPU time 3.41 seconds
Started Jun 02 03:02:13 PM PDT 24
Finished Jun 02 03:02:17 PM PDT 24
Peak memory 209200 kb
Host smart-a21667f8-3cae-4720-8b18-ca5311b0c554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602929286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2602929286
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.308164803
Short name T22
Test name
Test status
Simulation time 1805454614 ps
CPU time 25.17 seconds
Started Jun 02 03:02:13 PM PDT 24
Finished Jun 02 03:02:38 PM PDT 24
Peak memory 214264 kb
Host smart-d167faab-c1ad-48cc-b07d-bc749e53df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308164803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.308164803
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3748209290
Short name T285
Test name
Test status
Simulation time 266065877 ps
CPU time 3.02 seconds
Started Jun 02 03:02:14 PM PDT 24
Finished Jun 02 03:02:18 PM PDT 24
Peak memory 214264 kb
Host smart-2fe6d763-faae-4f38-9d98-dd5b84d0aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748209290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3748209290
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1134216945
Short name T779
Test name
Test status
Simulation time 135206150 ps
CPU time 2.31 seconds
Started Jun 02 03:02:12 PM PDT 24
Finished Jun 02 03:02:15 PM PDT 24
Peak memory 214836 kb
Host smart-8210e0f7-29c8-4a68-a32f-a0f6ac6934dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134216945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1134216945
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2102614203
Short name T791
Test name
Test status
Simulation time 317811794 ps
CPU time 3.33 seconds
Started Jun 02 03:02:09 PM PDT 24
Finished Jun 02 03:02:12 PM PDT 24
Peak memory 208788 kb
Host smart-d3eb8496-9d64-4795-a23c-596882281486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102614203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2102614203
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2679184318
Short name T680
Test name
Test status
Simulation time 32382421 ps
CPU time 2.32 seconds
Started Jun 02 03:02:09 PM PDT 24
Finished Jun 02 03:02:12 PM PDT 24
Peak memory 207232 kb
Host smart-65d96ef5-a3a7-48fc-97fb-2dff6ae685ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679184318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2679184318
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.151610510
Short name T618
Test name
Test status
Simulation time 456804120 ps
CPU time 2.39 seconds
Started Jun 02 03:02:07 PM PDT 24
Finished Jun 02 03:02:10 PM PDT 24
Peak memory 206944 kb
Host smart-ebd446b4-03f7-4526-bc27-756fa5160d8b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151610510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.151610510
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.396698621
Short name T410
Test name
Test status
Simulation time 3411517247 ps
CPU time 7.66 seconds
Started Jun 02 03:02:15 PM PDT 24
Finished Jun 02 03:02:23 PM PDT 24
Peak memory 208948 kb
Host smart-c129271c-4c3b-4210-ae94-d8286214a2ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396698621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.396698621
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1648210831
Short name T796
Test name
Test status
Simulation time 264205629 ps
CPU time 3.79 seconds
Started Jun 02 03:02:11 PM PDT 24
Finished Jun 02 03:02:15 PM PDT 24
Peak memory 218216 kb
Host smart-1ef036a8-fa02-4ed5-afd3-ac2f5fdaeb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648210831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1648210831
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1990264706
Short name T552
Test name
Test status
Simulation time 703836167 ps
CPU time 6.91 seconds
Started Jun 02 03:02:10 PM PDT 24
Finished Jun 02 03:02:17 PM PDT 24
Peak memory 208624 kb
Host smart-da732722-d6d5-49ed-b05f-5c2109a20348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990264706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1990264706
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.477520454
Short name T123
Test name
Test status
Simulation time 504573962 ps
CPU time 6.18 seconds
Started Jun 02 03:02:16 PM PDT 24
Finished Jun 02 03:02:22 PM PDT 24
Peak memory 214288 kb
Host smart-80a8e774-eb55-499e-9cbf-2643e6b832b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477520454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.477520454
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2481904188
Short name T43
Test name
Test status
Simulation time 225272080 ps
CPU time 2.56 seconds
Started Jun 02 03:02:11 PM PDT 24
Finished Jun 02 03:02:14 PM PDT 24
Peak memory 210160 kb
Host smart-85aeedd0-b632-474e-a91c-2045609ae4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481904188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2481904188
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2148042508
Short name T605
Test name
Test status
Simulation time 18506691 ps
CPU time 1 seconds
Started Jun 02 02:59:55 PM PDT 24
Finished Jun 02 02:59:56 PM PDT 24
Peak memory 206044 kb
Host smart-65bcb188-d58d-445d-be80-ac05a02a2193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148042508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2148042508
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1727625825
Short name T402
Test name
Test status
Simulation time 55491709 ps
CPU time 3.86 seconds
Started Jun 02 02:59:48 PM PDT 24
Finished Jun 02 02:59:52 PM PDT 24
Peak memory 214344 kb
Host smart-c9e513ca-9322-47cf-9a33-2a5fece597e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1727625825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1727625825
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1329823233
Short name T20
Test name
Test status
Simulation time 172883694 ps
CPU time 2.35 seconds
Started Jun 02 02:59:57 PM PDT 24
Finished Jun 02 03:00:00 PM PDT 24
Peak memory 221116 kb
Host smart-6fc6bea9-8dd1-4fc2-9eb1-1a8230f97aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329823233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1329823233
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3414067158
Short name T440
Test name
Test status
Simulation time 1013250570 ps
CPU time 29.38 seconds
Started Jun 02 02:59:48 PM PDT 24
Finished Jun 02 03:00:18 PM PDT 24
Peak memory 219812 kb
Host smart-a8c494a2-d5a1-4ac7-b286-875ca1a3c8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414067158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3414067158
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3580234574
Short name T859
Test name
Test status
Simulation time 158267716 ps
CPU time 2.44 seconds
Started Jun 02 02:59:54 PM PDT 24
Finished Jun 02 02:59:57 PM PDT 24
Peak memory 214288 kb
Host smart-8e15bef7-f7b3-4939-9314-cd07da7885df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580234574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3580234574
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3269780684
Short name T540
Test name
Test status
Simulation time 95580428 ps
CPU time 4 seconds
Started Jun 02 02:59:55 PM PDT 24
Finished Jun 02 02:59:59 PM PDT 24
Peak memory 214244 kb
Host smart-66256127-fe1a-4692-bc61-35eed367a8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269780684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3269780684
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1709415269
Short name T384
Test name
Test status
Simulation time 83849884 ps
CPU time 2.6 seconds
Started Jun 02 02:59:49 PM PDT 24
Finished Jun 02 02:59:52 PM PDT 24
Peak memory 207180 kb
Host smart-5073c85f-08e8-4ab2-9046-273f8f34449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709415269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1709415269
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1651655807
Short name T189
Test name
Test status
Simulation time 166572678 ps
CPU time 6.53 seconds
Started Jun 02 02:59:50 PM PDT 24
Finished Jun 02 02:59:57 PM PDT 24
Peak memory 208928 kb
Host smart-55fbffa5-b5bb-439c-8035-fa982994372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651655807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1651655807
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.943082423
Short name T13
Test name
Test status
Simulation time 1145930934 ps
CPU time 8.92 seconds
Started Jun 02 02:59:55 PM PDT 24
Finished Jun 02 03:00:04 PM PDT 24
Peak memory 230856 kb
Host smart-6b324ccd-2290-4dfe-b38e-676cd8ee02d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943082423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.943082423
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3498609231
Short name T810
Test name
Test status
Simulation time 355378026 ps
CPU time 8.39 seconds
Started Jun 02 02:59:48 PM PDT 24
Finished Jun 02 02:59:57 PM PDT 24
Peak memory 208060 kb
Host smart-056905d9-d4c3-42af-890d-b64346b1b021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498609231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3498609231
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3506253297
Short name T592
Test name
Test status
Simulation time 48446383 ps
CPU time 2.68 seconds
Started Jun 02 02:59:50 PM PDT 24
Finished Jun 02 02:59:54 PM PDT 24
Peak memory 206768 kb
Host smart-e1a7890f-e67d-4ea1-a1ae-3fbaab221108
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506253297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3506253297
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3124316969
Short name T525
Test name
Test status
Simulation time 617211617 ps
CPU time 7.5 seconds
Started Jun 02 02:59:48 PM PDT 24
Finished Jun 02 02:59:56 PM PDT 24
Peak memory 208252 kb
Host smart-0be5870b-1888-4651-8fd5-cbc8d1337956
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124316969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3124316969
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1480134253
Short name T751
Test name
Test status
Simulation time 61829418 ps
CPU time 3.07 seconds
Started Jun 02 02:59:48 PM PDT 24
Finished Jun 02 02:59:52 PM PDT 24
Peak memory 207052 kb
Host smart-bbe073c8-37b0-46cd-9dd3-afce578cbaef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480134253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1480134253
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1881400531
Short name T770
Test name
Test status
Simulation time 312146317 ps
CPU time 9.95 seconds
Started Jun 02 02:59:55 PM PDT 24
Finished Jun 02 03:00:05 PM PDT 24
Peak memory 220232 kb
Host smart-147bf5ff-f9ef-40a2-90c2-49c4f2b45e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881400531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1881400531
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.696709999
Short name T444
Test name
Test status
Simulation time 120830962 ps
CPU time 2.33 seconds
Started Jun 02 02:59:48 PM PDT 24
Finished Jun 02 02:59:51 PM PDT 24
Peak memory 206828 kb
Host smart-9d5424e8-2546-43b7-8f7a-6183ec95733d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696709999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.696709999
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1216548779
Short name T361
Test name
Test status
Simulation time 255223562 ps
CPU time 11.82 seconds
Started Jun 02 02:59:54 PM PDT 24
Finished Jun 02 03:00:06 PM PDT 24
Peak memory 218980 kb
Host smart-895838d6-9ea9-4146-9712-66777cb22ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216548779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1216548779
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2462751391
Short name T611
Test name
Test status
Simulation time 157040049 ps
CPU time 10.95 seconds
Started Jun 02 02:59:56 PM PDT 24
Finished Jun 02 03:00:07 PM PDT 24
Peak memory 222844 kb
Host smart-964769a2-7eeb-449a-b839-774725ea9323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462751391 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2462751391
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.4056353185
Short name T396
Test name
Test status
Simulation time 71891277 ps
CPU time 3.4 seconds
Started Jun 02 02:59:47 PM PDT 24
Finished Jun 02 02:59:51 PM PDT 24
Peak memory 209436 kb
Host smart-67c6c690-9bfa-4b65-9e67-70a99f18c156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056353185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.4056353185
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1207996941
Short name T368
Test name
Test status
Simulation time 108477598 ps
CPU time 2.98 seconds
Started Jun 02 02:59:58 PM PDT 24
Finished Jun 02 03:00:01 PM PDT 24
Peak memory 209888 kb
Host smart-d05d78e3-7ea2-45f9-99ec-10a31ff7f7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207996941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1207996941
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3528508795
Short name T14
Test name
Test status
Simulation time 59972945 ps
CPU time 0.73 seconds
Started Jun 02 03:02:21 PM PDT 24
Finished Jun 02 03:02:22 PM PDT 24
Peak memory 205948 kb
Host smart-f3d0d330-f7ea-4efe-9b3b-ac4a51fd065c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528508795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3528508795
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.254649651
Short name T228
Test name
Test status
Simulation time 136281632 ps
CPU time 3.01 seconds
Started Jun 02 03:02:21 PM PDT 24
Finished Jun 02 03:02:24 PM PDT 24
Peak memory 214248 kb
Host smart-ec573d6b-e31a-4842-bd8e-77d174e65994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254649651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.254649651
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2547916625
Short name T448
Test name
Test status
Simulation time 92346714 ps
CPU time 4.42 seconds
Started Jun 02 03:02:17 PM PDT 24
Finished Jun 02 03:02:22 PM PDT 24
Peak memory 208672 kb
Host smart-bfa5f295-308f-471b-9f7a-adf969258cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547916625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2547916625
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.855148416
Short name T51
Test name
Test status
Simulation time 72363864 ps
CPU time 3.44 seconds
Started Jun 02 03:02:18 PM PDT 24
Finished Jun 02 03:02:22 PM PDT 24
Peak memory 210008 kb
Host smart-0561573d-e7c9-44f6-bd13-1e2b9a9d0271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855148416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.855148416
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2974582712
Short name T315
Test name
Test status
Simulation time 255650206 ps
CPU time 7.16 seconds
Started Jun 02 03:02:17 PM PDT 24
Finished Jun 02 03:02:25 PM PDT 24
Peak memory 222404 kb
Host smart-fc32fa83-b2d4-440d-8b10-1b26363f7aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974582712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2974582712
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.4152118491
Short name T703
Test name
Test status
Simulation time 156446227 ps
CPU time 5.39 seconds
Started Jun 02 03:02:18 PM PDT 24
Finished Jun 02 03:02:24 PM PDT 24
Peak memory 210820 kb
Host smart-855ad54e-7e8b-415e-837f-e11d2b76d6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152118491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4152118491
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3234631347
Short name T196
Test name
Test status
Simulation time 2078167774 ps
CPU time 28.5 seconds
Started Jun 02 03:02:19 PM PDT 24
Finished Jun 02 03:02:48 PM PDT 24
Peak memory 208288 kb
Host smart-6f1a5e0b-96b8-4683-94f4-e52a5d514a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234631347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3234631347
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2104340067
Short name T708
Test name
Test status
Simulation time 86225211 ps
CPU time 3.81 seconds
Started Jun 02 03:02:19 PM PDT 24
Finished Jun 02 03:02:23 PM PDT 24
Peak memory 208636 kb
Host smart-5739796b-91c5-40ae-85bb-cf3d7bc53bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104340067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2104340067
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1826077353
Short name T890
Test name
Test status
Simulation time 1259808017 ps
CPU time 5.05 seconds
Started Jun 02 03:02:20 PM PDT 24
Finished Jun 02 03:02:26 PM PDT 24
Peak memory 209032 kb
Host smart-ffcc1fb6-2e2f-4eb5-a0ba-56133290bd76
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826077353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1826077353
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1836613033
Short name T545
Test name
Test status
Simulation time 775472795 ps
CPU time 3.96 seconds
Started Jun 02 03:02:19 PM PDT 24
Finished Jun 02 03:02:23 PM PDT 24
Peak memory 207020 kb
Host smart-03a43de2-c4ad-48a9-af00-59f56714ab2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836613033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1836613033
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.4269029884
Short name T829
Test name
Test status
Simulation time 80696640 ps
CPU time 2.51 seconds
Started Jun 02 03:02:18 PM PDT 24
Finished Jun 02 03:02:21 PM PDT 24
Peak memory 206936 kb
Host smart-e9fae1bb-5d20-46dd-a1eb-1c60f4a24a16
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269029884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4269029884
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1305037149
Short name T376
Test name
Test status
Simulation time 98186927 ps
CPU time 3.24 seconds
Started Jun 02 03:02:19 PM PDT 24
Finished Jun 02 03:02:23 PM PDT 24
Peak memory 209152 kb
Host smart-7f62e41c-ca79-4156-990e-89a82a35fa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305037149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1305037149
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3035344238
Short name T795
Test name
Test status
Simulation time 929414921 ps
CPU time 22.86 seconds
Started Jun 02 03:02:13 PM PDT 24
Finished Jun 02 03:02:36 PM PDT 24
Peak memory 208144 kb
Host smart-2cf76e3f-79d0-4e27-a12a-5125b6705c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035344238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3035344238
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.103059796
Short name T381
Test name
Test status
Simulation time 367202352 ps
CPU time 5.42 seconds
Started Jun 02 03:02:18 PM PDT 24
Finished Jun 02 03:02:24 PM PDT 24
Peak memory 208636 kb
Host smart-ad723ec5-aeb6-4a79-be27-b9313451eb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103059796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.103059796
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1231184626
Short name T177
Test name
Test status
Simulation time 428883981 ps
CPU time 2.52 seconds
Started Jun 02 03:02:20 PM PDT 24
Finished Jun 02 03:02:23 PM PDT 24
Peak memory 209916 kb
Host smart-785b3088-d73b-4b7b-8c47-439e81398e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231184626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1231184626
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1561627191
Short name T521
Test name
Test status
Simulation time 44251618 ps
CPU time 0.84 seconds
Started Jun 02 03:02:30 PM PDT 24
Finished Jun 02 03:02:31 PM PDT 24
Peak memory 205908 kb
Host smart-a39ceeaa-b8d2-4220-b564-94ae051361ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561627191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1561627191
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.647925319
Short name T79
Test name
Test status
Simulation time 112536551 ps
CPU time 2.2 seconds
Started Jun 02 03:02:30 PM PDT 24
Finished Jun 02 03:02:32 PM PDT 24
Peak memory 207376 kb
Host smart-1c532330-0811-4384-b112-0daef3bbb38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647925319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.647925319
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2755266702
Short name T352
Test name
Test status
Simulation time 253546808 ps
CPU time 5.99 seconds
Started Jun 02 03:02:29 PM PDT 24
Finished Jun 02 03:02:36 PM PDT 24
Peak memory 214216 kb
Host smart-4a2e03b0-aeaf-4bfc-9330-d9377aae2478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755266702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2755266702
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2608319055
Short name T717
Test name
Test status
Simulation time 111788829 ps
CPU time 2.84 seconds
Started Jun 02 03:02:29 PM PDT 24
Finished Jun 02 03:02:33 PM PDT 24
Peak memory 206092 kb
Host smart-d284bda0-05d0-48f0-a466-8124052a2ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608319055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2608319055
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.927384045
Short name T752
Test name
Test status
Simulation time 65048852 ps
CPU time 3.25 seconds
Started Jun 02 03:02:27 PM PDT 24
Finished Jun 02 03:02:30 PM PDT 24
Peak memory 207536 kb
Host smart-f5138083-319e-4b09-9759-17dcbc87f4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927384045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.927384045
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1882296654
Short name T538
Test name
Test status
Simulation time 523286477 ps
CPU time 3.81 seconds
Started Jun 02 03:02:28 PM PDT 24
Finished Jun 02 03:02:32 PM PDT 24
Peak memory 206904 kb
Host smart-b0e24f75-ccab-49b2-a411-62d8a9d82656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882296654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1882296654
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.485577941
Short name T433
Test name
Test status
Simulation time 61857907 ps
CPU time 3.13 seconds
Started Jun 02 03:02:28 PM PDT 24
Finished Jun 02 03:02:32 PM PDT 24
Peak memory 207056 kb
Host smart-f8ef21c3-270b-47dc-a45b-f6d6342a751c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485577941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.485577941
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.4008433008
Short name T716
Test name
Test status
Simulation time 226095213 ps
CPU time 5.88 seconds
Started Jun 02 03:02:25 PM PDT 24
Finished Jun 02 03:02:32 PM PDT 24
Peak memory 208612 kb
Host smart-1664e9ea-1156-49c2-bfa4-e1816a69d0f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008433008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.4008433008
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1438443971
Short name T720
Test name
Test status
Simulation time 1088224022 ps
CPU time 6.75 seconds
Started Jun 02 03:02:26 PM PDT 24
Finished Jun 02 03:02:33 PM PDT 24
Peak memory 207048 kb
Host smart-0605e152-b22b-4313-8b17-abe03db61c27
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438443971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1438443971
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.13926412
Short name T358
Test name
Test status
Simulation time 79582382 ps
CPU time 1.9 seconds
Started Jun 02 03:02:30 PM PDT 24
Finished Jun 02 03:02:32 PM PDT 24
Peak memory 215864 kb
Host smart-88b266ba-1c51-423b-ab1d-d00fb1013a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13926412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.13926412
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1360355661
Short name T437
Test name
Test status
Simulation time 73477435 ps
CPU time 2.24 seconds
Started Jun 02 03:02:20 PM PDT 24
Finished Jun 02 03:02:22 PM PDT 24
Peak memory 206868 kb
Host smart-63071929-26f9-42ae-b14d-0ecaf4ac2eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360355661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1360355661
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.773564010
Short name T681
Test name
Test status
Simulation time 918054254 ps
CPU time 9.8 seconds
Started Jun 02 03:02:28 PM PDT 24
Finished Jun 02 03:02:39 PM PDT 24
Peak memory 222572 kb
Host smart-c95e6961-e2df-4ab5-85b0-8e417ad12840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773564010 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.773564010
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1601903899
Short name T447
Test name
Test status
Simulation time 365011291 ps
CPU time 5.31 seconds
Started Jun 02 03:02:30 PM PDT 24
Finished Jun 02 03:02:36 PM PDT 24
Peak memory 214456 kb
Host smart-78a608a6-1ac1-4a6e-aa82-a6bc057fb5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601903899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1601903899
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.968294035
Short name T801
Test name
Test status
Simulation time 18947393 ps
CPU time 0.78 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:36 PM PDT 24
Peak memory 205912 kb
Host smart-8750d4b7-e019-405f-9d06-4a77744449e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968294035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.968294035
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2706051799
Short name T261
Test name
Test status
Simulation time 439350426 ps
CPU time 11.83 seconds
Started Jun 02 03:02:36 PM PDT 24
Finished Jun 02 03:02:48 PM PDT 24
Peak memory 215700 kb
Host smart-2e79eafa-a1d7-4668-ab58-e89b45dc16a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706051799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2706051799
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1292090676
Short name T29
Test name
Test status
Simulation time 494972655 ps
CPU time 5 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:41 PM PDT 24
Peak memory 221496 kb
Host smart-3db88242-050c-452a-9ea5-d18df3241421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292090676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1292090676
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1912309426
Short name T737
Test name
Test status
Simulation time 193137570 ps
CPU time 2.19 seconds
Started Jun 02 03:02:45 PM PDT 24
Finished Jun 02 03:02:48 PM PDT 24
Peak memory 209980 kb
Host smart-264a0da3-39a0-4b14-aea5-0ecc5f28d4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912309426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1912309426
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2214441927
Short name T463
Test name
Test status
Simulation time 361056415 ps
CPU time 4.44 seconds
Started Jun 02 03:02:36 PM PDT 24
Finished Jun 02 03:02:41 PM PDT 24
Peak memory 214316 kb
Host smart-dd08bf7c-09e1-4c83-bb26-422b2aa5c01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214441927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2214441927
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2927029376
Short name T652
Test name
Test status
Simulation time 200206705 ps
CPU time 5.31 seconds
Started Jun 02 03:02:37 PM PDT 24
Finished Jun 02 03:02:43 PM PDT 24
Peak memory 222380 kb
Host smart-f74189fe-dd2d-4116-86e7-c812bddea1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927029376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2927029376
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1163422838
Short name T771
Test name
Test status
Simulation time 55800195 ps
CPU time 2.7 seconds
Started Jun 02 03:02:37 PM PDT 24
Finished Jun 02 03:02:40 PM PDT 24
Peak memory 220244 kb
Host smart-8dafa5cf-a35f-4df6-8bc4-805bd6ba72ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163422838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1163422838
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.861060987
Short name T769
Test name
Test status
Simulation time 339642168 ps
CPU time 4.16 seconds
Started Jun 02 03:02:36 PM PDT 24
Finished Jun 02 03:02:41 PM PDT 24
Peak memory 209848 kb
Host smart-080cd7f7-91e9-407b-a0b5-ecbae6748738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861060987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.861060987
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2218499969
Short name T87
Test name
Test status
Simulation time 314116003 ps
CPU time 2.93 seconds
Started Jun 02 03:02:36 PM PDT 24
Finished Jun 02 03:02:40 PM PDT 24
Peak memory 207468 kb
Host smart-9df06e43-aa46-4103-bc2f-e162da6e9aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218499969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2218499969
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1512086857
Short name T725
Test name
Test status
Simulation time 1185535058 ps
CPU time 17.01 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:52 PM PDT 24
Peak memory 208612 kb
Host smart-92cbdebe-d1c3-4e2a-99b9-e7ec452ffd96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512086857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1512086857
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.944407113
Short name T81
Test name
Test status
Simulation time 60654522 ps
CPU time 3.13 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:39 PM PDT 24
Peak memory 208916 kb
Host smart-8550e4f4-47ca-4dcd-b930-46372b007099
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944407113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.944407113
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.310498998
Short name T523
Test name
Test status
Simulation time 1520533695 ps
CPU time 16.19 seconds
Started Jun 02 03:02:34 PM PDT 24
Finished Jun 02 03:02:51 PM PDT 24
Peak memory 208056 kb
Host smart-5f1171f1-e8e4-4d04-a6cc-4f1daf4fbd2f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310498998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.310498998
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.970775481
Short name T244
Test name
Test status
Simulation time 277871226 ps
CPU time 3.89 seconds
Started Jun 02 03:02:34 PM PDT 24
Finished Jun 02 03:02:38 PM PDT 24
Peak memory 214384 kb
Host smart-097abb76-eee6-4055-a384-55a55eceef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970775481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.970775481
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4022947030
Short name T756
Test name
Test status
Simulation time 183577183 ps
CPU time 3.86 seconds
Started Jun 02 03:02:36 PM PDT 24
Finished Jun 02 03:02:40 PM PDT 24
Peak memory 208636 kb
Host smart-3b1f78e4-3fe6-46b6-bf84-3f24b57a14c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022947030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4022947030
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.938914241
Short name T822
Test name
Test status
Simulation time 388504159 ps
CPU time 12.91 seconds
Started Jun 02 03:02:36 PM PDT 24
Finished Jun 02 03:02:50 PM PDT 24
Peak memory 215308 kb
Host smart-33746eae-4881-4fb5-93e8-71f8a48b6713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938914241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.938914241
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1659719446
Short name T811
Test name
Test status
Simulation time 592618321 ps
CPU time 5.77 seconds
Started Jun 02 03:02:38 PM PDT 24
Finished Jun 02 03:02:44 PM PDT 24
Peak memory 218404 kb
Host smart-470ace3f-c4d7-4661-b63f-e991d1161cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659719446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1659719446
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4176631278
Short name T65
Test name
Test status
Simulation time 522443020 ps
CPU time 3.31 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:39 PM PDT 24
Peak memory 210512 kb
Host smart-010e6e97-b47c-40ee-a5cb-a460a3544792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176631278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4176631278
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3581700747
Short name T655
Test name
Test status
Simulation time 80346140 ps
CPU time 0.78 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:36 PM PDT 24
Peak memory 205952 kb
Host smart-3975abf8-ef1e-4107-b0bc-33a63d25a41b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581700747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3581700747
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3068196909
Short name T389
Test name
Test status
Simulation time 67058486 ps
CPU time 4.32 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:40 PM PDT 24
Peak memory 214296 kb
Host smart-6c793333-9c9e-440b-bde7-a525e18c057d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3068196909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3068196909
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.678272975
Short name T30
Test name
Test status
Simulation time 262165492 ps
CPU time 2.16 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:38 PM PDT 24
Peak memory 215632 kb
Host smart-229970b9-2a1f-4ab6-a426-9d4ea0f6ec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678272975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.678272975
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2783545201
Short name T534
Test name
Test status
Simulation time 71841057 ps
CPU time 1.74 seconds
Started Jun 02 03:02:43 PM PDT 24
Finished Jun 02 03:02:45 PM PDT 24
Peak memory 207660 kb
Host smart-ead37814-36a0-4860-b07f-a78d1fcd6b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783545201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2783545201
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3871182843
Short name T509
Test name
Test status
Simulation time 67252219 ps
CPU time 2.73 seconds
Started Jun 02 03:02:39 PM PDT 24
Finished Jun 02 03:02:42 PM PDT 24
Peak memory 208696 kb
Host smart-3d021c78-836a-4c62-bf11-d52765195071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871182843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3871182843
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.583524991
Short name T64
Test name
Test status
Simulation time 483242280 ps
CPU time 5.85 seconds
Started Jun 02 03:02:36 PM PDT 24
Finished Jun 02 03:02:42 PM PDT 24
Peak memory 222328 kb
Host smart-3b368bec-e2b4-4d50-aa7b-20ed1ef95dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583524991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.583524991
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1130192862
Short name T799
Test name
Test status
Simulation time 116748874 ps
CPU time 4.79 seconds
Started Jun 02 03:02:36 PM PDT 24
Finished Jun 02 03:02:42 PM PDT 24
Peak memory 207332 kb
Host smart-f0cc56bc-6403-4579-8932-2419b8947a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130192862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1130192862
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3255856815
Short name T692
Test name
Test status
Simulation time 204629445 ps
CPU time 4.83 seconds
Started Jun 02 03:02:36 PM PDT 24
Finished Jun 02 03:02:42 PM PDT 24
Peak memory 208448 kb
Host smart-fecc1625-41de-43c7-92a6-d8f4229c0b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255856815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3255856815
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1816395792
Short name T748
Test name
Test status
Simulation time 502924220 ps
CPU time 2.59 seconds
Started Jun 02 03:02:45 PM PDT 24
Finished Jun 02 03:02:48 PM PDT 24
Peak memory 208732 kb
Host smart-a12d801a-77cf-4868-9757-28a23318ca07
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816395792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1816395792
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3328660195
Short name T496
Test name
Test status
Simulation time 835994334 ps
CPU time 4.1 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:40 PM PDT 24
Peak memory 208840 kb
Host smart-5870debd-2b08-47fa-bba5-304dc4700218
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328660195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3328660195
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.478953152
Short name T4
Test name
Test status
Simulation time 233422156 ps
CPU time 3.83 seconds
Started Jun 02 03:02:34 PM PDT 24
Finished Jun 02 03:02:38 PM PDT 24
Peak memory 208568 kb
Host smart-0b8b221c-3121-455b-812b-d40399418562
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478953152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.478953152
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2068942703
Short name T772
Test name
Test status
Simulation time 903053417 ps
CPU time 13.2 seconds
Started Jun 02 03:02:45 PM PDT 24
Finished Jun 02 03:02:59 PM PDT 24
Peak memory 209324 kb
Host smart-f2be6cdf-8c96-4879-af39-c337d7acb1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068942703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2068942703
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2396049916
Short name T414
Test name
Test status
Simulation time 200283464 ps
CPU time 2.68 seconds
Started Jun 02 03:02:36 PM PDT 24
Finished Jun 02 03:02:39 PM PDT 24
Peak memory 208076 kb
Host smart-8ca05159-b051-4843-94fc-f65af5301887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396049916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2396049916
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3363622723
Short name T848
Test name
Test status
Simulation time 436527393 ps
CPU time 13.53 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:49 PM PDT 24
Peak memory 221316 kb
Host smart-fc79609d-4f3a-43dd-9a98-eedc961fe9cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363622723 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3363622723
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3059326812
Short name T595
Test name
Test status
Simulation time 2183704184 ps
CPU time 48.56 seconds
Started Jun 02 03:02:37 PM PDT 24
Finished Jun 02 03:03:26 PM PDT 24
Peak memory 209276 kb
Host smart-65da3ef1-9e43-40cc-9684-93c8368c8e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059326812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3059326812
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3757528156
Short name T913
Test name
Test status
Simulation time 191115523 ps
CPU time 3.91 seconds
Started Jun 02 03:02:35 PM PDT 24
Finished Jun 02 03:02:39 PM PDT 24
Peak memory 210336 kb
Host smart-d1a25ffa-94e6-45a0-98d3-db8e9fac8615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757528156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3757528156
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3433746345
Short name T900
Test name
Test status
Simulation time 28502710 ps
CPU time 0.78 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:41 PM PDT 24
Peak memory 205856 kb
Host smart-83f09ed4-71c9-4fe6-8345-025d06e94a1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433746345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3433746345
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3864348944
Short name T399
Test name
Test status
Simulation time 326384815 ps
CPU time 17.08 seconds
Started Jun 02 03:02:41 PM PDT 24
Finished Jun 02 03:02:59 PM PDT 24
Peak memory 214268 kb
Host smart-8e41df6e-ca60-4e7d-a626-72f5c734f100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864348944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3864348944
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2950091812
Short name T793
Test name
Test status
Simulation time 66906774 ps
CPU time 3.07 seconds
Started Jun 02 03:02:41 PM PDT 24
Finished Jun 02 03:02:45 PM PDT 24
Peak memory 218780 kb
Host smart-1ea37e1e-0140-4a40-ba6d-7ec1fc02d228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950091812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2950091812
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2659789000
Short name T836
Test name
Test status
Simulation time 583949745 ps
CPU time 19.61 seconds
Started Jun 02 03:02:42 PM PDT 24
Finished Jun 02 03:03:03 PM PDT 24
Peak memory 214308 kb
Host smart-bffa1872-4fd0-4f2d-b7ad-2aba9cc80f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659789000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2659789000
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3871194390
Short name T61
Test name
Test status
Simulation time 348485720 ps
CPU time 3.24 seconds
Started Jun 02 03:02:38 PM PDT 24
Finished Jun 02 03:02:43 PM PDT 24
Peak memory 214260 kb
Host smart-950125ec-1c98-46ca-bec7-277e2043b04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871194390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3871194390
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1718649089
Short name T851
Test name
Test status
Simulation time 103049514 ps
CPU time 3.56 seconds
Started Jun 02 03:02:41 PM PDT 24
Finished Jun 02 03:02:45 PM PDT 24
Peak memory 207544 kb
Host smart-f57a4e9b-c85c-4e06-b4f3-da784826d4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718649089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1718649089
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.692493793
Short name T754
Test name
Test status
Simulation time 344045191 ps
CPU time 3.7 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:45 PM PDT 24
Peak memory 208452 kb
Host smart-446cdcab-1940-420d-871f-e1a176e025b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692493793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.692493793
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3892022
Short name T812
Test name
Test status
Simulation time 42021408 ps
CPU time 1.96 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:43 PM PDT 24
Peak memory 206916 kb
Host smart-7de21da7-988c-4bd1-85d0-eeaaae9f6703
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3892022
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1709890642
Short name T457
Test name
Test status
Simulation time 221714389 ps
CPU time 3.08 seconds
Started Jun 02 03:02:41 PM PDT 24
Finished Jun 02 03:02:45 PM PDT 24
Peak memory 206920 kb
Host smart-804cefcf-58b5-4f92-bec7-4a31bf3e483c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709890642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1709890642
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2109746873
Short name T506
Test name
Test status
Simulation time 26307766 ps
CPU time 1.99 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:43 PM PDT 24
Peak memory 208428 kb
Host smart-b12b75d5-13ed-4fc7-90b0-876d2d99c03b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109746873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2109746873
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2370633511
Short name T757
Test name
Test status
Simulation time 37486780 ps
CPU time 2.12 seconds
Started Jun 02 03:02:42 PM PDT 24
Finished Jun 02 03:02:44 PM PDT 24
Peak memory 209220 kb
Host smart-b6b958f7-fc83-44b9-a90b-21d5798ff452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370633511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2370633511
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2627480116
Short name T644
Test name
Test status
Simulation time 118942279 ps
CPU time 2.5 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:43 PM PDT 24
Peak memory 208520 kb
Host smart-11cb70a5-0d46-4243-9837-d9e78b517e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627480116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2627480116
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.376873181
Short name T735
Test name
Test status
Simulation time 6749902065 ps
CPU time 193.95 seconds
Started Jun 02 03:02:39 PM PDT 24
Finished Jun 02 03:05:54 PM PDT 24
Peak memory 223080 kb
Host smart-5b288ef9-65c6-47f7-a4d5-585541b51c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376873181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.376873181
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2261419390
Short name T121
Test name
Test status
Simulation time 558209993 ps
CPU time 19.75 seconds
Started Jun 02 03:02:43 PM PDT 24
Finished Jun 02 03:03:03 PM PDT 24
Peak memory 222532 kb
Host smart-48425c14-adaf-4d83-9476-d561af442016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261419390 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2261419390
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1373959191
Short name T272
Test name
Test status
Simulation time 228643072 ps
CPU time 4.78 seconds
Started Jun 02 03:02:38 PM PDT 24
Finished Jun 02 03:02:44 PM PDT 24
Peak memory 210088 kb
Host smart-df69e553-4edc-488d-bb25-353517855bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373959191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1373959191
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3742508319
Short name T178
Test name
Test status
Simulation time 66732714 ps
CPU time 2.44 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:43 PM PDT 24
Peak memory 214308 kb
Host smart-a059a7b5-2442-4eb4-9b0e-7fa37b934607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742508319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3742508319
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.12001698
Short name T577
Test name
Test status
Simulation time 42820977 ps
CPU time 0.79 seconds
Started Jun 02 03:02:48 PM PDT 24
Finished Jun 02 03:02:50 PM PDT 24
Peak memory 205880 kb
Host smart-2c3c7a49-dbe4-466b-9461-9d2483735d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12001698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.12001698
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1513679530
Short name T131
Test name
Test status
Simulation time 26539701 ps
CPU time 2.34 seconds
Started Jun 02 03:02:45 PM PDT 24
Finished Jun 02 03:02:48 PM PDT 24
Peak memory 214248 kb
Host smart-8f86b99b-4c75-400a-b085-64d46e940725
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513679530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1513679530
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.286480066
Short name T403
Test name
Test status
Simulation time 428660511 ps
CPU time 3.33 seconds
Started Jun 02 03:02:41 PM PDT 24
Finished Jun 02 03:02:45 PM PDT 24
Peak memory 209024 kb
Host smart-c8440d2f-ed95-430b-b7e2-41ed8d3cb3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286480066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.286480066
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1975055007
Short name T97
Test name
Test status
Simulation time 308254500 ps
CPU time 3.14 seconds
Started Jun 02 03:02:47 PM PDT 24
Finished Jun 02 03:02:51 PM PDT 24
Peak memory 220440 kb
Host smart-e3a55a59-55f0-4595-bd05-f695bc6309f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975055007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1975055007
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2166794137
Short name T90
Test name
Test status
Simulation time 446439087 ps
CPU time 3.76 seconds
Started Jun 02 03:02:46 PM PDT 24
Finished Jun 02 03:02:50 PM PDT 24
Peak memory 214312 kb
Host smart-a7c0d044-1911-4ff7-bf26-828e2735faf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166794137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2166794137
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.909475594
Short name T243
Test name
Test status
Simulation time 99994632 ps
CPU time 4.28 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:45 PM PDT 24
Peak memory 214256 kb
Host smart-5b9a3f14-6337-489b-b9f9-a426225b9902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909475594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.909475594
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2195321367
Short name T599
Test name
Test status
Simulation time 529846011 ps
CPU time 5.44 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:46 PM PDT 24
Peak memory 208648 kb
Host smart-508ad93b-4407-4f64-ad67-34a932e7f7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195321367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2195321367
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2878967992
Short name T568
Test name
Test status
Simulation time 612203046 ps
CPU time 6.79 seconds
Started Jun 02 03:02:41 PM PDT 24
Finished Jun 02 03:02:48 PM PDT 24
Peak memory 207860 kb
Host smart-d51fd7a5-5723-4720-a622-0f85ce033e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878967992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2878967992
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3924404070
Short name T632
Test name
Test status
Simulation time 86451384 ps
CPU time 4.07 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:45 PM PDT 24
Peak memory 208928 kb
Host smart-b94a983e-b857-486e-b0a6-fd5bbfe20723
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924404070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3924404070
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3345907120
Short name T642
Test name
Test status
Simulation time 6447412343 ps
CPU time 62.36 seconds
Started Jun 02 03:02:41 PM PDT 24
Finished Jun 02 03:03:44 PM PDT 24
Peak memory 207440 kb
Host smart-56a7ca31-3a58-4cc0-b7a9-1d1a30cc5d8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345907120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3345907120
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3040485615
Short name T803
Test name
Test status
Simulation time 34710745 ps
CPU time 2.2 seconds
Started Jun 02 03:02:40 PM PDT 24
Finished Jun 02 03:02:43 PM PDT 24
Peak memory 206872 kb
Host smart-737726db-3aaf-405a-94ea-b1dd28597806
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040485615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3040485615
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.465425680
Short name T431
Test name
Test status
Simulation time 89837355 ps
CPU time 2.04 seconds
Started Jun 02 03:02:46 PM PDT 24
Finished Jun 02 03:02:48 PM PDT 24
Peak memory 214344 kb
Host smart-9ad65e85-5dba-4b19-b0cb-1e06b3f1a1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465425680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.465425680
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2985672892
Short name T657
Test name
Test status
Simulation time 659626832 ps
CPU time 3.97 seconds
Started Jun 02 03:02:41 PM PDT 24
Finished Jun 02 03:02:46 PM PDT 24
Peak memory 207780 kb
Host smart-93d3cc42-338a-45f9-badb-874610d5e008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985672892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2985672892
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1119301852
Short name T758
Test name
Test status
Simulation time 257563891 ps
CPU time 10.82 seconds
Started Jun 02 03:02:48 PM PDT 24
Finished Jun 02 03:03:00 PM PDT 24
Peak memory 222556 kb
Host smart-ca413427-b142-44d1-ac43-4aa6f4f3270a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119301852 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1119301852
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1383332390
Short name T608
Test name
Test status
Simulation time 125524066 ps
CPU time 5.71 seconds
Started Jun 02 03:02:46 PM PDT 24
Finished Jun 02 03:02:53 PM PDT 24
Peak memory 214348 kb
Host smart-345f5700-02ac-44d8-a9bb-6b98e320e7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383332390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1383332390
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3973039963
Short name T606
Test name
Test status
Simulation time 470821487 ps
CPU time 1.88 seconds
Started Jun 02 03:02:46 PM PDT 24
Finished Jun 02 03:02:49 PM PDT 24
Peak memory 209844 kb
Host smart-ac4caf9c-95d6-4fcc-89aa-355cf6d23148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973039963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3973039963
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1137518204
Short name T553
Test name
Test status
Simulation time 9005760 ps
CPU time 0.8 seconds
Started Jun 02 03:02:53 PM PDT 24
Finished Jun 02 03:02:54 PM PDT 24
Peak memory 205872 kb
Host smart-ebf9c608-5527-484b-aad7-04e8aef7f520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137518204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1137518204
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2744174716
Short name T240
Test name
Test status
Simulation time 97288615 ps
CPU time 5.56 seconds
Started Jun 02 03:02:52 PM PDT 24
Finished Jun 02 03:02:58 PM PDT 24
Peak memory 215624 kb
Host smart-4dbbbcfd-2008-4628-9c52-4b87758ebce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744174716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2744174716
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1833058494
Short name T267
Test name
Test status
Simulation time 43518629 ps
CPU time 1.95 seconds
Started Jun 02 03:02:54 PM PDT 24
Finished Jun 02 03:02:56 PM PDT 24
Peak memory 207336 kb
Host smart-283abaa1-f97a-42dc-9e98-2f79a0186ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833058494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1833058494
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2242865631
Short name T844
Test name
Test status
Simulation time 60178905 ps
CPU time 2.25 seconds
Started Jun 02 03:02:54 PM PDT 24
Finished Jun 02 03:02:57 PM PDT 24
Peak memory 214364 kb
Host smart-1e2ad748-a9da-4287-9f65-e1f90146ec61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242865631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2242865631
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2248080703
Short name T213
Test name
Test status
Simulation time 107564881 ps
CPU time 4.29 seconds
Started Jun 02 03:02:53 PM PDT 24
Finished Jun 02 03:02:58 PM PDT 24
Peak memory 214324 kb
Host smart-61fec42f-2fa4-44eb-8ecd-65b1a7de884b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248080703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2248080703
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3261481947
Short name T491
Test name
Test status
Simulation time 164063951 ps
CPU time 5.07 seconds
Started Jun 02 03:02:55 PM PDT 24
Finished Jun 02 03:03:00 PM PDT 24
Peak memory 214280 kb
Host smart-11087e03-9bc2-4dca-9ca3-0f0f15dbc434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261481947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3261481947
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3102486690
Short name T436
Test name
Test status
Simulation time 200987502 ps
CPU time 4.6 seconds
Started Jun 02 03:02:52 PM PDT 24
Finished Jun 02 03:02:57 PM PDT 24
Peak memory 206740 kb
Host smart-84b186e1-c8ab-49a9-8086-c67da03dc391
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102486690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3102486690
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.499158244
Short name T439
Test name
Test status
Simulation time 2207125389 ps
CPU time 6.94 seconds
Started Jun 02 03:02:53 PM PDT 24
Finished Jun 02 03:03:00 PM PDT 24
Peak memory 207084 kb
Host smart-c598c866-98b7-4166-822c-39e1e2e583e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499158244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.499158244
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2424169977
Short name T645
Test name
Test status
Simulation time 64760212 ps
CPU time 3.1 seconds
Started Jun 02 03:02:51 PM PDT 24
Finished Jun 02 03:02:55 PM PDT 24
Peak memory 208948 kb
Host smart-e717214e-410b-4716-83f3-4bc9b3750bf4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424169977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2424169977
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2048440142
Short name T477
Test name
Test status
Simulation time 424406787 ps
CPU time 7.52 seconds
Started Jun 02 03:02:54 PM PDT 24
Finished Jun 02 03:03:02 PM PDT 24
Peak memory 214304 kb
Host smart-922c5a92-4a20-4b03-815c-f7ddbd8fea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048440142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2048440142
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.968800835
Short name T456
Test name
Test status
Simulation time 67964907 ps
CPU time 2.96 seconds
Started Jun 02 03:02:53 PM PDT 24
Finished Jun 02 03:02:56 PM PDT 24
Peak memory 208724 kb
Host smart-7494c434-7e37-4e59-a671-74b51b2a771a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968800835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.968800835
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.769950110
Short name T159
Test name
Test status
Simulation time 1404460965 ps
CPU time 12.23 seconds
Started Jun 02 03:02:53 PM PDT 24
Finished Jun 02 03:03:06 PM PDT 24
Peak memory 216240 kb
Host smart-195d3d11-5695-4228-823d-9d107d6475d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769950110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.769950110
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3402180163
Short name T298
Test name
Test status
Simulation time 115288118 ps
CPU time 4.13 seconds
Started Jun 02 03:02:52 PM PDT 24
Finished Jun 02 03:02:56 PM PDT 24
Peak memory 207352 kb
Host smart-35dbba33-d318-42d4-8a54-933c26689434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402180163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3402180163
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2886485452
Short name T42
Test name
Test status
Simulation time 1503025226 ps
CPU time 7.47 seconds
Started Jun 02 03:02:51 PM PDT 24
Finished Jun 02 03:02:59 PM PDT 24
Peak memory 210336 kb
Host smart-6acd57ba-11b1-40ed-857f-ecdb9c913601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886485452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2886485452
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.702426534
Short name T704
Test name
Test status
Simulation time 48374748 ps
CPU time 0.78 seconds
Started Jun 02 03:03:00 PM PDT 24
Finished Jun 02 03:03:01 PM PDT 24
Peak memory 205952 kb
Host smart-a7964df9-2b18-4696-ab75-93672f7b9259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702426534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.702426534
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.860706361
Short name T279
Test name
Test status
Simulation time 223519609 ps
CPU time 6.67 seconds
Started Jun 02 03:02:59 PM PDT 24
Finished Jun 02 03:03:06 PM PDT 24
Peak memory 215736 kb
Host smart-3f2c55a5-cf20-431a-afd0-947137944d6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860706361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.860706361
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.634302648
Short name T663
Test name
Test status
Simulation time 122028837 ps
CPU time 2.99 seconds
Started Jun 02 03:02:59 PM PDT 24
Finished Jun 02 03:03:03 PM PDT 24
Peak memory 222820 kb
Host smart-4fe6a498-cc79-4889-8119-56a1789a4306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634302648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.634302648
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3523448923
Short name T522
Test name
Test status
Simulation time 283546031 ps
CPU time 3.53 seconds
Started Jun 02 03:02:59 PM PDT 24
Finished Jun 02 03:03:04 PM PDT 24
Peak memory 208452 kb
Host smart-e74d43de-355f-4248-a63d-831051e49573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523448923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3523448923
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1222102827
Short name T88
Test name
Test status
Simulation time 680598599 ps
CPU time 11.14 seconds
Started Jun 02 03:02:59 PM PDT 24
Finished Jun 02 03:03:11 PM PDT 24
Peak memory 208924 kb
Host smart-8b0c4c0f-705f-422f-89a4-6865cdff2756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222102827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1222102827
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3179234762
Short name T622
Test name
Test status
Simulation time 180845498 ps
CPU time 2.85 seconds
Started Jun 02 03:02:57 PM PDT 24
Finished Jun 02 03:03:00 PM PDT 24
Peak memory 214176 kb
Host smart-3ee5596a-e3b8-461f-bbae-7b258658554f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179234762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3179234762
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1118886208
Short name T664
Test name
Test status
Simulation time 348197859 ps
CPU time 4.73 seconds
Started Jun 02 03:03:01 PM PDT 24
Finished Jun 02 03:03:06 PM PDT 24
Peak memory 222428 kb
Host smart-eebb4f4f-74c8-4e54-8525-d94496d6669f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118886208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1118886208
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3803382078
Short name T465
Test name
Test status
Simulation time 524065878 ps
CPU time 3.91 seconds
Started Jun 02 03:02:58 PM PDT 24
Finished Jun 02 03:03:03 PM PDT 24
Peak memory 207092 kb
Host smart-2640d904-0604-4b27-b898-0829add03391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803382078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3803382078
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4259992294
Short name T698
Test name
Test status
Simulation time 426233481 ps
CPU time 2.86 seconds
Started Jun 02 03:02:59 PM PDT 24
Finished Jun 02 03:03:03 PM PDT 24
Peak memory 208668 kb
Host smart-841e882f-52fd-4c28-8d31-784688d42c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259992294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4259992294
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2159075767
Short name T498
Test name
Test status
Simulation time 37113062 ps
CPU time 2.43 seconds
Started Jun 02 03:03:02 PM PDT 24
Finished Jun 02 03:03:05 PM PDT 24
Peak memory 207792 kb
Host smart-b47d1f52-5f9e-4f7d-9cb4-066e9ae4ed39
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159075767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2159075767
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1554762950
Short name T598
Test name
Test status
Simulation time 122949980 ps
CPU time 2.14 seconds
Started Jun 02 03:03:01 PM PDT 24
Finished Jun 02 03:03:04 PM PDT 24
Peak memory 207104 kb
Host smart-6d256487-8793-4be5-8ee5-f1d1e5c7310e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554762950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1554762950
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.157038900
Short name T485
Test name
Test status
Simulation time 79761753 ps
CPU time 3.29 seconds
Started Jun 02 03:03:02 PM PDT 24
Finished Jun 02 03:03:06 PM PDT 24
Peak memory 208580 kb
Host smart-e67cbca4-4cde-4626-9a83-2a83f23b82c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157038900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.157038900
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1211268851
Short name T721
Test name
Test status
Simulation time 85781337 ps
CPU time 2.01 seconds
Started Jun 02 03:02:57 PM PDT 24
Finished Jun 02 03:03:00 PM PDT 24
Peak memory 208268 kb
Host smart-9cc7ae61-d650-42b3-bbd4-84f64ea15fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211268851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1211268851
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1327316185
Short name T427
Test name
Test status
Simulation time 45285110 ps
CPU time 2.37 seconds
Started Jun 02 03:02:55 PM PDT 24
Finished Jun 02 03:02:58 PM PDT 24
Peak memory 207796 kb
Host smart-225a6941-41d7-46af-91d3-3efe600b340b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327316185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1327316185
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3161116942
Short name T842
Test name
Test status
Simulation time 8331207346 ps
CPU time 27.49 seconds
Started Jun 02 03:02:59 PM PDT 24
Finished Jun 02 03:03:27 PM PDT 24
Peak memory 215432 kb
Host smart-85d07450-4bab-421b-9112-01a3f7e60459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161116942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3161116942
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2273753923
Short name T299
Test name
Test status
Simulation time 117619437 ps
CPU time 5.86 seconds
Started Jun 02 03:02:58 PM PDT 24
Finished Jun 02 03:03:04 PM PDT 24
Peak memory 219568 kb
Host smart-9d7c52c9-9331-4277-9fa7-574bc3af9cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273753923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2273753923
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1071621797
Short name T738
Test name
Test status
Simulation time 335664473 ps
CPU time 2.26 seconds
Started Jun 02 03:03:01 PM PDT 24
Finished Jun 02 03:03:04 PM PDT 24
Peak memory 210092 kb
Host smart-88c975d8-6ac7-4379-b396-1b5e0380adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071621797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1071621797
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.378717890
Short name T99
Test name
Test status
Simulation time 46435758 ps
CPU time 0.77 seconds
Started Jun 02 03:03:13 PM PDT 24
Finished Jun 02 03:03:14 PM PDT 24
Peak memory 205940 kb
Host smart-de54059c-bd4b-4c57-90fe-6fdc03b8ec4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378717890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.378717890
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1932619596
Short name T394
Test name
Test status
Simulation time 5284466293 ps
CPU time 66.43 seconds
Started Jun 02 03:03:00 PM PDT 24
Finished Jun 02 03:04:07 PM PDT 24
Peak memory 214560 kb
Host smart-b8bed121-ad96-4128-b78d-128b0a216a07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932619596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1932619596
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1861662433
Short name T547
Test name
Test status
Simulation time 1486493267 ps
CPU time 7.39 seconds
Started Jun 02 03:03:06 PM PDT 24
Finished Jun 02 03:03:14 PM PDT 24
Peak memory 207992 kb
Host smart-35dd5d7b-8d38-401b-b33d-ff19ad891d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861662433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1861662433
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1627082556
Short name T438
Test name
Test status
Simulation time 212217169 ps
CPU time 2.68 seconds
Started Jun 02 03:03:05 PM PDT 24
Finished Jun 02 03:03:08 PM PDT 24
Peak memory 214272 kb
Host smart-0716a42c-d540-4d4b-aa35-92c87b62d06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627082556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1627082556
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.975935360
Short name T467
Test name
Test status
Simulation time 500777361 ps
CPU time 10.41 seconds
Started Jun 02 03:02:59 PM PDT 24
Finished Jun 02 03:03:10 PM PDT 24
Peak memory 219348 kb
Host smart-f2e5017a-baa1-44a4-b752-f21470a56203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975935360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.975935360
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.420904651
Short name T847
Test name
Test status
Simulation time 439509579 ps
CPU time 10.4 seconds
Started Jun 02 03:03:02 PM PDT 24
Finished Jun 02 03:03:13 PM PDT 24
Peak memory 208424 kb
Host smart-7005bc29-58b2-44eb-9e98-681d604eed1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420904651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.420904651
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.952971473
Short name T694
Test name
Test status
Simulation time 166371390 ps
CPU time 6.4 seconds
Started Jun 02 03:02:59 PM PDT 24
Finished Jun 02 03:03:06 PM PDT 24
Peak memory 207224 kb
Host smart-82607936-8ab7-4e40-a47a-4c91fe29730b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952971473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.952971473
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.965251571
Short name T887
Test name
Test status
Simulation time 212727385 ps
CPU time 7.43 seconds
Started Jun 02 03:03:00 PM PDT 24
Finished Jun 02 03:03:08 PM PDT 24
Peak memory 208136 kb
Host smart-27d4e289-49dd-42f5-b37b-0b25e1632dbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965251571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.965251571
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3248905417
Short name T556
Test name
Test status
Simulation time 109203967 ps
CPU time 2.03 seconds
Started Jun 02 03:03:06 PM PDT 24
Finished Jun 02 03:03:09 PM PDT 24
Peak memory 207536 kb
Host smart-fc18bd8a-ec9d-4a67-8be2-4f0ea1b450d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248905417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3248905417
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.959227762
Short name T84
Test name
Test status
Simulation time 46995830 ps
CPU time 2.49 seconds
Started Jun 02 03:03:00 PM PDT 24
Finished Jun 02 03:03:03 PM PDT 24
Peak memory 206692 kb
Host smart-36fb4531-17eb-412a-9930-a2617273f4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959227762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.959227762
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3592150170
Short name T306
Test name
Test status
Simulation time 1683087804 ps
CPU time 27.03 seconds
Started Jun 02 03:03:05 PM PDT 24
Finished Jun 02 03:03:33 PM PDT 24
Peak memory 222476 kb
Host smart-847a4929-5f14-459b-99ba-9d377a78ebc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592150170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3592150170
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2776977323
Short name T805
Test name
Test status
Simulation time 85569950 ps
CPU time 6.09 seconds
Started Jun 02 03:03:12 PM PDT 24
Finished Jun 02 03:03:19 PM PDT 24
Peak memory 222556 kb
Host smart-ca44b6f2-c9ad-46e5-93fe-0e910df9bac9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776977323 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2776977323
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1305056482
Short name T739
Test name
Test status
Simulation time 5236742100 ps
CPU time 34.39 seconds
Started Jun 02 03:03:07 PM PDT 24
Finished Jun 02 03:03:42 PM PDT 24
Peak memory 210648 kb
Host smart-64869072-01e6-438f-ae64-ce790d593979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305056482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1305056482
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1770871876
Short name T483
Test name
Test status
Simulation time 143266822 ps
CPU time 1.51 seconds
Started Jun 02 03:03:05 PM PDT 24
Finished Jun 02 03:03:07 PM PDT 24
Peak memory 208592 kb
Host smart-394d9a8b-753f-4e8e-9fc0-a8ba4d7b0336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770871876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1770871876
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1658777676
Short name T455
Test name
Test status
Simulation time 13432086 ps
CPU time 0.7 seconds
Started Jun 02 03:03:17 PM PDT 24
Finished Jun 02 03:03:20 PM PDT 24
Peak memory 205948 kb
Host smart-51e0925f-5ae6-456b-bd3d-0749bd4d92fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658777676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1658777676
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2377341784
Short name T518
Test name
Test status
Simulation time 327747627 ps
CPU time 10.44 seconds
Started Jun 02 03:03:11 PM PDT 24
Finished Jun 02 03:03:22 PM PDT 24
Peak memory 218024 kb
Host smart-f123b5cd-2f0e-42e8-a38b-a152ad1a11b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377341784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2377341784
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2771216005
Short name T787
Test name
Test status
Simulation time 30781159 ps
CPU time 1.81 seconds
Started Jun 02 03:03:10 PM PDT 24
Finished Jun 02 03:03:13 PM PDT 24
Peak memory 214308 kb
Host smart-d000adcb-cdb4-4494-9e01-2fde9c8b06eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771216005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2771216005
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2473280132
Short name T338
Test name
Test status
Simulation time 378836324 ps
CPU time 4.68 seconds
Started Jun 02 03:03:14 PM PDT 24
Finished Jun 02 03:03:19 PM PDT 24
Peak memory 222456 kb
Host smart-911ed33b-745f-4cb7-b695-e05a2e14b9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473280132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2473280132
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2351100543
Short name T342
Test name
Test status
Simulation time 1347890400 ps
CPU time 26.48 seconds
Started Jun 02 03:03:12 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 214324 kb
Host smart-fd94fe39-df1e-4406-9f8b-1996872b4435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351100543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2351100543
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1399913545
Short name T685
Test name
Test status
Simulation time 355332278 ps
CPU time 3.56 seconds
Started Jun 02 03:03:10 PM PDT 24
Finished Jun 02 03:03:14 PM PDT 24
Peak memory 208564 kb
Host smart-af9d974f-c13e-41b7-ac9c-30fe8957f4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399913545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1399913545
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1922199610
Short name T560
Test name
Test status
Simulation time 147722928 ps
CPU time 4.5 seconds
Started Jun 02 03:03:13 PM PDT 24
Finished Jun 02 03:03:18 PM PDT 24
Peak memory 206912 kb
Host smart-1b583967-6b86-45db-90d5-419950e0ca13
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922199610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1922199610
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3034393190
Short name T408
Test name
Test status
Simulation time 270995547 ps
CPU time 3.06 seconds
Started Jun 02 03:03:13 PM PDT 24
Finished Jun 02 03:03:17 PM PDT 24
Peak memory 207012 kb
Host smart-8b2e096f-ab80-473c-be31-e394f5404568
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034393190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3034393190
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1482068365
Short name T835
Test name
Test status
Simulation time 82559509 ps
CPU time 3.93 seconds
Started Jun 02 03:03:10 PM PDT 24
Finished Jun 02 03:03:14 PM PDT 24
Peak memory 208956 kb
Host smart-a96b01de-a1f0-4aa7-9fe9-1a0f9d3858fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482068365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1482068365
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.699276590
Short name T578
Test name
Test status
Simulation time 365831720 ps
CPU time 2.85 seconds
Started Jun 02 03:03:10 PM PDT 24
Finished Jun 02 03:03:13 PM PDT 24
Peak memory 210056 kb
Host smart-25ee3bf3-757d-43a7-8b1a-03ad017029c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699276590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.699276590
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3100070300
Short name T416
Test name
Test status
Simulation time 66910914 ps
CPU time 2.4 seconds
Started Jun 02 03:03:13 PM PDT 24
Finished Jun 02 03:03:17 PM PDT 24
Peak memory 208620 kb
Host smart-4394d253-d2a0-4bb6-a56f-576b936d6079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100070300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3100070300
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1548561023
Short name T624
Test name
Test status
Simulation time 1346339566 ps
CPU time 18.16 seconds
Started Jun 02 03:03:12 PM PDT 24
Finished Jun 02 03:03:31 PM PDT 24
Peak memory 215512 kb
Host smart-a9f2731b-448c-4b84-9a8f-23db3cbeb3d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548561023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1548561023
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.17948593
Short name T317
Test name
Test status
Simulation time 89154795 ps
CPU time 3.9 seconds
Started Jun 02 03:03:11 PM PDT 24
Finished Jun 02 03:03:15 PM PDT 24
Peak memory 218240 kb
Host smart-8ca6535f-ab36-4151-9ff5-619e8f03e00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17948593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.17948593
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1455191635
Short name T765
Test name
Test status
Simulation time 74255397 ps
CPU time 2.07 seconds
Started Jun 02 03:03:13 PM PDT 24
Finished Jun 02 03:03:16 PM PDT 24
Peak memory 213200 kb
Host smart-08f25ffb-8222-4831-a159-68be6628f28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455191635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1455191635
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2179369184
Short name T764
Test name
Test status
Simulation time 14052300 ps
CPU time 0.79 seconds
Started Jun 02 03:00:08 PM PDT 24
Finished Jun 02 03:00:09 PM PDT 24
Peak memory 205904 kb
Host smart-e88c792b-b4f6-45ef-815f-b6f3e197d9d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179369184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2179369184
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.881456775
Short name T390
Test name
Test status
Simulation time 503472132 ps
CPU time 13.95 seconds
Started Jun 02 03:00:01 PM PDT 24
Finished Jun 02 03:00:15 PM PDT 24
Peak memory 214316 kb
Host smart-6662ea0a-6889-4f6d-b9dc-d6ffaa11e922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881456775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.881456775
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1049255709
Short name T575
Test name
Test status
Simulation time 420599448 ps
CPU time 5.58 seconds
Started Jun 02 03:00:01 PM PDT 24
Finished Jun 02 03:00:07 PM PDT 24
Peak memory 218232 kb
Host smart-ec60eb8d-64b7-4cd9-97ed-f91957c6674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049255709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1049255709
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3149394350
Short name T283
Test name
Test status
Simulation time 57312557 ps
CPU time 3.14 seconds
Started Jun 02 03:00:01 PM PDT 24
Finished Jun 02 03:00:04 PM PDT 24
Peak memory 207560 kb
Host smart-30c787a7-6759-4798-99ac-0832aae04a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149394350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3149394350
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4131387320
Short name T814
Test name
Test status
Simulation time 473746849 ps
CPU time 3.76 seconds
Started Jun 02 03:00:01 PM PDT 24
Finished Jun 02 03:00:05 PM PDT 24
Peak memory 214648 kb
Host smart-91cfecd7-71f1-4dbe-b23d-b5e5fddf8fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131387320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4131387320
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3335978591
Short name T363
Test name
Test status
Simulation time 399903940 ps
CPU time 3.61 seconds
Started Jun 02 03:00:00 PM PDT 24
Finished Jun 02 03:00:04 PM PDT 24
Peak memory 214164 kb
Host smart-acf61e45-9fbe-4ca0-a061-e32d51df5151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335978591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3335978591
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2760085737
Short name T215
Test name
Test status
Simulation time 46824813 ps
CPU time 3.05 seconds
Started Jun 02 03:00:01 PM PDT 24
Finished Jun 02 03:00:05 PM PDT 24
Peak memory 208584 kb
Host smart-fa13a132-8b81-46f4-88b6-5502045160cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760085737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2760085737
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.717598931
Short name T857
Test name
Test status
Simulation time 11138945739 ps
CPU time 61.64 seconds
Started Jun 02 02:59:56 PM PDT 24
Finished Jun 02 03:00:58 PM PDT 24
Peak memory 208796 kb
Host smart-100ec8f6-522d-4bf3-9602-b4303f078616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717598931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.717598931
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3466908438
Short name T12
Test name
Test status
Simulation time 690115816 ps
CPU time 5.44 seconds
Started Jun 02 03:00:09 PM PDT 24
Finished Jun 02 03:00:15 PM PDT 24
Peak memory 230424 kb
Host smart-ab2ea382-4765-4402-b0e7-e9cec71ccae7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466908438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3466908438
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1387615573
Short name T413
Test name
Test status
Simulation time 120510476 ps
CPU time 2.44 seconds
Started Jun 02 02:59:54 PM PDT 24
Finished Jun 02 02:59:57 PM PDT 24
Peak memory 206088 kb
Host smart-b1c38d4e-4b31-44fe-b983-f66f5779b9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387615573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1387615573
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3681329209
Short name T193
Test name
Test status
Simulation time 384734045 ps
CPU time 2.46 seconds
Started Jun 02 02:59:54 PM PDT 24
Finished Jun 02 02:59:57 PM PDT 24
Peak memory 206912 kb
Host smart-32d542ce-8498-4674-9988-21deb4e436d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681329209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3681329209
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1695037913
Short name T604
Test name
Test status
Simulation time 54237863 ps
CPU time 2.34 seconds
Started Jun 02 02:59:58 PM PDT 24
Finished Jun 02 03:00:01 PM PDT 24
Peak memory 207172 kb
Host smart-b7df52fd-831e-4763-8098-47f32377742e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695037913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1695037913
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2635266795
Short name T672
Test name
Test status
Simulation time 207737974 ps
CPU time 2.63 seconds
Started Jun 02 02:59:58 PM PDT 24
Finished Jun 02 03:00:01 PM PDT 24
Peak memory 206904 kb
Host smart-2c5f7ff3-2d93-43af-ab77-c614c4ad75e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635266795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2635266795
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1791809021
Short name T564
Test name
Test status
Simulation time 216641805 ps
CPU time 3.45 seconds
Started Jun 02 03:00:07 PM PDT 24
Finished Jun 02 03:00:11 PM PDT 24
Peak memory 208544 kb
Host smart-50d4c03b-45ba-4863-ae9b-967d5438ec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791809021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1791809021
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.804142651
Short name T659
Test name
Test status
Simulation time 133769059 ps
CPU time 2.35 seconds
Started Jun 02 02:59:54 PM PDT 24
Finished Jun 02 02:59:57 PM PDT 24
Peak memory 207236 kb
Host smart-56926915-3c87-4e29-bc95-28e7fe162825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804142651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.804142651
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1086980240
Short name T356
Test name
Test status
Simulation time 205687405 ps
CPU time 5.87 seconds
Started Jun 02 03:00:07 PM PDT 24
Finished Jun 02 03:00:14 PM PDT 24
Peak memory 215340 kb
Host smart-1a69f577-8ea0-48af-ab70-8215093a040e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086980240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1086980240
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2061855145
Short name T747
Test name
Test status
Simulation time 983664388 ps
CPU time 8.36 seconds
Started Jun 02 03:00:09 PM PDT 24
Finished Jun 02 03:00:18 PM PDT 24
Peak memory 222616 kb
Host smart-d5a65bb0-a299-427e-b034-d19bcfa17e00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061855145 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2061855145
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3442629915
Short name T631
Test name
Test status
Simulation time 3628371706 ps
CPU time 23.3 seconds
Started Jun 02 03:00:01 PM PDT 24
Finished Jun 02 03:00:25 PM PDT 24
Peak memory 214388 kb
Host smart-4f935ad7-2c3b-4441-bb5e-a109bc797e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442629915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3442629915
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1506577832
Short name T370
Test name
Test status
Simulation time 178851355 ps
CPU time 2.98 seconds
Started Jun 02 03:00:09 PM PDT 24
Finished Jun 02 03:00:12 PM PDT 24
Peak memory 210872 kb
Host smart-4c4808e7-9cf1-491b-9628-b796116bc22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506577832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1506577832
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.4211812692
Short name T446
Test name
Test status
Simulation time 56996188 ps
CPU time 0.79 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:20 PM PDT 24
Peak memory 205876 kb
Host smart-3e513f5a-60cf-4179-b850-00a751e404a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211812692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.4211812692
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1017613427
Short name T109
Test name
Test status
Simulation time 54053126 ps
CPU time 3.31 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:23 PM PDT 24
Peak memory 214296 kb
Host smart-5e7902f6-eea1-4083-ace2-8cce0d1c971f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017613427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1017613427
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1296327601
Short name T638
Test name
Test status
Simulation time 65272102 ps
CPU time 2.15 seconds
Started Jun 02 03:03:17 PM PDT 24
Finished Jun 02 03:03:21 PM PDT 24
Peak memory 209884 kb
Host smart-b566cdfb-8172-423f-81b7-48a36f7423ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296327601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1296327601
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.908321369
Short name T775
Test name
Test status
Simulation time 102491574 ps
CPU time 2.6 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:22 PM PDT 24
Peak memory 209244 kb
Host smart-060a7c18-6fa1-4da6-9025-a57c0064fc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908321369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.908321369
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1165120678
Short name T311
Test name
Test status
Simulation time 70046491 ps
CPU time 1.98 seconds
Started Jun 02 03:03:21 PM PDT 24
Finished Jun 02 03:03:24 PM PDT 24
Peak memory 214328 kb
Host smart-20dfe3eb-adb4-4d3b-b94e-5f95670d9362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165120678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1165120678
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1095947830
Short name T773
Test name
Test status
Simulation time 38312652 ps
CPU time 2.14 seconds
Started Jun 02 03:03:16 PM PDT 24
Finished Jun 02 03:03:19 PM PDT 24
Peak memory 215440 kb
Host smart-596db4a2-89c8-4cc9-a0cd-56d3d68c2ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095947830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1095947830
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.121929636
Short name T696
Test name
Test status
Simulation time 862903853 ps
CPU time 4.4 seconds
Started Jun 02 03:03:19 PM PDT 24
Finished Jun 02 03:03:25 PM PDT 24
Peak memory 220072 kb
Host smart-72264cc1-c716-4afa-9941-7843f0aecc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121929636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.121929636
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2276295127
Short name T841
Test name
Test status
Simulation time 224149523 ps
CPU time 2.98 seconds
Started Jun 02 03:03:20 PM PDT 24
Finished Jun 02 03:03:24 PM PDT 24
Peak memory 207664 kb
Host smart-d3a8a264-ffef-4469-bbc3-32ebc0e6b6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276295127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2276295127
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.608764585
Short name T305
Test name
Test status
Simulation time 1424661418 ps
CPU time 44.66 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:04:04 PM PDT 24
Peak memory 209064 kb
Host smart-123b775f-1767-4876-a95a-72b8fa2e48a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608764585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.608764585
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1675185790
Short name T559
Test name
Test status
Simulation time 85958667 ps
CPU time 2.21 seconds
Started Jun 02 03:03:19 PM PDT 24
Finished Jun 02 03:03:23 PM PDT 24
Peak memory 208424 kb
Host smart-24218ecf-ef6f-41c4-9fb5-438fe516bbb3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675185790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1675185790
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3187629319
Short name T871
Test name
Test status
Simulation time 38076628 ps
CPU time 2.33 seconds
Started Jun 02 03:03:16 PM PDT 24
Finished Jun 02 03:03:19 PM PDT 24
Peak memory 206756 kb
Host smart-b066b4ff-e2a4-436b-9645-710060c62c39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187629319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3187629319
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.314788984
Short name T253
Test name
Test status
Simulation time 225608008 ps
CPU time 3.87 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:24 PM PDT 24
Peak memory 208600 kb
Host smart-0e5ddc81-0b12-44ec-8f62-c5875d99af89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314788984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.314788984
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2112596042
Short name T445
Test name
Test status
Simulation time 2317105412 ps
CPU time 22.82 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:42 PM PDT 24
Peak memory 209216 kb
Host smart-2017ea1a-eebd-4e8f-a4a9-67bb8fa90bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112596042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2112596042
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1328861294
Short name T567
Test name
Test status
Simulation time 242821932 ps
CPU time 2.81 seconds
Started Jun 02 03:03:16 PM PDT 24
Finished Jun 02 03:03:19 PM PDT 24
Peak memory 206964 kb
Host smart-db581d48-939b-4c82-809f-6549a909c400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328861294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1328861294
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.676873275
Short name T50
Test name
Test status
Simulation time 230623384 ps
CPU time 11.82 seconds
Started Jun 02 03:03:20 PM PDT 24
Finished Jun 02 03:03:33 PM PDT 24
Peak memory 215908 kb
Host smart-a18b28a6-749a-442a-a0ef-27032387d75d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676873275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.676873275
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2765730754
Short name T861
Test name
Test status
Simulation time 97568461 ps
CPU time 6.68 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:27 PM PDT 24
Peak memory 222700 kb
Host smart-e4e1faf8-14a8-44ed-bac8-c10db95d5f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765730754 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2765730754
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2264265304
Short name T257
Test name
Test status
Simulation time 11341451416 ps
CPU time 37.78 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:57 PM PDT 24
Peak memory 220436 kb
Host smart-7a3563ae-bc6a-47f1-8f15-2aab1facf7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264265304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2264265304
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.73353867
Short name T626
Test name
Test status
Simulation time 44675516 ps
CPU time 2 seconds
Started Jun 02 03:03:19 PM PDT 24
Finished Jun 02 03:03:22 PM PDT 24
Peak memory 210084 kb
Host smart-4bbbe670-141d-443e-bbd3-ee7fc8d22c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73353867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.73353867
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3069948500
Short name T660
Test name
Test status
Simulation time 126674620 ps
CPU time 0.77 seconds
Started Jun 02 03:03:23 PM PDT 24
Finished Jun 02 03:03:25 PM PDT 24
Peak memory 205924 kb
Host smart-657d095a-c572-487a-b8e0-3f0e4494ed8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069948500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3069948500
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.4183291265
Short name T36
Test name
Test status
Simulation time 199761953 ps
CPU time 3.63 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:23 PM PDT 24
Peak memory 215188 kb
Host smart-035f9937-2cf0-439f-b7b1-a527cf786a40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183291265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4183291265
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3811158537
Short name T732
Test name
Test status
Simulation time 102266642 ps
CPU time 4.21 seconds
Started Jun 02 03:03:17 PM PDT 24
Finished Jun 02 03:03:23 PM PDT 24
Peak memory 218200 kb
Host smart-ebbcda42-2553-4ee5-9c24-186015db234b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811158537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3811158537
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.180638984
Short name T74
Test name
Test status
Simulation time 41881770 ps
CPU time 2.37 seconds
Started Jun 02 03:03:17 PM PDT 24
Finished Jun 02 03:03:21 PM PDT 24
Peak memory 208732 kb
Host smart-653404ea-6d1b-4a29-90a9-96d06dc456a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180638984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.180638984
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1638671538
Short name T580
Test name
Test status
Simulation time 35720529 ps
CPU time 1.87 seconds
Started Jun 02 03:03:21 PM PDT 24
Finished Jun 02 03:03:23 PM PDT 24
Peak memory 214272 kb
Host smart-2afb2058-aebc-4a8f-94c4-6562bc4df8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638671538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1638671538
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.675234317
Short name T269
Test name
Test status
Simulation time 324114821 ps
CPU time 3.42 seconds
Started Jun 02 03:03:19 PM PDT 24
Finished Jun 02 03:03:24 PM PDT 24
Peak memory 220508 kb
Host smart-b28c9488-c9ae-4835-9fbc-b74b765f8d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675234317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.675234317
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.574558074
Short name T208
Test name
Test status
Simulation time 539426918 ps
CPU time 5.57 seconds
Started Jun 02 03:03:19 PM PDT 24
Finished Jun 02 03:03:26 PM PDT 24
Peak memory 222388 kb
Host smart-c930c6d7-dca5-41b4-b307-a3dd6d020101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574558074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.574558074
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3248366083
Short name T319
Test name
Test status
Simulation time 187740899 ps
CPU time 4.77 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:24 PM PDT 24
Peak memory 214388 kb
Host smart-3022822b-2017-4bb9-bb54-f5abced21094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248366083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3248366083
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.969259627
Short name T640
Test name
Test status
Simulation time 76433722 ps
CPU time 1.82 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:21 PM PDT 24
Peak memory 206784 kb
Host smart-25287375-ff86-4975-ad44-559ce26a322f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969259627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.969259627
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1572474910
Short name T449
Test name
Test status
Simulation time 70820681 ps
CPU time 3.47 seconds
Started Jun 02 03:03:18 PM PDT 24
Finished Jun 02 03:03:23 PM PDT 24
Peak memory 208060 kb
Host smart-66a55343-9181-4321-ae93-a94b0e920b0d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572474910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1572474910
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1813630527
Short name T840
Test name
Test status
Simulation time 231395429 ps
CPU time 3.28 seconds
Started Jun 02 03:03:16 PM PDT 24
Finished Jun 02 03:03:20 PM PDT 24
Peak memory 208884 kb
Host smart-be7a001c-1bf1-4836-8c60-6d853ff0ab59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813630527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1813630527
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1096650925
Short name T554
Test name
Test status
Simulation time 6258029862 ps
CPU time 62.73 seconds
Started Jun 02 03:03:19 PM PDT 24
Finished Jun 02 03:04:23 PM PDT 24
Peak memory 208060 kb
Host smart-d6cb65f3-a46c-4914-9b9d-15d16b719dad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096650925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1096650925
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1113153289
Short name T277
Test name
Test status
Simulation time 52657871 ps
CPU time 2.05 seconds
Started Jun 02 03:03:19 PM PDT 24
Finished Jun 02 03:03:23 PM PDT 24
Peak memory 209628 kb
Host smart-4839856e-9e23-4e24-9303-2c4c8a804fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113153289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1113153289
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1642039114
Short name T684
Test name
Test status
Simulation time 95532039 ps
CPU time 1.76 seconds
Started Jun 02 03:03:16 PM PDT 24
Finished Jun 02 03:03:19 PM PDT 24
Peak memory 207292 kb
Host smart-3d94d17f-fa26-49aa-9375-aea298fe9dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642039114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1642039114
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.960160659
Short name T325
Test name
Test status
Simulation time 2512183742 ps
CPU time 72.55 seconds
Started Jun 02 03:03:26 PM PDT 24
Finished Jun 02 03:04:39 PM PDT 24
Peak memory 216084 kb
Host smart-ebcccbbf-6d8d-4c26-b150-80074e0f598c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960160659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.960160659
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.4190184072
Short name T120
Test name
Test status
Simulation time 621854150 ps
CPU time 10.27 seconds
Started Jun 02 03:03:24 PM PDT 24
Finished Jun 02 03:03:35 PM PDT 24
Peak memory 219692 kb
Host smart-1e42c6b3-331c-4b33-9543-24d475f4b456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190184072 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.4190184072
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3966268982
Short name T641
Test name
Test status
Simulation time 215666615 ps
CPU time 6.13 seconds
Started Jun 02 03:03:20 PM PDT 24
Finished Jun 02 03:03:27 PM PDT 24
Peak memory 208280 kb
Host smart-a32c424d-4b75-43b4-bc38-110b828190ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966268982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3966268982
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3542341639
Short name T636
Test name
Test status
Simulation time 63229003 ps
CPU time 2.1 seconds
Started Jun 02 03:03:19 PM PDT 24
Finished Jun 02 03:03:22 PM PDT 24
Peak memory 210216 kb
Host smart-a46b7bd4-1d3b-4177-93c8-c79eda97494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542341639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3542341639
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3387547225
Short name T742
Test name
Test status
Simulation time 26305869 ps
CPU time 0.74 seconds
Started Jun 02 03:03:24 PM PDT 24
Finished Jun 02 03:03:26 PM PDT 24
Peak memory 205912 kb
Host smart-ba806ced-cb78-4e99-9de0-bfb63da8edb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387547225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3387547225
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3177772593
Short name T906
Test name
Test status
Simulation time 9004703339 ps
CPU time 140.06 seconds
Started Jun 02 03:03:24 PM PDT 24
Finished Jun 02 03:05:45 PM PDT 24
Peak memory 215076 kb
Host smart-fa8e8369-ff80-45f9-b832-deba5c51c118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177772593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3177772593
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1275536307
Short name T539
Test name
Test status
Simulation time 104413787 ps
CPU time 2.08 seconds
Started Jun 02 03:03:25 PM PDT 24
Finished Jun 02 03:03:27 PM PDT 24
Peak memory 218164 kb
Host smart-03b4150c-11ce-4dec-967d-f44be956968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275536307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1275536307
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1930260326
Short name T749
Test name
Test status
Simulation time 61103302 ps
CPU time 3.18 seconds
Started Jun 02 03:03:25 PM PDT 24
Finished Jun 02 03:03:29 PM PDT 24
Peak memory 214260 kb
Host smart-e23b5008-71be-4688-a54e-6bc09f5f643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930260326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1930260326
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3230540752
Short name T647
Test name
Test status
Simulation time 599376310 ps
CPU time 4.97 seconds
Started Jun 02 03:03:27 PM PDT 24
Finished Jun 02 03:03:33 PM PDT 24
Peak memory 214400 kb
Host smart-451c0eec-b6d9-44b2-b375-fa3012f100e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230540752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3230540752
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2755982929
Short name T513
Test name
Test status
Simulation time 615153716 ps
CPU time 3.83 seconds
Started Jun 02 03:03:24 PM PDT 24
Finished Jun 02 03:03:29 PM PDT 24
Peak memory 214252 kb
Host smart-6d9febf5-534a-4b9d-a9ca-c8d6f8a9843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755982929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2755982929
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.287029189
Short name T832
Test name
Test status
Simulation time 429422018 ps
CPU time 5.09 seconds
Started Jun 02 03:03:23 PM PDT 24
Finished Jun 02 03:03:29 PM PDT 24
Peak memory 214328 kb
Host smart-37795d6f-96f3-47bc-a51d-49a0fd8e8485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287029189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.287029189
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3947742715
Short name T236
Test name
Test status
Simulation time 140701943 ps
CPU time 3.82 seconds
Started Jun 02 03:03:26 PM PDT 24
Finished Jun 02 03:03:30 PM PDT 24
Peak memory 208900 kb
Host smart-099db588-2571-4a28-8614-368b72311830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947742715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3947742715
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3678406124
Short name T407
Test name
Test status
Simulation time 1963918975 ps
CPU time 7.73 seconds
Started Jun 02 03:03:24 PM PDT 24
Finished Jun 02 03:03:33 PM PDT 24
Peak memory 208180 kb
Host smart-8da427d8-c0a5-415a-8c68-2d02c705e530
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678406124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3678406124
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2722907242
Short name T341
Test name
Test status
Simulation time 249894981 ps
CPU time 5.32 seconds
Started Jun 02 03:03:23 PM PDT 24
Finished Jun 02 03:03:29 PM PDT 24
Peak memory 208216 kb
Host smart-49fb3df2-dca8-4b8b-90d7-c1a736730c7a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722907242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2722907242
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3359501679
Short name T339
Test name
Test status
Simulation time 194999296 ps
CPU time 5.37 seconds
Started Jun 02 03:03:26 PM PDT 24
Finished Jun 02 03:03:31 PM PDT 24
Peak memory 208720 kb
Host smart-120cf3a5-5538-46c7-a0bd-df0495545432
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359501679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3359501679
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1242199236
Short name T380
Test name
Test status
Simulation time 35572029 ps
CPU time 1.79 seconds
Started Jun 02 03:03:27 PM PDT 24
Finished Jun 02 03:03:30 PM PDT 24
Peak memory 208292 kb
Host smart-b80ed586-366b-4571-95be-e77b15d0390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242199236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1242199236
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.258150051
Short name T415
Test name
Test status
Simulation time 44323630 ps
CPU time 2.49 seconds
Started Jun 02 03:03:23 PM PDT 24
Finished Jun 02 03:03:26 PM PDT 24
Peak memory 207804 kb
Host smart-65719e5d-ad82-4f20-befe-7d279bdca374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258150051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.258150051
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2882806002
Short name T100
Test name
Test status
Simulation time 237081692 ps
CPU time 7.87 seconds
Started Jun 02 03:03:23 PM PDT 24
Finished Jun 02 03:03:31 PM PDT 24
Peak memory 222588 kb
Host smart-9b6c330d-4dc3-4bce-aaed-a67d93c84141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882806002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2882806002
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.211508005
Short name T124
Test name
Test status
Simulation time 45043120 ps
CPU time 3.16 seconds
Started Jun 02 03:03:24 PM PDT 24
Finished Jun 02 03:03:28 PM PDT 24
Peak memory 220104 kb
Host smart-981b7601-8fbc-42a6-8021-4651c6a4a37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211508005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.211508005
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2347256722
Short name T895
Test name
Test status
Simulation time 17175067 ps
CPU time 0.83 seconds
Started Jun 02 03:03:31 PM PDT 24
Finished Jun 02 03:03:36 PM PDT 24
Peak memory 205896 kb
Host smart-3995573c-a3cc-4751-9c2e-ded778244817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347256722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2347256722
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1382836334
Short name T508
Test name
Test status
Simulation time 1137582999 ps
CPU time 4.88 seconds
Started Jun 02 03:03:31 PM PDT 24
Finished Jun 02 03:03:37 PM PDT 24
Peak memory 209312 kb
Host smart-70c00943-eb90-44ec-b001-d4bed91e25bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382836334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1382836334
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.503481851
Short name T643
Test name
Test status
Simulation time 433258457 ps
CPU time 3.62 seconds
Started Jun 02 03:03:36 PM PDT 24
Finished Jun 02 03:03:40 PM PDT 24
Peak memory 210196 kb
Host smart-93858b0e-f33c-49e5-9bd1-64e3f2ea08dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503481851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.503481851
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1644726322
Short name T95
Test name
Test status
Simulation time 726403703 ps
CPU time 10.2 seconds
Started Jun 02 03:03:30 PM PDT 24
Finished Jun 02 03:03:40 PM PDT 24
Peak memory 214352 kb
Host smart-a3f13110-7969-4744-851a-ce4af788296b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644726322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1644726322
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.660122755
Short name T783
Test name
Test status
Simulation time 448291230 ps
CPU time 3.86 seconds
Started Jun 02 03:03:31 PM PDT 24
Finished Jun 02 03:03:36 PM PDT 24
Peak memory 221572 kb
Host smart-cd0a16ac-e8c3-415a-991f-2fd39177890a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660122755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.660122755
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4138396259
Short name T67
Test name
Test status
Simulation time 175164453 ps
CPU time 7.38 seconds
Started Jun 02 03:03:31 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 222528 kb
Host smart-c0228520-ef32-4884-9b59-db50fc6b69f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138396259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4138396259
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2643864628
Short name T594
Test name
Test status
Simulation time 697034169 ps
CPU time 6.13 seconds
Started Jun 02 03:03:25 PM PDT 24
Finished Jun 02 03:03:32 PM PDT 24
Peak memory 214324 kb
Host smart-a9c44f33-2567-4bcc-8fd5-0cd43048326a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643864628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2643864628
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4183952649
Short name T519
Test name
Test status
Simulation time 1192955495 ps
CPU time 17.37 seconds
Started Jun 02 03:03:23 PM PDT 24
Finished Jun 02 03:03:41 PM PDT 24
Peak memory 207972 kb
Host smart-5703e7cd-c87e-41c4-8e75-96b6a6604c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183952649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4183952649
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3406443287
Short name T122
Test name
Test status
Simulation time 61136509 ps
CPU time 3.32 seconds
Started Jun 02 03:03:25 PM PDT 24
Finished Jun 02 03:03:29 PM PDT 24
Peak memory 209052 kb
Host smart-70e4c3f4-9108-4fee-a84b-8834050c2ddc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406443287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3406443287
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1320806294
Short name T586
Test name
Test status
Simulation time 206672590 ps
CPU time 7.67 seconds
Started Jun 02 03:03:25 PM PDT 24
Finished Jun 02 03:03:33 PM PDT 24
Peak memory 208344 kb
Host smart-83a5a926-f8e8-495e-bad1-07783cc43cec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320806294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1320806294
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1159908971
Short name T833
Test name
Test status
Simulation time 2437806246 ps
CPU time 25.82 seconds
Started Jun 02 03:03:25 PM PDT 24
Finished Jun 02 03:03:52 PM PDT 24
Peak memory 208280 kb
Host smart-70350c6d-7f9e-4aa5-be4d-a394061c2d1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159908971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1159908971
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3060732217
Short name T806
Test name
Test status
Simulation time 142645638 ps
CPU time 2.11 seconds
Started Jun 02 03:03:30 PM PDT 24
Finished Jun 02 03:03:33 PM PDT 24
Peak memory 208536 kb
Host smart-0ad69417-9917-43f6-8939-875840458b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060732217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3060732217
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.4004610783
Short name T789
Test name
Test status
Simulation time 126772568 ps
CPU time 3.01 seconds
Started Jun 02 03:03:25 PM PDT 24
Finished Jun 02 03:03:28 PM PDT 24
Peak memory 207884 kb
Host smart-7e6a520e-c576-4a8d-b946-325047e31545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004610783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.4004610783
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.827213959
Short name T517
Test name
Test status
Simulation time 36580729 ps
CPU time 2.37 seconds
Started Jun 02 03:03:30 PM PDT 24
Finished Jun 02 03:03:33 PM PDT 24
Peak memory 220176 kb
Host smart-22c16fbe-4e5c-4970-9c0d-e328f4204e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827213959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.827213959
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3782648533
Short name T262
Test name
Test status
Simulation time 381586014 ps
CPU time 4.84 seconds
Started Jun 02 03:03:30 PM PDT 24
Finished Jun 02 03:03:35 PM PDT 24
Peak memory 207492 kb
Host smart-42aca213-41d0-4a3e-a698-f8066cf376eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782648533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3782648533
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3885733457
Short name T180
Test name
Test status
Simulation time 1037189280 ps
CPU time 4.65 seconds
Started Jun 02 03:03:30 PM PDT 24
Finished Jun 02 03:03:35 PM PDT 24
Peak memory 210380 kb
Host smart-40ff6125-a0a3-41fb-bbde-c74b96b0df56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885733457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3885733457
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2256782619
Short name T98
Test name
Test status
Simulation time 178993151 ps
CPU time 0.83 seconds
Started Jun 02 03:03:35 PM PDT 24
Finished Jun 02 03:03:36 PM PDT 24
Peak memory 205936 kb
Host smart-ffc9eea9-3dcf-4c44-bb33-4e78a14c1527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256782619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2256782619
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2749557868
Short name T372
Test name
Test status
Simulation time 115943333 ps
CPU time 2.48 seconds
Started Jun 02 03:03:31 PM PDT 24
Finished Jun 02 03:03:34 PM PDT 24
Peak memory 214308 kb
Host smart-71b17aed-7356-4bb2-8995-8303e71408c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749557868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2749557868
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.348022343
Short name T204
Test name
Test status
Simulation time 869318630 ps
CPU time 2.55 seconds
Started Jun 02 03:03:36 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 210096 kb
Host smart-f9d103bb-1dda-49a8-abfb-ad49b67ac4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348022343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.348022343
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3849994982
Short name T872
Test name
Test status
Simulation time 125341731 ps
CPU time 3.76 seconds
Started Jun 02 03:03:35 PM PDT 24
Finished Jun 02 03:03:40 PM PDT 24
Peak memory 218468 kb
Host smart-dcd67feb-516e-47ff-8431-eddaf678deae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849994982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3849994982
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.4253855148
Short name T219
Test name
Test status
Simulation time 804083590 ps
CPU time 5.93 seconds
Started Jun 02 03:03:35 PM PDT 24
Finished Jun 02 03:03:42 PM PDT 24
Peak memory 209300 kb
Host smart-6793a6b1-fa8a-4e7a-a540-431e62e5492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253855148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4253855148
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1216979493
Short name T364
Test name
Test status
Simulation time 149006134 ps
CPU time 4.58 seconds
Started Jun 02 03:03:35 PM PDT 24
Finished Jun 02 03:03:40 PM PDT 24
Peak memory 214224 kb
Host smart-53880ee6-6960-4876-a264-504d1c1ec621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216979493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1216979493
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2323954961
Short name T881
Test name
Test status
Simulation time 240533268 ps
CPU time 3.02 seconds
Started Jun 02 03:03:36 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 209656 kb
Host smart-e8f8052e-e67f-47d4-a509-9843fb0c2708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323954961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2323954961
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3242213903
Short name T324
Test name
Test status
Simulation time 43266556 ps
CPU time 3.05 seconds
Started Jun 02 03:03:29 PM PDT 24
Finished Jun 02 03:03:32 PM PDT 24
Peak memory 209912 kb
Host smart-c3dcacaa-3b96-426e-a09b-88091cf5c735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242213903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3242213903
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2816696222
Short name T192
Test name
Test status
Simulation time 124088549 ps
CPU time 2.37 seconds
Started Jun 02 03:03:36 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 207428 kb
Host smart-c29843a7-010e-422b-8753-83e9ddd174f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816696222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2816696222
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3175214042
Short name T489
Test name
Test status
Simulation time 56113559 ps
CPU time 2.91 seconds
Started Jun 02 03:03:35 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 208404 kb
Host smart-e0c5d314-adf1-4d7c-a720-e5ee8440fb9f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175214042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3175214042
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3973392287
Short name T420
Test name
Test status
Simulation time 140238111 ps
CPU time 3.42 seconds
Started Jun 02 03:03:36 PM PDT 24
Finished Jun 02 03:03:40 PM PDT 24
Peak memory 208524 kb
Host smart-3358b02c-e102-4aea-a18f-f164166d5e37
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973392287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3973392287
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3853311369
Short name T650
Test name
Test status
Simulation time 19984682 ps
CPU time 1.89 seconds
Started Jun 02 03:03:32 PM PDT 24
Finished Jun 02 03:03:34 PM PDT 24
Peak memory 206968 kb
Host smart-beaaa97d-9c7b-4617-a527-e230399fcc36
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853311369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3853311369
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4272952008
Short name T831
Test name
Test status
Simulation time 64931307 ps
CPU time 2.99 seconds
Started Jun 02 03:03:35 PM PDT 24
Finished Jun 02 03:03:38 PM PDT 24
Peak memory 209516 kb
Host smart-ff4bb13d-8de8-4236-b3b8-9949f54ca618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272952008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4272952008
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2081573062
Short name T780
Test name
Test status
Simulation time 66540365 ps
CPU time 2.62 seconds
Started Jun 02 03:03:31 PM PDT 24
Finished Jun 02 03:03:34 PM PDT 24
Peak memory 208404 kb
Host smart-ea2d9fe3-5d85-4191-a461-86e8f2e58707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081573062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2081573062
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3856296385
Short name T295
Test name
Test status
Simulation time 407744969 ps
CPU time 11.94 seconds
Started Jun 02 03:03:34 PM PDT 24
Finished Jun 02 03:03:47 PM PDT 24
Peak memory 214556 kb
Host smart-0ed7cc02-d7a6-4da6-ad95-3075d1baf7d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856296385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3856296385
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4204315848
Short name T227
Test name
Test status
Simulation time 128230531 ps
CPU time 5.3 seconds
Started Jun 02 03:03:35 PM PDT 24
Finished Jun 02 03:03:41 PM PDT 24
Peak memory 209260 kb
Host smart-ec8d062e-cebb-4dcc-91df-a41b43948bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204315848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4204315848
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.523318100
Short name T365
Test name
Test status
Simulation time 108892577 ps
CPU time 2.58 seconds
Started Jun 02 03:03:35 PM PDT 24
Finished Jun 02 03:03:38 PM PDT 24
Peak memory 210220 kb
Host smart-cba4347a-8453-42b7-8ad1-d57a558401ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523318100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.523318100
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3681841945
Short name T883
Test name
Test status
Simulation time 113757554 ps
CPU time 0.82 seconds
Started Jun 02 03:03:43 PM PDT 24
Finished Jun 02 03:03:44 PM PDT 24
Peak memory 205936 kb
Host smart-45f00261-cea0-4569-96a5-58bad395b65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681841945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3681841945
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.671265483
Short name T398
Test name
Test status
Simulation time 350785344 ps
CPU time 19.86 seconds
Started Jun 02 03:03:37 PM PDT 24
Finished Jun 02 03:03:57 PM PDT 24
Peak memory 214348 kb
Host smart-73e4f468-9cb9-4704-81cb-764668a5f26d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671265483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.671265483
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.116117179
Short name T27
Test name
Test status
Simulation time 2872522386 ps
CPU time 36.95 seconds
Started Jun 02 03:03:45 PM PDT 24
Finished Jun 02 03:04:23 PM PDT 24
Peak memory 222764 kb
Host smart-23517dad-6eec-497a-88b9-279dc0936445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116117179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.116117179
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1288466584
Short name T785
Test name
Test status
Simulation time 165105205 ps
CPU time 1.52 seconds
Started Jun 02 03:03:36 PM PDT 24
Finished Jun 02 03:03:38 PM PDT 24
Peak memory 207800 kb
Host smart-cbc2e049-6c95-4fa8-bfc2-f183b930c0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288466584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1288466584
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1662530756
Short name T83
Test name
Test status
Simulation time 69541725 ps
CPU time 2.85 seconds
Started Jun 02 03:03:52 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 214416 kb
Host smart-3a56d655-380a-46c7-a35d-4b3bb58118f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662530756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1662530756
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3007984823
Short name T689
Test name
Test status
Simulation time 97062432 ps
CPU time 2.92 seconds
Started Jun 02 03:03:45 PM PDT 24
Finished Jun 02 03:03:49 PM PDT 24
Peak memory 220700 kb
Host smart-ce01bb77-8039-4f2b-ae23-b9296c0b47cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007984823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3007984823
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_random.1504007975
Short name T899
Test name
Test status
Simulation time 891166575 ps
CPU time 10.46 seconds
Started Jun 02 03:03:37 PM PDT 24
Finished Jun 02 03:03:48 PM PDT 24
Peak memory 208684 kb
Host smart-10ff50fa-370b-4533-b29d-635d08cf7e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504007975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1504007975
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1850069678
Short name T241
Test name
Test status
Simulation time 192528514 ps
CPU time 2.89 seconds
Started Jun 02 03:03:35 PM PDT 24
Finished Jun 02 03:03:38 PM PDT 24
Peak memory 208272 kb
Host smart-771477da-ecc7-4b4d-9c04-3f7c2767e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850069678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1850069678
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3431749028
Short name T558
Test name
Test status
Simulation time 366195416 ps
CPU time 2.93 seconds
Started Jun 02 03:03:36 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 206908 kb
Host smart-3daeb163-0ecc-4e5f-aa05-7359a3117b44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431749028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3431749028
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3630207345
Short name T846
Test name
Test status
Simulation time 46791184 ps
CPU time 1.9 seconds
Started Jun 02 03:03:37 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 208832 kb
Host smart-92dac24c-b149-49cb-8974-7395c0cbeaaf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630207345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3630207345
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2115639038
Short name T473
Test name
Test status
Simulation time 67970129 ps
CPU time 3.36 seconds
Started Jun 02 03:03:37 PM PDT 24
Finished Jun 02 03:03:41 PM PDT 24
Peak memory 206812 kb
Host smart-c586f2ce-080c-4337-9fcd-d34cd059008c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115639038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2115639038
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1819025646
Short name T273
Test name
Test status
Simulation time 447741448 ps
CPU time 3.4 seconds
Started Jun 02 03:03:51 PM PDT 24
Finished Jun 02 03:03:55 PM PDT 24
Peak memory 209656 kb
Host smart-c37d9b62-0877-4997-a424-7e24b79951bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819025646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1819025646
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3010246982
Short name T912
Test name
Test status
Simulation time 416727062 ps
CPU time 2.85 seconds
Started Jun 02 03:03:36 PM PDT 24
Finished Jun 02 03:03:39 PM PDT 24
Peak memory 206716 kb
Host smart-c92b427f-4ce0-45d6-9ab3-8108c81e5053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010246982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3010246982
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.637701812
Short name T290
Test name
Test status
Simulation time 335223873 ps
CPU time 8.35 seconds
Started Jun 02 03:03:42 PM PDT 24
Finished Jun 02 03:03:51 PM PDT 24
Peak memory 220744 kb
Host smart-b203b58e-6a86-4bd4-ae99-e5ced3b709ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637701812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.637701812
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.611692413
Short name T151
Test name
Test status
Simulation time 1804294076 ps
CPU time 19.12 seconds
Started Jun 02 03:03:46 PM PDT 24
Finished Jun 02 03:04:05 PM PDT 24
Peak memory 222704 kb
Host smart-f8f2da85-4f67-4712-8824-9fd915db1c3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611692413 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.611692413
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.943093527
Short name T247
Test name
Test status
Simulation time 1996154894 ps
CPU time 39.13 seconds
Started Jun 02 03:03:49 PM PDT 24
Finished Jun 02 03:04:29 PM PDT 24
Peak memory 214328 kb
Host smart-1ff1b586-67ba-4c7f-a41b-5b30f0ea9326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943093527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.943093527
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.149936849
Short name T807
Test name
Test status
Simulation time 322050748 ps
CPU time 3.58 seconds
Started Jun 02 03:03:47 PM PDT 24
Finished Jun 02 03:03:51 PM PDT 24
Peak memory 210416 kb
Host smart-47478291-865d-4cf2-a5f8-f0bd32b8dd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149936849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.149936849
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2801311359
Short name T127
Test name
Test status
Simulation time 8456848 ps
CPU time 0.79 seconds
Started Jun 02 03:03:52 PM PDT 24
Finished Jun 02 03:03:53 PM PDT 24
Peak memory 205944 kb
Host smart-24a4f45a-c96b-4118-9ad9-f1c3dde0e766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801311359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2801311359
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2198690153
Short name T355
Test name
Test status
Simulation time 588545992 ps
CPU time 8.32 seconds
Started Jun 02 03:03:48 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 214960 kb
Host smart-c071a4b3-a49c-43b1-9b8d-ba0423a2decd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198690153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2198690153
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3466610875
Short name T628
Test name
Test status
Simulation time 50432056 ps
CPU time 2.27 seconds
Started Jun 02 03:03:41 PM PDT 24
Finished Jun 02 03:03:44 PM PDT 24
Peak memory 208952 kb
Host smart-644fa1aa-f836-4651-b159-a29b0bd8d8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466610875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3466610875
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1683585295
Short name T292
Test name
Test status
Simulation time 170553053 ps
CPU time 5.68 seconds
Started Jun 02 03:03:49 PM PDT 24
Finished Jun 02 03:03:55 PM PDT 24
Peak memory 222472 kb
Host smart-eab8eaf8-dfa2-4867-9ada-62ec57467826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683585295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1683585295
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.110993529
Short name T916
Test name
Test status
Simulation time 32388689 ps
CPU time 1.99 seconds
Started Jun 02 03:03:52 PM PDT 24
Finished Jun 02 03:03:55 PM PDT 24
Peak memory 214244 kb
Host smart-18ee1eae-e669-4848-bd49-31a1c6134643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110993529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.110993529
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_random.1309625366
Short name T722
Test name
Test status
Simulation time 185011488 ps
CPU time 2.81 seconds
Started Jun 02 03:03:46 PM PDT 24
Finished Jun 02 03:03:49 PM PDT 24
Peak memory 209304 kb
Host smart-883c7b75-4d79-46cd-aefe-b2d648f24671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309625366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1309625366
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3100890147
Short name T668
Test name
Test status
Simulation time 92799382 ps
CPU time 3.52 seconds
Started Jun 02 03:03:42 PM PDT 24
Finished Jun 02 03:03:46 PM PDT 24
Peak memory 206752 kb
Host smart-7652eb39-9a47-4f6f-9167-f050b6d7bdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100890147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3100890147
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.64476408
Short name T686
Test name
Test status
Simulation time 711805421 ps
CPU time 5.56 seconds
Started Jun 02 03:03:49 PM PDT 24
Finished Jun 02 03:03:55 PM PDT 24
Peak memory 207932 kb
Host smart-ad2c42cb-fe4a-4ba9-8464-f8eed80158c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64476408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.64476408
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1951248059
Short name T870
Test name
Test status
Simulation time 84400928 ps
CPU time 3.9 seconds
Started Jun 02 03:03:47 PM PDT 24
Finished Jun 02 03:03:51 PM PDT 24
Peak memory 209088 kb
Host smart-c1cae944-3dd3-4d13-9de5-ada306f38af5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951248059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1951248059
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2254013455
Short name T897
Test name
Test status
Simulation time 907508655 ps
CPU time 6.62 seconds
Started Jun 02 03:03:48 PM PDT 24
Finished Jun 02 03:03:55 PM PDT 24
Peak memory 207016 kb
Host smart-19a15377-3ce5-40ba-890a-1a77cf0c1d6e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254013455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2254013455
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2667351513
Short name T763
Test name
Test status
Simulation time 115511906 ps
CPU time 2.24 seconds
Started Jun 02 03:03:53 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 209428 kb
Host smart-00fb6ee1-6f66-423e-992a-b3ea40a8247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667351513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2667351513
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.4173800737
Short name T584
Test name
Test status
Simulation time 76025803 ps
CPU time 2.71 seconds
Started Jun 02 03:03:48 PM PDT 24
Finished Jun 02 03:03:51 PM PDT 24
Peak memory 208544 kb
Host smart-04699fc5-98e0-4220-9cd3-47e4bc32de34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173800737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.4173800737
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1648155025
Short name T225
Test name
Test status
Simulation time 443617678 ps
CPU time 6.95 seconds
Started Jun 02 03:03:42 PM PDT 24
Finished Jun 02 03:03:50 PM PDT 24
Peak memory 208260 kb
Host smart-6901daa4-d1e4-4d8a-b0c6-7e1a5c06941e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648155025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1648155025
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2312746147
Short name T474
Test name
Test status
Simulation time 57148940 ps
CPU time 0.93 seconds
Started Jun 02 03:04:01 PM PDT 24
Finished Jun 02 03:04:02 PM PDT 24
Peak memory 205944 kb
Host smart-770a2640-87e7-4107-a2be-4b165f883c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312746147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2312746147
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.209411087
Short name T860
Test name
Test status
Simulation time 142288511 ps
CPU time 2.99 seconds
Started Jun 02 03:03:52 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 214388 kb
Host smart-db9273d6-b18b-497c-b05c-44fb7b35863f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209411087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.209411087
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2825160539
Short name T374
Test name
Test status
Simulation time 237836717 ps
CPU time 4.3 seconds
Started Jun 02 03:03:59 PM PDT 24
Finished Jun 02 03:04:04 PM PDT 24
Peak memory 218284 kb
Host smart-ebe8d917-c669-4a3e-86be-c715ae6adb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825160539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2825160539
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4063459358
Short name T819
Test name
Test status
Simulation time 370526105 ps
CPU time 3.94 seconds
Started Jun 02 03:03:52 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 218240 kb
Host smart-7491a392-176a-4b63-a8de-876149f0f884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063459358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4063459358
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1528247787
Short name T19
Test name
Test status
Simulation time 63730991 ps
CPU time 2.52 seconds
Started Jun 02 03:03:52 PM PDT 24
Finished Jun 02 03:03:55 PM PDT 24
Peak memory 220704 kb
Host smart-88325c3a-78eb-49d0-b3a9-6a1cbcd0b012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528247787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1528247787
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.849755355
Short name T566
Test name
Test status
Simulation time 78769144 ps
CPU time 2.72 seconds
Started Jun 02 03:03:56 PM PDT 24
Finished Jun 02 03:03:59 PM PDT 24
Peak memory 222424 kb
Host smart-c9f4a22e-f66a-4493-b728-641f6f6f93d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849755355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.849755355
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4004274331
Short name T486
Test name
Test status
Simulation time 203244468 ps
CPU time 5.43 seconds
Started Jun 02 03:03:53 PM PDT 24
Finished Jun 02 03:03:59 PM PDT 24
Peak memory 222436 kb
Host smart-6b1c9641-6046-4417-92da-07a35d9145a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004274331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4004274331
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3791108
Short name T280
Test name
Test status
Simulation time 85369623 ps
CPU time 4.02 seconds
Started Jun 02 03:03:52 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 208576 kb
Host smart-cf63f1df-d7d8-45b9-8201-d5b5c3d442ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3791108
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3910660388
Short name T817
Test name
Test status
Simulation time 22545317 ps
CPU time 1.79 seconds
Started Jun 02 03:03:55 PM PDT 24
Finished Jun 02 03:03:57 PM PDT 24
Peak memory 206844 kb
Host smart-1952ce3f-0a44-4f56-8855-16e9a016fdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910660388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3910660388
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.840411058
Short name T536
Test name
Test status
Simulation time 74030965 ps
CPU time 2.31 seconds
Started Jun 02 03:03:50 PM PDT 24
Finished Jun 02 03:03:52 PM PDT 24
Peak memory 207156 kb
Host smart-9e694b75-d444-4d8b-8df1-1ef287007383
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840411058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.840411058
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.139053146
Short name T745
Test name
Test status
Simulation time 230270683 ps
CPU time 2.96 seconds
Started Jun 02 03:03:52 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 206948 kb
Host smart-eecf77b2-7671-42ee-9b30-1dcc435ba58d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139053146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.139053146
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3016805993
Short name T683
Test name
Test status
Simulation time 142473511 ps
CPU time 3.77 seconds
Started Jun 02 03:03:52 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 208760 kb
Host smart-75844123-22c8-4ad0-949c-61c71f6a5aba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016805993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3016805993
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1134922831
Short name T713
Test name
Test status
Simulation time 542179167 ps
CPU time 3.78 seconds
Started Jun 02 03:03:58 PM PDT 24
Finished Jun 02 03:04:03 PM PDT 24
Peak memory 214320 kb
Host smart-7f324d91-2a01-464f-aa39-7de50cd0ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134922831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1134922831
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1518666004
Short name T531
Test name
Test status
Simulation time 70633804 ps
CPU time 2.99 seconds
Started Jun 02 03:03:52 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 208100 kb
Host smart-8e313d34-e69a-4bc4-a9a2-172e48aaed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518666004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1518666004
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3517427872
Short name T726
Test name
Test status
Simulation time 39412851 ps
CPU time 2.92 seconds
Started Jun 02 03:03:54 PM PDT 24
Finished Jun 02 03:03:58 PM PDT 24
Peak memory 214304 kb
Host smart-1ad41438-659a-4654-84ba-951270f113f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517427872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3517427872
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3361658688
Short name T369
Test name
Test status
Simulation time 114747904 ps
CPU time 1.62 seconds
Started Jun 02 03:03:55 PM PDT 24
Finished Jun 02 03:03:57 PM PDT 24
Peak memory 209672 kb
Host smart-e051c472-e9b2-4a37-8d06-1bad4aff2c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361658688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3361658688
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1405745461
Short name T583
Test name
Test status
Simulation time 91179196 ps
CPU time 0.85 seconds
Started Jun 02 03:04:05 PM PDT 24
Finished Jun 02 03:04:06 PM PDT 24
Peak memory 205924 kb
Host smart-6c4f4564-8a83-4e00-b487-eb76518c2153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405745461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1405745461
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3115578100
Short name T28
Test name
Test status
Simulation time 44204897 ps
CPU time 2.26 seconds
Started Jun 02 03:03:57 PM PDT 24
Finished Jun 02 03:03:59 PM PDT 24
Peak memory 210008 kb
Host smart-26f53335-8625-49ee-92d8-75a860e890c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115578100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3115578100
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1125617991
Short name T60
Test name
Test status
Simulation time 465702479 ps
CPU time 5.67 seconds
Started Jun 02 03:03:59 PM PDT 24
Finished Jun 02 03:04:05 PM PDT 24
Peak memory 208812 kb
Host smart-1925decc-705e-4abe-a6e5-e269dcbd391a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125617991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1125617991
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2905471890
Short name T905
Test name
Test status
Simulation time 334806997 ps
CPU time 5.42 seconds
Started Jun 02 03:03:57 PM PDT 24
Finished Jun 02 03:04:03 PM PDT 24
Peak memory 214300 kb
Host smart-cfb4d2d8-0fd0-4ecb-b91f-5df7ca5379ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905471890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2905471890
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3962456265
Short name T232
Test name
Test status
Simulation time 241615251 ps
CPU time 2.37 seconds
Started Jun 02 03:04:01 PM PDT 24
Finished Jun 02 03:04:04 PM PDT 24
Peak memory 214256 kb
Host smart-1c20bd3c-491d-4627-a9bb-497f6bceb5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962456265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3962456265
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.116771692
Short name T507
Test name
Test status
Simulation time 383736927 ps
CPU time 3.75 seconds
Started Jun 02 03:04:01 PM PDT 24
Finished Jun 02 03:04:05 PM PDT 24
Peak memory 222556 kb
Host smart-45a09fa9-5467-4153-b8b7-539ce798ef28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116771692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.116771692
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1696654425
Short name T340
Test name
Test status
Simulation time 922063942 ps
CPU time 8.69 seconds
Started Jun 02 03:03:55 PM PDT 24
Finished Jun 02 03:04:05 PM PDT 24
Peak memory 208960 kb
Host smart-6b2561a7-8d66-415e-96d4-c9eac72a5b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696654425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1696654425
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2493308568
Short name T527
Test name
Test status
Simulation time 143392983 ps
CPU time 4.64 seconds
Started Jun 02 03:04:00 PM PDT 24
Finished Jun 02 03:04:05 PM PDT 24
Peak memory 208848 kb
Host smart-947f46d7-4f08-4e2d-9a88-c2382551a6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493308568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2493308568
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1179918712
Short name T882
Test name
Test status
Simulation time 154759448 ps
CPU time 3.58 seconds
Started Jun 02 03:03:56 PM PDT 24
Finished Jun 02 03:04:00 PM PDT 24
Peak memory 206988 kb
Host smart-ff6f99f9-4d4f-4f77-84e4-5848852492a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179918712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1179918712
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2194038057
Short name T300
Test name
Test status
Simulation time 1816836645 ps
CPU time 5.95 seconds
Started Jun 02 03:03:57 PM PDT 24
Finished Jun 02 03:04:03 PM PDT 24
Peak memory 208044 kb
Host smart-70613e42-940d-41ed-b143-d3140b94c0b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194038057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2194038057
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2268534099
Short name T430
Test name
Test status
Simulation time 1171266085 ps
CPU time 31.46 seconds
Started Jun 02 03:04:03 PM PDT 24
Finished Jun 02 03:04:35 PM PDT 24
Peak memory 208528 kb
Host smart-d140369e-2eab-4ad0-8388-f113f7d0fb24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268534099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2268534099
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1847966748
Short name T468
Test name
Test status
Simulation time 126190268 ps
CPU time 2.54 seconds
Started Jun 02 03:03:56 PM PDT 24
Finished Jun 02 03:03:59 PM PDT 24
Peak memory 208208 kb
Host smart-9b071279-70a3-4bcd-8f66-62709d132c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847966748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1847966748
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3720368757
Short name T813
Test name
Test status
Simulation time 92963886 ps
CPU time 2.61 seconds
Started Jun 02 03:03:58 PM PDT 24
Finished Jun 02 03:04:01 PM PDT 24
Peak memory 206848 kb
Host smart-8a360fb8-1e5f-459a-b4f7-17433819fdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720368757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3720368757
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.588014644
Short name T873
Test name
Test status
Simulation time 3196640624 ps
CPU time 15.96 seconds
Started Jun 02 03:03:54 PM PDT 24
Finished Jun 02 03:04:10 PM PDT 24
Peak memory 208160 kb
Host smart-6608dc3d-cc59-45db-ae30-9434012ed3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588014644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.588014644
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1504007279
Short name T105
Test name
Test status
Simulation time 59571962 ps
CPU time 2.82 seconds
Started Jun 02 03:04:02 PM PDT 24
Finished Jun 02 03:04:05 PM PDT 24
Peak memory 210132 kb
Host smart-42215cc2-e35d-4b38-a927-3138881fa137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504007279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1504007279
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3152070314
Short name T419
Test name
Test status
Simulation time 12884091 ps
CPU time 0.97 seconds
Started Jun 02 03:04:08 PM PDT 24
Finished Jun 02 03:04:09 PM PDT 24
Peak memory 205860 kb
Host smart-abaa0edf-2b2e-449e-b4f3-43d2208e2e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152070314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3152070314
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2787143177
Short name T395
Test name
Test status
Simulation time 122732348 ps
CPU time 4.65 seconds
Started Jun 02 03:04:04 PM PDT 24
Finished Jun 02 03:04:09 PM PDT 24
Peak memory 222548 kb
Host smart-79805c96-cab4-45b8-8659-466bd80617e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787143177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2787143177
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3031385376
Short name T71
Test name
Test status
Simulation time 221480852 ps
CPU time 2.71 seconds
Started Jun 02 03:04:08 PM PDT 24
Finished Jun 02 03:04:11 PM PDT 24
Peak memory 216344 kb
Host smart-d6106a54-1be0-48d1-89e7-7395baa55035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031385376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3031385376
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.337519470
Short name T459
Test name
Test status
Simulation time 45567283 ps
CPU time 2.36 seconds
Started Jun 02 03:04:02 PM PDT 24
Finished Jun 02 03:04:05 PM PDT 24
Peak memory 208848 kb
Host smart-1d21550d-05c9-47d5-b6c5-13742ae6b84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337519470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.337519470
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3319135105
Short name T673
Test name
Test status
Simulation time 444183535 ps
CPU time 2.01 seconds
Started Jun 02 03:04:03 PM PDT 24
Finished Jun 02 03:04:06 PM PDT 24
Peak memory 214320 kb
Host smart-30dee18d-97dd-4759-bfb3-607378ad4bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319135105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3319135105
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3278215082
Short name T824
Test name
Test status
Simulation time 166278017 ps
CPU time 3.47 seconds
Started Jun 02 03:04:05 PM PDT 24
Finished Jun 02 03:04:09 PM PDT 24
Peak memory 214252 kb
Host smart-b9779f81-4b37-4bf0-bd71-d214f94207c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278215082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3278215082
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.798444644
Short name T533
Test name
Test status
Simulation time 1301634408 ps
CPU time 3.3 seconds
Started Jun 02 03:04:02 PM PDT 24
Finished Jun 02 03:04:06 PM PDT 24
Peak memory 214284 kb
Host smart-a840d768-9115-4bd0-a8d8-d38c688c8d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798444644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.798444644
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.384183429
Short name T265
Test name
Test status
Simulation time 90167829 ps
CPU time 4.88 seconds
Started Jun 02 03:04:03 PM PDT 24
Finished Jun 02 03:04:10 PM PDT 24
Peak memory 218488 kb
Host smart-d4ad5272-41ba-4523-9bdf-8f2bed1d1134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384183429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.384183429
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1422186051
Short name T576
Test name
Test status
Simulation time 494214120 ps
CPU time 2.49 seconds
Started Jun 02 03:04:11 PM PDT 24
Finished Jun 02 03:04:13 PM PDT 24
Peak memory 207080 kb
Host smart-51f190d7-a7ea-46d8-a46e-c5a23d5cc076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422186051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1422186051
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2372473620
Short name T479
Test name
Test status
Simulation time 28857227 ps
CPU time 2.18 seconds
Started Jun 02 03:04:06 PM PDT 24
Finished Jun 02 03:04:09 PM PDT 24
Peak memory 206852 kb
Host smart-8e46dff8-6e34-4df5-bacb-247a11acdfd6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372473620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2372473620
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.428420081
Short name T639
Test name
Test status
Simulation time 155565582 ps
CPU time 3.99 seconds
Started Jun 02 03:04:04 PM PDT 24
Finished Jun 02 03:04:09 PM PDT 24
Peak memory 207956 kb
Host smart-d822aca1-85bf-48fa-86cd-25c746da595a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428420081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.428420081
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1154737229
Short name T327
Test name
Test status
Simulation time 103709467 ps
CPU time 4.37 seconds
Started Jun 02 03:04:08 PM PDT 24
Finished Jun 02 03:04:13 PM PDT 24
Peak memory 206920 kb
Host smart-87e4d8f2-902a-4ee6-937f-b13414e8db45
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154737229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1154737229
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.805442324
Short name T17
Test name
Test status
Simulation time 557129945 ps
CPU time 4.94 seconds
Started Jun 02 03:04:04 PM PDT 24
Finished Jun 02 03:04:10 PM PDT 24
Peak memory 214236 kb
Host smart-f44710ac-ce39-4cb5-9c8d-733676e770cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805442324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.805442324
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.791278932
Short name T425
Test name
Test status
Simulation time 126540180 ps
CPU time 2.63 seconds
Started Jun 02 03:04:04 PM PDT 24
Finished Jun 02 03:04:07 PM PDT 24
Peak memory 206924 kb
Host smart-a97c2a0d-1be1-4644-9a12-7e1c4d769e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791278932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.791278932
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.538306528
Short name T161
Test name
Test status
Simulation time 6577655792 ps
CPU time 31.04 seconds
Started Jun 02 03:04:04 PM PDT 24
Finished Jun 02 03:04:35 PM PDT 24
Peak memory 217268 kb
Host smart-3069750d-22d0-4329-b266-08bd5bd5b744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538306528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.538306528
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.196104163
Short name T690
Test name
Test status
Simulation time 218605954 ps
CPU time 7.07 seconds
Started Jun 02 03:04:04 PM PDT 24
Finished Jun 02 03:04:12 PM PDT 24
Peak memory 222548 kb
Host smart-ba39147e-a373-4680-81de-34f013e704ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196104163 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.196104163
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3862069560
Short name T697
Test name
Test status
Simulation time 130025345 ps
CPU time 4.52 seconds
Started Jun 02 03:04:05 PM PDT 24
Finished Jun 02 03:04:10 PM PDT 24
Peak memory 218168 kb
Host smart-900f28d6-056d-4116-ac6b-2d1508a253e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862069560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3862069560
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.709983348
Short name T125
Test name
Test status
Simulation time 476887885 ps
CPU time 4.38 seconds
Started Jun 02 03:04:06 PM PDT 24
Finished Jun 02 03:04:11 PM PDT 24
Peak memory 210224 kb
Host smart-c04a1728-0a74-4f1d-bce7-dcd0dac25924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709983348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.709983348
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.152906194
Short name T441
Test name
Test status
Simulation time 140055091 ps
CPU time 0.76 seconds
Started Jun 02 03:00:22 PM PDT 24
Finished Jun 02 03:00:24 PM PDT 24
Peak memory 205888 kb
Host smart-d5c5f34b-6a38-4066-8284-91ecad7be364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152906194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.152906194
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2294031363
Short name T400
Test name
Test status
Simulation time 63528779 ps
CPU time 4.61 seconds
Started Jun 02 03:00:16 PM PDT 24
Finished Jun 02 03:00:21 PM PDT 24
Peak memory 214964 kb
Host smart-ba10ef74-e50f-493e-a3f5-e5cc8f9441b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294031363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2294031363
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.572071606
Short name T661
Test name
Test status
Simulation time 51123600 ps
CPU time 2.59 seconds
Started Jun 02 03:00:15 PM PDT 24
Finished Jun 02 03:00:18 PM PDT 24
Peak memory 218380 kb
Host smart-f4d8e6aa-1ada-4ca5-9dbd-7136ac4c293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572071606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.572071606
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1774992551
Short name T271
Test name
Test status
Simulation time 43266951 ps
CPU time 2.44 seconds
Started Jun 02 03:00:15 PM PDT 24
Finished Jun 02 03:00:19 PM PDT 24
Peak memory 214736 kb
Host smart-78a686d3-a524-462a-b81c-b90af9b64101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774992551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1774992551
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3001909152
Short name T310
Test name
Test status
Simulation time 308158015 ps
CPU time 2.1 seconds
Started Jun 02 03:00:15 PM PDT 24
Finished Jun 02 03:00:18 PM PDT 24
Peak memory 214276 kb
Host smart-46ecf83e-d523-4865-b5a9-fa1d7624e4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001909152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3001909152
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2178827121
Short name T528
Test name
Test status
Simulation time 354919457 ps
CPU time 3.2 seconds
Started Jun 02 03:00:16 PM PDT 24
Finished Jun 02 03:00:19 PM PDT 24
Peak memory 206420 kb
Host smart-149a2f05-6c9d-43da-8f34-76cd614d1068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178827121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2178827121
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3305383161
Short name T502
Test name
Test status
Simulation time 222530337 ps
CPU time 6.09 seconds
Started Jun 02 03:00:16 PM PDT 24
Finished Jun 02 03:00:23 PM PDT 24
Peak memory 208668 kb
Host smart-e07c67cf-11a8-4e8e-a8f0-3bb1180687b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305383161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3305383161
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3493548124
Short name T45
Test name
Test status
Simulation time 546627676 ps
CPU time 7.1 seconds
Started Jun 02 03:00:24 PM PDT 24
Finished Jun 02 03:00:31 PM PDT 24
Peak memory 233888 kb
Host smart-d3db3862-2109-4b24-a720-c757d27577a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493548124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3493548124
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.340700394
Short name T691
Test name
Test status
Simulation time 245469500 ps
CPU time 3.11 seconds
Started Jun 02 03:00:08 PM PDT 24
Finished Jun 02 03:00:11 PM PDT 24
Peak memory 206796 kb
Host smart-e21d3a5a-7a16-463a-a934-ddced4ea2b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340700394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.340700394
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2857491779
Short name T35
Test name
Test status
Simulation time 206886026 ps
CPU time 3.99 seconds
Started Jun 02 03:00:07 PM PDT 24
Finished Jun 02 03:00:12 PM PDT 24
Peak memory 208868 kb
Host smart-f8dea64f-6ddd-4d63-9543-67787c7b8d79
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857491779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2857491779
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4127725335
Short name T452
Test name
Test status
Simulation time 5702123999 ps
CPU time 37.8 seconds
Started Jun 02 03:00:09 PM PDT 24
Finished Jun 02 03:00:47 PM PDT 24
Peak memory 209016 kb
Host smart-801990e5-a9c2-4398-9fe8-0d894b0d38f0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127725335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4127725335
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3055639658
Short name T296
Test name
Test status
Simulation time 48637522 ps
CPU time 2.6 seconds
Started Jun 02 03:00:07 PM PDT 24
Finished Jun 02 03:00:10 PM PDT 24
Peak memory 208064 kb
Host smart-52b2dfc9-13c2-4d1b-8992-bc261c1d2b28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055639658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3055639658
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1377436528
Short name T620
Test name
Test status
Simulation time 65472843 ps
CPU time 2.73 seconds
Started Jun 02 03:00:24 PM PDT 24
Finished Jun 02 03:00:27 PM PDT 24
Peak memory 215996 kb
Host smart-5e10cbc7-a059-4faf-aee8-f9d943eea92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377436528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1377436528
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1555825884
Short name T674
Test name
Test status
Simulation time 1428643784 ps
CPU time 11.77 seconds
Started Jun 02 03:00:07 PM PDT 24
Finished Jun 02 03:00:19 PM PDT 24
Peak memory 208496 kb
Host smart-0d4036e2-0306-424e-aa8e-7ed29e0ab8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555825884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1555825884
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.721192630
Short name T9
Test name
Test status
Simulation time 13342171349 ps
CPU time 287.15 seconds
Started Jun 02 03:00:22 PM PDT 24
Finished Jun 02 03:05:10 PM PDT 24
Peak memory 222712 kb
Host smart-d15cb713-4463-4793-8675-077a5af2e441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721192630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.721192630
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3180070080
Short name T154
Test name
Test status
Simulation time 501109693 ps
CPU time 7.51 seconds
Started Jun 02 03:00:23 PM PDT 24
Finished Jun 02 03:00:31 PM PDT 24
Peak memory 222632 kb
Host smart-a1b3bd82-2877-4296-a915-1a3469db5788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180070080 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3180070080
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2070902204
Short name T15
Test name
Test status
Simulation time 114456478 ps
CPU time 5.28 seconds
Started Jun 02 03:00:17 PM PDT 24
Finished Jun 02 03:00:23 PM PDT 24
Peak memory 208648 kb
Host smart-22b3b0ce-f8c8-431e-92ac-813795b37d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070902204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2070902204
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.175420854
Short name T718
Test name
Test status
Simulation time 94999188 ps
CPU time 2.17 seconds
Started Jun 02 03:00:22 PM PDT 24
Finished Jun 02 03:00:25 PM PDT 24
Peak memory 209844 kb
Host smart-8783314a-c94f-4db9-91c7-89ed47650ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175420854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.175420854
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1663322188
Short name T529
Test name
Test status
Simulation time 32965346 ps
CPU time 0.75 seconds
Started Jun 02 03:04:07 PM PDT 24
Finished Jun 02 03:04:09 PM PDT 24
Peak memory 205932 kb
Host smart-b26b2b32-2c09-476c-9216-6d3d603e1ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663322188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1663322188
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1866501991
Short name T401
Test name
Test status
Simulation time 172147883 ps
CPU time 8.94 seconds
Started Jun 02 03:04:03 PM PDT 24
Finished Jun 02 03:04:13 PM PDT 24
Peak memory 214360 kb
Host smart-1ca77547-b8d3-4ad3-bac6-f275ae530b9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866501991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1866501991
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2433625564
Short name T823
Test name
Test status
Simulation time 132975578 ps
CPU time 2.37 seconds
Started Jun 02 03:04:05 PM PDT 24
Finished Jun 02 03:04:08 PM PDT 24
Peak memory 209056 kb
Host smart-a200cae2-bca6-4b79-8905-c1b0639453fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433625564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2433625564
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1980508436
Short name T516
Test name
Test status
Simulation time 52761924 ps
CPU time 1.75 seconds
Started Jun 02 03:04:03 PM PDT 24
Finished Jun 02 03:04:05 PM PDT 24
Peak memory 207172 kb
Host smart-a133f7de-2527-4fa4-bde4-3c2f8cce343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980508436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1980508436
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4014360469
Short name T820
Test name
Test status
Simulation time 323181361 ps
CPU time 6.23 seconds
Started Jun 02 03:04:06 PM PDT 24
Finished Jun 02 03:04:13 PM PDT 24
Peak memory 222408 kb
Host smart-66ed18af-1584-4231-b0fd-b64b639ede09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014360469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4014360469
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1374977114
Short name T707
Test name
Test status
Simulation time 79245699 ps
CPU time 1.92 seconds
Started Jun 02 03:04:03 PM PDT 24
Finished Jun 02 03:04:06 PM PDT 24
Peak memory 214232 kb
Host smart-5f79fc70-8656-4a33-9686-242596dbc3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374977114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1374977114
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2549636262
Short name T610
Test name
Test status
Simulation time 800889931 ps
CPU time 4.66 seconds
Started Jun 02 03:04:07 PM PDT 24
Finished Jun 02 03:04:12 PM PDT 24
Peak memory 214312 kb
Host smart-1f07c5d1-8476-413b-a57f-bedbc45c3201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549636262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2549636262
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1770953098
Short name T682
Test name
Test status
Simulation time 84359589 ps
CPU time 3.78 seconds
Started Jun 02 03:04:05 PM PDT 24
Finished Jun 02 03:04:09 PM PDT 24
Peak memory 218952 kb
Host smart-c084bb2e-7d67-4fe0-98ec-20500142fc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770953098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1770953098
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.4140764360
Short name T259
Test name
Test status
Simulation time 208629831 ps
CPU time 3.93 seconds
Started Jun 02 03:04:03 PM PDT 24
Finished Jun 02 03:04:08 PM PDT 24
Peak memory 206940 kb
Host smart-cd4d5c0c-06e9-4463-b4b3-b79bc9dd41bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140764360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.4140764360
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2470370378
Short name T723
Test name
Test status
Simulation time 34592035 ps
CPU time 2.5 seconds
Started Jun 02 03:04:03 PM PDT 24
Finished Jun 02 03:04:06 PM PDT 24
Peak memory 208624 kb
Host smart-0e5cfe32-a2a4-43dd-8570-018c470a1c59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470370378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2470370378
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1827875692
Short name T195
Test name
Test status
Simulation time 83764494 ps
CPU time 2.51 seconds
Started Jun 02 03:04:04 PM PDT 24
Finished Jun 02 03:04:08 PM PDT 24
Peak memory 208552 kb
Host smart-529fb52b-4c2a-4117-9290-dd19f7cc1c9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827875692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1827875692
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3205090772
Short name T762
Test name
Test status
Simulation time 32532052 ps
CPU time 2.29 seconds
Started Jun 02 03:04:06 PM PDT 24
Finished Jun 02 03:04:09 PM PDT 24
Peak memory 207444 kb
Host smart-44b7b389-e7e5-4e61-aa53-bff14396e351
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205090772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3205090772
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2154647664
Short name T867
Test name
Test status
Simulation time 190675038 ps
CPU time 3.13 seconds
Started Jun 02 03:04:04 PM PDT 24
Finished Jun 02 03:04:08 PM PDT 24
Peak memory 214316 kb
Host smart-3d9f8ac5-e047-4b8d-a4f4-9cf705e4616a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154647664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2154647664
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1777441586
Short name T653
Test name
Test status
Simulation time 191154003 ps
CPU time 4.38 seconds
Started Jun 02 03:04:02 PM PDT 24
Finished Jun 02 03:04:07 PM PDT 24
Peak memory 208356 kb
Host smart-368f1d19-746c-4cf8-a02e-3893674acdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777441586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1777441586
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.751440225
Short name T206
Test name
Test status
Simulation time 3235585893 ps
CPU time 73.81 seconds
Started Jun 02 03:04:11 PM PDT 24
Finished Jun 02 03:05:25 PM PDT 24
Peak memory 215372 kb
Host smart-f1f1c8d4-5c68-4404-8362-d583233972b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751440225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.751440225
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1732749126
Short name T304
Test name
Test status
Simulation time 149700080 ps
CPU time 4.94 seconds
Started Jun 02 03:04:04 PM PDT 24
Finished Jun 02 03:04:10 PM PDT 24
Peak memory 208852 kb
Host smart-3312c41e-701f-4344-8dfb-2d72986dc0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732749126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1732749126
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1076155336
Short name T171
Test name
Test status
Simulation time 91304200 ps
CPU time 1.71 seconds
Started Jun 02 03:04:07 PM PDT 24
Finished Jun 02 03:04:09 PM PDT 24
Peak memory 210084 kb
Host smart-ae7f267b-81e4-44af-a90b-91b4ceccd9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076155336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1076155336
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3639095642
Short name T753
Test name
Test status
Simulation time 12465126 ps
CPU time 0.81 seconds
Started Jun 02 03:04:09 PM PDT 24
Finished Jun 02 03:04:11 PM PDT 24
Peak memory 205952 kb
Host smart-3ca6bb0e-c5f6-4656-9ddb-a58a7bc744c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639095642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3639095642
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2606287569
Short name T911
Test name
Test status
Simulation time 1869988735 ps
CPU time 7.94 seconds
Started Jun 02 03:04:14 PM PDT 24
Finished Jun 02 03:04:22 PM PDT 24
Peak memory 214940 kb
Host smart-12de23af-6154-4a00-84dd-c07b6cd9af95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606287569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2606287569
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.586278478
Short name T18
Test name
Test status
Simulation time 82484815 ps
CPU time 2.94 seconds
Started Jun 02 03:04:16 PM PDT 24
Finished Jun 02 03:04:19 PM PDT 24
Peak memory 214552 kb
Host smart-8c8d2d19-03bc-40be-91b5-75978a752441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586278478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.586278478
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.326475248
Short name T569
Test name
Test status
Simulation time 58418683 ps
CPU time 2.4 seconds
Started Jun 02 03:04:16 PM PDT 24
Finished Jun 02 03:04:19 PM PDT 24
Peak memory 218404 kb
Host smart-274bcb24-bda2-4ea4-834d-8ed6a6b8c426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326475248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.326475248
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.703504094
Short name T93
Test name
Test status
Simulation time 222854669 ps
CPU time 7.86 seconds
Started Jun 02 03:04:07 PM PDT 24
Finished Jun 02 03:04:16 PM PDT 24
Peak memory 214256 kb
Host smart-3a6dd36d-ac3a-4c9b-9ce7-b5b3a7a2b7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703504094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.703504094
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2887486303
Short name T875
Test name
Test status
Simulation time 76125507 ps
CPU time 2.75 seconds
Started Jun 02 03:04:18 PM PDT 24
Finished Jun 02 03:04:21 PM PDT 24
Peak memory 214200 kb
Host smart-f9b61db9-72f0-4734-8519-eeaece920d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887486303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2887486303
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3136677179
Short name T665
Test name
Test status
Simulation time 80683587 ps
CPU time 3.9 seconds
Started Jun 02 03:04:09 PM PDT 24
Finished Jun 02 03:04:13 PM PDT 24
Peak memory 218196 kb
Host smart-2a827df8-72a9-4432-b87b-3ad27ae3c631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136677179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3136677179
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3442217242
Short name T313
Test name
Test status
Simulation time 83709174 ps
CPU time 4.13 seconds
Started Jun 02 03:04:14 PM PDT 24
Finished Jun 02 03:04:19 PM PDT 24
Peak memory 222348 kb
Host smart-897d6fba-46be-4e21-aebd-fee575b6f107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442217242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3442217242
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1778065104
Short name T378
Test name
Test status
Simulation time 33159886 ps
CPU time 2.4 seconds
Started Jun 02 03:04:17 PM PDT 24
Finished Jun 02 03:04:20 PM PDT 24
Peak memory 206124 kb
Host smart-22730115-c7b6-4f28-a65a-72a5ac24594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778065104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1778065104
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1911467564
Short name T460
Test name
Test status
Simulation time 81092188 ps
CPU time 1.93 seconds
Started Jun 02 03:04:17 PM PDT 24
Finished Jun 02 03:04:19 PM PDT 24
Peak memory 207640 kb
Host smart-0214876e-6efa-4e98-b911-c8373d0d340f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911467564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1911467564
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2275467171
Short name T746
Test name
Test status
Simulation time 32864622 ps
CPU time 2.49 seconds
Started Jun 02 03:04:14 PM PDT 24
Finished Jun 02 03:04:17 PM PDT 24
Peak memory 206880 kb
Host smart-40916696-3cb7-4df7-900e-9784e90ba6cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275467171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2275467171
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3710269601
Short name T275
Test name
Test status
Simulation time 597444194 ps
CPU time 3.54 seconds
Started Jun 02 03:04:18 PM PDT 24
Finished Jun 02 03:04:22 PM PDT 24
Peak memory 207304 kb
Host smart-1ac28e81-56c8-4c2c-98a9-a142a3d87375
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710269601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3710269601
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.510012452
Short name T709
Test name
Test status
Simulation time 282209004 ps
CPU time 2.35 seconds
Started Jun 02 03:04:09 PM PDT 24
Finished Jun 02 03:04:12 PM PDT 24
Peak memory 209316 kb
Host smart-22ab564a-b6bb-40bd-9e38-8afb1b585dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510012452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.510012452
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2482414375
Short name T503
Test name
Test status
Simulation time 62269850 ps
CPU time 2.5 seconds
Started Jun 02 03:04:17 PM PDT 24
Finished Jun 02 03:04:21 PM PDT 24
Peak memory 208260 kb
Host smart-1ebd057a-8a8d-467f-b81d-c9fb3553a3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482414375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2482414375
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2179711538
Short name T794
Test name
Test status
Simulation time 572425995 ps
CPU time 19.81 seconds
Started Jun 02 03:04:13 PM PDT 24
Finished Jun 02 03:04:34 PM PDT 24
Peak memory 216120 kb
Host smart-772ab54c-7b62-49f0-822f-09a273065ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179711538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2179711538
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.4245755233
Short name T727
Test name
Test status
Simulation time 230441426 ps
CPU time 10.4 seconds
Started Jun 02 03:04:25 PM PDT 24
Finished Jun 02 03:04:36 PM PDT 24
Peak memory 222584 kb
Host smart-9b40ef76-5fb9-4200-8efd-dc7ac6e008fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245755233 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.4245755233
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3036931143
Short name T891
Test name
Test status
Simulation time 232670053 ps
CPU time 2.54 seconds
Started Jun 02 03:04:21 PM PDT 24
Finished Jun 02 03:04:24 PM PDT 24
Peak memory 210232 kb
Host smart-ee71d2c4-9b5a-49da-bb6a-8d402294ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036931143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3036931143
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3382073065
Short name T417
Test name
Test status
Simulation time 43096750 ps
CPU time 0.76 seconds
Started Jun 02 03:04:25 PM PDT 24
Finished Jun 02 03:04:27 PM PDT 24
Peak memory 205852 kb
Host smart-25d9a027-311c-4be4-a6ba-fe09a58f60e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382073065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3382073065
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3421181308
Short name T72
Test name
Test status
Simulation time 114434624 ps
CPU time 3.54 seconds
Started Jun 02 03:04:14 PM PDT 24
Finished Jun 02 03:04:19 PM PDT 24
Peak memory 220944 kb
Host smart-4ddb8e01-d5e3-4afb-8bb9-1fcc00b558ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421181308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3421181308
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1343740422
Short name T587
Test name
Test status
Simulation time 77174138 ps
CPU time 1.96 seconds
Started Jun 02 03:04:17 PM PDT 24
Finished Jun 02 03:04:20 PM PDT 24
Peak memory 207092 kb
Host smart-b7400650-cb8c-4b8f-a2c7-4b18178829fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343740422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1343740422
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.98071782
Short name T91
Test name
Test status
Simulation time 229943796 ps
CPU time 3.97 seconds
Started Jun 02 03:04:19 PM PDT 24
Finished Jun 02 03:04:23 PM PDT 24
Peak memory 214316 kb
Host smart-5b3a3f0b-32e5-40ba-aa74-455525e054c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98071782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.98071782
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3082253754
Short name T284
Test name
Test status
Simulation time 598871732 ps
CPU time 5.89 seconds
Started Jun 02 03:04:18 PM PDT 24
Finished Jun 02 03:04:24 PM PDT 24
Peak memory 221324 kb
Host smart-29ed99e6-7144-46ae-a8d2-1e5827061494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082253754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3082253754
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1035426819
Short name T492
Test name
Test status
Simulation time 647643609 ps
CPU time 3.34 seconds
Started Jun 02 03:04:19 PM PDT 24
Finished Jun 02 03:04:23 PM PDT 24
Peak memory 209164 kb
Host smart-e90720ed-1f71-4f40-b47f-8640d7fb1382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035426819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1035426819
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3809259443
Short name T858
Test name
Test status
Simulation time 113712998 ps
CPU time 4.11 seconds
Started Jun 02 03:04:25 PM PDT 24
Finished Jun 02 03:04:30 PM PDT 24
Peak memory 210188 kb
Host smart-f9a1a4c0-cb8f-44ff-83e4-b6900632355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809259443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3809259443
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2923472400
Short name T915
Test name
Test status
Simulation time 44397102 ps
CPU time 1.96 seconds
Started Jun 02 03:04:07 PM PDT 24
Finished Jun 02 03:04:10 PM PDT 24
Peak memory 207248 kb
Host smart-c7f8a153-e48b-4c7a-9d4d-0ef8ec0e51f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923472400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2923472400
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4098868089
Short name T573
Test name
Test status
Simulation time 98265942 ps
CPU time 2.1 seconds
Started Jun 02 03:04:19 PM PDT 24
Finished Jun 02 03:04:21 PM PDT 24
Peak memory 208636 kb
Host smart-cc020c2e-30d8-49d1-a816-a3c8ff54a116
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098868089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4098868089
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.956800063
Short name T885
Test name
Test status
Simulation time 53725627 ps
CPU time 2.85 seconds
Started Jun 02 03:04:07 PM PDT 24
Finished Jun 02 03:04:10 PM PDT 24
Peak memory 206840 kb
Host smart-95d9eef7-071b-48fb-84e0-35250a120603
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956800063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.956800063
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3680982319
Short name T712
Test name
Test status
Simulation time 569297786 ps
CPU time 14.36 seconds
Started Jun 02 03:04:25 PM PDT 24
Finished Jun 02 03:04:40 PM PDT 24
Peak memory 206912 kb
Host smart-28fe2e09-fb9f-4e64-a9bb-1646d6ac53e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680982319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3680982319
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2219573947
Short name T362
Test name
Test status
Simulation time 408732517 ps
CPU time 3.82 seconds
Started Jun 02 03:04:16 PM PDT 24
Finished Jun 02 03:04:20 PM PDT 24
Peak memory 208076 kb
Host smart-a42d4b7e-bb6f-4718-89c3-8f5ac5ecb214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219573947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2219573947
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2505555081
Short name T482
Test name
Test status
Simulation time 5070041250 ps
CPU time 30.57 seconds
Started Jun 02 03:04:18 PM PDT 24
Finished Jun 02 03:04:50 PM PDT 24
Peak memory 208296 kb
Host smart-351f1c47-2cc1-4a5f-ad9b-28466a338ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505555081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2505555081
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4142840326
Short name T59
Test name
Test status
Simulation time 2677843806 ps
CPU time 37.58 seconds
Started Jun 02 03:04:16 PM PDT 24
Finished Jun 02 03:04:54 PM PDT 24
Peak memory 216340 kb
Host smart-7555a0ae-56e6-4b4a-af44-4439ac9c607a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142840326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4142840326
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2975916419
Short name T804
Test name
Test status
Simulation time 923747612 ps
CPU time 6.36 seconds
Started Jun 02 03:04:14 PM PDT 24
Finished Jun 02 03:04:21 PM PDT 24
Peak memory 209840 kb
Host smart-19daae71-810f-4fb5-a635-eed5b8a57534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975916419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2975916419
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.913996843
Short name T103
Test name
Test status
Simulation time 81067618 ps
CPU time 2.13 seconds
Started Jun 02 03:04:16 PM PDT 24
Finished Jun 02 03:04:19 PM PDT 24
Peak memory 209972 kb
Host smart-4bf8168d-63bf-4c33-a6bd-6ed9f36d92ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913996843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.913996843
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2908923326
Short name T818
Test name
Test status
Simulation time 58017991 ps
CPU time 0.85 seconds
Started Jun 02 03:04:21 PM PDT 24
Finished Jun 02 03:04:22 PM PDT 24
Peak memory 205936 kb
Host smart-24c3dbc7-356d-4485-9b0c-9b2941f5ba72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908923326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2908923326
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2691461224
Short name T337
Test name
Test status
Simulation time 1010901089 ps
CPU time 53.38 seconds
Started Jun 02 03:04:15 PM PDT 24
Finished Jun 02 03:05:09 PM PDT 24
Peak memory 222492 kb
Host smart-8c06f739-1660-4c8a-a603-f2185b6989f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691461224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2691461224
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.759746151
Short name T695
Test name
Test status
Simulation time 314482720 ps
CPU time 2.74 seconds
Started Jun 02 03:04:19 PM PDT 24
Finished Jun 02 03:04:22 PM PDT 24
Peak memory 222744 kb
Host smart-4b573868-e1f3-4193-a14c-9f1b0f31a10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759746151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.759746151
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2929515752
Short name T907
Test name
Test status
Simulation time 29032561 ps
CPU time 1.66 seconds
Started Jun 02 03:04:18 PM PDT 24
Finished Jun 02 03:04:20 PM PDT 24
Peak memory 208940 kb
Host smart-f91d3b6d-cf5b-4722-abf1-9a894ec3abbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929515752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2929515752
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.227912053
Short name T312
Test name
Test status
Simulation time 213606586 ps
CPU time 2.9 seconds
Started Jun 02 03:04:16 PM PDT 24
Finished Jun 02 03:04:20 PM PDT 24
Peak memory 214400 kb
Host smart-2b147257-6331-4410-b28a-07833de512a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227912053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.227912053
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3246852392
Short name T252
Test name
Test status
Simulation time 351164576 ps
CPU time 3.47 seconds
Started Jun 02 03:04:16 PM PDT 24
Finished Jun 02 03:04:20 PM PDT 24
Peak memory 214296 kb
Host smart-69c685cb-457f-4de9-b2c1-a0227e2fe81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246852392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3246852392
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.525259280
Short name T453
Test name
Test status
Simulation time 212458935 ps
CPU time 3.2 seconds
Started Jun 02 03:04:17 PM PDT 24
Finished Jun 02 03:04:21 PM PDT 24
Peak memory 206100 kb
Host smart-ad707d31-7565-4c53-b1a0-8f295bd5a8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525259280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.525259280
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4040655883
Short name T461
Test name
Test status
Simulation time 88157416 ps
CPU time 3.99 seconds
Started Jun 02 03:04:16 PM PDT 24
Finished Jun 02 03:04:21 PM PDT 24
Peak memory 214304 kb
Host smart-94e306ce-44a7-4608-ac87-404c43ebaf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040655883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4040655883
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3659887187
Short name T877
Test name
Test status
Simulation time 33332564 ps
CPU time 2.39 seconds
Started Jun 02 03:04:15 PM PDT 24
Finished Jun 02 03:04:18 PM PDT 24
Peak memory 206912 kb
Host smart-efc73069-6d05-4666-a934-d9f0d22d57fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659887187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3659887187
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.286599434
Short name T476
Test name
Test status
Simulation time 149280587 ps
CPU time 3.04 seconds
Started Jun 02 03:04:15 PM PDT 24
Finished Jun 02 03:04:19 PM PDT 24
Peak memory 208716 kb
Host smart-06b9a3c2-9c81-4c34-b0e3-14cc0ecfa812
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286599434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.286599434
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3340686897
Short name T892
Test name
Test status
Simulation time 52765876 ps
CPU time 2.78 seconds
Started Jun 02 03:04:18 PM PDT 24
Finished Jun 02 03:04:22 PM PDT 24
Peak memory 208040 kb
Host smart-99879240-4342-48aa-8ec4-515bfa8fab4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340686897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3340686897
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3532540390
Short name T454
Test name
Test status
Simulation time 69838194 ps
CPU time 3.25 seconds
Started Jun 02 03:04:17 PM PDT 24
Finished Jun 02 03:04:20 PM PDT 24
Peak memory 208460 kb
Host smart-4152d2b6-fab5-4e04-855e-afee943258a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532540390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3532540390
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2988390200
Short name T609
Test name
Test status
Simulation time 301250188 ps
CPU time 6.21 seconds
Started Jun 02 03:04:15 PM PDT 24
Finished Jun 02 03:04:22 PM PDT 24
Peak memory 216368 kb
Host smart-ddf09aa1-bd6d-4234-905f-7e55dccfc4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988390200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2988390200
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3631368965
Short name T386
Test name
Test status
Simulation time 393512553 ps
CPU time 2.53 seconds
Started Jun 02 03:04:17 PM PDT 24
Finished Jun 02 03:04:20 PM PDT 24
Peak memory 206800 kb
Host smart-e5a8a078-a6bd-4b26-888e-9ceb3de9901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631368965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3631368965
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.959621858
Short name T73
Test name
Test status
Simulation time 3817413732 ps
CPU time 15.7 seconds
Started Jun 02 03:04:15 PM PDT 24
Finished Jun 02 03:04:31 PM PDT 24
Peak memory 220908 kb
Host smart-18660cce-e31e-4b64-9764-acc79b2145ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959621858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.959621858
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1570837674
Short name T153
Test name
Test status
Simulation time 1051626893 ps
CPU time 8.43 seconds
Started Jun 02 03:04:21 PM PDT 24
Finished Jun 02 03:04:30 PM PDT 24
Peak memory 222556 kb
Host smart-dc92ec43-b639-4eca-8361-c3c3dfbc9e6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570837674 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1570837674
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.908598507
Short name T293
Test name
Test status
Simulation time 101777099 ps
CPU time 5.19 seconds
Started Jun 02 03:04:17 PM PDT 24
Finished Jun 02 03:04:23 PM PDT 24
Peak memory 218160 kb
Host smart-a5e27d12-ab71-4418-a2d5-ae19b92ae013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908598507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.908598507
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1023509093
Short name T903
Test name
Test status
Simulation time 697468086 ps
CPU time 2.31 seconds
Started Jun 02 03:04:14 PM PDT 24
Finished Jun 02 03:04:17 PM PDT 24
Peak memory 210480 kb
Host smart-57f14532-3380-4b3c-9c1d-d59026329314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023509093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1023509093
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1718803342
Short name T510
Test name
Test status
Simulation time 20854879 ps
CPU time 0.84 seconds
Started Jun 02 03:04:29 PM PDT 24
Finished Jun 02 03:04:30 PM PDT 24
Peak memory 205940 kb
Host smart-540dff94-0c58-4e46-8ae1-aee060298985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718803342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1718803342
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2146042979
Short name T874
Test name
Test status
Simulation time 113414628 ps
CPU time 4.6 seconds
Started Jun 02 03:04:30 PM PDT 24
Finished Jun 02 03:04:35 PM PDT 24
Peak memory 221540 kb
Host smart-7551050c-4d3a-4dc9-9e2c-60fa3042e2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146042979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2146042979
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1820040209
Short name T629
Test name
Test status
Simulation time 121729239 ps
CPU time 2.07 seconds
Started Jun 02 03:04:19 PM PDT 24
Finished Jun 02 03:04:21 PM PDT 24
Peak memory 207792 kb
Host smart-1c70eb95-a725-4f09-af10-df00fc12c6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820040209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1820040209
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4208792125
Short name T336
Test name
Test status
Simulation time 305343707 ps
CPU time 6.57 seconds
Started Jun 02 03:04:21 PM PDT 24
Finished Jun 02 03:04:29 PM PDT 24
Peak memory 219180 kb
Host smart-8bb489df-7c03-4635-9878-74d1d154ec55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208792125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4208792125
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1128002068
Short name T714
Test name
Test status
Simulation time 57541588 ps
CPU time 2.85 seconds
Started Jun 02 03:04:27 PM PDT 24
Finished Jun 02 03:04:31 PM PDT 24
Peak memory 214300 kb
Host smart-4dbf0fee-0487-4695-833f-f6d431052e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128002068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1128002068
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1565155078
Short name T590
Test name
Test status
Simulation time 901404423 ps
CPU time 4.4 seconds
Started Jun 02 03:04:21 PM PDT 24
Finished Jun 02 03:04:26 PM PDT 24
Peak memory 206412 kb
Host smart-26db0027-6c6c-49d1-ae13-a22002191c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565155078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1565155078
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3143216608
Short name T345
Test name
Test status
Simulation time 5915851666 ps
CPU time 51.15 seconds
Started Jun 02 03:04:20 PM PDT 24
Finished Jun 02 03:05:12 PM PDT 24
Peak memory 220008 kb
Host smart-d6bc6c8e-cf4c-43d6-9352-5fa3804228e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143216608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3143216608
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.751077510
Short name T581
Test name
Test status
Simulation time 275502119 ps
CPU time 4.38 seconds
Started Jun 02 03:04:22 PM PDT 24
Finished Jun 02 03:04:26 PM PDT 24
Peak memory 207976 kb
Host smart-41e5392d-03b3-478f-a9cf-0853321cc124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751077510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.751077510
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1110854162
Short name T843
Test name
Test status
Simulation time 393226426 ps
CPU time 6.8 seconds
Started Jun 02 03:04:20 PM PDT 24
Finished Jun 02 03:04:27 PM PDT 24
Peak memory 208696 kb
Host smart-9c096dab-4c7f-4ef9-9271-72ebaf5e33e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110854162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1110854162
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2391428772
Short name T197
Test name
Test status
Simulation time 40383047 ps
CPU time 2.51 seconds
Started Jun 02 03:04:21 PM PDT 24
Finished Jun 02 03:04:24 PM PDT 24
Peak memory 207272 kb
Host smart-80e348ba-7df1-40bb-bad9-d689a0af6913
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391428772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2391428772
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1681175097
Short name T85
Test name
Test status
Simulation time 58706642 ps
CPU time 3 seconds
Started Jun 02 03:04:23 PM PDT 24
Finished Jun 02 03:04:26 PM PDT 24
Peak memory 206864 kb
Host smart-a3e04873-b591-4ae0-a0e5-ba357a80252e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681175097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1681175097
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3666430436
Short name T303
Test name
Test status
Simulation time 580876712 ps
CPU time 3.36 seconds
Started Jun 02 03:04:29 PM PDT 24
Finished Jun 02 03:04:33 PM PDT 24
Peak memory 208872 kb
Host smart-6c083605-7938-4b4d-ac8d-33b7c23dbb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666430436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3666430436
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1684469588
Short name T429
Test name
Test status
Simulation time 201531903 ps
CPU time 4.65 seconds
Started Jun 02 03:04:23 PM PDT 24
Finished Jun 02 03:04:28 PM PDT 24
Peak memory 208616 kb
Host smart-800eeb68-d4a6-4e38-b1cf-7dac0299692a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684469588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1684469588
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3943573682
Short name T729
Test name
Test status
Simulation time 360347338 ps
CPU time 7.68 seconds
Started Jun 02 03:04:21 PM PDT 24
Finished Jun 02 03:04:29 PM PDT 24
Peak memory 208632 kb
Host smart-1e9630f3-2a62-45ab-9cdc-5865e74c069e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943573682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3943573682
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.811116405
Short name T579
Test name
Test status
Simulation time 27905341 ps
CPU time 1.83 seconds
Started Jun 02 03:04:27 PM PDT 24
Finished Jun 02 03:04:29 PM PDT 24
Peak memory 210120 kb
Host smart-5d6c4af9-ca33-4dfa-a01d-370fa757556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811116405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.811116405
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2814570793
Short name T405
Test name
Test status
Simulation time 49615900 ps
CPU time 0.9 seconds
Started Jun 02 03:04:35 PM PDT 24
Finished Jun 02 03:04:36 PM PDT 24
Peak memory 206168 kb
Host smart-daa190c7-301e-4fd8-8ddb-88e055c4f767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814570793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2814570793
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.433291079
Short name T677
Test name
Test status
Simulation time 184182207 ps
CPU time 2.19 seconds
Started Jun 02 03:04:34 PM PDT 24
Finished Jun 02 03:04:37 PM PDT 24
Peak memory 209604 kb
Host smart-8f7dd097-df4d-4bfe-a2a2-f96c7114b83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433291079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.433291079
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.904060671
Short name T383
Test name
Test status
Simulation time 100123798 ps
CPU time 2.24 seconds
Started Jun 02 03:04:32 PM PDT 24
Finished Jun 02 03:04:35 PM PDT 24
Peak memory 207552 kb
Host smart-848a84da-4151-44a0-abac-fa02ccbfd22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904060671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.904060671
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1257445563
Short name T94
Test name
Test status
Simulation time 4138503005 ps
CPU time 47.11 seconds
Started Jun 02 03:04:39 PM PDT 24
Finished Jun 02 03:05:26 PM PDT 24
Peak memory 214352 kb
Host smart-33ebed00-da43-4d10-a09c-6222f0834d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257445563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1257445563
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3242837591
Short name T234
Test name
Test status
Simulation time 184784114 ps
CPU time 3.02 seconds
Started Jun 02 03:04:37 PM PDT 24
Finished Jun 02 03:04:40 PM PDT 24
Peak memory 222436 kb
Host smart-f65d9355-2591-44b0-b29e-a85ba3835964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242837591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3242837591
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3974185588
Short name T205
Test name
Test status
Simulation time 82938635 ps
CPU time 2.27 seconds
Started Jun 02 03:04:36 PM PDT 24
Finished Jun 02 03:04:39 PM PDT 24
Peak memory 209376 kb
Host smart-447c2b46-6cc1-45b1-bfb5-3fe695cc0bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974185588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3974185588
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1392020807
Short name T649
Test name
Test status
Simulation time 93032048 ps
CPU time 4.08 seconds
Started Jun 02 03:04:34 PM PDT 24
Finished Jun 02 03:04:38 PM PDT 24
Peak memory 214320 kb
Host smart-bbcf382f-fc08-4c27-971f-abcae934c57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392020807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1392020807
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3697707392
Short name T901
Test name
Test status
Simulation time 33524100 ps
CPU time 2.27 seconds
Started Jun 02 03:04:29 PM PDT 24
Finished Jun 02 03:04:32 PM PDT 24
Peak memory 208812 kb
Host smart-1c70d835-ff1b-443d-a033-316e2676cc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697707392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3697707392
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.906512887
Short name T328
Test name
Test status
Simulation time 163017329 ps
CPU time 2.49 seconds
Started Jun 02 03:04:29 PM PDT 24
Finished Jun 02 03:04:32 PM PDT 24
Peak memory 206764 kb
Host smart-abd7e5ec-e2b1-41d7-a4eb-ff68c3df7c4c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906512887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.906512887
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.817797175
Short name T648
Test name
Test status
Simulation time 127437215 ps
CPU time 4.39 seconds
Started Jun 02 03:04:27 PM PDT 24
Finished Jun 02 03:04:32 PM PDT 24
Peak memory 207936 kb
Host smart-fcd1d72a-88b7-4b76-a82c-19d41be7e968
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817797175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.817797175
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.11584982
Short name T800
Test name
Test status
Simulation time 366772774 ps
CPU time 3.36 seconds
Started Jun 02 03:04:33 PM PDT 24
Finished Jun 02 03:04:37 PM PDT 24
Peak memory 206888 kb
Host smart-ce092e10-5587-495c-87c7-88f970c76b16
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11584982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.11584982
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3304808167
Short name T792
Test name
Test status
Simulation time 462222272 ps
CPU time 3.65 seconds
Started Jun 02 03:04:36 PM PDT 24
Finished Jun 02 03:04:41 PM PDT 24
Peak memory 218128 kb
Host smart-ce9bb29c-d10b-4c56-8c7b-5e089f65db16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304808167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3304808167
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3823945106
Short name T450
Test name
Test status
Simulation time 272044018 ps
CPU time 3.66 seconds
Started Jun 02 03:04:27 PM PDT 24
Finished Jun 02 03:04:32 PM PDT 24
Peak memory 208572 kb
Host smart-5075cb46-c11a-42a5-a3b8-873eef754509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823945106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3823945106
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3235438392
Short name T255
Test name
Test status
Simulation time 1325587063 ps
CPU time 24.66 seconds
Started Jun 02 03:04:33 PM PDT 24
Finished Jun 02 03:04:59 PM PDT 24
Peak memory 222416 kb
Host smart-49191394-ea51-42ec-acff-4b3d29a85f27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235438392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3235438392
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3420639204
Short name T893
Test name
Test status
Simulation time 2193061709 ps
CPU time 22.68 seconds
Started Jun 02 03:04:34 PM PDT 24
Finished Jun 02 03:04:58 PM PDT 24
Peak memory 222696 kb
Host smart-4dafedc4-0aa6-49a2-903c-d082c02215e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420639204 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3420639204
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1936448381
Short name T505
Test name
Test status
Simulation time 109770340 ps
CPU time 2.37 seconds
Started Jun 02 03:04:34 PM PDT 24
Finished Jun 02 03:04:37 PM PDT 24
Peak memory 208312 kb
Host smart-c6f675d1-6d5d-4b5c-802c-76dc537e27ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936448381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1936448381
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.785176994
Short name T544
Test name
Test status
Simulation time 91156341 ps
CPU time 3.57 seconds
Started Jun 02 03:04:35 PM PDT 24
Finished Jun 02 03:04:39 PM PDT 24
Peak memory 210484 kb
Host smart-c1624493-fe53-462e-9f2d-c0e0a51ca2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785176994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.785176994
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.729956942
Short name T767
Test name
Test status
Simulation time 15899192 ps
CPU time 0.7 seconds
Started Jun 02 03:04:33 PM PDT 24
Finished Jun 02 03:04:34 PM PDT 24
Peak memory 205948 kb
Host smart-ae3585c5-64cd-46bc-a9d2-e877df7155bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729956942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.729956942
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1343062394
Short name T671
Test name
Test status
Simulation time 2211930854 ps
CPU time 30.61 seconds
Started Jun 02 03:04:37 PM PDT 24
Finished Jun 02 03:05:08 PM PDT 24
Peak memory 219860 kb
Host smart-8ae127a7-6b3d-47c4-8191-79fe3efa82ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343062394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1343062394
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.4078874890
Short name T256
Test name
Test status
Simulation time 194247372 ps
CPU time 3.74 seconds
Started Jun 02 03:04:36 PM PDT 24
Finished Jun 02 03:04:41 PM PDT 24
Peak memory 209096 kb
Host smart-37c02677-38c2-4e9a-9271-8a5de8623e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078874890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4078874890
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2771964018
Short name T619
Test name
Test status
Simulation time 82792559 ps
CPU time 1.87 seconds
Started Jun 02 03:04:32 PM PDT 24
Finished Jun 02 03:04:35 PM PDT 24
Peak memory 214248 kb
Host smart-c7197e34-e54b-4fa7-918e-c6d7e552cb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771964018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2771964018
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1076075967
Short name T635
Test name
Test status
Simulation time 1858574762 ps
CPU time 52.32 seconds
Started Jun 02 03:04:35 PM PDT 24
Finished Jun 02 03:05:28 PM PDT 24
Peak memory 214276 kb
Host smart-6056ceea-f5e3-40af-a423-203bbcd5e59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076075967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1076075967
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.544624110
Short name T688
Test name
Test status
Simulation time 215361527 ps
CPU time 5.79 seconds
Started Jun 02 03:04:32 PM PDT 24
Finished Jun 02 03:04:38 PM PDT 24
Peak memory 209628 kb
Host smart-3430de70-6b68-45f9-a15c-98e30050069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544624110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.544624110
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.733772278
Short name T914
Test name
Test status
Simulation time 48689409 ps
CPU time 2.56 seconds
Started Jun 02 03:04:37 PM PDT 24
Finished Jun 02 03:04:40 PM PDT 24
Peak memory 207968 kb
Host smart-d69178ae-d451-4b6d-a811-12e77cfc17d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733772278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.733772278
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1868993459
Short name T379
Test name
Test status
Simulation time 40528689 ps
CPU time 2.71 seconds
Started Jun 02 03:04:34 PM PDT 24
Finished Jun 02 03:04:37 PM PDT 24
Peak memory 208648 kb
Host smart-11a8b5f9-423e-432a-a71b-75229e34d888
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868993459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1868993459
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1624514028
Short name T705
Test name
Test status
Simulation time 637815162 ps
CPU time 4.14 seconds
Started Jun 02 03:04:34 PM PDT 24
Finished Jun 02 03:04:39 PM PDT 24
Peak memory 206920 kb
Host smart-d98e2280-46fc-4609-881b-854b416cab2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624514028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1624514028
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.367389154
Short name T435
Test name
Test status
Simulation time 230908685 ps
CPU time 5.36 seconds
Started Jun 02 03:04:38 PM PDT 24
Finished Jun 02 03:04:44 PM PDT 24
Peak memory 208128 kb
Host smart-96fb47c2-cc1a-4507-b611-e8b195f08ae2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367389154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.367389154
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3043417954
Short name T646
Test name
Test status
Simulation time 166873869 ps
CPU time 2.22 seconds
Started Jun 02 03:04:33 PM PDT 24
Finished Jun 02 03:04:36 PM PDT 24
Peak memory 209004 kb
Host smart-3335bb92-f565-4a89-8b1a-ebd3c39ec27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043417954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3043417954
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1171284499
Short name T790
Test name
Test status
Simulation time 162249297 ps
CPU time 4.25 seconds
Started Jun 02 03:04:34 PM PDT 24
Finished Jun 02 03:04:39 PM PDT 24
Peak memory 208512 kb
Host smart-1d4f7d66-e533-4b81-a0a7-b1b4c06bb22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171284499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1171284499
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2797277620
Short name T514
Test name
Test status
Simulation time 1168527297 ps
CPU time 27.98 seconds
Started Jun 02 03:04:36 PM PDT 24
Finished Jun 02 03:05:04 PM PDT 24
Peak memory 209572 kb
Host smart-9526783e-1daf-4c16-8f7e-8121a0940760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797277620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2797277620
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.520411991
Short name T526
Test name
Test status
Simulation time 312338938 ps
CPU time 3.54 seconds
Started Jun 02 03:04:36 PM PDT 24
Finished Jun 02 03:04:40 PM PDT 24
Peak memory 209944 kb
Host smart-70166e20-d74c-454e-8c7b-5bb8d1bd9e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520411991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.520411991
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1402912804
Short name T464
Test name
Test status
Simulation time 85780431 ps
CPU time 0.79 seconds
Started Jun 02 03:04:39 PM PDT 24
Finished Jun 02 03:04:40 PM PDT 24
Peak memory 205852 kb
Host smart-8e54d4c5-ec7a-4da0-b35a-93e268574fcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402912804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1402912804
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1513485867
Short name T140
Test name
Test status
Simulation time 132546247 ps
CPU time 4.4 seconds
Started Jun 02 03:04:40 PM PDT 24
Finished Jun 02 03:04:45 PM PDT 24
Peak memory 214256 kb
Host smart-1478a659-07f8-4058-acaf-76304a1a1f99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513485867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1513485867
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1472167023
Short name T199
Test name
Test status
Simulation time 487343183 ps
CPU time 3.88 seconds
Started Jun 02 03:04:39 PM PDT 24
Finished Jun 02 03:04:44 PM PDT 24
Peak memory 219884 kb
Host smart-fcf7628a-41ca-4df7-8a1b-aac7e512a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472167023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1472167023
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.369378367
Short name T830
Test name
Test status
Simulation time 136863222 ps
CPU time 1.78 seconds
Started Jun 02 03:04:40 PM PDT 24
Finished Jun 02 03:04:42 PM PDT 24
Peak memory 208400 kb
Host smart-cd3398ad-b296-4b48-8451-a5e43c691550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369378367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.369378367
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1427229901
Short name T52
Test name
Test status
Simulation time 407753305 ps
CPU time 4.04 seconds
Started Jun 02 03:04:40 PM PDT 24
Finished Jun 02 03:04:45 PM PDT 24
Peak memory 214312 kb
Host smart-5af9f40b-75bc-4f8a-9afb-36ee44023e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427229901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1427229901
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2768422689
Short name T334
Test name
Test status
Simulation time 93953550 ps
CPU time 4.51 seconds
Started Jun 02 03:04:42 PM PDT 24
Finished Jun 02 03:04:47 PM PDT 24
Peak memory 214320 kb
Host smart-aac4db01-b029-45a2-b61a-51878bcc1ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768422689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2768422689
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4180197592
Short name T443
Test name
Test status
Simulation time 147068679 ps
CPU time 5.81 seconds
Started Jun 02 03:04:40 PM PDT 24
Finished Jun 02 03:04:47 PM PDT 24
Peak memory 214440 kb
Host smart-f4e8fd57-119b-41fe-8ea8-8e9c4016b5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180197592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4180197592
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1017084890
Short name T530
Test name
Test status
Simulation time 527043563 ps
CPU time 9.04 seconds
Started Jun 02 03:04:44 PM PDT 24
Finished Jun 02 03:04:53 PM PDT 24
Peak memory 207632 kb
Host smart-9e801933-28c6-4f6b-8ee8-061ff2989888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017084890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1017084890
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3128581727
Short name T693
Test name
Test status
Simulation time 30396925 ps
CPU time 2 seconds
Started Jun 02 03:04:35 PM PDT 24
Finished Jun 02 03:04:38 PM PDT 24
Peak memory 208744 kb
Host smart-3caa5132-72f6-4b2b-a372-a2d59f96f0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128581727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3128581727
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1364240099
Short name T825
Test name
Test status
Simulation time 169261537 ps
CPU time 2.18 seconds
Started Jun 02 03:04:36 PM PDT 24
Finished Jun 02 03:04:39 PM PDT 24
Peak memory 208696 kb
Host smart-27962688-4221-4b11-b6af-aa0b4efd5eeb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364240099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1364240099
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3743721898
Short name T246
Test name
Test status
Simulation time 234756055 ps
CPU time 2.54 seconds
Started Jun 02 03:04:37 PM PDT 24
Finished Jun 02 03:04:40 PM PDT 24
Peak memory 206904 kb
Host smart-649d4859-bdd6-45fa-946e-9bde4301bd39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743721898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3743721898
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1409571633
Short name T475
Test name
Test status
Simulation time 54594561 ps
CPU time 2.78 seconds
Started Jun 02 03:04:34 PM PDT 24
Finished Jun 02 03:04:37 PM PDT 24
Peak memory 207948 kb
Host smart-dcd175dd-a1e5-4107-83a4-f3c745b2fc91
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409571633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1409571633
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2345171749
Short name T382
Test name
Test status
Simulation time 284445367 ps
CPU time 2.67 seconds
Started Jun 02 03:04:43 PM PDT 24
Finished Jun 02 03:04:46 PM PDT 24
Peak memory 209824 kb
Host smart-868ba0ea-0dd0-46c0-a71a-450f0b6147e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345171749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2345171749
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1710522083
Short name T375
Test name
Test status
Simulation time 577948557 ps
CPU time 12.36 seconds
Started Jun 02 03:04:34 PM PDT 24
Finished Jun 02 03:04:47 PM PDT 24
Peak memory 208460 kb
Host smart-5dd6c183-109e-4931-9910-59eda5977105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710522083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1710522083
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.426212903
Short name T242
Test name
Test status
Simulation time 4192422001 ps
CPU time 37.99 seconds
Started Jun 02 03:04:39 PM PDT 24
Finished Jun 02 03:05:17 PM PDT 24
Peak memory 220796 kb
Host smart-29d0c90c-17ba-45b5-9f20-44e1616983b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426212903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.426212903
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1268362704
Short name T118
Test name
Test status
Simulation time 246065137 ps
CPU time 15.61 seconds
Started Jun 02 03:04:39 PM PDT 24
Finished Jun 02 03:04:56 PM PDT 24
Peak memory 220808 kb
Host smart-43e4ef34-6205-447d-9123-5f24b6203b35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268362704 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1268362704
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.217158652
Short name T393
Test name
Test status
Simulation time 101410780 ps
CPU time 4 seconds
Started Jun 02 03:04:43 PM PDT 24
Finished Jun 02 03:04:47 PM PDT 24
Peak memory 208040 kb
Host smart-9bd5ff3a-8195-4077-a864-208c28d64c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217158652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.217158652
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1252774635
Short name T730
Test name
Test status
Simulation time 66162739 ps
CPU time 1.86 seconds
Started Jun 02 03:04:40 PM PDT 24
Finished Jun 02 03:04:43 PM PDT 24
Peak memory 208508 kb
Host smart-2ab92cd8-2951-4a79-b01d-39cba3d94ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252774635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1252774635
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.765779401
Short name T862
Test name
Test status
Simulation time 11792915 ps
CPU time 0.8 seconds
Started Jun 02 03:04:45 PM PDT 24
Finished Jun 02 03:04:46 PM PDT 24
Peak memory 206196 kb
Host smart-7d0c2d00-a91a-4ce7-a395-f2c88c2cc173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765779401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.765779401
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.110027208
Short name T260
Test name
Test status
Simulation time 36356914 ps
CPU time 2.83 seconds
Started Jun 02 03:04:44 PM PDT 24
Finished Jun 02 03:04:47 PM PDT 24
Peak memory 214384 kb
Host smart-f73a1d75-4c8c-4326-b386-765752e63143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110027208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.110027208
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.92651675
Short name T231
Test name
Test status
Simulation time 419668108 ps
CPU time 11.06 seconds
Started Jun 02 03:04:45 PM PDT 24
Finished Jun 02 03:04:56 PM PDT 24
Peak memory 208552 kb
Host smart-5a3d2af2-8e00-482b-83da-507cc27f939a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92651675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.92651675
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.829411983
Short name T512
Test name
Test status
Simulation time 310258836 ps
CPU time 3.32 seconds
Started Jun 02 03:04:44 PM PDT 24
Finished Jun 02 03:04:48 PM PDT 24
Peak memory 222284 kb
Host smart-d917716b-ef54-4df4-b44b-77162e5367f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829411983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.829411983
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1009664513
Short name T706
Test name
Test status
Simulation time 345871386 ps
CPU time 4.06 seconds
Started Jun 02 03:04:44 PM PDT 24
Finished Jun 02 03:04:49 PM PDT 24
Peak memory 222512 kb
Host smart-b5a5f65d-97bf-44dc-a589-55f951d71b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009664513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1009664513
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2173136977
Short name T209
Test name
Test status
Simulation time 1268769760 ps
CPU time 3.87 seconds
Started Jun 02 03:04:43 PM PDT 24
Finished Jun 02 03:04:48 PM PDT 24
Peak memory 214292 kb
Host smart-1d5d0ef3-f517-4ea9-92e1-6ce8fb72de27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173136977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2173136977
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2788299163
Short name T715
Test name
Test status
Simulation time 197270100 ps
CPU time 3.63 seconds
Started Jun 02 03:04:44 PM PDT 24
Finished Jun 02 03:04:48 PM PDT 24
Peak memory 208280 kb
Host smart-73cb354e-0b0d-435b-a061-2ddd7eaf3106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788299163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2788299163
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1199721659
Short name T572
Test name
Test status
Simulation time 229536605 ps
CPU time 2.44 seconds
Started Jun 02 03:04:41 PM PDT 24
Finished Jun 02 03:04:44 PM PDT 24
Peak memory 206808 kb
Host smart-fce0254f-e15d-49b6-a92a-bee1f427493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199721659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1199721659
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1479463003
Short name T733
Test name
Test status
Simulation time 94102657 ps
CPU time 2.34 seconds
Started Jun 02 03:04:40 PM PDT 24
Finished Jun 02 03:04:43 PM PDT 24
Peak memory 207036 kb
Host smart-e721ae41-fc57-4b42-82f0-2e87a5d49813
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479463003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1479463003
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4056531637
Short name T591
Test name
Test status
Simulation time 117446021 ps
CPU time 4.78 seconds
Started Jun 02 03:04:44 PM PDT 24
Finished Jun 02 03:04:49 PM PDT 24
Peak memory 208572 kb
Host smart-7ede921d-c147-49f9-a2b1-e47497928967
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056531637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4056531637
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3728073100
Short name T301
Test name
Test status
Simulation time 210635982 ps
CPU time 3.71 seconds
Started Jun 02 03:04:40 PM PDT 24
Finished Jun 02 03:04:44 PM PDT 24
Peak memory 208512 kb
Host smart-1271058e-49c4-4453-8d60-4c0f0aa60fcd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728073100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3728073100
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.249539678
Short name T889
Test name
Test status
Simulation time 205084344 ps
CPU time 2.73 seconds
Started Jun 02 03:04:48 PM PDT 24
Finished Jun 02 03:04:51 PM PDT 24
Peak memory 209684 kb
Host smart-9d95a305-1d0c-42a8-aaa1-05891063407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249539678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.249539678
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.606342267
Short name T896
Test name
Test status
Simulation time 561526967 ps
CPU time 4.14 seconds
Started Jun 02 03:04:41 PM PDT 24
Finished Jun 02 03:04:45 PM PDT 24
Peak memory 208228 kb
Host smart-e0d6d5be-0308-4454-a15a-607d4f9f5a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606342267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.606342267
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3919389562
Short name T278
Test name
Test status
Simulation time 1330777233 ps
CPU time 36.96 seconds
Started Jun 02 03:04:45 PM PDT 24
Finished Jun 02 03:05:23 PM PDT 24
Peak memory 222476 kb
Host smart-8d70b91a-0faf-4772-b898-1a4900a0496a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919389562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3919389562
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3543001689
Short name T104
Test name
Test status
Simulation time 192898123 ps
CPU time 9.37 seconds
Started Jun 02 03:04:47 PM PDT 24
Finished Jun 02 03:04:57 PM PDT 24
Peak memory 222552 kb
Host smart-ad23c166-eedc-4f12-8efb-1c740b1706da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543001689 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3543001689
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2580395227
Short name T357
Test name
Test status
Simulation time 5365222170 ps
CPU time 8.62 seconds
Started Jun 02 03:04:46 PM PDT 24
Finished Jun 02 03:04:56 PM PDT 24
Peak memory 214460 kb
Host smart-c016abb3-eda8-42ab-827d-7bf14b74963d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580395227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2580395227
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3640137697
Short name T169
Test name
Test status
Simulation time 71469145 ps
CPU time 1.74 seconds
Started Jun 02 03:04:45 PM PDT 24
Finished Jun 02 03:04:48 PM PDT 24
Peak memory 209824 kb
Host smart-00d42b00-3e5a-40ad-9234-e20eb5070c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640137697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3640137697
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3573322669
Short name T662
Test name
Test status
Simulation time 15746741 ps
CPU time 0.8 seconds
Started Jun 02 03:04:48 PM PDT 24
Finished Jun 02 03:04:49 PM PDT 24
Peak memory 205952 kb
Host smart-eced1bbd-fdb4-4a25-9da8-70eb8a417dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573322669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3573322669
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2102690966
Short name T282
Test name
Test status
Simulation time 81628252 ps
CPU time 4.86 seconds
Started Jun 02 03:04:45 PM PDT 24
Finished Jun 02 03:04:51 PM PDT 24
Peak memory 214256 kb
Host smart-b7709e7e-5bd7-45e7-95da-71a65d4cde0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102690966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2102690966
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3948361668
Short name T78
Test name
Test status
Simulation time 41292281 ps
CPU time 2.68 seconds
Started Jun 02 03:04:45 PM PDT 24
Finished Jun 02 03:04:49 PM PDT 24
Peak memory 218280 kb
Host smart-8d0c5bf8-d688-47eb-8704-60ee5fff0567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948361668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3948361668
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3604366759
Short name T24
Test name
Test status
Simulation time 7879053976 ps
CPU time 28.97 seconds
Started Jun 02 03:04:48 PM PDT 24
Finished Jun 02 03:05:17 PM PDT 24
Peak memory 222612 kb
Host smart-712b1bfd-be34-41f2-b384-37a1704253b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604366759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3604366759
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3291316569
Short name T351
Test name
Test status
Simulation time 319560930 ps
CPU time 3.55 seconds
Started Jun 02 03:04:48 PM PDT 24
Finished Jun 02 03:04:52 PM PDT 24
Peak memory 222404 kb
Host smart-c2942645-d063-4399-8e4c-31f0c65db109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291316569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3291316569
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1198243900
Short name T291
Test name
Test status
Simulation time 239532884 ps
CPU time 3.95 seconds
Started Jun 02 03:04:46 PM PDT 24
Finished Jun 02 03:04:50 PM PDT 24
Peak memory 219664 kb
Host smart-8690f4c6-4700-41a3-9af9-57de30b72123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198243900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1198243900
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_sideload.118443176
Short name T711
Test name
Test status
Simulation time 113501065 ps
CPU time 3.05 seconds
Started Jun 02 03:04:46 PM PDT 24
Finished Jun 02 03:04:50 PM PDT 24
Peak memory 207244 kb
Host smart-f43ddb2a-6f60-407e-9122-ca2648e0822b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118443176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.118443176
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4288613790
Short name T837
Test name
Test status
Simulation time 427614766 ps
CPU time 11.5 seconds
Started Jun 02 03:04:48 PM PDT 24
Finished Jun 02 03:05:00 PM PDT 24
Peak memory 208228 kb
Host smart-4bd18f98-e99c-4033-a4d2-367cfebb0f1c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288613790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4288613790
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3772133004
Short name T535
Test name
Test status
Simulation time 190126140 ps
CPU time 5.39 seconds
Started Jun 02 03:04:45 PM PDT 24
Finished Jun 02 03:04:51 PM PDT 24
Peak memory 207896 kb
Host smart-dc52dcb2-d20b-418e-8ea3-dae637eec164
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772133004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3772133004
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.438444656
Short name T838
Test name
Test status
Simulation time 117918345 ps
CPU time 2.34 seconds
Started Jun 02 03:04:44 PM PDT 24
Finished Jun 02 03:04:47 PM PDT 24
Peak memory 208764 kb
Host smart-2c752af4-0f54-4bc0-9071-09d2a356ca58
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438444656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.438444656
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.814989707
Short name T472
Test name
Test status
Simulation time 84258026 ps
CPU time 2.38 seconds
Started Jun 02 03:04:50 PM PDT 24
Finished Jun 02 03:04:53 PM PDT 24
Peak memory 209184 kb
Host smart-b6d0ce19-1f50-4ee5-9ba1-070f9ec97f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814989707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.814989707
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3032799826
Short name T188
Test name
Test status
Simulation time 108900205 ps
CPU time 3.44 seconds
Started Jun 02 03:04:45 PM PDT 24
Finished Jun 02 03:04:49 PM PDT 24
Peak memory 208476 kb
Host smart-380524aa-69f5-4fb5-ad5b-0a8edeee48b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032799826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3032799826
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1819273614
Short name T217
Test name
Test status
Simulation time 219434689 ps
CPU time 6.53 seconds
Started Jun 02 03:04:47 PM PDT 24
Finished Jun 02 03:04:54 PM PDT 24
Peak memory 216508 kb
Host smart-c296592c-6b4c-4999-afa9-e236e107b16a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819273614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1819273614
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.432350466
Short name T856
Test name
Test status
Simulation time 3443015705 ps
CPU time 20.75 seconds
Started Jun 02 03:04:48 PM PDT 24
Finished Jun 02 03:05:09 PM PDT 24
Peak memory 221404 kb
Host smart-f496239a-aeef-490a-acb2-bd68c6b59291
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432350466 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.432350466
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2945373030
Short name T834
Test name
Test status
Simulation time 1199487201 ps
CPU time 36.93 seconds
Started Jun 02 03:04:49 PM PDT 24
Finished Jun 02 03:05:27 PM PDT 24
Peak memory 218140 kb
Host smart-d4c027b0-d7c4-4400-828a-961c1988faa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945373030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2945373030
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1208253038
Short name T776
Test name
Test status
Simulation time 108885804 ps
CPU time 2.07 seconds
Started Jun 02 03:04:46 PM PDT 24
Finished Jun 02 03:04:48 PM PDT 24
Peak memory 210616 kb
Host smart-ea11e3b3-0b69-4fca-945a-fb4efc26e8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208253038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1208253038
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3940064532
Short name T815
Test name
Test status
Simulation time 12860076 ps
CPU time 0.9 seconds
Started Jun 02 03:00:30 PM PDT 24
Finished Jun 02 03:00:32 PM PDT 24
Peak memory 206240 kb
Host smart-72d72537-8872-4847-8016-10ca273eeafa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940064532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3940064532
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2006236821
Short name T744
Test name
Test status
Simulation time 332560675 ps
CPU time 2.14 seconds
Started Jun 02 03:00:24 PM PDT 24
Finished Jun 02 03:00:27 PM PDT 24
Peak memory 207760 kb
Host smart-919404ff-2689-4348-9311-39f1267ae1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006236821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2006236821
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.294565761
Short name T92
Test name
Test status
Simulation time 700160416 ps
CPU time 9.56 seconds
Started Jun 02 03:00:26 PM PDT 24
Finished Jun 02 03:00:36 PM PDT 24
Peak memory 208708 kb
Host smart-f8ba447a-802c-4fa5-9cd5-87e8edcfc8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294565761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.294565761
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3816489424
Short name T565
Test name
Test status
Simulation time 414891362 ps
CPU time 3.39 seconds
Started Jun 02 03:00:29 PM PDT 24
Finished Jun 02 03:00:33 PM PDT 24
Peak memory 206976 kb
Host smart-8c7368a3-75c1-4cf5-ba81-5987d0835b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816489424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3816489424
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1471900527
Short name T63
Test name
Test status
Simulation time 77650204 ps
CPU time 3.31 seconds
Started Jun 02 03:00:23 PM PDT 24
Finished Jun 02 03:00:27 PM PDT 24
Peak memory 214356 kb
Host smart-495c165c-ee5c-4b54-afa5-4284139ed523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471900527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1471900527
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.4131689906
Short name T320
Test name
Test status
Simulation time 201460814 ps
CPU time 4.84 seconds
Started Jun 02 03:00:23 PM PDT 24
Finished Jun 02 03:00:29 PM PDT 24
Peak memory 209788 kb
Host smart-698c566c-a972-4cc5-9cc1-896d0cb5a24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131689906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4131689906
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2028564613
Short name T434
Test name
Test status
Simulation time 272898256 ps
CPU time 9.46 seconds
Started Jun 02 03:00:23 PM PDT 24
Finished Jun 02 03:00:33 PM PDT 24
Peak memory 208076 kb
Host smart-8ef5d799-52e3-4cb8-844e-e1cb4e6d2023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028564613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2028564613
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3712793170
Short name T863
Test name
Test status
Simulation time 1152132650 ps
CPU time 3.72 seconds
Started Jun 02 03:00:23 PM PDT 24
Finished Jun 02 03:00:27 PM PDT 24
Peak memory 206900 kb
Host smart-3fc10a74-c9fd-4a7c-ba51-95c9888dc07b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712793170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3712793170
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1818005818
Short name T412
Test name
Test status
Simulation time 25830343 ps
CPU time 1.83 seconds
Started Jun 02 03:00:24 PM PDT 24
Finished Jun 02 03:00:26 PM PDT 24
Peak memory 206988 kb
Host smart-bf435ec5-34d9-416b-a76b-afb3dd33bd86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818005818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1818005818
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1293345522
Short name T478
Test name
Test status
Simulation time 2799036678 ps
CPU time 21.17 seconds
Started Jun 02 03:00:24 PM PDT 24
Finished Jun 02 03:00:45 PM PDT 24
Peak memory 208892 kb
Host smart-6358d531-3275-444d-b73b-bd3d97747b01
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293345522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1293345522
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1680308365
Short name T480
Test name
Test status
Simulation time 82144359 ps
CPU time 1.85 seconds
Started Jun 02 03:00:32 PM PDT 24
Finished Jun 02 03:00:34 PM PDT 24
Peak memory 208132 kb
Host smart-91d904bc-dba0-40fa-8357-a8a19ea22cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680308365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1680308365
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2807495286
Short name T497
Test name
Test status
Simulation time 170289089 ps
CPU time 3.67 seconds
Started Jun 02 03:00:22 PM PDT 24
Finished Jun 02 03:00:27 PM PDT 24
Peak memory 207896 kb
Host smart-c3afe27e-b154-49fd-8028-bc7a0d3d502d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807495286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2807495286
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3837058450
Short name T8
Test name
Test status
Simulation time 61623064690 ps
CPU time 340.82 seconds
Started Jun 02 03:00:28 PM PDT 24
Finished Jun 02 03:06:09 PM PDT 24
Peak memory 220336 kb
Host smart-6030dff7-f5b4-4c70-811c-eb9dae651fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837058450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3837058450
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.932707388
Short name T119
Test name
Test status
Simulation time 284213271 ps
CPU time 8.61 seconds
Started Jun 02 03:00:32 PM PDT 24
Finished Jun 02 03:00:41 PM PDT 24
Peak memory 218728 kb
Host smart-4d1d071d-5870-4907-9a7c-11815482dd89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932707388 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.932707388
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3618921363
Short name T866
Test name
Test status
Simulation time 100721476 ps
CPU time 3.77 seconds
Started Jun 02 03:00:32 PM PDT 24
Finished Jun 02 03:00:36 PM PDT 24
Peak memory 214312 kb
Host smart-a8c75ae1-5102-4cbf-b0be-2702a7a0ff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618921363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3618921363
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2285376072
Short name T750
Test name
Test status
Simulation time 75089342 ps
CPU time 1.41 seconds
Started Jun 02 03:00:29 PM PDT 24
Finished Jun 02 03:00:31 PM PDT 24
Peak memory 209656 kb
Host smart-598cbd9e-ca6a-4bb8-968d-91f3d609ecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285376072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2285376072
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.125925285
Short name T687
Test name
Test status
Simulation time 47476136 ps
CPU time 0.85 seconds
Started Jun 02 03:00:44 PM PDT 24
Finished Jun 02 03:00:45 PM PDT 24
Peak memory 205928 kb
Host smart-ddcbd342-a6c8-4cbc-a1f5-8bba96ca8c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125925285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.125925285
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.335056468
Short name T70
Test name
Test status
Simulation time 204336537 ps
CPU time 2.76 seconds
Started Jun 02 03:00:35 PM PDT 24
Finished Jun 02 03:00:38 PM PDT 24
Peak memory 210224 kb
Host smart-00a1fafa-9b30-4eab-a38c-1c6c6db795f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335056468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.335056468
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1380996260
Short name T77
Test name
Test status
Simulation time 228859287 ps
CPU time 3.1 seconds
Started Jun 02 03:00:34 PM PDT 24
Finished Jun 02 03:00:37 PM PDT 24
Peak memory 214228 kb
Host smart-b3aef3d6-0ef6-4f67-92c4-00bc1727b967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380996260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1380996260
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1939855879
Short name T743
Test name
Test status
Simulation time 769738568 ps
CPU time 2.18 seconds
Started Jun 02 03:00:35 PM PDT 24
Finished Jun 02 03:00:38 PM PDT 24
Peak memory 214340 kb
Host smart-17c969e3-d44a-4565-a310-7a5328544e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939855879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1939855879
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.914827918
Short name T349
Test name
Test status
Simulation time 474377741 ps
CPU time 6.34 seconds
Started Jun 02 03:00:34 PM PDT 24
Finished Jun 02 03:00:41 PM PDT 24
Peak memory 222284 kb
Host smart-a6294365-a7b3-4941-9dae-4618675d7dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914827918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.914827918
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1917536405
Short name T798
Test name
Test status
Simulation time 240117316 ps
CPU time 5.22 seconds
Started Jun 02 03:00:36 PM PDT 24
Finished Jun 02 03:00:42 PM PDT 24
Peak memory 214264 kb
Host smart-6e67af3c-9578-4ad3-800a-51bbc62aa824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917536405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1917536405
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3798528917
Short name T651
Test name
Test status
Simulation time 254484443 ps
CPU time 5.99 seconds
Started Jun 02 03:00:34 PM PDT 24
Finished Jun 02 03:00:41 PM PDT 24
Peak memory 207804 kb
Host smart-30e51b5d-98e1-4d69-a9cb-0406ce0c2786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798528917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3798528917
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.743474244
Short name T343
Test name
Test status
Simulation time 122623371 ps
CPU time 3.06 seconds
Started Jun 02 03:00:34 PM PDT 24
Finished Jun 02 03:00:37 PM PDT 24
Peak memory 206804 kb
Host smart-0ade5cd5-8dbc-4764-ad5b-a738aea3f429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743474244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.743474244
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1339019446
Short name T542
Test name
Test status
Simulation time 625004213 ps
CPU time 4.41 seconds
Started Jun 02 03:00:33 PM PDT 24
Finished Jun 02 03:00:38 PM PDT 24
Peak memory 206788 kb
Host smart-b5393d47-afde-460d-984e-e02481f42575
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339019446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1339019446
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1413092470
Short name T784
Test name
Test status
Simulation time 44988650 ps
CPU time 2.42 seconds
Started Jun 02 03:00:34 PM PDT 24
Finished Jun 02 03:00:37 PM PDT 24
Peak memory 207144 kb
Host smart-3d70afd7-94eb-4357-9256-3172329e1f06
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413092470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1413092470
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1754944890
Short name T226
Test name
Test status
Simulation time 3350225195 ps
CPU time 28.59 seconds
Started Jun 02 03:00:34 PM PDT 24
Finished Jun 02 03:01:03 PM PDT 24
Peak memory 208140 kb
Host smart-28e394ca-caa1-4c44-b8d5-78b3406b3dbf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754944890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1754944890
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3700339444
Short name T258
Test name
Test status
Simulation time 128056349 ps
CPU time 3.46 seconds
Started Jun 02 03:00:34 PM PDT 24
Finished Jun 02 03:00:38 PM PDT 24
Peak memory 209860 kb
Host smart-1a8bafef-ccdb-40e8-9570-415dd761720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700339444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3700339444
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2966298628
Short name T597
Test name
Test status
Simulation time 122915906 ps
CPU time 2.68 seconds
Started Jun 02 03:00:34 PM PDT 24
Finished Jun 02 03:00:37 PM PDT 24
Peak memory 206804 kb
Host smart-3ba07bc2-3dd0-4544-b148-86a0dff9fe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966298628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2966298628
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2112595280
Short name T158
Test name
Test status
Simulation time 1072291541 ps
CPU time 24.49 seconds
Started Jun 02 03:00:35 PM PDT 24
Finished Jun 02 03:01:00 PM PDT 24
Peak memory 216804 kb
Host smart-c17be555-5c85-4f21-988a-e15f769cafc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112595280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2112595280
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2769023721
Short name T781
Test name
Test status
Simulation time 106041863 ps
CPU time 3.5 seconds
Started Jun 02 03:00:35 PM PDT 24
Finished Jun 02 03:00:39 PM PDT 24
Peak memory 207436 kb
Host smart-0b36fee6-28ee-4d43-b0c1-57fbbb681d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769023721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2769023721
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.489133127
Short name T855
Test name
Test status
Simulation time 181512550 ps
CPU time 4.99 seconds
Started Jun 02 03:00:35 PM PDT 24
Finished Jun 02 03:00:40 PM PDT 24
Peak memory 211020 kb
Host smart-f93d3771-ca7f-4cb4-b059-fe8263fa88f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489133127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.489133127
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1647551931
Short name T487
Test name
Test status
Simulation time 13471821 ps
CPU time 0.72 seconds
Started Jun 02 03:00:45 PM PDT 24
Finished Jun 02 03:00:46 PM PDT 24
Peak memory 206012 kb
Host smart-ec775941-3ac5-4950-816c-d2aa3888f988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647551931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1647551931
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3025868238
Short name T254
Test name
Test status
Simulation time 1026608242 ps
CPU time 14.74 seconds
Started Jun 02 03:00:41 PM PDT 24
Finished Jun 02 03:00:56 PM PDT 24
Peak memory 215576 kb
Host smart-1566a760-0ae0-4750-b7b7-3869168f12b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025868238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3025868238
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1875632772
Short name T307
Test name
Test status
Simulation time 628221643 ps
CPU time 7.37 seconds
Started Jun 02 03:00:43 PM PDT 24
Finished Jun 02 03:00:50 PM PDT 24
Peak memory 214384 kb
Host smart-7c132e60-ad5f-429b-af13-53d4179d70cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875632772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1875632772
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2832834775
Short name T80
Test name
Test status
Simulation time 116868331 ps
CPU time 3.16 seconds
Started Jun 02 03:00:48 PM PDT 24
Finished Jun 02 03:00:52 PM PDT 24
Peak memory 214364 kb
Host smart-0c071eba-f5a3-47fb-8d3b-5602dabe77b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832834775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2832834775
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1271515543
Short name T731
Test name
Test status
Simulation time 135006306 ps
CPU time 5.46 seconds
Started Jun 02 03:00:50 PM PDT 24
Finished Jun 02 03:00:56 PM PDT 24
Peak memory 209948 kb
Host smart-2a66163e-1f1c-4fc9-a50c-a2167fb4bff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271515543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1271515543
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.263702307
Short name T613
Test name
Test status
Simulation time 398385565 ps
CPU time 4.39 seconds
Started Jun 02 03:00:43 PM PDT 24
Finished Jun 02 03:00:48 PM PDT 24
Peak memory 207408 kb
Host smart-707a47f3-295a-4c94-94fc-23df93579ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263702307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.263702307
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2475073539
Short name T548
Test name
Test status
Simulation time 48662385 ps
CPU time 2.97 seconds
Started Jun 02 03:00:40 PM PDT 24
Finished Jun 02 03:00:43 PM PDT 24
Peak memory 208516 kb
Host smart-4808bfdc-a028-49e8-a1f3-b0665ccdcc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475073539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2475073539
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1475362568
Short name T658
Test name
Test status
Simulation time 543497053 ps
CPU time 13.32 seconds
Started Jun 02 03:00:43 PM PDT 24
Finished Jun 02 03:00:57 PM PDT 24
Peak memory 208024 kb
Host smart-d7bd7b3a-3aff-4a72-899c-1894fa553461
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475362568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1475362568
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2642476970
Short name T734
Test name
Test status
Simulation time 72795524 ps
CPU time 3.58 seconds
Started Jun 02 03:00:44 PM PDT 24
Finished Jun 02 03:00:48 PM PDT 24
Peak memory 208960 kb
Host smart-fc73a9fb-a4a1-493e-b332-366965b0c4e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642476970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2642476970
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1162169763
Short name T451
Test name
Test status
Simulation time 201144597 ps
CPU time 2.37 seconds
Started Jun 02 03:00:41 PM PDT 24
Finished Jun 02 03:00:44 PM PDT 24
Peak memory 206980 kb
Host smart-33a0dd7a-e60e-4c58-98cf-8e343846aaa0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162169763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1162169763
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1129294182
Short name T266
Test name
Test status
Simulation time 584989527 ps
CPU time 3 seconds
Started Jun 02 03:00:46 PM PDT 24
Finished Jun 02 03:00:50 PM PDT 24
Peak memory 207264 kb
Host smart-02b71ded-bc9b-445b-bc2f-aa761308188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129294182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1129294182
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2821082509
Short name T656
Test name
Test status
Simulation time 582359236 ps
CPU time 5.52 seconds
Started Jun 02 03:00:44 PM PDT 24
Finished Jun 02 03:00:50 PM PDT 24
Peak memory 206696 kb
Host smart-caeeb9da-e27c-4515-8b38-f6d33330bf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821082509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2821082509
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.990672422
Short name T264
Test name
Test status
Simulation time 2016373160 ps
CPU time 21.86 seconds
Started Jun 02 03:00:46 PM PDT 24
Finished Jun 02 03:01:08 PM PDT 24
Peak memory 222484 kb
Host smart-a81abaf7-2373-477a-bc0d-0b18abe75bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990672422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.990672422
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.266498140
Short name T760
Test name
Test status
Simulation time 288643386 ps
CPU time 6.7 seconds
Started Jun 02 03:00:49 PM PDT 24
Finished Jun 02 03:00:56 PM PDT 24
Peak memory 209784 kb
Host smart-447a8ae6-38ab-4a72-a86c-f79987811d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266498140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.266498140
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3184366631
Short name T700
Test name
Test status
Simulation time 403772276 ps
CPU time 3.65 seconds
Started Jun 02 03:00:45 PM PDT 24
Finished Jun 02 03:00:49 PM PDT 24
Peak memory 210948 kb
Host smart-340f9e37-cd1d-4fcc-bfe5-786f0274e941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184366631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3184366631
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1235824068
Short name T406
Test name
Test status
Simulation time 33085546 ps
CPU time 0.87 seconds
Started Jun 02 03:00:54 PM PDT 24
Finished Jun 02 03:00:55 PM PDT 24
Peak memory 205932 kb
Host smart-d74cc556-c0bf-451d-93ce-2cf8dc09387e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235824068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1235824068
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3554562178
Short name T32
Test name
Test status
Simulation time 88621106 ps
CPU time 3.82 seconds
Started Jun 02 03:00:55 PM PDT 24
Finished Jun 02 03:00:59 PM PDT 24
Peak memory 215544 kb
Host smart-c29680c5-4130-42ab-be31-6327e016d55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554562178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3554562178
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3430967521
Short name T289
Test name
Test status
Simulation time 1216127965 ps
CPU time 39.47 seconds
Started Jun 02 03:00:50 PM PDT 24
Finished Jun 02 03:01:30 PM PDT 24
Peak memory 214308 kb
Host smart-907ec957-b7c0-45ab-92ee-78ec1e6189b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430967521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3430967521
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.789435986
Short name T909
Test name
Test status
Simulation time 106318454 ps
CPU time 3.33 seconds
Started Jun 02 03:00:55 PM PDT 24
Finished Jun 02 03:00:59 PM PDT 24
Peak memory 214316 kb
Host smart-bb5e7a2c-4799-46f1-bcff-c485aabecddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789435986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.789435986
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1956770674
Short name T797
Test name
Test status
Simulation time 968382686 ps
CPU time 3.5 seconds
Started Jun 02 03:00:52 PM PDT 24
Finished Jun 02 03:00:57 PM PDT 24
Peak memory 214172 kb
Host smart-3a5e64c3-1dfd-49cb-99c5-4225f2bd1294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956770674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1956770674
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3173148387
Short name T551
Test name
Test status
Simulation time 3874993672 ps
CPU time 16.87 seconds
Started Jun 02 03:00:53 PM PDT 24
Finished Jun 02 03:01:10 PM PDT 24
Peak memory 220856 kb
Host smart-38d9ee3e-732f-4f09-937b-d60001496471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173148387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3173148387
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1882538144
Short name T493
Test name
Test status
Simulation time 1180493669 ps
CPU time 11.74 seconds
Started Jun 02 03:00:52 PM PDT 24
Finished Jun 02 03:01:04 PM PDT 24
Peak memory 208392 kb
Host smart-1abbad73-662f-4fe0-ae13-1e5b02d255ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882538144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1882538144
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.736229409
Short name T615
Test name
Test status
Simulation time 77815320 ps
CPU time 1.72 seconds
Started Jun 02 03:00:47 PM PDT 24
Finished Jun 02 03:00:49 PM PDT 24
Peak memory 206856 kb
Host smart-422b7d44-c47a-4c98-a48f-42986c7537bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736229409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.736229409
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3743126022
Short name T500
Test name
Test status
Simulation time 96280885 ps
CPU time 3.43 seconds
Started Jun 02 03:00:46 PM PDT 24
Finished Jun 02 03:00:50 PM PDT 24
Peak memory 208624 kb
Host smart-2dffd998-81ec-449c-a050-02693780fa56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743126022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3743126022
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.916743562
Short name T908
Test name
Test status
Simulation time 959634679 ps
CPU time 8.38 seconds
Started Jun 02 03:00:45 PM PDT 24
Finished Jun 02 03:00:54 PM PDT 24
Peak memory 206832 kb
Host smart-e2d41f61-f0c0-4a14-923e-95def06e5dcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916743562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.916743562
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1243913454
Short name T102
Test name
Test status
Simulation time 193510045 ps
CPU time 2.62 seconds
Started Jun 02 03:00:51 PM PDT 24
Finished Jun 02 03:00:54 PM PDT 24
Peak memory 206936 kb
Host smart-ea06f250-2a7d-4000-b6de-66d38abbcab5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243913454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1243913454
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1609227225
Short name T614
Test name
Test status
Simulation time 90585621 ps
CPU time 1.55 seconds
Started Jun 02 03:00:52 PM PDT 24
Finished Jun 02 03:00:55 PM PDT 24
Peak memory 207752 kb
Host smart-12f40e53-63eb-4104-b342-e4d73cf1a497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609227225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1609227225
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3342811715
Short name T617
Test name
Test status
Simulation time 2750665969 ps
CPU time 37.32 seconds
Started Jun 02 03:00:51 PM PDT 24
Finished Jun 02 03:01:29 PM PDT 24
Peak memory 208608 kb
Host smart-7b9bac07-8f03-49d0-9858-3d584323e9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342811715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3342811715
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1869230805
Short name T202
Test name
Test status
Simulation time 2883501939 ps
CPU time 65.29 seconds
Started Jun 02 03:00:55 PM PDT 24
Finished Jun 02 03:02:00 PM PDT 24
Peak memory 216804 kb
Host smart-9c8e9e84-8620-4929-b69d-614c73832c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869230805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1869230805
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1219836268
Short name T904
Test name
Test status
Simulation time 717455241 ps
CPU time 5.07 seconds
Started Jun 02 03:00:52 PM PDT 24
Finished Jun 02 03:00:58 PM PDT 24
Peak memory 209656 kb
Host smart-c4ae5ae1-1a6e-4769-9067-0a63e2b22baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219836268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1219836268
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3574886406
Short name T377
Test name
Test status
Simulation time 57904029 ps
CPU time 2.41 seconds
Started Jun 02 03:00:52 PM PDT 24
Finished Jun 02 03:00:56 PM PDT 24
Peak memory 210276 kb
Host smart-d2ff2c5b-9f80-47a1-a827-2c6ff9af9346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574886406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3574886406
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2942917714
Short name T782
Test name
Test status
Simulation time 42672588 ps
CPU time 0.75 seconds
Started Jun 02 03:01:06 PM PDT 24
Finished Jun 02 03:01:07 PM PDT 24
Peak memory 205952 kb
Host smart-a40c3170-b711-46f8-bf95-ae5f38e169bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942917714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2942917714
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3868945790
Short name T207
Test name
Test status
Simulation time 668926099 ps
CPU time 2.04 seconds
Started Jun 02 03:00:59 PM PDT 24
Finished Jun 02 03:01:01 PM PDT 24
Peak memory 208680 kb
Host smart-c0eaa4a4-6414-414d-92ae-859385517b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868945790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3868945790
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3209694681
Short name T593
Test name
Test status
Simulation time 116564949 ps
CPU time 2.21 seconds
Started Jun 02 03:00:58 PM PDT 24
Finished Jun 02 03:01:01 PM PDT 24
Peak memory 209480 kb
Host smart-cabd779d-cc51-4da4-aa98-2fefa5c51501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209694681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3209694681
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1292132212
Short name T616
Test name
Test status
Simulation time 54315708 ps
CPU time 3.03 seconds
Started Jun 02 03:00:59 PM PDT 24
Finished Jun 02 03:01:03 PM PDT 24
Peak memory 214520 kb
Host smart-0e7060cb-4f09-45cf-89e6-186bfefb72f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292132212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1292132212
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3697631419
Short name T235
Test name
Test status
Simulation time 419292066 ps
CPU time 3.96 seconds
Started Jun 02 03:01:01 PM PDT 24
Finished Jun 02 03:01:05 PM PDT 24
Peak memory 221884 kb
Host smart-3d5bc535-2db9-4a16-b48f-2a6c8b6cbd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697631419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3697631419
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4054575925
Short name T68
Test name
Test status
Simulation time 60132219 ps
CPU time 3.78 seconds
Started Jun 02 03:00:59 PM PDT 24
Finished Jun 02 03:01:03 PM PDT 24
Peak memory 214392 kb
Host smart-2607e389-2155-4261-bebb-51fe356ef8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054575925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4054575925
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2666857979
Short name T321
Test name
Test status
Simulation time 190871536 ps
CPU time 8.17 seconds
Started Jun 02 03:00:58 PM PDT 24
Finished Jun 02 03:01:07 PM PDT 24
Peak memory 210596 kb
Host smart-87d18508-e98e-43fe-b00f-0c5dd553489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666857979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2666857979
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.629666608
Short name T702
Test name
Test status
Simulation time 25599198 ps
CPU time 2.21 seconds
Started Jun 02 03:00:54 PM PDT 24
Finished Jun 02 03:00:57 PM PDT 24
Peak memory 208908 kb
Host smart-a4e0448f-1ec3-4a19-a456-0eb27db8dd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629666608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.629666608
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1339362987
Short name T884
Test name
Test status
Simulation time 115485418 ps
CPU time 4.22 seconds
Started Jun 02 03:01:00 PM PDT 24
Finished Jun 02 03:01:05 PM PDT 24
Peak memory 208668 kb
Host smart-f627b4e4-a252-4982-ad58-3506faba9789
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339362987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1339362987
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2267488467
Short name T499
Test name
Test status
Simulation time 63095818 ps
CPU time 2.76 seconds
Started Jun 02 03:00:52 PM PDT 24
Finished Jun 02 03:00:55 PM PDT 24
Peak memory 206956 kb
Host smart-e497aae6-72c9-477c-bd97-575b1eb53edd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267488467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2267488467
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.457449245
Short name T495
Test name
Test status
Simulation time 1342049971 ps
CPU time 36.44 seconds
Started Jun 02 03:00:59 PM PDT 24
Finished Jun 02 03:01:36 PM PDT 24
Peak memory 208976 kb
Host smart-9f7c2333-7504-4105-92a5-5c0a0cfe53d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457449245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.457449245
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2329524345
Short name T541
Test name
Test status
Simulation time 661297632 ps
CPU time 3.03 seconds
Started Jun 02 03:01:04 PM PDT 24
Finished Jun 02 03:01:08 PM PDT 24
Peak memory 207968 kb
Host smart-69ef0664-c80e-47af-9ef3-acb5feefd30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329524345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2329524345
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1504130220
Short name T488
Test name
Test status
Simulation time 412217936 ps
CPU time 2.97 seconds
Started Jun 02 03:00:51 PM PDT 24
Finished Jun 02 03:00:55 PM PDT 24
Peak memory 208432 kb
Host smart-c6bccb97-455d-4d7f-922e-8458b724190a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504130220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1504130220
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3828403859
Short name T625
Test name
Test status
Simulation time 25529274806 ps
CPU time 111.59 seconds
Started Jun 02 03:01:04 PM PDT 24
Finished Jun 02 03:02:57 PM PDT 24
Peak memory 215728 kb
Host smart-0a092056-aef4-4383-b22f-ed1a78131495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828403859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3828403859
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3268844731
Short name T501
Test name
Test status
Simulation time 3785803719 ps
CPU time 37.09 seconds
Started Jun 02 03:00:59 PM PDT 24
Finished Jun 02 03:01:36 PM PDT 24
Peak memory 207940 kb
Host smart-63c903d1-a67b-4cd0-8897-ccdf2c99e3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268844731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3268844731
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2160097588
Short name T511
Test name
Test status
Simulation time 62501666 ps
CPU time 2.05 seconds
Started Jun 02 03:01:04 PM PDT 24
Finished Jun 02 03:01:07 PM PDT 24
Peak memory 209940 kb
Host smart-e3846c95-7682-456e-996b-f87e0f284785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160097588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2160097588
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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