Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	33	1			T48	1		T49	1		T33	1
auto[OpGenId]	14	1			T58	1		T73	1		T9	1
auto[OpGenSwOut]	24	1			T59	1		T66	1		T218	1
auto[OpGenHwOut]	21	1			T40	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1595	1			T40	1		T28	5		T51	3
auto[StInit]	77	1			T57	1		T19	1		T51	1
auto[StCreatorRootKey]	48	1			T59	1		T62	1		T64	1
auto[StOwnerIntKey]	42	1			T2	1		T67	1		T44	1
auto[StOwnerKey]	32	1			T37	1		T70	1		T6	1
auto[StDisabled]	429	1			T28	13		T51	5		T75	1
auto[StInvalid]	50	1			T17	1		T53	1		T61	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3256

1

T1

1

T2

2

T3

1

auto[1]

92

1

T40

1

T59

1

T6

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1590	1			T28	5		T51	3		T124	3
auto[StReset]	auto[1]	5	1			T40	1		T226	1		T55	1
auto[StInit]	auto[0]	42	1			T57	1		T19	1		T51	1
auto[StInit]	auto[1]	35	1			T58	1		T8	1		T41	1
auto[StCreatorRootKey]	auto[0]	27	1			T62	1		T64	1		T63	1
auto[StCreatorRootKey]	auto[1]	21	1			T59	1		T65	1		T227	1
auto[StOwnerIntKey]	auto[0]	30	1			T2	1		T67	1		T44	1
auto[StOwnerIntKey]	auto[1]	12	1			T66	1		T68	1		T69	1
auto[StOwnerKey]	auto[0]	25	1			T37	1		T70	1		T71	1
auto[StOwnerKey]	auto[1]	7	1			T6	1		T73	1		T218	1
auto[StDisabled]	auto[0]	417	1			T28	13		T51	5		T75	1
auto[StDisabled]	auto[1]	12	1			T7	1		T48	1		T154	1
auto[StInvalid]	auto[0]	50	1			T17	1		T53	1		T61	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	4	1			T226	1		T55	1		T228	1
auto[StReset]	auto[OpGenHwOut]	1	1			T40	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	15	1			T33	1		T229	1		T230	1
auto[StInit]	auto[OpGenId]	4	1			T58	1		T86	1		T231	1
auto[StInit]	auto[OpGenSwOut]	8	1			T78	1		T229	1		T209	1
auto[StInit]	auto[OpGenHwOut]	8	1			T8	1		T41	1		T232	1
auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T49	1		T50	1		T139	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T9	1		T233	1		T228	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T59	1		T227	1		T68	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	5	1			T65	1		T207	1		T23	1
auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T68	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenId]	4	1			T234	1		T235	1		T236	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T66	1		T69	1		T83	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T237	1		T238	1		T239	1
auto[StOwnerKey]	auto[OpAdvance]	2	1			T210	1		T240	1		-	-
auto[StOwnerKey]	auto[OpGenId]	1	1			T73	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T218	1		T241	1		T210	1
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T6	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	4	1			T48	1		T226	1		T242	1
auto[StDisabled]	auto[OpGenId]	2	1			T243	1		T244	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T210	1		T236	1		T245	1
auto[StDisabled]	auto[OpGenHwOut]	3	1			T7	1		T154	1		T246	1