Summary for Variable aes_sl_avail
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for aes_sl_avail
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4657 |
1 |
|
|
T1 |
9 |
|
T4 |
2 |
|
T15 |
11 |
auto[1] |
552 |
1 |
|
|
T46 |
1 |
|
T47 |
3 |
|
T28 |
7 |
Summary for Variable aes_sl_avail_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for aes_sl_avail_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4657 |
1 |
|
|
T1 |
9 |
|
T4 |
2 |
|
T15 |
11 |
auto[1] |
552 |
1 |
|
|
T46 |
1 |
|
T47 |
3 |
|
T28 |
7 |
Summary for Variable kmac_sl_avail
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_sl_avail
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4650 |
1 |
|
|
T1 |
9 |
|
T4 |
2 |
|
T15 |
11 |
auto[1] |
559 |
1 |
|
|
T36 |
1 |
|
T38 |
4 |
|
T39 |
3 |
Summary for Variable kmac_sl_avail_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_sl_avail_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4650 |
1 |
|
|
T1 |
9 |
|
T4 |
2 |
|
T15 |
11 |
auto[1] |
559 |
1 |
|
|
T36 |
1 |
|
T38 |
4 |
|
T39 |
3 |
Summary for Variable op
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for op
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[OpAdvance] |
417 |
1 |
|
|
T17 |
1 |
|
T5 |
1 |
|
T28 |
6 |
auto[OpGenId] |
1052 |
1 |
|
|
T4 |
1 |
|
T17 |
4 |
|
T5 |
3 |
auto[OpGenSwOut] |
1082 |
1 |
|
|
T5 |
2 |
|
T18 |
2 |
|
T36 |
2 |
auto[OpGenHwOut] |
2587 |
1 |
|
|
T1 |
9 |
|
T4 |
1 |
|
T15 |
11 |
auto[OpDisable] |
71 |
1 |
|
|
T28 |
3 |
|
T60 |
1 |
|
T74 |
1 |
Summary for Variable op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for op_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[OpAdvance] |
417 |
1 |
|
|
T17 |
1 |
|
T5 |
1 |
|
T28 |
6 |
auto[OpGenId] |
1052 |
1 |
|
|
T4 |
1 |
|
T17 |
4 |
|
T5 |
3 |
auto[OpGenSwOut] |
1082 |
1 |
|
|
T5 |
2 |
|
T18 |
2 |
|
T36 |
2 |
auto[OpGenHwOut] |
2587 |
1 |
|
|
T1 |
9 |
|
T4 |
1 |
|
T15 |
11 |
auto[OpDisable] |
71 |
1 |
|
|
T28 |
3 |
|
T60 |
1 |
|
T74 |
1 |
Summary for Variable otbn_sl_avail
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otbn_sl_avail
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4683 |
1 |
|
|
T1 |
6 |
|
T4 |
2 |
|
T15 |
6 |
auto[1] |
526 |
1 |
|
|
T1 |
3 |
|
T15 |
5 |
|
T5 |
1 |
Summary for Variable otbn_sl_avail_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otbn_sl_avail_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4683 |
1 |
|
|
T1 |
6 |
|
T4 |
2 |
|
T15 |
6 |
auto[1] |
526 |
1 |
|
|
T1 |
3 |
|
T15 |
5 |
|
T5 |
1 |
Summary for Variable regwen_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for regwen_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4917 |
1 |
|
|
T1 |
9 |
|
T4 |
2 |
|
T15 |
11 |
auto[1] |
292 |
1 |
|
|
T130 |
15 |
|
T151 |
4 |
|
T152 |
8 |
Summary for Variable sideload_clear
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
8 |
0 |
8 |
100.00 |
Automatically Generated Bins for sideload_clear
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1814 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T15 |
2 |
auto[1] |
696 |
1 |
|
|
T1 |
3 |
|
T4 |
1 |
|
T15 |
3 |
auto[2] |
628 |
1 |
|
|
T15 |
1 |
|
T17 |
1 |
|
T5 |
1 |
auto[3] |
663 |
1 |
|
|
T1 |
4 |
|
T15 |
3 |
|
T36 |
1 |
auto[4] |
352 |
1 |
|
|
T15 |
1 |
|
T5 |
1 |
|
T38 |
1 |
auto[5] |
326 |
1 |
|
|
T15 |
1 |
|
T17 |
1 |
|
T46 |
1 |
auto[6] |
361 |
1 |
|
|
T1 |
1 |
|
T5 |
2 |
|
T39 |
1 |
auto[7] |
369 |
1 |
|
|
T5 |
1 |
|
T18 |
2 |
|
T38 |
1 |
Summary for Variable sideload_clear_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for sideload_clear_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
clear_all |
1408 |
1 |
|
|
T1 |
1 |
|
T15 |
2 |
|
T17 |
1 |
clear_one[1] |
696 |
1 |
|
|
T1 |
3 |
|
T4 |
1 |
|
T15 |
3 |
clear_one[2] |
628 |
1 |
|
|
T15 |
1 |
|
T17 |
1 |
|
T5 |
1 |
clear_one[3] |
663 |
1 |
|
|
T1 |
4 |
|
T15 |
3 |
|
T36 |
1 |
clear_none |
1814 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T15 |
2 |
Summary for Variable state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
7 |
0 |
7 |
100.00 |
Automatically Generated Bins for state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
969 |
1 |
|
|
T1 |
1 |
|
T4 |
2 |
|
T15 |
3 |
auto[StInit] |
639 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T17 |
1 |
auto[StCreatorRootKey] |
540 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T5 |
1 |
auto[StOwnerIntKey] |
503 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T5 |
1 |
auto[StOwnerKey] |
456 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T5 |
1 |
auto[StDisabled] |
1805 |
1 |
|
|
T1 |
4 |
|
T15 |
4 |
|
T5 |
3 |
auto[StInvalid] |
297 |
1 |
|
|
T17 |
4 |
|
T18 |
5 |
|
T53 |
4 |
Summary for Variable state_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
7 |
0 |
7 |
100.00 |
Automatically Generated Bins for state_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
969 |
1 |
|
|
T1 |
1 |
|
T4 |
2 |
|
T15 |
3 |
auto[StInit] |
639 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T17 |
1 |
auto[StCreatorRootKey] |
540 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T5 |
1 |
auto[StOwnerIntKey] |
503 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T5 |
1 |
auto[StOwnerKey] |
456 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T5 |
1 |
auto[StDisabled] |
1805 |
1 |
|
|
T1 |
4 |
|
T15 |
4 |
|
T5 |
3 |
auto[StInvalid] |
297 |
1 |
|
|
T17 |
4 |
|
T18 |
5 |
|
T53 |
4 |
Summary for Cross sideload_clear_x_state_op_cross
Samples crossed: sideload_clear state op
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
280 |
56 |
224 |
80.00 |
56 |
Automatically Generated Cross Bins for sideload_clear_x_state_op_cross
Uncovered bins
sideload_clear | state | op | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] |
[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]] |
[auto[OpDisable]] |
-- |
-- |
5 |
|
[auto[0]] |
[auto[StInvalid]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[1] - auto[6]] |
[auto[StReset]] |
[auto[OpAdvance]] |
-- |
-- |
6 |
|
[auto[1] - auto[6]] |
[auto[StReset]] |
[auto[OpDisable]] |
-- |
-- |
6 |
|
[auto[1] - auto[6]] |
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]] |
[auto[OpDisable]] |
-- |
-- |
24 |
|
[auto[1] - auto[6]] |
[auto[StInvalid]] |
[auto[OpDisable]] |
-- |
-- |
6 |
|
[auto[7]] |
[auto[StReset] , auto[StInit]] |
[auto[OpAdvance]] |
-- |
-- |
2 |
|
[auto[7]] |
[auto[StReset] , auto[StInit]] |
[auto[OpDisable]] |
-- |
-- |
2 |
|
[auto[7]] |
[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]] |
[auto[OpDisable]] |
-- |
-- |
3 |
|
[auto[7]] |
[auto[StInvalid]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
Covered bins
sideload_clear | state | op | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[StReset] |
auto[OpAdvance] |
3 |
1 |
|
|
T151 |
1 |
|
T247 |
1 |
|
T248 |
1 |
auto[0] |
auto[StReset] |
auto[OpGenId] |
143 |
1 |
|
|
T164 |
1 |
|
T28 |
1 |
|
T95 |
1 |
auto[0] |
auto[StReset] |
auto[OpGenSwOut] |
158 |
1 |
|
|
T46 |
1 |
|
T28 |
3 |
|
T70 |
1 |
auto[0] |
auto[StReset] |
auto[OpGenHwOut] |
262 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T15 |
1 |
auto[0] |
auto[StInit] |
auto[OpAdvance] |
37 |
1 |
|
|
T17 |
1 |
|
T25 |
1 |
|
T51 |
1 |
auto[0] |
auto[StInit] |
auto[OpGenId] |
83 |
1 |
|
|
T28 |
2 |
|
T89 |
1 |
|
T52 |
1 |
auto[0] |
auto[StInit] |
auto[OpGenSwOut] |
104 |
1 |
|
|
T28 |
3 |
|
T211 |
1 |
|
T249 |
1 |
auto[0] |
auto[StInit] |
auto[OpGenHwOut] |
176 |
1 |
|
|
T5 |
1 |
|
T36 |
1 |
|
T38 |
1 |
auto[0] |
auto[StCreatorRootKey] |
auto[OpAdvance] |
20 |
1 |
|
|
T250 |
1 |
|
T74 |
1 |
|
T130 |
1 |
auto[0] |
auto[StCreatorRootKey] |
auto[OpGenId] |
50 |
1 |
|
|
T224 |
1 |
|
T73 |
1 |
|
T64 |
1 |
auto[0] |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
42 |
1 |
|
|
T96 |
1 |
|
T28 |
1 |
|
T214 |
1 |
auto[0] |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
70 |
1 |
|
|
T15 |
1 |
|
T38 |
1 |
|
T97 |
1 |
auto[0] |
auto[StOwnerIntKey] |
auto[OpAdvance] |
11 |
1 |
|
|
T73 |
1 |
|
T218 |
1 |
|
T151 |
1 |
auto[0] |
auto[StOwnerIntKey] |
auto[OpGenId] |
31 |
1 |
|
|
T28 |
1 |
|
T6 |
1 |
|
T51 |
1 |
auto[0] |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
38 |
1 |
|
|
T28 |
1 |
|
T7 |
1 |
|
T146 |
1 |
auto[0] |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
56 |
1 |
|
|
T28 |
1 |
|
T60 |
1 |
|
T251 |
1 |
auto[0] |
auto[StOwnerKey] |
auto[OpAdvance] |
9 |
1 |
|
|
T153 |
1 |
|
T252 |
1 |
|
T230 |
1 |
auto[0] |
auto[StOwnerKey] |
auto[OpGenId] |
23 |
1 |
|
|
T93 |
1 |
|
T60 |
1 |
|
T64 |
3 |
auto[0] |
auto[StOwnerKey] |
auto[OpGenSwOut] |
18 |
1 |
|
|
T253 |
1 |
|
T78 |
1 |
|
T226 |
2 |
auto[0] |
auto[StOwnerKey] |
auto[OpGenHwOut] |
42 |
1 |
|
|
T90 |
1 |
|
T145 |
1 |
|
T113 |
2 |
auto[0] |
auto[StDisabled] |
auto[OpAdvance] |
31 |
1 |
|
|
T28 |
1 |
|
T153 |
1 |
|
T78 |
1 |
auto[0] |
auto[StDisabled] |
auto[OpGenId] |
72 |
1 |
|
|
T28 |
1 |
|
T144 |
1 |
|
T223 |
1 |
auto[0] |
auto[StDisabled] |
auto[OpGenSwOut] |
64 |
1 |
|
|
T46 |
1 |
|
T28 |
3 |
|
T95 |
1 |
auto[0] |
auto[StDisabled] |
auto[OpGenHwOut] |
170 |
1 |
|
|
T38 |
2 |
|
T47 |
1 |
|
T97 |
1 |
auto[0] |
auto[StDisabled] |
auto[OpDisable] |
20 |
1 |
|
|
T254 |
1 |
|
T77 |
1 |
|
T78 |
1 |
auto[0] |
auto[StInvalid] |
auto[OpAdvance] |
9 |
1 |
|
|
T53 |
1 |
|
T54 |
1 |
|
T255 |
1 |
auto[0] |
auto[StInvalid] |
auto[OpGenId] |
25 |
1 |
|
|
T17 |
1 |
|
T53 |
1 |
|
T61 |
1 |
auto[0] |
auto[StInvalid] |
auto[OpGenSwOut] |
26 |
1 |
|
|
T219 |
1 |
|
T256 |
1 |
|
T257 |
1 |
auto[0] |
auto[StInvalid] |
auto[OpGenHwOut] |
21 |
1 |
|
|
T18 |
1 |
|
T219 |
1 |
|
T258 |
1 |
auto[1] |
auto[StReset] |
auto[OpGenId] |
23 |
1 |
|
|
T4 |
1 |
|
T59 |
1 |
|
T6 |
1 |
auto[1] |
auto[StReset] |
auto[OpGenSwOut] |
14 |
1 |
|
|
T28 |
1 |
|
T70 |
1 |
|
T53 |
1 |
auto[1] |
auto[StReset] |
auto[OpGenHwOut] |
42 |
1 |
|
|
T212 |
1 |
|
T145 |
1 |
|
T259 |
1 |
auto[1] |
auto[StInit] |
auto[OpAdvance] |
2 |
1 |
|
|
T260 |
1 |
|
T261 |
1 |
|
- |
- |
auto[1] |
auto[StInit] |
auto[OpGenId] |
9 |
1 |
|
|
T64 |
1 |
|
T262 |
1 |
|
T263 |
1 |
auto[1] |
auto[StInit] |
auto[OpGenSwOut] |
16 |
1 |
|
|
T25 |
1 |
|
T264 |
1 |
|
T68 |
1 |
auto[1] |
auto[StInit] |
auto[OpGenHwOut] |
21 |
1 |
|
|
T47 |
1 |
|
T28 |
1 |
|
T148 |
1 |
auto[1] |
auto[StCreatorRootKey] |
auto[OpAdvance] |
9 |
1 |
|
|
T152 |
3 |
|
T205 |
1 |
|
T207 |
1 |
auto[1] |
auto[StCreatorRootKey] |
auto[OpGenId] |
15 |
1 |
|
|
T28 |
1 |
|
T29 |
1 |
|
T126 |
1 |
auto[1] |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
13 |
1 |
|
|
T36 |
1 |
|
T51 |
1 |
|
T265 |
1 |
auto[1] |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
43 |
1 |
|
|
T47 |
1 |
|
T28 |
1 |
|
T145 |
1 |
auto[1] |
auto[StOwnerIntKey] |
auto[OpAdvance] |
7 |
1 |
|
|
T60 |
1 |
|
T266 |
1 |
|
T141 |
1 |
auto[1] |
auto[StOwnerIntKey] |
auto[OpGenId] |
16 |
1 |
|
|
T96 |
1 |
|
T28 |
1 |
|
T267 |
1 |
auto[1] |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
14 |
1 |
|
|
T52 |
1 |
|
T126 |
1 |
|
T81 |
1 |
auto[1] |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
43 |
1 |
|
|
T1 |
1 |
|
T39 |
1 |
|
T46 |
1 |
auto[1] |
auto[StOwnerKey] |
auto[OpAdvance] |
10 |
1 |
|
|
T28 |
1 |
|
T64 |
1 |
|
T268 |
1 |
auto[1] |
auto[StOwnerKey] |
auto[OpGenId] |
15 |
1 |
|
|
T71 |
1 |
|
T269 |
1 |
|
T270 |
1 |
auto[1] |
auto[StOwnerKey] |
auto[OpGenSwOut] |
9 |
1 |
|
|
T74 |
1 |
|
T154 |
1 |
|
T155 |
1 |
auto[1] |
auto[StOwnerKey] |
auto[OpGenHwOut] |
44 |
1 |
|
|
T15 |
1 |
|
T28 |
1 |
|
T91 |
1 |
auto[1] |
auto[StDisabled] |
auto[OpAdvance] |
29 |
1 |
|
|
T5 |
1 |
|
T51 |
1 |
|
T249 |
1 |
auto[1] |
auto[StDisabled] |
auto[OpGenId] |
43 |
1 |
|
|
T96 |
1 |
|
T214 |
1 |
|
T60 |
1 |
auto[1] |
auto[StDisabled] |
auto[OpGenSwOut] |
54 |
1 |
|
|
T28 |
3 |
|
T224 |
1 |
|
T60 |
1 |
auto[1] |
auto[StDisabled] |
auto[OpGenHwOut] |
144 |
1 |
|
|
T1 |
2 |
|
T15 |
2 |
|
T47 |
1 |
auto[1] |
auto[StDisabled] |
auto[OpDisable] |
17 |
1 |
|
|
T28 |
2 |
|
T60 |
1 |
|
T74 |
1 |
auto[1] |
auto[StInvalid] |
auto[OpAdvance] |
4 |
1 |
|
|
T271 |
1 |
|
T272 |
1 |
|
T100 |
1 |
auto[1] |
auto[StInvalid] |
auto[OpGenId] |
12 |
1 |
|
|
T17 |
1 |
|
T18 |
1 |
|
T202 |
1 |
auto[1] |
auto[StInvalid] |
auto[OpGenSwOut] |
14 |
1 |
|
|
T54 |
1 |
|
T273 |
2 |
|
T200 |
1 |
auto[1] |
auto[StInvalid] |
auto[OpGenHwOut] |
14 |
1 |
|
|
T54 |
1 |
|
T102 |
1 |
|
T258 |
1 |
auto[2] |
auto[StReset] |
auto[OpGenId] |
17 |
1 |
|
|
T76 |
1 |
|
T103 |
1 |
|
T229 |
1 |
auto[2] |
auto[StReset] |
auto[OpGenSwOut] |
15 |
1 |
|
|
T28 |
1 |
|
T26 |
1 |
|
T74 |
1 |
auto[2] |
auto[StReset] |
auto[OpGenHwOut] |
48 |
1 |
|
|
T18 |
1 |
|
T38 |
2 |
|
T6 |
1 |
auto[2] |
auto[StInit] |
auto[OpAdvance] |
5 |
1 |
|
|
T64 |
1 |
|
T274 |
1 |
|
T106 |
1 |
auto[2] |
auto[StInit] |
auto[OpGenId] |
6 |
1 |
|
|
T25 |
1 |
|
T60 |
1 |
|
T154 |
1 |
auto[2] |
auto[StInit] |
auto[OpGenSwOut] |
8 |
1 |
|
|
T28 |
1 |
|
T64 |
1 |
|
T237 |
1 |
auto[2] |
auto[StInit] |
auto[OpGenHwOut] |
26 |
1 |
|
|
T26 |
1 |
|
T74 |
1 |
|
T126 |
1 |
auto[2] |
auto[StCreatorRootKey] |
auto[OpAdvance] |
9 |
1 |
|
|
T65 |
1 |
|
T275 |
1 |
|
T276 |
1 |
auto[2] |
auto[StCreatorRootKey] |
auto[OpGenId] |
13 |
1 |
|
|
T5 |
1 |
|
T211 |
1 |
|
T65 |
1 |
auto[2] |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
14 |
1 |
|
|
T28 |
1 |
|
T6 |
1 |
|
T52 |
1 |
auto[2] |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
32 |
1 |
|
|
T164 |
1 |
|
T28 |
1 |
|
T90 |
1 |
auto[2] |
auto[StOwnerIntKey] |
auto[OpAdvance] |
13 |
1 |
|
|
T151 |
1 |
|
T242 |
1 |
|
T277 |
1 |
auto[2] |
auto[StOwnerIntKey] |
auto[OpGenId] |
9 |
1 |
|
|
T64 |
1 |
|
T278 |
1 |
|
T279 |
1 |
auto[2] |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
9 |
1 |
|
|
T164 |
1 |
|
T83 |
1 |
|
T235 |
1 |
auto[2] |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
30 |
1 |
|
|
T28 |
1 |
|
T149 |
1 |
|
T26 |
1 |
auto[2] |
auto[StOwnerKey] |
auto[OpAdvance] |
5 |
1 |
|
|
T51 |
1 |
|
T280 |
1 |
|
T201 |
1 |
auto[2] |
auto[StOwnerKey] |
auto[OpGenId] |
9 |
1 |
|
|
T28 |
1 |
|
T130 |
2 |
|
T281 |
1 |
auto[2] |
auto[StOwnerKey] |
auto[OpGenSwOut] |
8 |
1 |
|
|
T65 |
1 |
|
T151 |
1 |
|
T230 |
1 |
auto[2] |
auto[StOwnerKey] |
auto[OpGenHwOut] |
41 |
1 |
|
|
T47 |
1 |
|
T48 |
1 |
|
T64 |
1 |
auto[2] |
auto[StDisabled] |
auto[OpAdvance] |
17 |
1 |
|
|
T28 |
1 |
|
T282 |
1 |
|
T283 |
1 |
auto[2] |
auto[StDisabled] |
auto[OpGenId] |
41 |
1 |
|
|
T130 |
2 |
|
T78 |
1 |
|
T126 |
2 |
auto[2] |
auto[StDisabled] |
auto[OpGenSwOut] |
41 |
1 |
|
|
T64 |
1 |
|
T130 |
2 |
|
T65 |
1 |
auto[2] |
auto[StDisabled] |
auto[OpGenHwOut] |
160 |
1 |
|
|
T15 |
1 |
|
T38 |
1 |
|
T39 |
1 |
auto[2] |
auto[StDisabled] |
auto[OpDisable] |
6 |
1 |
|
|
T138 |
1 |
|
T284 |
1 |
|
T285 |
1 |
auto[2] |
auto[StInvalid] |
auto[OpAdvance] |
5 |
1 |
|
|
T286 |
1 |
|
T287 |
1 |
|
T288 |
1 |
auto[2] |
auto[StInvalid] |
auto[OpGenId] |
17 |
1 |
|
|
T17 |
1 |
|
T18 |
1 |
|
T54 |
1 |
auto[2] |
auto[StInvalid] |
auto[OpGenSwOut] |
7 |
1 |
|
|
T202 |
1 |
|
T289 |
1 |
|
T290 |
1 |
auto[2] |
auto[StInvalid] |
auto[OpGenHwOut] |
17 |
1 |
|
|
T53 |
1 |
|
T61 |
1 |
|
T54 |
1 |
auto[3] |
auto[StReset] |
auto[OpGenId] |
16 |
1 |
|
|
T64 |
1 |
|
T291 |
1 |
|
T276 |
1 |
auto[3] |
auto[StReset] |
auto[OpGenSwOut] |
24 |
1 |
|
|
T28 |
1 |
|
T6 |
1 |
|
T51 |
1 |
auto[3] |
auto[StReset] |
auto[OpGenHwOut] |
39 |
1 |
|
|
T15 |
1 |
|
T215 |
1 |
|
T145 |
1 |
auto[3] |
auto[StInit] |
auto[OpAdvance] |
7 |
1 |
|
|
T153 |
3 |
|
T292 |
1 |
|
T293 |
1 |
auto[3] |
auto[StInit] |
auto[OpGenId] |
6 |
1 |
|
|
T294 |
1 |
|
T295 |
1 |
|
T296 |
1 |
auto[3] |
auto[StInit] |
auto[OpGenSwOut] |
7 |
1 |
|
|
T95 |
1 |
|
T254 |
1 |
|
T81 |
1 |
auto[3] |
auto[StInit] |
auto[OpGenHwOut] |
25 |
1 |
|
|
T1 |
1 |
|
T60 |
1 |
|
T145 |
1 |
auto[3] |
auto[StCreatorRootKey] |
auto[OpAdvance] |
6 |
1 |
|
|
T223 |
1 |
|
T270 |
1 |
|
T297 |
1 |
auto[3] |
auto[StCreatorRootKey] |
auto[OpGenId] |
12 |
1 |
|
|
T89 |
1 |
|
T64 |
2 |
|
T105 |
1 |
auto[3] |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
5 |
1 |
|
|
T60 |
1 |
|
T151 |
1 |
|
T298 |
1 |
auto[3] |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
44 |
1 |
|
|
T1 |
1 |
|
T39 |
1 |
|
T91 |
1 |
auto[3] |
auto[StOwnerIntKey] |
auto[OpAdvance] |
8 |
1 |
|
|
T28 |
1 |
|
T25 |
1 |
|
T107 |
1 |
auto[3] |
auto[StOwnerIntKey] |
auto[OpGenId] |
10 |
1 |
|
|
T51 |
1 |
|
T64 |
1 |
|
T68 |
1 |
auto[3] |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
12 |
1 |
|
|
T36 |
1 |
|
T223 |
1 |
|
T65 |
1 |
auto[3] |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
44 |
1 |
|
|
T15 |
1 |
|
T51 |
1 |
|
T145 |
1 |
auto[3] |
auto[StOwnerKey] |
auto[OpAdvance] |
5 |
1 |
|
|
T299 |
2 |
|
T300 |
1 |
|
T301 |
1 |
auto[3] |
auto[StOwnerKey] |
auto[OpGenId] |
16 |
1 |
|
|
T164 |
1 |
|
T60 |
1 |
|
T78 |
1 |
auto[3] |
auto[StOwnerKey] |
auto[OpGenSwOut] |
11 |
1 |
|
|
T223 |
1 |
|
T153 |
2 |
|
T126 |
1 |
auto[3] |
auto[StOwnerKey] |
auto[OpGenHwOut] |
37 |
1 |
|
|
T94 |
1 |
|
T148 |
1 |
|
T302 |
1 |
auto[3] |
auto[StDisabled] |
auto[OpAdvance] |
26 |
1 |
|
|
T64 |
1 |
|
T152 |
1 |
|
T283 |
2 |
auto[3] |
auto[StDisabled] |
auto[OpGenId] |
47 |
1 |
|
|
T95 |
1 |
|
T224 |
1 |
|
T60 |
1 |
auto[3] |
auto[StDisabled] |
auto[OpGenSwOut] |
41 |
1 |
|
|
T28 |
1 |
|
T214 |
1 |
|
T146 |
1 |
auto[3] |
auto[StDisabled] |
auto[OpGenHwOut] |
163 |
1 |
|
|
T1 |
2 |
|
T15 |
1 |
|
T38 |
1 |
auto[3] |
auto[StDisabled] |
auto[OpDisable] |
13 |
1 |
|
|
T28 |
1 |
|
T81 |
1 |
|
T242 |
1 |
auto[3] |
auto[StInvalid] |
auto[OpAdvance] |
9 |
1 |
|
|
T102 |
1 |
|
T303 |
1 |
|
T304 |
1 |
auto[3] |
auto[StInvalid] |
auto[OpGenId] |
11 |
1 |
|
|
T27 |
1 |
|
T305 |
2 |
|
T200 |
1 |
auto[3] |
auto[StInvalid] |
auto[OpGenSwOut] |
10 |
1 |
|
|
T202 |
1 |
|
T287 |
1 |
|
T306 |
1 |
auto[3] |
auto[StInvalid] |
auto[OpGenHwOut] |
9 |
1 |
|
|
T102 |
1 |
|
T305 |
1 |
|
T286 |
1 |
auto[4] |
auto[StReset] |
auto[OpGenId] |
5 |
1 |
|
|
T48 |
1 |
|
T230 |
1 |
|
T166 |
1 |
auto[4] |
auto[StReset] |
auto[OpGenSwOut] |
10 |
1 |
|
|
T54 |
1 |
|
T296 |
1 |
|
T271 |
1 |
auto[4] |
auto[StReset] |
auto[OpGenHwOut] |
25 |
1 |
|
|
T15 |
1 |
|
T215 |
1 |
|
T8 |
1 |
auto[4] |
auto[StInit] |
auto[OpAdvance] |
4 |
1 |
|
|
T307 |
1 |
|
T115 |
2 |
|
T308 |
1 |
auto[4] |
auto[StInit] |
auto[OpGenId] |
7 |
1 |
|
|
T34 |
1 |
|
T309 |
1 |
|
T207 |
1 |
auto[4] |
auto[StInit] |
auto[OpGenSwOut] |
3 |
1 |
|
|
T6 |
1 |
|
T242 |
1 |
|
T208 |
1 |
auto[4] |
auto[StInit] |
auto[OpGenHwOut] |
9 |
1 |
|
|
T310 |
1 |
|
T68 |
1 |
|
T197 |
1 |
auto[4] |
auto[StCreatorRootKey] |
auto[OpAdvance] |
2 |
1 |
|
|
T115 |
1 |
|
T311 |
1 |
|
- |
- |
auto[4] |
auto[StCreatorRootKey] |
auto[OpGenId] |
7 |
1 |
|
|
T154 |
1 |
|
T81 |
1 |
|
T312 |
1 |
auto[4] |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
6 |
1 |
|
|
T313 |
1 |
|
T81 |
1 |
|
T242 |
1 |
auto[4] |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
16 |
1 |
|
|
T314 |
1 |
|
T315 |
1 |
|
T316 |
1 |
auto[4] |
auto[StOwnerIntKey] |
auto[OpAdvance] |
2 |
1 |
|
|
T34 |
1 |
|
T138 |
1 |
|
- |
- |
auto[4] |
auto[StOwnerIntKey] |
auto[OpGenId] |
5 |
1 |
|
|
T64 |
1 |
|
T284 |
1 |
|
T209 |
1 |
auto[4] |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
12 |
1 |
|
|
T48 |
1 |
|
T254 |
1 |
|
T317 |
1 |
auto[4] |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
18 |
1 |
|
|
T38 |
1 |
|
T318 |
1 |
|
T319 |
1 |
auto[4] |
auto[StOwnerKey] |
auto[OpAdvance] |
2 |
1 |
|
|
T64 |
1 |
|
T320 |
1 |
|
- |
- |
auto[4] |
auto[StOwnerKey] |
auto[OpGenId] |
3 |
1 |
|
|
T78 |
1 |
|
T321 |
1 |
|
T322 |
1 |
auto[4] |
auto[StOwnerKey] |
auto[OpGenSwOut] |
4 |
1 |
|
|
T209 |
1 |
|
T323 |
1 |
|
T324 |
1 |
auto[4] |
auto[StOwnerKey] |
auto[OpGenHwOut] |
32 |
1 |
|
|
T25 |
1 |
|
T214 |
1 |
|
T325 |
1 |
auto[4] |
auto[StDisabled] |
auto[OpAdvance] |
11 |
1 |
|
|
T28 |
1 |
|
T253 |
1 |
|
T326 |
1 |
auto[4] |
auto[StDisabled] |
auto[OpGenId] |
34 |
1 |
|
|
T28 |
1 |
|
T113 |
1 |
|
T64 |
1 |
auto[4] |
auto[StDisabled] |
auto[OpGenSwOut] |
27 |
1 |
|
|
T5 |
1 |
|
T28 |
1 |
|
T51 |
2 |
auto[4] |
auto[StDisabled] |
auto[OpGenHwOut] |
79 |
1 |
|
|
T39 |
2 |
|
T96 |
1 |
|
T97 |
1 |
auto[4] |
auto[StDisabled] |
auto[OpDisable] |
8 |
1 |
|
|
T118 |
1 |
|
T327 |
1 |
|
T311 |
1 |
auto[4] |
auto[StInvalid] |
auto[OpAdvance] |
1 |
1 |
|
|
T328 |
1 |
|
- |
- |
|
- |
- |
auto[4] |
auto[StInvalid] |
auto[OpGenId] |
9 |
1 |
|
|
T103 |
1 |
|
T273 |
1 |
|
T290 |
1 |
auto[4] |
auto[StInvalid] |
auto[OpGenSwOut] |
4 |
1 |
|
|
T329 |
1 |
|
T330 |
1 |
|
T331 |
1 |
auto[4] |
auto[StInvalid] |
auto[OpGenHwOut] |
7 |
1 |
|
|
T102 |
1 |
|
T258 |
1 |
|
T103 |
1 |
auto[5] |
auto[StReset] |
auto[OpGenId] |
9 |
1 |
|
|
T6 |
1 |
|
T332 |
1 |
|
T154 |
1 |
auto[5] |
auto[StReset] |
auto[OpGenSwOut] |
7 |
1 |
|
|
T65 |
1 |
|
T313 |
1 |
|
T68 |
1 |
auto[5] |
auto[StReset] |
auto[OpGenHwOut] |
20 |
1 |
|
|
T46 |
1 |
|
T94 |
1 |
|
T310 |
1 |
auto[5] |
auto[StInit] |
auto[OpAdvance] |
4 |
1 |
|
|
T333 |
1 |
|
T230 |
1 |
|
T334 |
1 |
auto[5] |
auto[StInit] |
auto[OpGenId] |
1 |
1 |
|
|
T28 |
1 |
|
- |
- |
|
- |
- |
auto[5] |
auto[StInit] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T87 |
1 |
|
T335 |
1 |
|
- |
- |
auto[5] |
auto[StInit] |
auto[OpGenHwOut] |
15 |
1 |
|
|
T15 |
1 |
|
T336 |
1 |
|
T337 |
1 |
auto[5] |
auto[StCreatorRootKey] |
auto[OpAdvance] |
2 |
1 |
|
|
T338 |
1 |
|
T339 |
1 |
|
- |
- |
auto[5] |
auto[StCreatorRootKey] |
auto[OpGenId] |
8 |
1 |
|
|
T71 |
1 |
|
T230 |
1 |
|
T83 |
1 |
auto[5] |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
6 |
1 |
|
|
T220 |
1 |
|
T317 |
1 |
|
T309 |
1 |
auto[5] |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
22 |
1 |
|
|
T148 |
1 |
|
T217 |
1 |
|
T340 |
1 |
auto[5] |
auto[StOwnerIntKey] |
auto[OpAdvance] |
2 |
1 |
|
|
T113 |
1 |
|
T341 |
1 |
|
- |
- |
auto[5] |
auto[StOwnerIntKey] |
auto[OpGenId] |
7 |
1 |
|
|
T65 |
1 |
|
T342 |
1 |
|
T83 |
1 |
auto[5] |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
12 |
1 |
|
|
T28 |
1 |
|
T343 |
1 |
|
T242 |
1 |
auto[5] |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
12 |
1 |
|
|
T47 |
1 |
|
T344 |
1 |
|
T345 |
1 |
auto[5] |
auto[StOwnerKey] |
auto[OpAdvance] |
5 |
1 |
|
|
T138 |
1 |
|
T338 |
1 |
|
T335 |
2 |
auto[5] |
auto[StOwnerKey] |
auto[OpGenId] |
9 |
1 |
|
|
T270 |
1 |
|
T280 |
1 |
|
T83 |
1 |
auto[5] |
auto[StOwnerKey] |
auto[OpGenSwOut] |
8 |
1 |
|
|
T26 |
1 |
|
T346 |
1 |
|
T276 |
1 |
auto[5] |
auto[StOwnerKey] |
auto[OpGenHwOut] |
11 |
1 |
|
|
T97 |
1 |
|
T347 |
1 |
|
T274 |
1 |
auto[5] |
auto[StDisabled] |
auto[OpAdvance] |
9 |
1 |
|
|
T113 |
1 |
|
T154 |
1 |
|
T205 |
1 |
auto[5] |
auto[StDisabled] |
auto[OpGenId] |
19 |
1 |
|
|
T28 |
1 |
|
T146 |
1 |
|
T113 |
1 |
auto[5] |
auto[StDisabled] |
auto[OpGenSwOut] |
31 |
1 |
|
|
T28 |
1 |
|
T95 |
1 |
|
T267 |
1 |
auto[5] |
auto[StDisabled] |
auto[OpGenHwOut] |
84 |
1 |
|
|
T97 |
1 |
|
T60 |
1 |
|
T64 |
2 |
auto[5] |
auto[StDisabled] |
auto[OpDisable] |
2 |
1 |
|
|
T348 |
1 |
|
T228 |
1 |
|
- |
- |
auto[5] |
auto[StInvalid] |
auto[OpAdvance] |
4 |
1 |
|
|
T200 |
2 |
|
T349 |
1 |
|
T350 |
1 |
auto[5] |
auto[StInvalid] |
auto[OpGenId] |
6 |
1 |
|
|
T17 |
1 |
|
T305 |
1 |
|
T351 |
1 |
auto[5] |
auto[StInvalid] |
auto[OpGenSwOut] |
6 |
1 |
|
|
T61 |
1 |
|
T255 |
1 |
|
T352 |
1 |
auto[5] |
auto[StInvalid] |
auto[OpGenHwOut] |
3 |
1 |
|
|
T257 |
1 |
|
T352 |
1 |
|
T353 |
1 |
auto[6] |
auto[StReset] |
auto[OpGenId] |
10 |
1 |
|
|
T147 |
1 |
|
T74 |
1 |
|
T343 |
1 |
auto[6] |
auto[StReset] |
auto[OpGenSwOut] |
9 |
1 |
|
|
T249 |
1 |
|
T74 |
1 |
|
T309 |
1 |
auto[6] |
auto[StReset] |
auto[OpGenHwOut] |
26 |
1 |
|
|
T94 |
1 |
|
T64 |
1 |
|
T343 |
1 |
auto[6] |
auto[StInit] |
auto[OpAdvance] |
7 |
1 |
|
|
T299 |
1 |
|
T279 |
1 |
|
T354 |
1 |
auto[6] |
auto[StInit] |
auto[OpGenId] |
7 |
1 |
|
|
T51 |
1 |
|
T207 |
1 |
|
T327 |
1 |
auto[6] |
auto[StInit] |
auto[OpGenSwOut] |
5 |
1 |
|
|
T343 |
1 |
|
T230 |
1 |
|
T208 |
1 |
auto[6] |
auto[StInit] |
auto[OpGenHwOut] |
16 |
1 |
|
|
T19 |
1 |
|
T26 |
1 |
|
T355 |
1 |
auto[6] |
auto[StCreatorRootKey] |
auto[OpAdvance] |
4 |
1 |
|
|
T93 |
1 |
|
T356 |
1 |
|
T357 |
1 |
auto[6] |
auto[StCreatorRootKey] |
auto[OpGenId] |
8 |
1 |
|
|
T154 |
1 |
|
T139 |
1 |
|
T209 |
1 |
auto[6] |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
3 |
1 |
|
|
T299 |
1 |
|
T358 |
1 |
|
T359 |
1 |
auto[6] |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
25 |
1 |
|
|
T28 |
1 |
|
T75 |
1 |
|
T325 |
1 |
auto[6] |
auto[StOwnerIntKey] |
auto[OpAdvance] |
2 |
1 |
|
|
T283 |
1 |
|
T360 |
1 |
|
- |
- |
auto[6] |
auto[StOwnerIntKey] |
auto[OpGenId] |
4 |
1 |
|
|
T75 |
1 |
|
T229 |
1 |
|
T361 |
1 |
auto[6] |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
8 |
1 |
|
|
T5 |
1 |
|
T64 |
1 |
|
T292 |
1 |
auto[6] |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
23 |
1 |
|
|
T91 |
1 |
|
T113 |
1 |
|
T74 |
1 |
auto[6] |
auto[StOwnerKey] |
auto[OpAdvance] |
4 |
1 |
|
|
T154 |
1 |
|
T299 |
1 |
|
T207 |
1 |
auto[6] |
auto[StOwnerKey] |
auto[OpGenId] |
10 |
1 |
|
|
T5 |
1 |
|
T51 |
1 |
|
T362 |
1 |
auto[6] |
auto[StOwnerKey] |
auto[OpGenSwOut] |
4 |
1 |
|
|
T363 |
1 |
|
T364 |
1 |
|
T365 |
1 |
auto[6] |
auto[StOwnerKey] |
auto[OpGenHwOut] |
19 |
1 |
|
|
T1 |
1 |
|
T39 |
1 |
|
T215 |
1 |
auto[6] |
auto[StDisabled] |
auto[OpAdvance] |
19 |
1 |
|
|
T223 |
1 |
|
T226 |
1 |
|
T242 |
1 |
auto[6] |
auto[StDisabled] |
auto[OpGenId] |
21 |
1 |
|
|
T28 |
1 |
|
T64 |
1 |
|
T130 |
1 |
auto[6] |
auto[StDisabled] |
auto[OpGenSwOut] |
24 |
1 |
|
|
T28 |
2 |
|
T214 |
1 |
|
T149 |
1 |
auto[6] |
auto[StDisabled] |
auto[OpGenHwOut] |
76 |
1 |
|
|
T96 |
1 |
|
T47 |
1 |
|
T28 |
1 |
auto[6] |
auto[StDisabled] |
auto[OpDisable] |
2 |
1 |
|
|
T366 |
1 |
|
T367 |
1 |
|
- |
- |
auto[6] |
auto[StInvalid] |
auto[OpAdvance] |
2 |
1 |
|
|
T61 |
1 |
|
T368 |
1 |
|
- |
- |
auto[6] |
auto[StInvalid] |
auto[OpGenId] |
4 |
1 |
|
|
T54 |
1 |
|
T329 |
1 |
|
T369 |
1 |
auto[6] |
auto[StInvalid] |
auto[OpGenSwOut] |
7 |
1 |
|
|
T53 |
1 |
|
T111 |
1 |
|
T289 |
1 |
auto[6] |
auto[StInvalid] |
auto[OpGenHwOut] |
12 |
1 |
|
|
T255 |
1 |
|
T351 |
1 |
|
T111 |
1 |
auto[7] |
auto[StReset] |
auto[OpGenId] |
10 |
1 |
|
|
T298 |
1 |
|
T275 |
1 |
|
T333 |
1 |
auto[7] |
auto[StReset] |
auto[OpGenSwOut] |
10 |
1 |
|
|
T28 |
1 |
|
T70 |
1 |
|
T95 |
1 |
auto[7] |
auto[StReset] |
auto[OpGenHwOut] |
24 |
1 |
|
|
T215 |
1 |
|
T370 |
1 |
|
T197 |
1 |
auto[7] |
auto[StInit] |
auto[OpGenId] |
3 |
1 |
|
|
T210 |
1 |
|
T371 |
1 |
|
T372 |
1 |
auto[7] |
auto[StInit] |
auto[OpGenSwOut] |
6 |
1 |
|
|
T35 |
1 |
|
T373 |
1 |
|
T374 |
1 |
auto[7] |
auto[StInit] |
auto[OpGenHwOut] |
12 |
1 |
|
|
T28 |
1 |
|
T215 |
1 |
|
T76 |
1 |
auto[7] |
auto[StCreatorRootKey] |
auto[OpAdvance] |
1 |
1 |
|
|
T375 |
1 |
|
- |
- |
|
- |
- |
auto[7] |
auto[StCreatorRootKey] |
auto[OpGenId] |
5 |
1 |
|
|
T264 |
1 |
|
T376 |
1 |
|
T105 |
1 |
auto[7] |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
13 |
1 |
|
|
T65 |
1 |
|
T343 |
1 |
|
T365 |
1 |
auto[7] |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
15 |
1 |
|
|
T51 |
1 |
|
T377 |
1 |
|
T378 |
1 |
auto[7] |
auto[StOwnerIntKey] |
auto[OpAdvance] |
5 |
1 |
|
|
T226 |
1 |
|
T379 |
4 |
|
- |
- |
auto[7] |
auto[StOwnerIntKey] |
auto[OpGenId] |
6 |
1 |
|
|
T78 |
1 |
|
T242 |
1 |
|
T348 |
1 |
auto[7] |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
10 |
1 |
|
|
T64 |
1 |
|
T81 |
1 |
|
T274 |
1 |
auto[7] |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
24 |
1 |
|
|
T97 |
1 |
|
T90 |
1 |
|
T94 |
1 |
auto[7] |
auto[StOwnerKey] |
auto[OpAdvance] |
5 |
1 |
|
|
T380 |
1 |
|
T309 |
1 |
|
T335 |
1 |
auto[7] |
auto[StOwnerKey] |
auto[OpGenId] |
9 |
1 |
|
|
T96 |
1 |
|
T224 |
1 |
|
T51 |
1 |
auto[7] |
auto[StOwnerKey] |
auto[OpGenSwOut] |
11 |
1 |
|
|
T149 |
1 |
|
T229 |
1 |
|
T379 |
1 |
auto[7] |
auto[StOwnerKey] |
auto[OpGenHwOut] |
18 |
1 |
|
|
T38 |
1 |
|
T298 |
1 |
|
T381 |
1 |
auto[7] |
auto[StDisabled] |
auto[OpAdvance] |
17 |
1 |
|
|
T28 |
1 |
|
T60 |
1 |
|
T113 |
1 |
auto[7] |
auto[StDisabled] |
auto[OpGenId] |
32 |
1 |
|
|
T5 |
1 |
|
T130 |
1 |
|
T65 |
1 |
auto[7] |
auto[StDisabled] |
auto[OpGenSwOut] |
33 |
1 |
|
|
T93 |
1 |
|
T60 |
1 |
|
T267 |
1 |
auto[7] |
auto[StDisabled] |
auto[OpGenHwOut] |
75 |
1 |
|
|
T97 |
1 |
|
T28 |
1 |
|
T325 |
1 |
auto[7] |
auto[StDisabled] |
auto[OpDisable] |
3 |
1 |
|
|
T382 |
1 |
|
T311 |
1 |
|
T383 |
1 |
auto[7] |
auto[StInvalid] |
auto[OpAdvance] |
7 |
1 |
|
|
T219 |
1 |
|
T273 |
1 |
|
T351 |
1 |
auto[7] |
auto[StInvalid] |
auto[OpGenId] |
4 |
1 |
|
|
T289 |
1 |
|
T384 |
1 |
|
T385 |
1 |
auto[7] |
auto[StInvalid] |
auto[OpGenSwOut] |
5 |
1 |
|
|
T18 |
2 |
|
T272 |
1 |
|
T386 |
1 |
auto[7] |
auto[StInvalid] |
auto[OpGenHwOut] |
6 |
1 |
|
|
T255 |
1 |
|
T304 |
1 |
|
T384 |
1 |
Summary for Cross sideload_clear_x_sl_avail_cross
Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
40 |
19 |
21 |
52.50 |
19 |
Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross
Element holes
sideload_clear_cp | aes_sl_avail | kmac_sl_avail | otbn_sl_avail | COUNT | AT LEAST | NUMBER | STATUS |
[clear_all] |
[auto[0]] |
[auto[1]] |
* |
-- |
-- |
2 |
|
[clear_all] |
[auto[1]] |
* |
* |
-- |
-- |
4 |
|
[clear_one[1]] |
[auto[1]] |
* |
* |
-- |
-- |
4 |
|
[clear_one[2]] |
* |
[auto[1]] |
* |
-- |
-- |
4 |
|
[clear_one[3]] |
* |
* |
[auto[1]] |
-- |
-- |
4 |
|
Uncovered bins
sideload_clear_cp | aes_sl_avail | kmac_sl_avail | otbn_sl_avail | COUNT | AT LEAST | NUMBER | STATUS |
[clear_all] |
[auto[0]] |
[auto[0]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
sideload_clear_cp | aes_sl_avail | kmac_sl_avail | otbn_sl_avail | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
clear_all |
auto[0] |
auto[0] |
auto[0] |
1408 |
1 |
|
|
T1 |
1 |
|
T15 |
2 |
|
T17 |
1 |
clear_one[1] |
auto[0] |
auto[0] |
auto[0] |
400 |
1 |
|
|
T4 |
1 |
|
T17 |
1 |
|
T18 |
1 |
clear_one[1] |
auto[0] |
auto[0] |
auto[1] |
128 |
1 |
|
|
T1 |
3 |
|
T15 |
3 |
|
T5 |
1 |
clear_one[1] |
auto[0] |
auto[1] |
auto[0] |
124 |
1 |
|
|
T39 |
1 |
|
T90 |
1 |
|
T214 |
1 |
clear_one[1] |
auto[0] |
auto[1] |
auto[1] |
44 |
1 |
|
|
T7 |
1 |
|
T74 |
1 |
|
T217 |
1 |
clear_one[2] |
auto[0] |
auto[0] |
auto[0] |
381 |
1 |
|
|
T17 |
1 |
|
T5 |
1 |
|
T18 |
2 |
clear_one[2] |
auto[0] |
auto[0] |
auto[1] |
100 |
1 |
|
|
T15 |
1 |
|
T164 |
2 |
|
T28 |
2 |
clear_one[2] |
auto[1] |
auto[0] |
auto[0] |
98 |
1 |
|
|
T47 |
1 |
|
T94 |
3 |
|
T215 |
1 |
clear_one[2] |
auto[1] |
auto[0] |
auto[1] |
49 |
1 |
|
|
T28 |
4 |
|
T6 |
1 |
|
T212 |
1 |
clear_one[3] |
auto[0] |
auto[0] |
auto[0] |
366 |
1 |
|
|
T1 |
4 |
|
T15 |
3 |
|
T164 |
1 |
clear_one[3] |
auto[0] |
auto[1] |
auto[0] |
131 |
1 |
|
|
T36 |
1 |
|
T38 |
1 |
|
T39 |
2 |
clear_one[3] |
auto[1] |
auto[0] |
auto[0] |
124 |
1 |
|
|
T47 |
1 |
|
T89 |
1 |
|
T94 |
2 |
clear_one[3] |
auto[1] |
auto[1] |
auto[0] |
42 |
1 |
|
|
T46 |
1 |
|
T28 |
1 |
|
T144 |
1 |
clear_none |
auto[0] |
auto[0] |
auto[0] |
1304 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T15 |
1 |
clear_none |
auto[0] |
auto[0] |
auto[1] |
123 |
1 |
|
|
T15 |
1 |
|
T46 |
1 |
|
T28 |
2 |
clear_none |
auto[0] |
auto[1] |
auto[0] |
121 |
1 |
|
|
T38 |
3 |
|
T97 |
2 |
|
T28 |
1 |
clear_none |
auto[0] |
auto[1] |
auto[1] |
27 |
1 |
|
|
T226 |
1 |
|
T242 |
1 |
|
T307 |
3 |
clear_none |
auto[1] |
auto[0] |
auto[0] |
139 |
1 |
|
|
T47 |
1 |
|
T94 |
1 |
|
T145 |
1 |
clear_none |
auto[1] |
auto[0] |
auto[1] |
30 |
1 |
|
|
T6 |
1 |
|
T249 |
1 |
|
T130 |
2 |
clear_none |
auto[1] |
auto[1] |
auto[0] |
45 |
1 |
|
|
T28 |
2 |
|
T7 |
1 |
|
T149 |
1 |
clear_none |
auto[1] |
auto[1] |
auto[1] |
25 |
1 |
|
|
T144 |
1 |
|
T270 |
1 |
|
T387 |
1 |
Summary for Cross sideload_clear_x_regwen_cross
Samples crossed: sideload_clear_cp regwen_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
10 |
0 |
10 |
100.00 |
|
Automatically Generated Cross Bins for sideload_clear_x_regwen_cross
Bins
sideload_clear_cp | regwen_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
clear_all |
auto[0] |
1328 |
1 |
|
|
T1 |
1 |
|
T15 |
2 |
|
T17 |
1 |
clear_all |
auto[1] |
80 |
1 |
|
|
T130 |
7 |
|
T380 |
1 |
|
T299 |
2 |
clear_one[1] |
auto[0] |
653 |
1 |
|
|
T1 |
3 |
|
T4 |
1 |
|
T15 |
3 |
clear_one[1] |
auto[1] |
43 |
1 |
|
|
T151 |
2 |
|
T152 |
5 |
|
T380 |
1 |
clear_one[2] |
auto[0] |
593 |
1 |
|
|
T15 |
1 |
|
T17 |
1 |
|
T5 |
1 |
clear_one[2] |
auto[1] |
35 |
1 |
|
|
T130 |
5 |
|
T151 |
1 |
|
T280 |
1 |
clear_one[3] |
auto[0] |
630 |
1 |
|
|
T1 |
4 |
|
T15 |
3 |
|
T36 |
1 |
clear_one[3] |
auto[1] |
33 |
1 |
|
|
T152 |
2 |
|
T153 |
4 |
|
T283 |
4 |
clear_none |
auto[0] |
1713 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T15 |
2 |
clear_none |
auto[1] |
101 |
1 |
|
|
T130 |
3 |
|
T151 |
1 |
|
T152 |
1 |