Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10571

1

T1

8

T2

4

T4

14

auto[Attestation]

7205

1

T1

4

T2

6

T4

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2605	1			T2	2		T4	2		T5	2
auto[Aes]	3194	1			T2	2		T4	3		T5	1
auto[Kmac]	3232	1			T2	1		T4	6		T5	2
auto[Otbn]	3278	1			T1	12		T2	1		T4	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7372	1			T1	8		T2	3		T4	3
auto[OpGenId]	5467	1			T2	4		T4	6		T5	11
auto[OpGenSwOut]	5560	1			T2	4		T4	4		T5	3
auto[OpGenHwOut]	6749	1			T1	12		T2	2		T4	9
auto[OpDisable]	145	1			T28	3		T51	1		T52	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10212

1

T1

8

T2

11

T4

13

auto[OpDoneFail]

15081

1

T1

12

T2

2

T4

9

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5980	1			T1	5		T2	2		T4	9
auto[StInit]	3616	1			T1	2		T2	2		T4	2
auto[StCreatorRootKey]	3096	1			T1	2		T2	5		T4	5
auto[StOwnerIntKey]	2650	1			T1	2		T2	4		T4	6
auto[StOwnerKey]	2332	1			T1	2		T15	2		T5	6
auto[StDisabled]	7619	1			T1	7		T15	7		T5	9

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	304	1			T46	1		T59	2		T28	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	95	1			T28	3		T149	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T28	3		T6	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	61	1			T2	1		T37	1		T92	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	65	1			T28	1		T6	1		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	228	1			T28	3		T92	1		T95	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	307	1			T46	1		T164	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	104	1			T36	1		T28	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	64	1			T211	1		T213	1		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	62	1			T28	1		T89	1		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	71	1			T28	1		T223	1		T113	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	204	1			T28	2		T89	3		T51	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	305	1			T4	1		T59	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	90	1			T28	2		T92	1		T25	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T4	1		T37	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	73	1			T36	1		T28	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	50	1			T36	1		T37	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	214	1			T28	6		T93	1		T224	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	312	1			T4	1		T18	1		T37	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	87	1			T212	1		T60	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	72	1			T36	1		T28	2		T51	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T5	1		T164	1		T89	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	56	1			T36	1		T28	1		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	214	1			T5	1		T28	2		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	72	1			T28	3		T60	3		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	99	1			T28	1		T44	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	82	1			T25	1		T51	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	67	1			T2	1		T28	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T37	1		T28	4		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	203	1			T28	9		T93	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	51	1			T28	4		T113	1		T64	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	101	1			T224	1		T51	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	70	1			T2	1		T59	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	77	1			T2	1		T164	1		T28	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	61	1			T28	1		T7	1		T144	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	205	1			T46	1		T28	3		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	76	1			T28	4		T60	2		T124	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	116	1			T37	1		T164	1		T28	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T4	1		T28	3		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	70	1			T164	1		T28	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	46	1			T164	1		T28	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	173	1			T5	1		T28	3		T93	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	73	1			T28	4		T51	1		T60	6
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	83	1			T57	1		T70	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T96	1		T28	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T36	1		T164	1		T28	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	60	1			T28	1		T26	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	208	1			T28	6		T93	1		T95	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	246	1			T4	1		T18	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T57	1		T28	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	74	1			T28	1		T6	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T28	2		T70	1		T89	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	44	1			T5	1		T37	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	162	1			T5	1		T28	5		T93	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	429	1			T4	1		T18	2		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	107	1			T28	1		T94	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T47	1		T28	1		T94	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	100	1			T4	1		T46	1		T28	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T5	1		T94	1		T51	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	283	1			T46	1		T96	1		T47	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	468	1			T38	7		T164	2		T89	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	103	1			T5	1		T28	2		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T38	1		T97	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	99	1			T4	2		T39	1		T97	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	79	1			T36	1		T38	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	279	1			T38	3		T39	1		T28	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	474	1			T1	4		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	109	1			T57	1		T28	2		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T1	1		T164	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T1	1		T15	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	88	1			T36	2		T46	1		T164	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	285	1			T1	2		T15	2		T28	7
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T28	4		T60	1		T124	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	110	1			T28	1		T89	1		T25	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T4	1		T36	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	62	1			T36	1		T37	1		T28	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	38	1			T25	1		T146	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	172	1			T28	9		T51	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	49	1			T28	4		T51	1		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	111	1			T46	1		T47	1		T28	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	114	1			T28	1		T89	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	88	1			T4	1		T47	1		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	86	1			T36	1		T47	1		T164	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	262	1			T96	1		T47	1		T28	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	53	1			T28	9		T124	1		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	127	1			T36	1		T38	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T39	1		T28	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T2	1		T4	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	80	1			T36	1		T97	1		T164	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	267	1			T38	1		T39	3		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	48	1			T28	5		T60	1		T124	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	116	1			T1	1		T15	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T15	1		T28	3		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T28	2		T91	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	76	1			T1	1		T15	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	286	1			T1	2		T15	2		T5	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	187	1			T2	1		T37	1		T28	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	645	1			T46	1		T59	2		T28	9
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	187	1			T28	2		T89	1		T211	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	625	1			T36	1		T46	1		T164	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	199	1			T4	1		T36	2		T37	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	617	1			T4	1		T59	1		T28	9
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	181	1			T36	2		T164	1		T28	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	625	1			T4	1		T5	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	186	1			T2	1		T37	1		T28	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	391	1			T28	13		T93	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	193	1			T2	2		T164	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	372	1			T46	1		T28	8		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	181	1			T4	1		T164	2		T28	6
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	383	1			T5	1		T37	1		T164	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	207	1			T36	1		T96	1		T164	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	381	1			T57	1		T28	11		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	163	1			T5	1		T37	1		T28	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	523	1			T4	1		T5	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	274	1			T4	1		T46	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	833	1			T4	1		T5	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T4	2		T36	1		T38	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	864	1			T5	1		T38	10		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	284	1			T1	2		T15	1		T36	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	883	1			T1	6		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	148	1			T4	1		T36	2		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	362	1			T28	14		T89	1		T25	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	269	1			T4	1		T36	1		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	441	1			T46	1		T96	1		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	250	1			T2	1		T4	1		T36	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	461	1			T36	1		T38	2		T39	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	256	1			T1	1		T15	2		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	461	1			T1	3		T15	3		T5	1