Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31178

1

T1

25

T2

14

T4

22

auto[1]

288

1

T130

10

T150

1

T151

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31185	1			T1	25		T2	14		T4	22
auto[134217728:268435455]	8	1			T299	1		T379	1		T297	2
auto[268435456:402653183]	7	1			T151	2		T153	1		T283	1
auto[402653184:536870911]	3	1			T408	1		T409	1		T410	1
auto[536870912:671088639]	7	1			T283	1		T155	1		T393	1
auto[671088640:805306367]	9	1			T130	1		T299	1		T411	1
auto[805306368:939524095]	10	1			T130	1		T299	1		T252	1
auto[939524096:1073741823]	13	1			T130	1		T151	1		T283	1
auto[1073741824:1207959551]	9	1			T152	1		T153	1		T283	1
auto[1207959552:1342177279]	16	1			T153	1		T283	2		T380	1
auto[1342177280:1476395007]	9	1			T152	1		T153	1		T155	1
auto[1476395008:1610612735]	4	1			T299	1		T115	1		T412	1
auto[1610612736:1744830463]	17	1			T130	1		T151	2		T283	1
auto[1744830464:1879048191]	7	1			T411	1		T413	1		T412	1
auto[1879048192:2013265919]	8	1			T151	1		T283	1		T380	1
auto[2013265920:2147483647]	7	1			T130	1		T380	1		T338	1
auto[2147483648:2281701375]	7	1			T151	1		T283	1		T335	1
auto[2281701376:2415919103]	10	1			T130	1		T380	1		T307	2
auto[2415919104:2550136831]	11	1			T150	1		T380	1		T299	1
auto[2550136832:2684354559]	5	1			T338	1		T394	1		T414	1
auto[2684354560:2818572287]	16	1			T283	1		T307	2		T411	1
auto[2818572288:2952790015]	8	1			T130	1		T280	1		T411	1
auto[2952790016:3087007743]	9	1			T394	1		T414	1		T412	1
auto[3087007744:3221225471]	14	1			T130	2		T151	1		T307	1
auto[3221225472:3355443199]	8	1			T283	1		T260	1		T414	1
auto[3355443200:3489660927]	9	1			T130	1		T380	1		T155	1
auto[3489660928:3623878655]	8	1			T260	1		T395	1		T115	2
auto[3623878656:3758096383]	7	1			T252	1		T393	1		T395	1
auto[3758096384:3892314111]	9	1			T411	1		T415	1		T394	1
auto[3892314112:4026531839]	10	1			T299	1		T297	1		T338	1
auto[4026531840:4160749567]	5	1			T338	1		T115	1		T308	1
auto[4160749568:4294967295]	11	1			T380	1		T155	1		T297	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31178	1			T1	25		T2	14		T4	22
auto[0:134217727]	auto[1]	7	1			T153	1		T283	1		T411	1
auto[134217728:268435455]	auto[1]	8	1			T299	1		T379	1		T297	2
auto[268435456:402653183]	auto[1]	7	1			T151	2		T153	1		T283	1
auto[402653184:536870911]	auto[1]	3	1			T408	1		T409	1		T410	1
auto[536870912:671088639]	auto[1]	7	1			T283	1		T155	1		T393	1
auto[671088640:805306367]	auto[1]	9	1			T130	1		T299	1		T411	1
auto[805306368:939524095]	auto[1]	10	1			T130	1		T299	1		T252	1
auto[939524096:1073741823]	auto[1]	13	1			T130	1		T151	1		T283	1
auto[1073741824:1207959551]	auto[1]	9	1			T152	1		T153	1		T283	1
auto[1207959552:1342177279]	auto[1]	16	1			T153	1		T283	2		T380	1
auto[1342177280:1476395007]	auto[1]	9	1			T152	1		T153	1		T155	1
auto[1476395008:1610612735]	auto[1]	4	1			T299	1		T115	1		T412	1
auto[1610612736:1744830463]	auto[1]	17	1			T130	1		T151	2		T283	1
auto[1744830464:1879048191]	auto[1]	7	1			T411	1		T413	1		T412	1
auto[1879048192:2013265919]	auto[1]	8	1			T151	1		T283	1		T380	1
auto[2013265920:2147483647]	auto[1]	7	1			T130	1		T380	1		T338	1
auto[2147483648:2281701375]	auto[1]	7	1			T151	1		T283	1		T335	1
auto[2281701376:2415919103]	auto[1]	10	1			T130	1		T380	1		T307	2
auto[2415919104:2550136831]	auto[1]	11	1			T150	1		T380	1		T299	1
auto[2550136832:2684354559]	auto[1]	5	1			T338	1		T394	1		T414	1
auto[2684354560:2818572287]	auto[1]	16	1			T283	1		T307	2		T411	1
auto[2818572288:2952790015]	auto[1]	8	1			T130	1		T280	1		T411	1
auto[2952790016:3087007743]	auto[1]	9	1			T394	1		T414	1		T412	1
auto[3087007744:3221225471]	auto[1]	14	1			T130	2		T151	1		T307	1
auto[3221225472:3355443199]	auto[1]	8	1			T283	1		T260	1		T414	1
auto[3355443200:3489660927]	auto[1]	9	1			T130	1		T380	1		T155	1
auto[3489660928:3623878655]	auto[1]	8	1			T260	1		T395	1		T115	2
auto[3623878656:3758096383]	auto[1]	7	1			T252	1		T393	1		T395	1
auto[3758096384:3892314111]	auto[1]	9	1			T411	1		T415	1		T394	1
auto[3892314112:4026531839]	auto[1]	10	1			T299	1		T297	1		T338	1
auto[4026531840:4160749567]	auto[1]	5	1			T338	1		T115	1		T308	1
auto[4160749568:4294967295]	auto[1]	11	1			T380	1		T155	1		T297	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1413

1

T4

3

T17

4

T5

2

auto[1]

1661

1

T4

1

T17

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T18	1		T164	1		T28	1
auto[134217728:268435455]	92	1			T17	1		T28	3		T70	1
auto[268435456:402653183]	90	1			T4	1		T59	2		T19	1
auto[402653184:536870911]	88	1			T17	1		T18	1		T57	1
auto[536870912:671088639]	94	1			T40	1		T28	1		T6	1
auto[671088640:805306367]	91	1			T28	1		T51	1		T53	1
auto[805306368:939524095]	86	1			T17	1		T6	1		T93	1
auto[939524096:1073741823]	87	1			T28	1		T93	1		T212	1
auto[1073741824:1207959551]	114	1			T164	1		T59	1		T28	3
auto[1207959552:1342177279]	93	1			T4	1		T17	1		T28	1
auto[1342177280:1476395007]	94	1			T28	1		T51	2		T53	1
auto[1476395008:1610612735]	99	1			T28	1		T25	1		T212	1
auto[1610612736:1744830463]	99	1			T18	1		T28	1		T214	1
auto[1744830464:1879048191]	104	1			T59	1		T28	5		T6	1
auto[1879048192:2013265919]	90	1			T57	1		T28	1		T89	1
auto[2013265920:2147483647]	113	1			T5	1		T57	1		T28	3
auto[2147483648:2281701375]	112	1			T57	1		T28	7		T89	2
auto[2281701376:2415919103]	90	1			T28	2		T70	1		T213	1
auto[2415919104:2550136831]	98	1			T5	1		T28	2		T51	1
auto[2550136832:2684354559]	112	1			T4	1		T59	1		T28	5
auto[2684354560:2818572287]	97	1			T17	1		T5	1		T89	1
auto[2818572288:2952790015]	99	1			T53	1		T7	1		T60	2
auto[2952790016:3087007743]	79	1			T164	1		T28	1		T25	1
auto[3087007744:3221225471]	101	1			T28	5		T70	1		T144	1
auto[3221225472:3355443199]	92	1			T28	1		T6	1		T75	1
auto[3355443200:3489660927]	86	1			T28	4		T6	1		T48	1
auto[3489660928:3623878655]	79	1			T28	1		T75	1		T60	1
auto[3623878656:3758096383]	98	1			T28	1		T70	1		T51	2
auto[3758096384:3892314111]	99	1			T164	1		T28	1		T89	1
auto[3892314112:4026531839]	105	1			T4	1		T28	1		T25	1
auto[4026531840:4160749567]	113	1			T36	1		T28	2		T51	1
auto[4160749568:4294967295]	92	1			T18	1		T58	1		T7	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	39	1			T70	1		T223	1		T78	2
auto[0:134217727]	auto[1]	49	1			T18	1		T164	1		T28	1
auto[134217728:268435455]	auto[0]	41	1			T17	1		T28	2		T70	1
auto[134217728:268435455]	auto[1]	51	1			T28	1		T8	1		T250	1
auto[268435456:402653183]	auto[0]	37	1			T4	1		T59	2		T212	1
auto[268435456:402653183]	auto[1]	53	1			T19	1		T7	1		T60	1
auto[402653184:536870911]	auto[0]	43	1			T17	1		T18	1		T57	1
auto[402653184:536870911]	auto[1]	45	1			T28	2		T51	1		T60	1
auto[536870912:671088639]	auto[0]	47	1			T51	1		T223	1		T64	1
auto[536870912:671088639]	auto[1]	47	1			T40	1		T28	1		T6	1
auto[671088640:805306367]	auto[0]	37	1			T249	1		T313	1		T343	1
auto[671088640:805306367]	auto[1]	54	1			T28	1		T51	1		T53	1
auto[805306368:939524095]	auto[0]	43	1			T17	1		T64	1		T270	1
auto[805306368:939524095]	auto[1]	43	1			T6	1		T93	1		T211	1
auto[939524096:1073741823]	auto[0]	45	1			T28	1		T58	1		T416	1
auto[939524096:1073741823]	auto[1]	42	1			T93	1		T212	1		T61	1
auto[1073741824:1207959551]	auto[0]	55	1			T164	1		T59	1		T28	3
auto[1073741824:1207959551]	auto[1]	59	1			T51	1		T53	1		T64	1
auto[1207959552:1342177279]	auto[0]	44	1			T4	1		T17	1		T28	1
auto[1207959552:1342177279]	auto[1]	49	1			T89	2		T58	1		T52	1
auto[1342177280:1476395007]	auto[0]	47	1			T51	2		T53	1		T66	1
auto[1342177280:1476395007]	auto[1]	47	1			T28	1		T113	1		T54	1
auto[1476395008:1610612735]	auto[0]	39	1			T28	1		T25	1		T214	1
auto[1476395008:1610612735]	auto[1]	60	1			T212	1		T60	1		T144	1
auto[1610612736:1744830463]	auto[0]	39	1			T28	1		T66	1		T64	1
auto[1610612736:1744830463]	auto[1]	60	1			T18	1		T214	1		T60	1
auto[1744830464:1879048191]	auto[0]	47	1			T59	1		T28	1		T51	1
auto[1744830464:1879048191]	auto[1]	57	1			T28	4		T6	1		T147	1
auto[1879048192:2013265919]	auto[0]	41	1			T28	1		T89	1		T93	1
auto[1879048192:2013265919]	auto[1]	49	1			T57	1		T26	1		T64	1
auto[2013265920:2147483647]	auto[0]	48	1			T5	1		T28	2		T70	1
auto[2013265920:2147483647]	auto[1]	65	1			T57	1		T28	1		T93	1
auto[2147483648:2281701375]	auto[0]	62	1			T57	1		T28	2		T89	1
auto[2147483648:2281701375]	auto[1]	50	1			T28	5		T89	1		T51	1
auto[2281701376:2415919103]	auto[0]	43	1			T28	1		T70	1		T58	1
auto[2281701376:2415919103]	auto[1]	47	1			T28	1		T213	1		T113	1
auto[2415919104:2550136831]	auto[0]	48	1			T5	1		T28	2		T51	1
auto[2415919104:2550136831]	auto[1]	50	1			T212	1		T213	1		T74	1
auto[2550136832:2684354559]	auto[0]	53	1			T4	1		T59	1		T28	3
auto[2550136832:2684354559]	auto[1]	59	1			T28	2		T52	1		T7	1
auto[2684354560:2818572287]	auto[0]	44	1			T64	1		T102	1		T50	1
auto[2684354560:2818572287]	auto[1]	53	1			T17	1		T5	1		T89	1
auto[2818572288:2952790015]	auto[0]	37	1			T7	1		T60	2		T130	1
auto[2818572288:2952790015]	auto[1]	62	1			T53	1		T74	1		T65	1
auto[2952790016:3087007743]	auto[0]	43	1			T51	3		T60	1		T61	1
auto[2952790016:3087007743]	auto[1]	36	1			T164	1		T28	1		T25	1
auto[3087007744:3221225471]	auto[0]	39	1			T28	1		T144	1		T48	1
auto[3087007744:3221225471]	auto[1]	62	1			T28	4		T70	1		T48	1
auto[3221225472:3355443199]	auto[0]	49	1			T6	1		T60	1		T149	1
auto[3221225472:3355443199]	auto[1]	43	1			T28	1		T75	1		T52	1
auto[3355443200:3489660927]	auto[0]	39	1			T28	2		T6	1		T151	1
auto[3355443200:3489660927]	auto[1]	47	1			T28	2		T48	1		T249	1
auto[3489660928:3623878655]	auto[0]	34	1			T60	1		T249	1		T20	1
auto[3489660928:3623878655]	auto[1]	45	1			T28	1		T75	1		T74	1
auto[3623878656:3758096383]	auto[0]	43	1			T28	1		T70	1		T51	1
auto[3623878656:3758096383]	auto[1]	55	1			T51	1		T214	1		T60	1
auto[3758096384:3892314111]	auto[0]	44	1			T60	1		T20	1		T74	1
auto[3758096384:3892314111]	auto[1]	55	1			T164	1		T28	1		T89	1
auto[3892314112:4026531839]	auto[0]	47	1			T51	1		T75	1		T211	1
auto[3892314112:4026531839]	auto[1]	58	1			T4	1		T28	1		T25	1
auto[4026531840:4160749567]	auto[0]	54	1			T28	1		T147	1		T8	1
auto[4026531840:4160749567]	auto[1]	59	1			T36	1		T28	1		T51	1
auto[4160749568:4294967295]	auto[0]	42	1			T18	1		T58	1		T7	1
auto[4160749568:4294967295]	auto[1]	50	1			T149	1		T74	1		T104	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1389

1

T4

2

T17

3

T18

2

auto[1]

1684

1

T4

2

T17

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T28	3		T70	1		T89	1
auto[134217728:268435455]	81	1			T28	4		T89	1		T147	1
auto[268435456:402653183]	99	1			T17	1		T59	2		T89	1
auto[402653184:536870911]	97	1			T28	5		T89	1		T6	2
auto[536870912:671088639]	101	1			T18	1		T59	1		T28	2
auto[671088640:805306367]	91	1			T28	4		T51	2		T416	1
auto[805306368:939524095]	99	1			T4	1		T17	1		T40	1
auto[939524096:1073741823]	100	1			T28	1		T51	1		T75	1
auto[1073741824:1207959551]	101	1			T17	1		T5	1		T36	1
auto[1207959552:1342177279]	84	1			T164	1		T70	1		T51	1
auto[1342177280:1476395007]	111	1			T5	1		T164	2		T70	1
auto[1476395008:1610612735]	98	1			T17	1		T28	1		T93	1
auto[1610612736:1744830463]	92	1			T89	1		T6	1		T25	1
auto[1744830464:1879048191]	88	1			T28	1		T60	1		T48	1
auto[1879048192:2013265919]	109	1			T18	1		T28	2		T70	2
auto[2013265920:2147483647]	96	1			T17	1		T75	1		T7	1
auto[2147483648:2281701375]	91	1			T57	1		T28	4		T89	1
auto[2281701376:2415919103]	78	1			T4	1		T57	1		T28	2
auto[2415919104:2550136831]	110	1			T18	1		T28	3		T6	1
auto[2550136832:2684354559]	103	1			T4	1		T28	4		T93	1
auto[2684354560:2818572287]	106	1			T5	1		T28	2		T51	2
auto[2818572288:2952790015]	87	1			T28	1		T51	1		T214	1
auto[2952790016:3087007743]	107	1			T18	1		T28	2		T51	2
auto[3087007744:3221225471]	100	1			T57	1		T28	2		T25	1
auto[3221225472:3355443199]	96	1			T59	1		T28	1		T48	1
auto[3355443200:3489660927]	100	1			T28	1		T19	1		T51	2
auto[3489660928:3623878655]	100	1			T28	1		T70	1		T51	1
auto[3623878656:3758096383]	100	1			T6	1		T51	1		T53	1
auto[3758096384:3892314111]	89	1			T59	1		T28	4		T58	1
auto[3892314112:4026531839]	87	1			T4	1		T25	1		T213	1
auto[4026531840:4160749567]	86	1			T164	1		T28	2		T51	2
auto[4160749568:4294967295]	98	1			T28	3		T6	1		T51	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T28	1		T70	1		T89	1
auto[0:134217727]	auto[1]	45	1			T28	2		T93	1		T64	1
auto[134217728:268435455]	auto[0]	35	1			T28	1		T223	1		T64	2
auto[134217728:268435455]	auto[1]	46	1			T28	3		T89	1		T147	1
auto[268435456:402653183]	auto[0]	51	1			T59	2		T89	1		T75	1
auto[268435456:402653183]	auto[1]	48	1			T17	1		T26	1		T74	1
auto[402653184:536870911]	auto[0]	41	1			T28	2		T89	1		T6	1
auto[402653184:536870911]	auto[1]	56	1			T28	3		T6	1		T93	1
auto[536870912:671088639]	auto[0]	52	1			T18	1		T59	1		T28	1
auto[536870912:671088639]	auto[1]	49	1			T28	1		T211	1		T60	1
auto[671088640:805306367]	auto[0]	41	1			T28	1		T51	1		T416	1
auto[671088640:805306367]	auto[1]	50	1			T28	3		T51	1		T53	1
auto[805306368:939524095]	auto[0]	41	1			T17	1		T28	1		T130	1
auto[805306368:939524095]	auto[1]	58	1			T4	1		T40	1		T57	1
auto[939524096:1073741823]	auto[0]	52	1			T28	1		T75	1		T53	1
auto[939524096:1073741823]	auto[1]	48	1			T51	1		T213	1		T52	1
auto[1073741824:1207959551]	auto[0]	55	1			T17	1		T36	1		T28	1
auto[1073741824:1207959551]	auto[1]	46	1			T5	1		T75	1		T113	1
auto[1207959552:1342177279]	auto[0]	31	1			T70	1		T58	1		T65	1
auto[1207959552:1342177279]	auto[1]	53	1			T164	1		T51	1		T416	1
auto[1342177280:1476395007]	auto[0]	47	1			T70	1		T51	1		T249	1
auto[1342177280:1476395007]	auto[1]	64	1			T5	1		T164	2		T60	2
auto[1476395008:1610612735]	auto[0]	47	1			T17	1		T58	1		T249	1
auto[1476395008:1610612735]	auto[1]	51	1			T28	1		T93	1		T212	1
auto[1610612736:1744830463]	auto[0]	44	1			T6	1		T25	1		T51	1
auto[1610612736:1744830463]	auto[1]	48	1			T89	1		T52	1		T53	1
auto[1744830464:1879048191]	auto[0]	45	1			T28	1		T48	1		T20	1
auto[1744830464:1879048191]	auto[1]	43	1			T60	1		T149	1		T73	1
auto[1879048192:2013265919]	auto[0]	44	1			T18	1		T28	1		T52	1
auto[1879048192:2013265919]	auto[1]	65	1			T28	1		T70	2		T51	2
auto[2013265920:2147483647]	auto[0]	46	1			T7	1		T60	1		T64	1
auto[2013265920:2147483647]	auto[1]	50	1			T17	1		T75	1		T64	3
auto[2147483648:2281701375]	auto[0]	41	1			T28	2		T64	2		T151	1
auto[2147483648:2281701375]	auto[1]	50	1			T57	1		T28	2		T89	1
auto[2281701376:2415919103]	auto[0]	24	1			T57	1		T66	1		T74	1
auto[2281701376:2415919103]	auto[1]	54	1			T4	1		T28	2		T51	1
auto[2415919104:2550136831]	auto[0]	42	1			T51	1		T64	1		T54	1
auto[2415919104:2550136831]	auto[1]	68	1			T18	1		T28	3		T6	1
auto[2550136832:2684354559]	auto[0]	44	1			T4	1		T28	2		T7	1
auto[2550136832:2684354559]	auto[1]	59	1			T28	2		T93	1		T7	1
auto[2684354560:2818572287]	auto[0]	48	1			T28	1		T51	1		T60	2
auto[2684354560:2818572287]	auto[1]	58	1			T5	1		T28	1		T51	1
auto[2818572288:2952790015]	auto[0]	40	1			T214	1		T58	1		T147	1
auto[2818572288:2952790015]	auto[1]	47	1			T28	1		T51	1		T124	1
auto[2952790016:3087007743]	auto[0]	49	1			T51	2		T54	2		T29	1
auto[2952790016:3087007743]	auto[1]	58	1			T18	1		T28	2		T7	1
auto[3087007744:3221225471]	auto[0]	45	1			T57	1		T28	2		T25	1
auto[3087007744:3221225471]	auto[1]	55	1			T60	1		T144	1		T61	1
auto[3221225472:3355443199]	auto[0]	36	1			T59	1		T28	1		T149	2
auto[3221225472:3355443199]	auto[1]	60	1			T48	1		T223	1		T64	1
auto[3355443200:3489660927]	auto[0]	43	1			T51	1		T213	1		T61	1
auto[3355443200:3489660927]	auto[1]	57	1			T28	1		T19	1		T51	1
auto[3489660928:3623878655]	auto[0]	48	1			T70	1		T51	1		T211	1
auto[3489660928:3623878655]	auto[1]	52	1			T28	1		T75	1		T113	1
auto[3623878656:3758096383]	auto[0]	51	1			T21	1		T54	1		T29	1
auto[3623878656:3758096383]	auto[1]	49	1			T6	1		T51	1		T53	1
auto[3758096384:3892314111]	auto[0]	38	1			T59	1		T28	1		T270	1
auto[3758096384:3892314111]	auto[1]	51	1			T28	3		T58	1		T52	1
auto[3892314112:4026531839]	auto[0]	37	1			T4	1		T25	1		T217	1
auto[3892314112:4026531839]	auto[1]	50	1			T213	1		T214	1		T149	1
auto[4026531840:4160749567]	auto[0]	45	1			T51	2		T48	1		T149	1
auto[4026531840:4160749567]	auto[1]	41	1			T164	1		T28	2		T212	1
auto[4160749568:4294967295]	auto[0]	43	1			T28	2		T51	1		T20	1
auto[4160749568:4294967295]	auto[1]	55	1			T28	1		T6	1		T53	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1366

1

T4

3

T17

4

T5

1

auto[1]

1707

1

T4

1

T17

1

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T89	1		T19	1		T51	1
auto[134217728:268435455]	78	1			T28	1		T93	1		T147	1
auto[268435456:402653183]	105	1			T40	1		T28	1		T53	1
auto[402653184:536870911]	95	1			T57	1		T164	1		T28	1
auto[536870912:671088639]	107	1			T164	1		T59	1		T28	3
auto[671088640:805306367]	91	1			T59	1		T28	2		T25	1
auto[805306368:939524095]	91	1			T18	1		T28	1		T51	3
auto[939524096:1073741823]	92	1			T28	1		T75	1		T60	1
auto[1073741824:1207959551]	94	1			T4	1		T17	1		T28	3
auto[1207959552:1342177279]	97	1			T4	1		T59	1		T28	2
auto[1342177280:1476395007]	101	1			T28	3		T70	1		T58	1
auto[1476395008:1610612735]	101	1			T17	1		T28	3		T70	1
auto[1610612736:1744830463]	99	1			T57	1		T28	1		T51	1
auto[1744830464:1879048191]	101	1			T17	1		T28	2		T51	1
auto[1879048192:2013265919]	99	1			T36	1		T59	1		T28	3
auto[2013265920:2147483647]	91	1			T93	1		T51	1		T213	1
auto[2147483648:2281701375]	92	1			T28	2		T93	1		T212	1
auto[2281701376:2415919103]	77	1			T18	1		T59	1		T28	1
auto[2415919104:2550136831]	94	1			T57	1		T28	2		T89	1
auto[2550136832:2684354559]	109	1			T28	3		T70	1		T51	1
auto[2684354560:2818572287]	93	1			T4	1		T28	3		T51	1
auto[2818572288:2952790015]	114	1			T17	1		T28	3		T89	1
auto[2952790016:3087007743]	95	1			T28	2		T89	1		T6	2
auto[3087007744:3221225471]	104	1			T28	1		T93	1		T58	2
auto[3221225472:3355443199]	91	1			T28	1		T58	1		T416	1
auto[3355443200:3489660927]	98	1			T5	2		T57	1		T28	2
auto[3489660928:3623878655]	110	1			T18	1		T28	2		T51	1
auto[3623878656:3758096383]	102	1			T18	1		T164	1		T28	1
auto[3758096384:3892314111]	93	1			T4	1		T28	1		T51	2
auto[3892314112:4026531839]	93	1			T164	1		T28	2		T89	1
auto[4026531840:4160749567]	96	1			T28	2		T70	1		T51	1
auto[4160749568:4294967295]	73	1			T17	1		T5	1		T28	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	35	1			T51	1		T7	1		T48	1
auto[0:134217727]	auto[1]	62	1			T89	1		T19	1		T75	1
auto[134217728:268435455]	auto[0]	38	1			T8	1		T61	1		T310	1
auto[134217728:268435455]	auto[1]	40	1			T28	1		T93	1		T147	1
auto[268435456:402653183]	auto[0]	48	1			T28	1		T53	1		T250	1
auto[268435456:402653183]	auto[1]	57	1			T40	1		T104	1		T73	1
auto[402653184:536870911]	auto[0]	38	1			T57	1		T164	1		T28	1
auto[402653184:536870911]	auto[1]	57	1			T75	1		T60	2		T149	1
auto[536870912:671088639]	auto[0]	53	1			T59	1		T28	2		T89	1
auto[536870912:671088639]	auto[1]	54	1			T164	1		T28	1		T25	1
auto[671088640:805306367]	auto[0]	40	1			T59	1		T8	1		T223	1
auto[671088640:805306367]	auto[1]	51	1			T28	2		T25	1		T52	1
auto[805306368:939524095]	auto[0]	38	1			T20	1		T130	1		T65	1
auto[805306368:939524095]	auto[1]	53	1			T18	1		T28	1		T51	3
auto[939524096:1073741823]	auto[0]	36	1			T152	1		T68	1		T417	1
auto[939524096:1073741823]	auto[1]	56	1			T28	1		T75	1		T60	1
auto[1073741824:1207959551]	auto[0]	37	1			T17	1		T28	1		T249	1
auto[1073741824:1207959551]	auto[1]	57	1			T4	1		T28	2		T6	1
auto[1207959552:1342177279]	auto[0]	48	1			T4	1		T59	1		T28	2
auto[1207959552:1342177279]	auto[1]	49	1			T124	1		T113	3		T65	1
auto[1342177280:1476395007]	auto[0]	49	1			T28	2		T70	1		T58	1
auto[1342177280:1476395007]	auto[1]	52	1			T28	1		T113	2		T65	1
auto[1476395008:1610612735]	auto[0]	42	1			T17	1		T28	1		T70	1
auto[1476395008:1610612735]	auto[1]	59	1			T28	2		T60	1		T250	1
auto[1610612736:1744830463]	auto[0]	37	1			T149	1		T20	1		T64	1
auto[1610612736:1744830463]	auto[1]	62	1			T57	1		T28	1		T51	1
auto[1744830464:1879048191]	auto[0]	50	1			T211	1		T29	1		T65	1
auto[1744830464:1879048191]	auto[1]	51	1			T17	1		T28	2		T51	1
auto[1879048192:2013265919]	auto[0]	47	1			T36	1		T59	1		T6	1
auto[1879048192:2013265919]	auto[1]	52	1			T28	3		T60	1		T48	1
auto[2013265920:2147483647]	auto[0]	37	1			T213	1		T60	1		T149	1
auto[2013265920:2147483647]	auto[1]	54	1			T93	1		T51	1		T113	1
auto[2147483648:2281701375]	auto[0]	40	1			T28	1		T212	1		T8	1
auto[2147483648:2281701375]	auto[1]	52	1			T28	1		T93	1		T53	1
auto[2281701376:2415919103]	auto[0]	37	1			T18	1		T59	1		T70	2
auto[2281701376:2415919103]	auto[1]	40	1			T28	1		T60	1		T8	1
auto[2415919104:2550136831]	auto[0]	43	1			T57	1		T60	1		T144	1
auto[2415919104:2550136831]	auto[1]	51	1			T28	2		T89	1		T64	2
auto[2550136832:2684354559]	auto[0]	49	1			T28	1		T75	1		T52	1
auto[2550136832:2684354559]	auto[1]	60	1			T28	2		T70	1		T51	1
auto[2684354560:2818572287]	auto[0]	43	1			T4	1		T28	3		T51	1
auto[2684354560:2818572287]	auto[1]	50	1			T53	1		T144	1		T48	1
auto[2818572288:2952790015]	auto[0]	48	1			T17	1		T28	1		T51	1
auto[2818572288:2952790015]	auto[1]	66	1			T28	2		T89	1		T25	1
auto[2952790016:3087007743]	auto[0]	39	1			T89	1		T25	1		T51	1
auto[2952790016:3087007743]	auto[1]	56	1			T28	2		T6	2		T212	1
auto[3087007744:3221225471]	auto[0]	53	1			T28	1		T58	1		T144	1
auto[3087007744:3221225471]	auto[1]	51	1			T93	1		T58	1		T64	2
auto[3221225472:3355443199]	auto[0]	40	1			T58	1		T416	1		T74	1
auto[3221225472:3355443199]	auto[1]	51	1			T28	1		T53	1		T60	1
auto[3355443200:3489660927]	auto[0]	48	1			T5	1		T57	1		T28	1
auto[3355443200:3489660927]	auto[1]	50	1			T5	1		T28	1		T51	1
auto[3489660928:3623878655]	auto[0]	54	1			T18	1		T28	2		T51	1
auto[3489660928:3623878655]	auto[1]	56	1			T52	1		T7	1		T60	1
auto[3623878656:3758096383]	auto[0]	47	1			T51	1		T7	1		T270	1
auto[3623878656:3758096383]	auto[1]	55	1			T18	1		T164	1		T28	1
auto[3758096384:3892314111]	auto[0]	43	1			T4	1		T28	1		T51	1
auto[3758096384:3892314111]	auto[1]	50	1			T51	1		T7	1		T48	1
auto[3892314112:4026531839]	auto[0]	36	1			T89	1		T60	1		T74	1
auto[3892314112:4026531839]	auto[1]	57	1			T164	1		T28	2		T249	1
auto[4026531840:4160749567]	auto[0]	44	1			T70	1		T51	1		T66	1
auto[4026531840:4160749567]	auto[1]	52	1			T28	2		T213	1		T73	1
auto[4160749568:4294967295]	auto[0]	29	1			T17	1		T28	1		T6	1
auto[4160749568:4294967295]	auto[1]	44	1			T5	1		T28	2		T89	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1410

1

T4

3

T17

3

T5

1

auto[1]

1663

1

T4

1

T17

2

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T57	1		T28	1		T58	1
auto[134217728:268435455]	88	1			T164	1		T59	1		T28	4
auto[268435456:402653183]	91	1			T4	1		T18	1		T28	2
auto[402653184:536870911]	105	1			T28	1		T89	1		T416	1
auto[536870912:671088639]	100	1			T4	1		T28	2		T51	1
auto[671088640:805306367]	93	1			T18	1		T51	1		T64	1
auto[805306368:939524095]	99	1			T28	3		T6	1		T93	1
auto[939524096:1073741823]	104	1			T17	2		T28	3		T51	4
auto[1073741824:1207959551]	111	1			T28	2		T70	1		T25	1
auto[1207959552:1342177279]	84	1			T4	1		T17	1		T164	1
auto[1342177280:1476395007]	99	1			T59	1		T28	1		T6	2
auto[1476395008:1610612735]	84	1			T164	1		T28	2		T70	1
auto[1610612736:1744830463]	113	1			T18	1		T57	1		T28	1
auto[1744830464:1879048191]	104	1			T28	4		T93	1		T7	1
auto[1879048192:2013265919]	91	1			T57	1		T51	3		T8	1
auto[2013265920:2147483647]	101	1			T5	1		T28	2		T70	1
auto[2147483648:2281701375]	101	1			T28	2		T93	1		T51	2
auto[2281701376:2415919103]	104	1			T59	1		T28	3		T89	1
auto[2415919104:2550136831]	101	1			T59	1		T28	3		T147	1
auto[2550136832:2684354559]	98	1			T17	1		T59	1		T28	1
auto[2684354560:2818572287]	99	1			T28	3		T58	1		T53	2
auto[2818572288:2952790015]	107	1			T5	1		T18	1		T36	1
auto[2952790016:3087007743]	91	1			T28	2		T70	1		T51	1
auto[3087007744:3221225471]	86	1			T28	2		T89	1		T6	1
auto[3221225472:3355443199]	82	1			T28	1		T60	1		T64	1
auto[3355443200:3489660927]	80	1			T5	1		T28	2		T58	1
auto[3489660928:3623878655]	81	1			T4	1		T28	2		T6	1
auto[3623878656:3758096383]	104	1			T164	1		T28	1		T75	1
auto[3758096384:3892314111]	104	1			T28	2		T211	1		T214	1
auto[3892314112:4026531839]	90	1			T28	1		T70	1		T89	2
auto[4026531840:4160749567]	98	1			T28	2		T19	1		T51	1
auto[4160749568:4294967295]	87	1			T17	1		T40	1		T57	1