Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2688

1

T4

4

T17

5

T5

3

auto[1]

277

1

T130

5

T150

7

T151

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T59	1		T28	1		T250	1
auto[134217728:268435455]	90	1			T28	4		T51	1		T214	1
auto[268435456:402653183]	104	1			T4	1		T60	1		T149	1
auto[402653184:536870911]	88	1			T60	2		T147	1		T26	1
auto[536870912:671088639]	89	1			T5	1		T53	1		T149	1
auto[671088640:805306367]	82	1			T18	1		T164	1		T28	4
auto[805306368:939524095]	110	1			T17	1		T28	1		T6	1
auto[939524096:1073741823]	82	1			T25	1		T7	1		T64	1
auto[1073741824:1207959551]	106	1			T28	2		T89	1		T93	1
auto[1207959552:1342177279]	89	1			T28	2		T211	1		T144	1
auto[1342177280:1476395007]	96	1			T28	1		T25	1		T213	1
auto[1476395008:1610612735]	103	1			T28	5		T64	2		T270	2
auto[1610612736:1744830463]	84	1			T28	1		T89	1		T51	2
auto[1744830464:1879048191]	90	1			T28	2		T70	1		T51	1
auto[1879048192:2013265919]	75	1			T4	1		T5	1		T59	1
auto[2013265920:2147483647]	115	1			T4	1		T28	3		T25	1
auto[2147483648:2281701375]	104	1			T164	1		T28	3		T51	1
auto[2281701376:2415919103]	86	1			T51	1		T211	1		T212	1
auto[2415919104:2550136831]	98	1			T28	1		T6	1		T25	1
auto[2550136832:2684354559]	89	1			T4	1		T17	1		T18	1
auto[2684354560:2818572287]	89	1			T28	3		T89	1		T6	1
auto[2818572288:2952790015]	82	1			T51	1		T60	3		T144	1
auto[2952790016:3087007743]	89	1			T28	2		T52	1		T48	1
auto[3087007744:3221225471]	97	1			T59	1		T28	1		T212	1
auto[3221225472:3355443199]	88	1			T28	3		T51	1		T213	2
auto[3355443200:3489660927]	106	1			T28	1		T89	1		T51	1
auto[3489660928:3623878655]	93	1			T36	1		T28	4		T51	1
auto[3623878656:3758096383]	100	1			T28	2		T20	1		T64	3
auto[3758096384:3892314111]	85	1			T17	1		T18	1		T164	1
auto[3892314112:4026531839]	88	1			T5	1		T18	1		T28	2
auto[4026531840:4160749567]	86	1			T17	1		T164	1		T28	1
auto[4160749568:4294967295]	83	1			T17	1		T6	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	84	1			T59	1		T28	1		T250	1
auto[0:134217727]	auto[1]	15	1			T150	2		T151	1		T155	1
auto[134217728:268435455]	auto[0]	85	1			T28	4		T51	1		T214	1
auto[134217728:268435455]	auto[1]	5	1			T150	1		T411	1		T379	1
auto[268435456:402653183]	auto[0]	94	1			T4	1		T60	1		T149	1
auto[268435456:402653183]	auto[1]	10	1			T283	2		T380	1		T155	1
auto[402653184:536870911]	auto[0]	82	1			T60	2		T147	1		T26	1
auto[402653184:536870911]	auto[1]	6	1			T155	1		T411	1		T379	1
auto[536870912:671088639]	auto[0]	80	1			T5	1		T53	1		T149	1
auto[536870912:671088639]	auto[1]	9	1			T153	1		T283	1		T307	1
auto[671088640:805306367]	auto[0]	75	1			T18	1		T164	1		T28	4
auto[671088640:805306367]	auto[1]	7	1			T130	1		T155	1		T413	1
auto[805306368:939524095]	auto[0]	96	1			T17	1		T28	1		T6	1
auto[805306368:939524095]	auto[1]	14	1			T153	1		T283	1		T155	1
auto[939524096:1073741823]	auto[0]	72	1			T25	1		T7	1		T64	1
auto[939524096:1073741823]	auto[1]	10	1			T151	1		T153	1		T380	1
auto[1073741824:1207959551]	auto[0]	100	1			T28	2		T89	1		T93	1
auto[1073741824:1207959551]	auto[1]	6	1			T151	1		T299	1		T414	1
auto[1207959552:1342177279]	auto[0]	77	1			T28	2		T211	1		T144	1
auto[1207959552:1342177279]	auto[1]	12	1			T130	1		T153	1		T283	1
auto[1342177280:1476395007]	auto[0]	80	1			T28	1		T25	1		T213	1
auto[1342177280:1476395007]	auto[1]	16	1			T130	1		T150	1		T151	1
auto[1476395008:1610612735]	auto[0]	92	1			T28	5		T64	2		T270	2
auto[1476395008:1610612735]	auto[1]	11	1			T252	1		T307	1		T247	1
auto[1610612736:1744830463]	auto[0]	72	1			T28	1		T89	1		T51	2
auto[1610612736:1744830463]	auto[1]	12	1			T151	1		T307	1		T411	1
auto[1744830464:1879048191]	auto[0]	83	1			T28	2		T70	1		T51	1
auto[1744830464:1879048191]	auto[1]	7	1			T307	1		T393	3		T412	1
auto[1879048192:2013265919]	auto[0]	69	1			T4	1		T5	1		T59	1
auto[1879048192:2013265919]	auto[1]	6	1			T299	1		T252	1		T411	1
auto[2013265920:2147483647]	auto[0]	108	1			T4	1		T28	3		T25	1
auto[2013265920:2147483647]	auto[1]	7	1			T151	1		T283	1		T248	1
auto[2147483648:2281701375]	auto[0]	95	1			T164	1		T28	3		T51	1
auto[2147483648:2281701375]	auto[1]	9	1			T153	1		T283	1		T380	1
auto[2281701376:2415919103]	auto[0]	81	1			T51	1		T211	1		T212	1
auto[2281701376:2415919103]	auto[1]	5	1			T150	1		T153	1		T414	2
auto[2415919104:2550136831]	auto[0]	87	1			T28	1		T6	1		T25	1
auto[2415919104:2550136831]	auto[1]	11	1			T151	1		T153	1		T380	1
auto[2550136832:2684354559]	auto[0]	83	1			T4	1		T17	1		T18	1
auto[2550136832:2684354559]	auto[1]	6	1			T151	1		T299	1		T393	1
auto[2684354560:2818572287]	auto[0]	77	1			T28	3		T89	1		T6	1
auto[2684354560:2818572287]	auto[1]	12	1			T280	1		T307	2		T394	1
auto[2818572288:2952790015]	auto[0]	74	1			T51	1		T60	3		T144	1
auto[2818572288:2952790015]	auto[1]	8	1			T150	1		T283	1		T307	1
auto[2952790016:3087007743]	auto[0]	76	1			T28	2		T52	1		T48	1
auto[2952790016:3087007743]	auto[1]	13	1			T150	1		T280	1		T247	1
auto[3087007744:3221225471]	auto[0]	92	1			T59	1		T28	1		T212	1
auto[3087007744:3221225471]	auto[1]	5	1			T130	1		T155	1		T252	1
auto[3221225472:3355443199]	auto[0]	79	1			T28	3		T51	1		T213	2
auto[3221225472:3355443199]	auto[1]	9	1			T307	1		T411	1		T393	1
auto[3355443200:3489660927]	auto[0]	99	1			T28	1		T89	1		T51	1
auto[3355443200:3489660927]	auto[1]	7	1			T152	1		T412	1		T425	1
auto[3489660928:3623878655]	auto[0]	85	1			T36	1		T28	4		T51	1
auto[3489660928:3623878655]	auto[1]	8	1			T153	1		T247	1		T415	1
auto[3623878656:3758096383]	auto[0]	89	1			T28	2		T20	1		T64	3
auto[3623878656:3758096383]	auto[1]	11	1			T153	1		T283	1		T393	1
auto[3758096384:3892314111]	auto[0]	79	1			T17	1		T18	1		T164	1
auto[3758096384:3892314111]	auto[1]	6	1			T393	2		T335	1		T409	1
auto[3892314112:4026531839]	auto[0]	83	1			T5	1		T18	1		T28	2
auto[3892314112:4026531839]	auto[1]	5	1			T299	1		T423	1		T431	1
auto[4026531840:4160749567]	auto[0]	81	1			T17	1		T164	1		T28	1
auto[4026531840:4160749567]	auto[1]	5	1			T130	1		T307	1		T379	1
auto[4160749568:4294967295]	auto[0]	79	1			T17	1		T6	1		T48	1
auto[4160749568:4294967295]	auto[1]	4	1			T151	1		T307	1		T423	1