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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1385 1 T4 3 T17 4 T18 2
auto[1] 1688 1 T4 1 T17 1 T5 3


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 83 1 T5 1 T18 2 T28 2
auto[134217728:268435455] 75 1 T28 3 T70 1 T52 2
auto[268435456:402653183] 96 1 T28 1 T70 1 T51 1
auto[402653184:536870911] 98 1 T59 1 T28 5 T25 1
auto[536870912:671088639] 95 1 T57 2 T28 2 T6 2
auto[671088640:805306367] 99 1 T164 1 T59 1 T28 5
auto[805306368:939524095] 92 1 T28 2 T53 1 T60 1
auto[939524096:1073741823] 94 1 T89 1 T51 1 T144 1
auto[1073741824:1207959551] 110 1 T4 1 T51 1 T75 1
auto[1207959552:1342177279] 103 1 T4 1 T28 1 T6 1
auto[1342177280:1476395007] 89 1 T28 1 T70 1 T89 1
auto[1476395008:1610612735] 119 1 T17 1 T36 1 T57 1
auto[1610612736:1744830463] 85 1 T164 1 T28 2 T89 1
auto[1744830464:1879048191] 98 1 T51 2 T7 1 T61 1
auto[1879048192:2013265919] 100 1 T28 3 T70 2 T6 1
auto[2013265920:2147483647] 78 1 T28 1 T51 1 T214 1
auto[2147483648:2281701375] 130 1 T4 1 T28 2 T93 1
auto[2281701376:2415919103] 98 1 T59 1 T6 1 T75 1
auto[2415919104:2550136831] 101 1 T28 3 T75 1 T8 1
auto[2550136832:2684354559] 90 1 T5 1 T40 1 T28 1
auto[2684354560:2818572287] 93 1 T164 1 T28 3 T53 1
auto[2818572288:2952790015] 103 1 T5 1 T28 1 T19 1
auto[2952790016:3087007743] 101 1 T57 1 T59 1 T28 1
auto[3087007744:3221225471] 102 1 T28 2 T25 1 T211 1
auto[3221225472:3355443199] 110 1 T18 1 T164 1 T28 1
auto[3355443200:3489660927] 92 1 T17 2 T18 1 T28 1
auto[3489660928:3623878655] 87 1 T17 1 T28 2 T6 1
auto[3623878656:3758096383] 77 1 T28 2 T51 2 T144 1
auto[3758096384:3892314111] 88 1 T17 1 T59 1 T28 3
auto[3892314112:4026531839] 109 1 T28 2 T93 1 T58 1
auto[4026531840:4160749567] 76 1 T28 2 T89 1 T51 1
auto[4160749568:4294967295] 102 1 T4 1 T28 2 T213 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 42 1 T18 1 T28 1 T66 1
auto[0:134217727] auto[1] 41 1 T5 1 T18 1 T28 1
auto[134217728:268435455] auto[0] 27 1 T70 1 T249 1 T54 1
auto[134217728:268435455] auto[1] 48 1 T28 3 T52 2 T60 1
auto[268435456:402653183] auto[0] 49 1 T28 1 T70 1 T51 1
auto[268435456:402653183] auto[1] 47 1 T212 1 T61 1 T250 1
auto[402653184:536870911] auto[0] 42 1 T59 1 T28 1 T25 1
auto[402653184:536870911] auto[1] 56 1 T28 4 T58 1 T48 1
auto[536870912:671088639] auto[0] 40 1 T57 1 T6 1 T51 1
auto[536870912:671088639] auto[1] 55 1 T57 1 T28 2 T6 1
auto[671088640:805306367] auto[0] 49 1 T164 1 T59 1 T28 2
auto[671088640:805306367] auto[1] 50 1 T28 3 T25 1 T64 2
auto[805306368:939524095] auto[0] 43 1 T28 1 T250 1 T64 2
auto[805306368:939524095] auto[1] 49 1 T28 1 T53 1 T60 1
auto[939524096:1073741823] auto[0] 39 1 T51 1 T48 1 T223 1
auto[939524096:1073741823] auto[1] 55 1 T89 1 T144 1 T64 2
auto[1073741824:1207959551] auto[0] 44 1 T4 1 T51 1 T61 1
auto[1073741824:1207959551] auto[1] 66 1 T75 1 T212 1 T60 3
auto[1207959552:1342177279] auto[0] 47 1 T28 1 T6 1 T7 1
auto[1207959552:1342177279] auto[1] 56 1 T4 1 T113 1 T64 1
auto[1342177280:1476395007] auto[0] 40 1 T75 1 T20 1 T65 2
auto[1342177280:1476395007] auto[1] 49 1 T28 1 T70 1 T89 1
auto[1476395008:1610612735] auto[0] 59 1 T17 1 T28 2 T25 1
auto[1476395008:1610612735] auto[1] 60 1 T36 1 T57 1 T51 1
auto[1610612736:1744830463] auto[0] 36 1 T214 1 T52 1 T223 1
auto[1610612736:1744830463] auto[1] 49 1 T164 1 T28 2 T89 1
auto[1744830464:1879048191] auto[0] 47 1 T7 1 T61 1 T66 1
auto[1744830464:1879048191] auto[1] 51 1 T51 2 T113 1 T64 1
auto[1879048192:2013265919] auto[0] 60 1 T28 2 T70 2 T6 1
auto[1879048192:2013265919] auto[1] 40 1 T28 1 T51 1 T124 1
auto[2013265920:2147483647] auto[0] 35 1 T214 1 T249 1 T64 1
auto[2013265920:2147483647] auto[1] 43 1 T28 1 T51 1 T144 1
auto[2147483648:2281701375] auto[0] 57 1 T4 1 T51 2 T20 1
auto[2147483648:2281701375] auto[1] 73 1 T28 2 T93 1 T60 1
auto[2281701376:2415919103] auto[0] 38 1 T59 1 T144 1 T220 1
auto[2281701376:2415919103] auto[1] 60 1 T6 1 T75 1 T213 1
auto[2415919104:2550136831] auto[0] 53 1 T28 1 T8 1 T54 1
auto[2415919104:2550136831] auto[1] 48 1 T28 2 T75 1 T48 1
auto[2550136832:2684354559] auto[0] 43 1 T28 1 T113 1 T64 1
auto[2550136832:2684354559] auto[1] 47 1 T5 1 T40 1 T6 1
auto[2684354560:2818572287] auto[0] 36 1 T28 3 T61 1 T54 1
auto[2684354560:2818572287] auto[1] 57 1 T164 1 T53 1 T60 1
auto[2818572288:2952790015] auto[0] 49 1 T51 2 T8 1 T74 2
auto[2818572288:2952790015] auto[1] 54 1 T5 1 T28 1 T19 1
auto[2952790016:3087007743] auto[0] 43 1 T57 1 T75 1 T53 1
auto[2952790016:3087007743] auto[1] 58 1 T59 1 T28 1 T213 1
auto[3087007744:3221225471] auto[0] 47 1 T28 1 T64 1 T219 1
auto[3087007744:3221225471] auto[1] 55 1 T28 1 T25 1 T211 1
auto[3221225472:3355443199] auto[0] 43 1 T18 1 T28 1 T89 1
auto[3221225472:3355443199] auto[1] 67 1 T164 1 T70 1 T89 1
auto[3355443200:3489660927] auto[0] 42 1 T17 1 T51 2 T65 1
auto[3355443200:3489660927] auto[1] 50 1 T17 1 T18 1 T28 1
auto[3489660928:3623878655] auto[0] 40 1 T17 1 T28 1 T51 1
auto[3489660928:3623878655] auto[1] 47 1 T28 1 T6 1 T51 2
auto[3623878656:3758096383] auto[0] 26 1 T28 1 T51 1 T258 1
auto[3623878656:3758096383] auto[1] 51 1 T28 1 T51 1 T144 1
auto[3758096384:3892314111] auto[0] 40 1 T17 1 T59 1 T28 2
auto[3758096384:3892314111] auto[1] 48 1 T28 1 T93 1 T212 1
auto[3892314112:4026531839] auto[0] 50 1 T28 1 T58 1 T60 2
auto[3892314112:4026531839] auto[1] 59 1 T28 1 T93 1 T223 1
auto[4026531840:4160749567] auto[0] 34 1 T28 1 T89 1 T60 3
auto[4026531840:4160749567] auto[1] 42 1 T28 1 T51 1 T68 1
auto[4160749568:4294967295] auto[0] 45 1 T4 1 T213 1 T58 1
auto[4160749568:4294967295] auto[1] 57 1 T28 2 T53 1 T113 1

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