Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4050

1

T4

6

T17

10

T5

4

auto[1]

2098

1

T4

2

T5

2

T18

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	188	1			T28	6		T51	4		T75	2
auto[134217728:268435455]	208	1			T28	4		T89	2		T75	2
auto[268435456:402653183]	168	1			T28	2		T89	2		T51	4
auto[402653184:536870911]	208	1			T57	2		T164	2		T28	2
auto[536870912:671088639]	172	1			T57	2		T164	2		T25	4
auto[671088640:805306367]	190	1			T28	4		T93	2		T7	2
auto[805306368:939524095]	180	1			T28	2		T89	4		T6	2
auto[939524096:1073741823]	184	1			T17	2		T59	2		T28	4
auto[1073741824:1207959551]	208	1			T164	2		T28	6		T212	4
auto[1207959552:1342177279]	186	1			T28	2		T89	2		T51	4
auto[1342177280:1476395007]	170	1			T28	4		T6	2		T212	2
auto[1476395008:1610612735]	182	1			T40	2		T19	2		T51	2
auto[1610612736:1744830463]	184	1			T17	4		T28	6		T144	2
auto[1744830464:1879048191]	154	1			T4	4		T17	2		T28	2
auto[1879048192:2013265919]	168	1			T28	12		T416	2		T249	2
auto[2013265920:2147483647]	202	1			T5	2		T28	6		T51	4
auto[2147483648:2281701375]	182	1			T28	4		T70	2		T6	2
auto[2281701376:2415919103]	212	1			T18	2		T28	2		T6	2
auto[2415919104:2550136831]	206	1			T28	4		T89	2		T51	4
auto[2550136832:2684354559]	206	1			T5	2		T59	2		T28	8
auto[2684354560:2818572287]	168	1			T25	2		T223	2		T113	2
auto[2818572288:2952790015]	210	1			T28	4		T6	2		T51	2
auto[2952790016:3087007743]	202	1			T4	2		T36	2		T28	6
auto[3087007744:3221225471]	236	1			T28	6		T93	2		T60	2
auto[3221225472:3355443199]	176	1			T28	2		T70	2		T75	2
auto[3355443200:3489660927]	176	1			T18	4		T57	2		T59	2
auto[3489660928:3623878655]	206	1			T4	2		T17	2		T59	2
auto[3623878656:3758096383]	196	1			T5	2		T57	2		T28	6
auto[3758096384:3892314111]	204	1			T164	2		T416	2		T48	2
auto[3892314112:4026531839]	230	1			T28	2		T58	4		T48	2
auto[4026531840:4160749567]	212	1			T51	2		T60	2		T149	2
auto[4160749568:4294967295]	174	1			T18	2		T59	2		T28	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	132	1			T28	6		T51	2		T75	2
auto[0:134217727]	auto[1]	56	1			T51	2		T214	2		T64	6
auto[134217728:268435455]	auto[0]	106	1			T28	2		T89	2		T75	2
auto[134217728:268435455]	auto[1]	102	1			T28	2		T7	2		T144	2
auto[268435456:402653183]	auto[0]	104	1			T89	2		T51	2		T53	2
auto[268435456:402653183]	auto[1]	64	1			T28	2		T51	2		T60	2
auto[402653184:536870911]	auto[0]	134	1			T57	2		T164	2		T28	2
auto[402653184:536870911]	auto[1]	74	1			T70	2		T212	2		T21	2
auto[536870912:671088639]	auto[0]	108	1			T57	2		T51	2		T113	2
auto[536870912:671088639]	auto[1]	64	1			T164	2		T25	4		T61	2
auto[671088640:805306367]	auto[0]	128	1			T28	4		T93	2		T64	8
auto[671088640:805306367]	auto[1]	62	1			T7	2		T26	2		T124	2
auto[805306368:939524095]	auto[0]	132	1			T89	4		T6	2		T51	4
auto[805306368:939524095]	auto[1]	48	1			T28	2		T73	2		T217	2
auto[939524096:1073741823]	auto[0]	122	1			T17	2		T59	2		T28	4
auto[939524096:1073741823]	auto[1]	62	1			T6	2		T110	2		T43	2
auto[1073741824:1207959551]	auto[0]	144	1			T164	2		T28	2		T212	4
auto[1073741824:1207959551]	auto[1]	64	1			T28	4		T144	2		T249	2
auto[1207959552:1342177279]	auto[0]	128	1			T89	2		T60	2		T113	2
auto[1207959552:1342177279]	auto[1]	58	1			T28	2		T51	4		T52	2
auto[1342177280:1476395007]	auto[0]	98	1			T28	4		T6	2		T212	2
auto[1342177280:1476395007]	auto[1]	72	1			T53	2		T60	2		T30	2
auto[1476395008:1610612735]	auto[0]	116	1			T40	2		T51	2		T7	4
auto[1476395008:1610612735]	auto[1]	66	1			T19	2		T7	2		T147	2
auto[1610612736:1744830463]	auto[0]	116	1			T17	4		T28	2		T144	2
auto[1610612736:1744830463]	auto[1]	68	1			T28	4		T250	2		T54	2
auto[1744830464:1879048191]	auto[0]	104	1			T4	2		T17	2		T28	2
auto[1744830464:1879048191]	auto[1]	50	1			T4	2		T51	2		T217	2
auto[1879048192:2013265919]	auto[0]	108	1			T28	8		T416	2		T20	2
auto[1879048192:2013265919]	auto[1]	60	1			T28	4		T249	2		T64	2
auto[2013265920:2147483647]	auto[0]	134	1			T5	2		T60	2		T48	2
auto[2013265920:2147483647]	auto[1]	68	1			T28	6		T51	4		T61	2
auto[2147483648:2281701375]	auto[0]	128	1			T28	2		T6	2		T93	2
auto[2147483648:2281701375]	auto[1]	54	1			T28	2		T70	2		T48	2
auto[2281701376:2415919103]	auto[0]	140	1			T18	2		T6	2		T93	2
auto[2281701376:2415919103]	auto[1]	72	1			T28	2		T51	2		T144	2
auto[2415919104:2550136831]	auto[0]	122	1			T89	2		T51	4		T213	2
auto[2415919104:2550136831]	auto[1]	84	1			T28	4		T249	2		T65	4
auto[2550136832:2684354559]	auto[0]	140	1			T5	2		T28	8		T89	2
auto[2550136832:2684354559]	auto[1]	66	1			T59	2		T53	2		T74	2
auto[2684354560:2818572287]	auto[0]	110	1			T223	2		T113	2		T65	2
auto[2684354560:2818572287]	auto[1]	58	1			T25	2		T155	2		T126	4
auto[2818572288:2952790015]	auto[0]	140	1			T28	4		T51	2		T75	2
auto[2818572288:2952790015]	auto[1]	70	1			T6	2		T48	2		T113	2
auto[2952790016:3087007743]	auto[0]	134	1			T4	2		T28	4		T60	2
auto[2952790016:3087007743]	auto[1]	68	1			T36	2		T28	2		T75	2
auto[3087007744:3221225471]	auto[0]	152	1			T28	4		T93	2		T60	2
auto[3087007744:3221225471]	auto[1]	84	1			T28	2		T124	2		T65	2
auto[3221225472:3355443199]	auto[0]	118	1			T28	2		T70	2		T75	2
auto[3221225472:3355443199]	auto[1]	58	1			T60	2		T104	2		T64	2
auto[3355443200:3489660927]	auto[0]	120	1			T18	2		T59	2		T51	4
auto[3355443200:3489660927]	auto[1]	56	1			T18	2		T57	2		T28	2
auto[3489660928:3623878655]	auto[0]	136	1			T4	2		T17	2		T59	2
auto[3489660928:3623878655]	auto[1]	70	1			T28	4		T26	4		T223	2
auto[3623878656:3758096383]	auto[0]	146	1			T57	2		T28	6		T58	2
auto[3623878656:3758096383]	auto[1]	50	1			T5	2		T54	2		T270	2
auto[3758096384:3892314111]	auto[0]	132	1			T48	2		T74	2		T64	4
auto[3758096384:3892314111]	auto[1]	72	1			T164	2		T416	2		T64	4
auto[3892314112:4026531839]	auto[0]	150	1			T58	4		T48	2		T20	2
auto[3892314112:4026531839]	auto[1]	80	1			T28	2		T249	2		T250	2
auto[4026531840:4160749567]	auto[0]	146	1			T51	2		T60	2		T149	2
auto[4026531840:4160749567]	auto[1]	66	1			T270	2		T310	2		T380	2
auto[4160749568:4294967295]	auto[0]	122	1			T18	2		T70	2		T51	2
auto[4160749568:4294967295]	auto[1]	52	1			T59	2		T28	2		T25	2