Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.04 98.19 98.23 100.00 99.11 98.41 91.19


Total test records in report: 1075
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T1006 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2962580102 Jun 04 01:31:18 PM PDT 24 Jun 04 01:31:26 PM PDT 24 215849073 ps
T1007 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3855197410 Jun 04 01:31:19 PM PDT 24 Jun 04 01:31:25 PM PDT 24 1305851252 ps
T1008 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1964405953 Jun 04 01:31:29 PM PDT 24 Jun 04 01:31:30 PM PDT 24 35570856 ps
T1009 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2546206355 Jun 04 01:31:35 PM PDT 24 Jun 04 01:31:37 PM PDT 24 29514189 ps
T1010 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.161395771 Jun 04 01:31:18 PM PDT 24 Jun 04 01:31:23 PM PDT 24 94920248 ps
T1011 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1795833325 Jun 04 01:30:51 PM PDT 24 Jun 04 01:30:55 PM PDT 24 332275086 ps
T1012 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1054959169 Jun 04 01:30:26 PM PDT 24 Jun 04 01:30:29 PM PDT 24 211916565 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3057277960 Jun 04 01:30:32 PM PDT 24 Jun 04 01:30:35 PM PDT 24 312757419 ps
T1014 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2513209285 Jun 04 01:30:41 PM PDT 24 Jun 04 01:30:50 PM PDT 24 237672741 ps
T1015 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2131985646 Jun 04 01:31:02 PM PDT 24 Jun 04 01:31:08 PM PDT 24 1401423150 ps
T1016 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1342681553 Jun 04 01:30:34 PM PDT 24 Jun 04 01:30:36 PM PDT 24 111143850 ps
T1017 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3875516573 Jun 04 01:31:02 PM PDT 24 Jun 04 01:31:04 PM PDT 24 122983477 ps
T1018 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3893279255 Jun 04 01:30:50 PM PDT 24 Jun 04 01:30:52 PM PDT 24 9748371 ps
T1019 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2631571814 Jun 04 01:30:40 PM PDT 24 Jun 04 01:30:43 PM PDT 24 260744338 ps
T1020 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2316490443 Jun 04 01:31:15 PM PDT 24 Jun 04 01:31:16 PM PDT 24 40178199 ps
T1021 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3634426849 Jun 04 01:30:25 PM PDT 24 Jun 04 01:30:30 PM PDT 24 73954676 ps
T1022 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.867896764 Jun 04 01:31:18 PM PDT 24 Jun 04 01:31:24 PM PDT 24 273778565 ps
T1023 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2770852883 Jun 04 01:31:26 PM PDT 24 Jun 04 01:31:28 PM PDT 24 22043533 ps
T1024 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2379952703 Jun 04 01:31:22 PM PDT 24 Jun 04 01:31:25 PM PDT 24 132958845 ps
T1025 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1890041481 Jun 04 01:30:41 PM PDT 24 Jun 04 01:30:44 PM PDT 24 23110488 ps
T1026 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3106161489 Jun 04 01:30:42 PM PDT 24 Jun 04 01:30:45 PM PDT 24 118172599 ps
T1027 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.137930505 Jun 04 01:31:27 PM PDT 24 Jun 04 01:31:42 PM PDT 24 383913475 ps
T1028 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3849953561 Jun 04 01:30:41 PM PDT 24 Jun 04 01:30:45 PM PDT 24 76918035 ps
T1029 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1957964623 Jun 04 01:31:02 PM PDT 24 Jun 04 01:31:05 PM PDT 24 38615704 ps
T1030 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2964925045 Jun 04 01:31:11 PM PDT 24 Jun 04 01:31:16 PM PDT 24 119531426 ps
T1031 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2546374305 Jun 04 01:31:02 PM PDT 24 Jun 04 01:31:05 PM PDT 24 32003871 ps
T1032 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1994349367 Jun 04 01:31:39 PM PDT 24 Jun 04 01:31:41 PM PDT 24 14498787 ps
T1033 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3387175574 Jun 04 01:31:22 PM PDT 24 Jun 04 01:31:25 PM PDT 24 32206443 ps
T190 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.563579051 Jun 04 01:30:42 PM PDT 24 Jun 04 01:30:50 PM PDT 24 1083204765 ps
T1034 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.539492915 Jun 04 01:31:28 PM PDT 24 Jun 04 01:31:33 PM PDT 24 169346294 ps
T1035 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4113427714 Jun 04 01:31:02 PM PDT 24 Jun 04 01:31:03 PM PDT 24 36451007 ps
T1036 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.307632789 Jun 04 01:31:34 PM PDT 24 Jun 04 01:31:35 PM PDT 24 9312705 ps
T1037 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2700797885 Jun 04 01:30:16 PM PDT 24 Jun 04 01:30:22 PM PDT 24 103579233 ps
T1038 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4106527102 Jun 04 01:31:00 PM PDT 24 Jun 04 01:31:03 PM PDT 24 144818592 ps
T1039 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1875283800 Jun 04 01:30:50 PM PDT 24 Jun 04 01:30:52 PM PDT 24 142811919 ps
T1040 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2526384083 Jun 04 01:31:09 PM PDT 24 Jun 04 01:31:12 PM PDT 24 37056057 ps
T1041 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.463554566 Jun 04 01:31:09 PM PDT 24 Jun 04 01:31:11 PM PDT 24 108823631 ps
T179 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.289443305 Jun 04 01:31:29 PM PDT 24 Jun 04 01:31:33 PM PDT 24 57307008 ps
T1042 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.597420713 Jun 04 01:31:27 PM PDT 24 Jun 04 01:31:29 PM PDT 24 134797031 ps
T1043 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4095773816 Jun 04 01:31:36 PM PDT 24 Jun 04 01:31:38 PM PDT 24 10933741 ps
T1044 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1214379342 Jun 04 01:30:41 PM PDT 24 Jun 04 01:30:45 PM PDT 24 260352116 ps
T1045 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1023760244 Jun 04 01:30:42 PM PDT 24 Jun 04 01:30:48 PM PDT 24 679825730 ps
T1046 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3625440542 Jun 04 01:31:37 PM PDT 24 Jun 04 01:31:38 PM PDT 24 7837625 ps
T1047 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2910706902 Jun 04 01:31:18 PM PDT 24 Jun 04 01:31:20 PM PDT 24 33395554 ps
T1048 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3698938111 Jun 04 01:30:52 PM PDT 24 Jun 04 01:30:58 PM PDT 24 561250273 ps
T1049 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3833755049 Jun 04 01:30:42 PM PDT 24 Jun 04 01:30:44 PM PDT 24 82900158 ps
T1050 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2202104718 Jun 04 01:30:26 PM PDT 24 Jun 04 01:30:31 PM PDT 24 80265606 ps
T1051 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2910197263 Jun 04 01:31:11 PM PDT 24 Jun 04 01:31:26 PM PDT 24 1025374419 ps
T185 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3804843669 Jun 04 01:30:52 PM PDT 24 Jun 04 01:30:58 PM PDT 24 337607994 ps
T1052 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1263888402 Jun 04 01:31:00 PM PDT 24 Jun 04 01:31:02 PM PDT 24 113692845 ps
T1053 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3404649904 Jun 04 01:30:34 PM PDT 24 Jun 04 01:30:35 PM PDT 24 114265072 ps
T1054 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3997579696 Jun 04 01:31:36 PM PDT 24 Jun 04 01:31:38 PM PDT 24 27100730 ps
T1055 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1897792131 Jun 04 01:30:35 PM PDT 24 Jun 04 01:30:37 PM PDT 24 35446255 ps
T1056 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1051593448 Jun 04 01:31:37 PM PDT 24 Jun 04 01:31:39 PM PDT 24 13835930 ps
T175 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2476851405 Jun 04 01:31:19 PM PDT 24 Jun 04 01:31:25 PM PDT 24 1148261260 ps
T1057 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.970214163 Jun 04 01:30:53 PM PDT 24 Jun 04 01:30:59 PM PDT 24 803001143 ps
T1058 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3188409748 Jun 04 01:30:49 PM PDT 24 Jun 04 01:30:52 PM PDT 24 175853610 ps
T1059 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4098519891 Jun 04 01:31:22 PM PDT 24 Jun 04 01:31:24 PM PDT 24 91092396 ps
T176 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.731478985 Jun 04 01:31:09 PM PDT 24 Jun 04 01:31:15 PM PDT 24 773105599 ps
T1060 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2436234326 Jun 04 01:31:35 PM PDT 24 Jun 04 01:31:36 PM PDT 24 12828631 ps
T1061 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3104062785 Jun 04 01:31:11 PM PDT 24 Jun 04 01:31:14 PM PDT 24 209289729 ps
T1062 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.465314371 Jun 04 01:31:27 PM PDT 24 Jun 04 01:31:29 PM PDT 24 12533773 ps
T1063 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2008560103 Jun 04 01:30:41 PM PDT 24 Jun 04 01:31:00 PM PDT 24 1028360504 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1149022961 Jun 04 01:31:31 PM PDT 24 Jun 04 01:31:33 PM PDT 24 206936742 ps
T1065 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3699667070 Jun 04 01:30:25 PM PDT 24 Jun 04 01:30:28 PM PDT 24 86038267 ps
T1066 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2286420581 Jun 04 01:31:37 PM PDT 24 Jun 04 01:31:38 PM PDT 24 45021539 ps
T1067 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.791780924 Jun 04 01:31:31 PM PDT 24 Jun 04 01:31:32 PM PDT 24 103558239 ps
T1068 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1162923160 Jun 04 01:31:13 PM PDT 24 Jun 04 01:31:18 PM PDT 24 53232179 ps
T1069 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1670531184 Jun 04 01:30:17 PM PDT 24 Jun 04 01:30:20 PM PDT 24 130087505 ps
T1070 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.248236604 Jun 04 01:31:18 PM PDT 24 Jun 04 01:31:21 PM PDT 24 54275062 ps
T1071 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3274312541 Jun 04 01:31:12 PM PDT 24 Jun 04 01:31:17 PM PDT 24 263132835 ps
T1072 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3728428516 Jun 04 01:30:17 PM PDT 24 Jun 04 01:30:20 PM PDT 24 294849574 ps
T1073 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2148576305 Jun 04 01:30:49 PM PDT 24 Jun 04 01:30:51 PM PDT 24 101076636 ps
T1074 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3348710838 Jun 04 01:31:04 PM PDT 24 Jun 04 01:31:06 PM PDT 24 42882490 ps
T1075 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3200502093 Jun 04 01:31:15 PM PDT 24 Jun 04 01:31:18 PM PDT 24 95635262 ps

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2948072188
Short name T5
Test name
Test status
Simulation time 18148846225 ps
CPU time 45.88 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 02:00:30 PM PDT 24
Peak memory 208624 kb
Host smart-fe6a61c9-5ff4-4cf3-a953-ee11c884f001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948072188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2948072188
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1015750690
Short name T28
Test name
Test status
Simulation time 42840056818 ps
CPU time 84.13 seconds
Started Jun 04 01:58:24 PM PDT 24
Finished Jun 04 01:59:49 PM PDT 24
Peak memory 216060 kb
Host smart-6da24c39-647b-4262-a539-01a515241935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015750690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1015750690
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1640936707
Short name T6
Test name
Test status
Simulation time 79271992 ps
CPU time 3.99 seconds
Started Jun 04 01:58:38 PM PDT 24
Finished Jun 04 01:58:43 PM PDT 24
Peak memory 222472 kb
Host smart-9494fd1e-f17d-4621-bd42-dbd30fda4f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640936707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1640936707
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2553822837
Short name T64
Test name
Test status
Simulation time 1779357477 ps
CPU time 22.76 seconds
Started Jun 04 01:58:24 PM PDT 24
Finished Jun 04 01:58:48 PM PDT 24
Peak memory 220812 kb
Host smart-8a92d67d-58f1-4ab7-85b7-0a5cf3720a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553822837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2553822837
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3343984911
Short name T140
Test name
Test status
Simulation time 1643892578 ps
CPU time 8.4 seconds
Started Jun 04 01:59:41 PM PDT 24
Finished Jun 04 01:59:50 PM PDT 24
Peak memory 218768 kb
Host smart-f69983a0-f237-4031-9971-bff3f9e3acce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343984911 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3343984911
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.14283138
Short name T11
Test name
Test status
Simulation time 1632867433 ps
CPU time 9.09 seconds
Started Jun 04 01:57:09 PM PDT 24
Finished Jun 04 01:57:19 PM PDT 24
Peak memory 234368 kb
Host smart-a3bfd429-c54d-4782-80c1-8e6613182609
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14283138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.14283138
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1973535951
Short name T67
Test name
Test status
Simulation time 102599053 ps
CPU time 2.49 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:29 PM PDT 24
Peak memory 210184 kb
Host smart-dba0e0fd-bfba-477a-9615-1c505545c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973535951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1973535951
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.4284783478
Short name T138
Test name
Test status
Simulation time 1141309031 ps
CPU time 16.87 seconds
Started Jun 04 01:57:57 PM PDT 24
Finished Jun 04 01:58:14 PM PDT 24
Peak memory 220724 kb
Host smart-73309ccb-7f2f-4a20-9a70-133e9e960247
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284783478 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.4284783478
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2878523894
Short name T65
Test name
Test status
Simulation time 1182882788 ps
CPU time 15.1 seconds
Started Jun 04 02:00:56 PM PDT 24
Finished Jun 04 02:01:12 PM PDT 24
Peak memory 215456 kb
Host smart-970622ed-b4fb-4f2c-9800-8dfcba0cdc20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878523894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2878523894
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2522437103
Short name T130
Test name
Test status
Simulation time 727320365 ps
CPU time 12.08 seconds
Started Jun 04 01:58:22 PM PDT 24
Finished Jun 04 01:58:34 PM PDT 24
Peak memory 214296 kb
Host smart-21ae19a1-90dc-4300-8984-5ce691e60ac7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2522437103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2522437103
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3476592464
Short name T18
Test name
Test status
Simulation time 85966052 ps
CPU time 2.76 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 214300 kb
Host smart-6ba8514f-a891-4923-ba9e-69ee185dd989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476592464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3476592464
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1383879431
Short name T9
Test name
Test status
Simulation time 741456889 ps
CPU time 2.76 seconds
Started Jun 04 01:58:26 PM PDT 24
Finished Jun 04 01:58:30 PM PDT 24
Peak memory 210468 kb
Host smart-cfcaeada-70f4-4f73-ad66-af588120051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383879431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1383879431
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2912094158
Short name T127
Test name
Test status
Simulation time 484273535 ps
CPU time 10.92 seconds
Started Jun 04 01:31:11 PM PDT 24
Finished Jun 04 01:31:24 PM PDT 24
Peak memory 214156 kb
Host smart-5892d044-8bfe-456d-80d0-321e2a161217
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912094158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2912094158
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.852639942
Short name T308
Test name
Test status
Simulation time 4065015981 ps
CPU time 58.42 seconds
Started Jun 04 02:00:04 PM PDT 24
Finished Jun 04 02:01:03 PM PDT 24
Peak memory 215864 kb
Host smart-8ce357c2-5c45-4b75-8cd8-c038906b83a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852639942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.852639942
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1511665496
Short name T307
Test name
Test status
Simulation time 6437546543 ps
CPU time 40.41 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:40 PM PDT 24
Peak memory 215540 kb
Host smart-070c1cb3-b8a1-4d80-b0a7-131e96c8f12e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511665496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1511665496
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3523707943
Short name T14
Test name
Test status
Simulation time 26578870 ps
CPU time 0.89 seconds
Started Jun 04 01:58:21 PM PDT 24
Finished Jun 04 01:58:23 PM PDT 24
Peak memory 206116 kb
Host smart-4dcc2d70-6e78-476f-9e57-8b1ee750fb61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523707943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3523707943
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1015696753
Short name T60
Test name
Test status
Simulation time 238479058 ps
CPU time 11.61 seconds
Started Jun 04 01:59:56 PM PDT 24
Finished Jun 04 02:00:09 PM PDT 24
Peak memory 222368 kb
Host smart-5f76d2de-f2a8-4bd8-abc9-11f05c06da2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015696753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1015696753
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1366944992
Short name T106
Test name
Test status
Simulation time 196907640 ps
CPU time 7.85 seconds
Started Jun 04 01:59:55 PM PDT 24
Finished Jun 04 02:00:04 PM PDT 24
Peak memory 221984 kb
Host smart-9cecd218-5cc8-469d-af0a-9454ee4456bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366944992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1366944992
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.101044625
Short name T51
Test name
Test status
Simulation time 3865675854 ps
CPU time 25.48 seconds
Started Jun 04 02:00:19 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 222288 kb
Host smart-200dfb35-dd42-42df-8b5a-132db3f426f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101044625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.101044625
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.284706797
Short name T411
Test name
Test status
Simulation time 7733914053 ps
CPU time 65.3 seconds
Started Jun 04 01:58:13 PM PDT 24
Finished Jun 04 01:59:20 PM PDT 24
Peak memory 215924 kb
Host smart-49d6404e-9124-4f9d-9546-bb30b836f758
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284706797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.284706797
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3226605921
Short name T229
Test name
Test status
Simulation time 20345309355 ps
CPU time 91.01 seconds
Started Jun 04 01:57:28 PM PDT 24
Finished Jun 04 01:59:00 PM PDT 24
Peak memory 222724 kb
Host smart-36945a9d-971a-494f-819f-2191496a5296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226605921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3226605921
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3231173733
Short name T132
Test name
Test status
Simulation time 191172536 ps
CPU time 6.91 seconds
Started Jun 04 01:30:28 PM PDT 24
Finished Jun 04 01:30:36 PM PDT 24
Peak memory 220436 kb
Host smart-20e95980-2938-452d-92d0-13fd9f612e98
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231173733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3231173733
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2892442167
Short name T40
Test name
Test status
Simulation time 69028796 ps
CPU time 2.93 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:22 PM PDT 24
Peak memory 222628 kb
Host smart-a075dfcd-a3ed-469b-a927-b111b65b8194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892442167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2892442167
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3325051832
Short name T299
Test name
Test status
Simulation time 1296032720 ps
CPU time 64.51 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:01:34 PM PDT 24
Peak memory 215648 kb
Host smart-a41c861c-9be5-4abe-bd34-6e4705d405e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325051832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3325051832
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3941148492
Short name T105
Test name
Test status
Simulation time 172196149 ps
CPU time 4.23 seconds
Started Jun 04 01:58:49 PM PDT 24
Finished Jun 04 01:58:55 PM PDT 24
Peak memory 222532 kb
Host smart-e53eee03-3176-44bd-ac86-3e1a04ac8c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941148492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3941148492
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2219488615
Short name T283
Test name
Test status
Simulation time 237767832 ps
CPU time 12.75 seconds
Started Jun 04 02:01:04 PM PDT 24
Finished Jun 04 02:01:19 PM PDT 24
Peak memory 214284 kb
Host smart-7d7fb3e2-3705-40c5-9273-ad99f88935da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219488615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2219488615
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1894340274
Short name T83
Test name
Test status
Simulation time 3378233623 ps
CPU time 67.22 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:02:26 PM PDT 24
Peak memory 222472 kb
Host smart-b0d88cb2-5510-4d60-8a31-8974fa38e813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894340274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1894340274
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1871171558
Short name T43
Test name
Test status
Simulation time 95930831 ps
CPU time 4.1 seconds
Started Jun 04 02:00:47 PM PDT 24
Finished Jun 04 02:00:52 PM PDT 24
Peak memory 209704 kb
Host smart-a5dfdcb0-1047-4495-a324-9357200b6a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871171558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1871171558
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2192063112
Short name T22
Test name
Test status
Simulation time 410484287 ps
CPU time 1.75 seconds
Started Jun 04 01:58:06 PM PDT 24
Finished Jun 04 01:58:08 PM PDT 24
Peak memory 220416 kb
Host smart-9074eac1-8c89-4343-b161-8c3e944dc2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192063112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2192063112
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1965688276
Short name T154
Test name
Test status
Simulation time 8426165892 ps
CPU time 82.62 seconds
Started Jun 04 02:00:41 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 216836 kb
Host smart-11af47c9-ad34-474d-9cdc-e6a990d5d292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965688276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1965688276
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.113997425
Short name T30
Test name
Test status
Simulation time 119213759 ps
CPU time 3.33 seconds
Started Jun 04 02:01:02 PM PDT 24
Finished Jun 04 02:01:07 PM PDT 24
Peak memory 209304 kb
Host smart-a02d5c9d-a2eb-49dd-8aae-0d582fc2783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113997425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.113997425
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2578584823
Short name T115
Test name
Test status
Simulation time 1014600625 ps
CPU time 51.87 seconds
Started Jun 04 01:58:28 PM PDT 24
Finished Jun 04 01:59:21 PM PDT 24
Peak memory 214348 kb
Host smart-eee3164e-7dba-4e18-9a99-3232a9789d73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578584823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2578584823
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3353500791
Short name T126
Test name
Test status
Simulation time 580054204 ps
CPU time 18.25 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:25 PM PDT 24
Peak memory 222724 kb
Host smart-79074cb9-3b33-414f-b1ee-d52d02b41bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353500791 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3353500791
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2609252388
Short name T168
Test name
Test status
Simulation time 419335371 ps
CPU time 7.59 seconds
Started Jun 04 01:31:00 PM PDT 24
Finished Jun 04 01:31:09 PM PDT 24
Peak memory 214008 kb
Host smart-e425e486-5e33-4c17-9403-97469d0346ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609252388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2609252388
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1862088282
Short name T37
Test name
Test status
Simulation time 161449609 ps
CPU time 2.34 seconds
Started Jun 04 02:00:17 PM PDT 24
Finished Jun 04 02:00:20 PM PDT 24
Peak memory 210476 kb
Host smart-ad14e86d-68cb-405b-af6b-31725d228a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862088282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1862088282
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3567552335
Short name T102
Test name
Test status
Simulation time 55197554 ps
CPU time 3.21 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:55 PM PDT 24
Peak memory 214284 kb
Host smart-5a4b2c9e-5dde-480e-a535-5ff5394b4417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567552335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3567552335
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3985761806
Short name T333
Test name
Test status
Simulation time 64051496 ps
CPU time 2.28 seconds
Started Jun 04 01:58:22 PM PDT 24
Finished Jun 04 01:58:25 PM PDT 24
Peak memory 221544 kb
Host smart-a3d009f5-bb74-4bfe-ba2f-9185d858763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985761806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3985761806
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.914384323
Short name T410
Test name
Test status
Simulation time 86998319 ps
CPU time 5.42 seconds
Started Jun 04 02:00:51 PM PDT 24
Finished Jun 04 02:00:58 PM PDT 24
Peak memory 214296 kb
Host smart-94e9b08c-2783-4477-9c86-d5fd309f2a46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914384323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.914384323
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3231610294
Short name T48
Test name
Test status
Simulation time 415803544 ps
CPU time 5.12 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:11 PM PDT 24
Peak memory 210476 kb
Host smart-ea6dafae-796d-495b-a13a-ec5202b38bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231610294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3231610294
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.353189924
Short name T177
Test name
Test status
Simulation time 883745010 ps
CPU time 6.67 seconds
Started Jun 04 01:30:49 PM PDT 24
Finished Jun 04 01:30:57 PM PDT 24
Peak memory 205700 kb
Host smart-3b8a2aa9-fb7d-404d-bc6e-bda14a5f8d16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353189924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
353189924
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2631905954
Short name T210
Test name
Test status
Simulation time 5143085138 ps
CPU time 49.52 seconds
Started Jun 04 01:59:15 PM PDT 24
Finished Jun 04 02:00:06 PM PDT 24
Peak memory 215736 kb
Host smart-18a75f7b-b657-4e5e-a88c-04d93bcedcef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631905954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2631905954
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2035273761
Short name T61
Test name
Test status
Simulation time 80935181 ps
CPU time 2.29 seconds
Started Jun 04 01:57:46 PM PDT 24
Finished Jun 04 01:57:50 PM PDT 24
Peak memory 214168 kb
Host smart-8a176758-ff0a-4a79-bc8f-ec5c37eea218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035273761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2035273761
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.4254293378
Short name T335
Test name
Test status
Simulation time 182650305 ps
CPU time 10.31 seconds
Started Jun 04 01:59:26 PM PDT 24
Finished Jun 04 01:59:37 PM PDT 24
Peak memory 214872 kb
Host smart-f2beb48b-aeaa-4e86-9da0-d3ec087f974b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254293378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.4254293378
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2800020699
Short name T150
Test name
Test status
Simulation time 39892902 ps
CPU time 2.6 seconds
Started Jun 04 01:57:40 PM PDT 24
Finished Jun 04 01:57:44 PM PDT 24
Peak memory 215388 kb
Host smart-b558e272-1e13-455b-bc42-258913a0ad6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2800020699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2800020699
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3342589166
Short name T237
Test name
Test status
Simulation time 1581767192 ps
CPU time 37.16 seconds
Started Jun 04 01:57:55 PM PDT 24
Finished Jun 04 01:58:33 PM PDT 24
Peak memory 222504 kb
Host smart-13cfbe1a-ee3c-47fc-9ee3-82b342790c48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342589166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3342589166
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1838629478
Short name T55
Test name
Test status
Simulation time 1379731189 ps
CPU time 14.17 seconds
Started Jun 04 02:00:33 PM PDT 24
Finished Jun 04 02:00:49 PM PDT 24
Peak memory 215620 kb
Host smart-1096bbfc-c5db-491f-8e64-47ba242685c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838629478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1838629478
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2303780326
Short name T100
Test name
Test status
Simulation time 124193667 ps
CPU time 2.3 seconds
Started Jun 04 01:59:50 PM PDT 24
Finished Jun 04 01:59:54 PM PDT 24
Peak memory 214352 kb
Host smart-118b2be7-c0c2-4f29-b5d5-41acf2b67bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303780326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2303780326
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_random.105886186
Short name T249
Test name
Test status
Simulation time 2038450201 ps
CPU time 34.17 seconds
Started Jun 04 01:57:02 PM PDT 24
Finished Jun 04 01:57:37 PM PDT 24
Peak memory 218172 kb
Host smart-eb0c4a35-bc47-4a77-a922-b812643aa1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105886186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.105886186
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.25186223
Short name T328
Test name
Test status
Simulation time 27339664 ps
CPU time 2.09 seconds
Started Jun 04 01:58:59 PM PDT 24
Finished Jun 04 01:59:02 PM PDT 24
Peak memory 214264 kb
Host smart-bdff91fb-9e87-4e25-9f16-64647865b3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25186223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.25186223
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.927242747
Short name T228
Test name
Test status
Simulation time 2558868246 ps
CPU time 57.34 seconds
Started Jun 04 01:59:25 PM PDT 24
Finished Jun 04 02:00:23 PM PDT 24
Peak memory 222552 kb
Host smart-1a651bfc-6658-441c-bd82-bf4562b29306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927242747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.927242747
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3035218885
Short name T273
Test name
Test status
Simulation time 93210388 ps
CPU time 2.1 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:07 PM PDT 24
Peak memory 214296 kb
Host smart-5df05e90-f05d-45f7-af36-a034417dd3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035218885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3035218885
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.906759093
Short name T33
Test name
Test status
Simulation time 629670300 ps
CPU time 4.66 seconds
Started Jun 04 02:00:16 PM PDT 24
Finished Jun 04 02:00:21 PM PDT 24
Peak memory 222608 kb
Host smart-47bb70dd-7f08-485d-ab0f-7a4efd4b4e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906759093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.906759093
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1771987779
Short name T2
Test name
Test status
Simulation time 356498762 ps
CPU time 2.53 seconds
Started Jun 04 02:00:42 PM PDT 24
Finished Jun 04 02:00:46 PM PDT 24
Peak memory 209968 kb
Host smart-ff872977-5498-47a0-a059-219cb3b6f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771987779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1771987779
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1963587555
Short name T959
Test name
Test status
Simulation time 640158081 ps
CPU time 3.05 seconds
Started Jun 04 01:30:25 PM PDT 24
Finished Jun 04 01:30:29 PM PDT 24
Peak memory 214248 kb
Host smart-cc99387d-83cb-4a6a-aa7a-ca9923e28fd6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963587555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1963587555
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.4059552572
Short name T193
Test name
Test status
Simulation time 100060798 ps
CPU time 4.78 seconds
Started Jun 04 01:31:29 PM PDT 24
Finished Jun 04 01:31:34 PM PDT 24
Peak memory 213780 kb
Host smart-723f5d8e-cd8a-446a-a9a0-ceb0205a3c09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059552572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.4059552572
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.254404811
Short name T289
Test name
Test status
Simulation time 76797098 ps
CPU time 3.33 seconds
Started Jun 04 01:57:17 PM PDT 24
Finished Jun 04 01:57:21 PM PDT 24
Peak memory 214348 kb
Host smart-ec10ec25-24cd-48f6-8e58-49e175dda101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254404811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.254404811
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3655298585
Short name T81
Test name
Test status
Simulation time 400723317 ps
CPU time 19.94 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:30 PM PDT 24
Peak memory 222528 kb
Host smart-1baeeacd-6f44-41bd-af2e-33666234116d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655298585 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3655298585
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.447771554
Short name T215
Test name
Test status
Simulation time 79482343 ps
CPU time 2.83 seconds
Started Jun 04 01:57:30 PM PDT 24
Finished Jun 04 01:57:33 PM PDT 24
Peak memory 209028 kb
Host smart-f3d06474-a7be-4e62-864b-9c50c1e67ff9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447771554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.447771554
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.187781337
Short name T113
Test name
Test status
Simulation time 717723085 ps
CPU time 12.97 seconds
Started Jun 04 01:59:45 PM PDT 24
Finished Jun 04 01:59:59 PM PDT 24
Peak memory 220464 kb
Host smart-b1935d07-9de2-4147-8101-d3599ce9535b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187781337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.187781337
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1835235064
Short name T247
Test name
Test status
Simulation time 38839617 ps
CPU time 2.56 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:52 PM PDT 24
Peak memory 214324 kb
Host smart-b077b086-5b5e-47a8-be39-15c2378cc32c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835235064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1835235064
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1894963270
Short name T286
Test name
Test status
Simulation time 99336966 ps
CPU time 3.14 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:21 PM PDT 24
Peak memory 222404 kb
Host smart-c78c2026-afa6-4190-8b51-b3d428d49c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894963270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1894963270
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1508950634
Short name T192
Test name
Test status
Simulation time 226284443 ps
CPU time 4.41 seconds
Started Jun 04 01:59:45 PM PDT 24
Finished Jun 04 01:59:51 PM PDT 24
Peak memory 210376 kb
Host smart-aa5e5cf9-57fe-4815-818f-7f05dd8629ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508950634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1508950634
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.4282455076
Short name T165
Test name
Test status
Simulation time 161677131 ps
CPU time 6.62 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:40 PM PDT 24
Peak memory 218592 kb
Host smart-26a1df8c-a758-4b7d-ad67-79a9f51e273a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282455076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.4282455076
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.612252157
Short name T167
Test name
Test status
Simulation time 88382458 ps
CPU time 2.06 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:32 PM PDT 24
Peak memory 217316 kb
Host smart-fa1d88f4-1a83-4682-ab52-2f0e4f568be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612252157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.612252157
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.783747357
Short name T71
Test name
Test status
Simulation time 44449217 ps
CPU time 2.65 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:21 PM PDT 24
Peak memory 217344 kb
Host smart-f7c7aaed-255b-44b2-be96-fafe112e9e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783747357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.783747357
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2916564330
Short name T323
Test name
Test status
Simulation time 416925835 ps
CPU time 4.33 seconds
Started Jun 04 01:57:09 PM PDT 24
Finished Jun 04 01:57:14 PM PDT 24
Peak memory 218324 kb
Host smart-8effbcfb-4a2f-4bd7-ad30-4f71d6307472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916564330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2916564330
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2926077684
Short name T429
Test name
Test status
Simulation time 53157830 ps
CPU time 3.06 seconds
Started Jun 04 01:57:19 PM PDT 24
Finished Jun 04 01:57:23 PM PDT 24
Peak memory 215244 kb
Host smart-eddb895c-de9c-4430-81c5-35b4d8a44a81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926077684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2926077684
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2585682753
Short name T322
Test name
Test status
Simulation time 60421805 ps
CPU time 3.07 seconds
Started Jun 04 01:58:50 PM PDT 24
Finished Jun 04 01:58:54 PM PDT 24
Peak memory 207076 kb
Host smart-0152dc0d-eca3-450d-965d-fccf6d487b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585682753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2585682753
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3910884572
Short name T350
Test name
Test status
Simulation time 489824384 ps
CPU time 5.77 seconds
Started Jun 04 01:59:37 PM PDT 24
Finished Jun 04 01:59:43 PM PDT 24
Peak memory 214596 kb
Host smart-8793a191-e7e8-4256-9191-24ddac515e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910884572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3910884572
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.212686076
Short name T409
Test name
Test status
Simulation time 2966405494 ps
CPU time 38.93 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 02:00:22 PM PDT 24
Peak memory 215364 kb
Host smart-e290ac70-8fc4-4c9d-bc6b-3b7f3057683d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212686076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.212686076
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2221660415
Short name T68
Test name
Test status
Simulation time 3061666435 ps
CPU time 19.04 seconds
Started Jun 04 01:59:47 PM PDT 24
Finished Jun 04 02:00:07 PM PDT 24
Peak memory 215036 kb
Host smart-e2ae108e-a99d-498d-8196-a7dedb80f152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221660415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2221660415
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3515752966
Short name T329
Test name
Test status
Simulation time 170099199 ps
CPU time 2.96 seconds
Started Jun 04 01:59:56 PM PDT 24
Finished Jun 04 02:00:01 PM PDT 24
Peak memory 214400 kb
Host smart-0ac661d2-1aab-423c-8d55-0515e7354e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515752966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3515752966
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1915893446
Short name T311
Test name
Test status
Simulation time 16972779005 ps
CPU time 445.45 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:07:55 PM PDT 24
Peak memory 222632 kb
Host smart-d844e451-3b0d-4217-ace5-4484998e920b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915893446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1915893446
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2210349532
Short name T260
Test name
Test status
Simulation time 191371217 ps
CPU time 8.92 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:50 PM PDT 24
Peak memory 214348 kb
Host smart-f84e1672-caf0-4992-b10f-caa0ecf184c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210349532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2210349532
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3500873135
Short name T109
Test name
Test status
Simulation time 297022536 ps
CPU time 4.24 seconds
Started Jun 04 02:00:51 PM PDT 24
Finished Jun 04 02:00:57 PM PDT 24
Peak memory 220252 kb
Host smart-9577dccd-275c-478a-a7e0-962678f1e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500873135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3500873135
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1128520800
Short name T339
Test name
Test status
Simulation time 421771880 ps
CPU time 20.82 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:25 PM PDT 24
Peak memory 215336 kb
Host smart-b7e1f5fb-aec7-4970-ab17-ada40bdd973c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128520800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1128520800
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3149488452
Short name T169
Test name
Test status
Simulation time 224155612 ps
CPU time 5.9 seconds
Started Jun 04 01:30:25 PM PDT 24
Finished Jun 04 01:30:32 PM PDT 24
Peak memory 213860 kb
Host smart-b6663659-b47b-4e7d-a21f-ade2977dde64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149488452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3149488452
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.463224596
Short name T183
Test name
Test status
Simulation time 141297532 ps
CPU time 5.35 seconds
Started Jun 04 01:31:10 PM PDT 24
Finished Jun 04 01:31:17 PM PDT 24
Peak memory 213844 kb
Host smart-ff4a4d11-7f10-4ed4-905b-6e8eaa7c738f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463224596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.463224596
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.731478985
Short name T176
Test name
Test status
Simulation time 773105599 ps
CPU time 4.67 seconds
Started Jun 04 01:31:09 PM PDT 24
Finished Jun 04 01:31:15 PM PDT 24
Peak memory 213900 kb
Host smart-ae9d91e8-44e0-41f7-aa80-16100a033987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731478985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.731478985
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2119827368
Short name T191
Test name
Test status
Simulation time 54029455 ps
CPU time 3.18 seconds
Started Jun 04 01:31:19 PM PDT 24
Finished Jun 04 01:31:23 PM PDT 24
Peak memory 213916 kb
Host smart-97e6f521-8b4e-4364-bc67-1cb3f26901fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119827368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2119827368
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.289443305
Short name T179
Test name
Test status
Simulation time 57307008 ps
CPU time 2.97 seconds
Started Jun 04 01:31:29 PM PDT 24
Finished Jun 04 01:31:33 PM PDT 24
Peak memory 213756 kb
Host smart-0d86facb-ae82-4a77-b12c-efa7b44b85f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289443305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.289443305
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.869595070
Short name T170
Test name
Test status
Simulation time 222069201 ps
CPU time 4.69 seconds
Started Jun 04 01:31:29 PM PDT 24
Finished Jun 04 01:31:35 PM PDT 24
Peak memory 213824 kb
Host smart-b001f32e-9e6a-44b5-b84b-ad33adb6d2d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869595070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.869595070
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.563579051
Short name T190
Test name
Test status
Simulation time 1083204765 ps
CPU time 7.05 seconds
Started Jun 04 01:30:42 PM PDT 24
Finished Jun 04 01:30:50 PM PDT 24
Peak memory 213768 kb
Host smart-f6067130-26c0-49ea-a7a5-dcdab9c2fd0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563579051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
563579051
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3804843669
Short name T185
Test name
Test status
Simulation time 337607994 ps
CPU time 5.13 seconds
Started Jun 04 01:30:52 PM PDT 24
Finished Jun 04 01:30:58 PM PDT 24
Peak memory 213876 kb
Host smart-066900cf-d883-4ea8-a904-631a43a6786e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804843669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3804843669
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1123030264
Short name T172
Test name
Test status
Simulation time 1140064683 ps
CPU time 11.06 seconds
Started Jun 04 01:31:01 PM PDT 24
Finished Jun 04 01:31:13 PM PDT 24
Peak memory 216224 kb
Host smart-70c0c2e3-5a11-4906-999c-2780c3fef85f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123030264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1123030264
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1466018323
Short name T415
Test name
Test status
Simulation time 79770934 ps
CPU time 2.92 seconds
Started Jun 04 01:57:02 PM PDT 24
Finished Jun 04 01:57:06 PM PDT 24
Peak memory 222560 kb
Host smart-5f2de8f1-3a9e-4ad2-9f39-8d28a6e5270c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466018323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1466018323
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1149253620
Short name T634
Test name
Test status
Simulation time 245135644 ps
CPU time 2.17 seconds
Started Jun 04 01:57:09 PM PDT 24
Finished Jun 04 01:57:13 PM PDT 24
Peak memory 220968 kb
Host smart-f5807b4a-fead-4a97-acbb-2b770ecc7c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149253620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1149253620
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.4081468483
Short name T586
Test name
Test status
Simulation time 569695858 ps
CPU time 3.34 seconds
Started Jun 04 01:57:03 PM PDT 24
Finished Jun 04 01:57:07 PM PDT 24
Peak memory 207632 kb
Host smart-6fad8f34-e400-4220-98ef-31dd7fde9ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081468483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4081468483
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3342063936
Short name T293
Test name
Test status
Simulation time 100963845 ps
CPU time 2.83 seconds
Started Jun 04 01:58:39 PM PDT 24
Finished Jun 04 01:58:43 PM PDT 24
Peak memory 218444 kb
Host smart-ae391333-336f-4eca-b4e7-8f21f4e6c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342063936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3342063936
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1313083500
Short name T226
Test name
Test status
Simulation time 580344812 ps
CPU time 8.67 seconds
Started Jun 04 01:58:37 PM PDT 24
Finished Jun 04 01:58:47 PM PDT 24
Peak memory 222476 kb
Host smart-06e41035-219c-4dcd-8668-1d2224dd2a6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313083500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1313083500
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2665233869
Short name T235
Test name
Test status
Simulation time 927794855 ps
CPU time 4.68 seconds
Started Jun 04 01:58:44 PM PDT 24
Finished Jun 04 01:58:50 PM PDT 24
Peak memory 214252 kb
Host smart-805efc34-0221-4635-a631-a0c49271742f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665233869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2665233869
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.4040082960
Short name T244
Test name
Test status
Simulation time 356288528 ps
CPU time 3.82 seconds
Started Jun 04 01:59:22 PM PDT 24
Finished Jun 04 01:59:26 PM PDT 24
Peak memory 216956 kb
Host smart-8211ad4a-a101-486a-a7e1-45f507dc15c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040082960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.4040082960
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.4061182414
Short name T372
Test name
Test status
Simulation time 3995565265 ps
CPU time 11.26 seconds
Started Jun 04 01:59:21 PM PDT 24
Finished Jun 04 01:59:33 PM PDT 24
Peak memory 222500 kb
Host smart-e494b2a6-5003-473f-8b84-6a1f2421bd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061182414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.4061182414
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2917361398
Short name T137
Test name
Test status
Simulation time 819438884 ps
CPU time 12.55 seconds
Started Jun 04 01:59:50 PM PDT 24
Finished Jun 04 02:00:05 PM PDT 24
Peak memory 219584 kb
Host smart-228b3c10-f6f7-4632-8af5-48220a015832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917361398 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2917361398
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1564976152
Short name T367
Test name
Test status
Simulation time 257848526 ps
CPU time 16.94 seconds
Started Jun 04 02:00:01 PM PDT 24
Finished Jun 04 02:00:19 PM PDT 24
Peak memory 222616 kb
Host smart-a0a3abbb-771f-49bb-a38f-ffe9084dcc6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564976152 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1564976152
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1785165688
Short name T352
Test name
Test status
Simulation time 367890097 ps
CPU time 4.27 seconds
Started Jun 04 02:00:28 PM PDT 24
Finished Jun 04 02:00:34 PM PDT 24
Peak memory 214324 kb
Host smart-83de2656-7319-45ad-bae1-f38dafa37b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785165688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1785165688
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.958532122
Short name T375
Test name
Test status
Simulation time 369938919 ps
CPU time 2.78 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:30 PM PDT 24
Peak memory 215652 kb
Host smart-f28898de-a3da-4086-9852-12a2fac6ea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958532122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.958532122
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1688803406
Short name T891
Test name
Test status
Simulation time 848758796 ps
CPU time 11.83 seconds
Started Jun 04 02:00:34 PM PDT 24
Finished Jun 04 02:00:47 PM PDT 24
Peak memory 214356 kb
Host smart-acc95cd1-5298-4a02-84cd-2a59e99d645a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688803406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1688803406
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1210049895
Short name T73
Test name
Test status
Simulation time 78726305 ps
CPU time 3.65 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:03 PM PDT 24
Peak memory 209472 kb
Host smart-8adf7b85-5a5e-4fb3-aa66-23e5cbf3ffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210049895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1210049895
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2094815238
Short name T166
Test name
Test status
Simulation time 59608801 ps
CPU time 3.68 seconds
Started Jun 04 01:57:51 PM PDT 24
Finished Jun 04 01:57:55 PM PDT 24
Peak memory 218024 kb
Host smart-946f6d07-35a7-4d91-bb89-ef34df1e0aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094815238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2094815238
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3404217863
Short name T990
Test name
Test status
Simulation time 733819841 ps
CPU time 4.98 seconds
Started Jun 04 01:30:17 PM PDT 24
Finished Jun 04 01:30:23 PM PDT 24
Peak memory 205748 kb
Host smart-722ea5ed-b461-4758-a8ca-c418814f42a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404217863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
404217863
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2557883797
Short name T924
Test name
Test status
Simulation time 654068305 ps
CPU time 9.58 seconds
Started Jun 04 01:30:18 PM PDT 24
Finished Jun 04 01:30:28 PM PDT 24
Peak memory 205692 kb
Host smart-6ed8ae10-4e7c-45bb-b048-06a1f5bbb9f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557883797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
557883797
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1706940929
Short name T1002
Test name
Test status
Simulation time 35080068 ps
CPU time 1.06 seconds
Started Jun 04 01:30:18 PM PDT 24
Finished Jun 04 01:30:20 PM PDT 24
Peak memory 205664 kb
Host smart-5cab2cb2-0a7c-44e4-8328-cabed8511506
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706940929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
706940929
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.480026344
Short name T956
Test name
Test status
Simulation time 208849925 ps
CPU time 2.42 seconds
Started Jun 04 01:30:25 PM PDT 24
Finished Jun 04 01:30:29 PM PDT 24
Peak memory 213960 kb
Host smart-b1001fee-6e38-4e70-9384-270230df6919
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480026344 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.480026344
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1947486439
Short name T986
Test name
Test status
Simulation time 53767722 ps
CPU time 1.09 seconds
Started Jun 04 01:30:16 PM PDT 24
Finished Jun 04 01:30:18 PM PDT 24
Peak memory 205444 kb
Host smart-96222ee3-0f8e-470c-8c8a-0f7f9be77392
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947486439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1947486439
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.400795014
Short name T971
Test name
Test status
Simulation time 22249646 ps
CPU time 0.71 seconds
Started Jun 04 01:30:17 PM PDT 24
Finished Jun 04 01:30:19 PM PDT 24
Peak memory 205352 kb
Host smart-ef4ffb72-005b-443e-9acf-562535e36e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400795014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.400795014
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1450773039
Short name T994
Test name
Test status
Simulation time 85004422 ps
CPU time 1.23 seconds
Started Jun 04 01:30:18 PM PDT 24
Finished Jun 04 01:30:20 PM PDT 24
Peak memory 205700 kb
Host smart-3ddd4432-4e17-433b-9230-30bc0cdb7ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450773039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1450773039
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3728428516
Short name T1072
Test name
Test status
Simulation time 294849574 ps
CPU time 2.52 seconds
Started Jun 04 01:30:17 PM PDT 24
Finished Jun 04 01:30:20 PM PDT 24
Peak memory 214284 kb
Host smart-00122d0a-2df2-4d4c-9d83-2e91883a8b40
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728428516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3728428516
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2700797885
Short name T1037
Test name
Test status
Simulation time 103579233 ps
CPU time 4.56 seconds
Started Jun 04 01:30:16 PM PDT 24
Finished Jun 04 01:30:22 PM PDT 24
Peak memory 214328 kb
Host smart-3ffc7260-46f8-4a9c-a75f-288d57e3c48d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700797885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2700797885
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1670531184
Short name T1069
Test name
Test status
Simulation time 130087505 ps
CPU time 2.23 seconds
Started Jun 04 01:30:17 PM PDT 24
Finished Jun 04 01:30:20 PM PDT 24
Peak memory 213888 kb
Host smart-479f0d31-d231-4b8e-a84b-d201b91c5d6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670531184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1670531184
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4207095460
Short name T181
Test name
Test status
Simulation time 105147082 ps
CPU time 2.89 seconds
Started Jun 04 01:30:15 PM PDT 24
Finished Jun 04 01:30:19 PM PDT 24
Peak memory 213872 kb
Host smart-07495db6-d574-4e47-937b-8d4046c65579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207095460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4207095460
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.4000033124
Short name T979
Test name
Test status
Simulation time 373448285 ps
CPU time 14.55 seconds
Started Jun 04 01:30:26 PM PDT 24
Finished Jun 04 01:30:41 PM PDT 24
Peak memory 205696 kb
Host smart-426ab1f9-2b5a-4186-9910-79f9a208f602
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000033124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.4
000033124
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.369782472
Short name T929
Test name
Test status
Simulation time 2914555500 ps
CPU time 11.06 seconds
Started Jun 04 01:30:24 PM PDT 24
Finished Jun 04 01:30:35 PM PDT 24
Peak memory 205784 kb
Host smart-07a6b2ca-e3b0-471f-99f4-18683cd4241c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369782472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.369782472
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2912481845
Short name T963
Test name
Test status
Simulation time 20562542 ps
CPU time 1 seconds
Started Jun 04 01:30:24 PM PDT 24
Finished Jun 04 01:30:27 PM PDT 24
Peak memory 205516 kb
Host smart-52964fc6-2f0b-48f4-9fc4-8077187b04d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912481845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
912481845
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1054959169
Short name T1012
Test name
Test status
Simulation time 211916565 ps
CPU time 1.67 seconds
Started Jun 04 01:30:26 PM PDT 24
Finished Jun 04 01:30:29 PM PDT 24
Peak memory 213832 kb
Host smart-b999d586-82ff-4000-bc7e-9af4e5005edd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054959169 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1054959169
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3699667070
Short name T1065
Test name
Test status
Simulation time 86038267 ps
CPU time 1.14 seconds
Started Jun 04 01:30:25 PM PDT 24
Finished Jun 04 01:30:28 PM PDT 24
Peak memory 205704 kb
Host smart-0abf3401-8fc7-4904-9e19-64322470a253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699667070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3699667070
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3012712813
Short name T946
Test name
Test status
Simulation time 20636204 ps
CPU time 0.83 seconds
Started Jun 04 01:30:24 PM PDT 24
Finished Jun 04 01:30:26 PM PDT 24
Peak memory 205384 kb
Host smart-0afe7909-1031-4ba6-bfdb-04af386d3191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012712813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3012712813
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.507900912
Short name T162
Test name
Test status
Simulation time 118369471 ps
CPU time 3.9 seconds
Started Jun 04 01:30:25 PM PDT 24
Finished Jun 04 01:30:31 PM PDT 24
Peak memory 205748 kb
Host smart-b054447e-ffc4-4fe8-9490-beb2bbd3234e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507900912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.507900912
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2202104718
Short name T1050
Test name
Test status
Simulation time 80265606 ps
CPU time 2.94 seconds
Started Jun 04 01:30:26 PM PDT 24
Finished Jun 04 01:30:31 PM PDT 24
Peak memory 213936 kb
Host smart-b6951e07-01b4-4373-b8cc-f74dae120a5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202104718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2202104718
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1432966638
Short name T922
Test name
Test status
Simulation time 67740057 ps
CPU time 1.36 seconds
Started Jun 04 01:31:10 PM PDT 24
Finished Jun 04 01:31:12 PM PDT 24
Peak memory 205780 kb
Host smart-88a71677-e81a-4b8c-89c7-c36e04fc0e4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432966638 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1432966638
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1957964623
Short name T1029
Test name
Test status
Simulation time 38615704 ps
CPU time 1.5 seconds
Started Jun 04 01:31:02 PM PDT 24
Finished Jun 04 01:31:05 PM PDT 24
Peak memory 205624 kb
Host smart-665c3854-ee72-44cd-8f42-6193fd43236d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957964623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1957964623
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3875516573
Short name T1017
Test name
Test status
Simulation time 122983477 ps
CPU time 0.97 seconds
Started Jun 04 01:31:02 PM PDT 24
Finished Jun 04 01:31:04 PM PDT 24
Peak memory 205316 kb
Host smart-0743125c-2748-4ecf-8a9b-389a1ad0e337
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875516573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3875516573
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2964925045
Short name T1030
Test name
Test status
Simulation time 119531426 ps
CPU time 2.99 seconds
Started Jun 04 01:31:11 PM PDT 24
Finished Jun 04 01:31:16 PM PDT 24
Peak memory 205648 kb
Host smart-cbe313a8-0663-4763-994d-9f0e7a75c2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964925045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2964925045
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.348192205
Short name T131
Test name
Test status
Simulation time 284711013 ps
CPU time 2.04 seconds
Started Jun 04 01:31:01 PM PDT 24
Finished Jun 04 01:31:04 PM PDT 24
Peak memory 214212 kb
Host smart-a83b0b06-54e9-4154-bc36-1a82ce524838
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348192205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.348192205
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1876230434
Short name T972
Test name
Test status
Simulation time 582483103 ps
CPU time 6.82 seconds
Started Jun 04 01:31:02 PM PDT 24
Finished Jun 04 01:31:10 PM PDT 24
Peak memory 214256 kb
Host smart-66f3471e-d05b-4d62-b4b0-607bb6aede47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876230434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1876230434
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1505294615
Short name T947
Test name
Test status
Simulation time 76119770 ps
CPU time 1.44 seconds
Started Jun 04 01:31:02 PM PDT 24
Finished Jun 04 01:31:04 PM PDT 24
Peak memory 213920 kb
Host smart-c3afee15-059e-4a8d-9842-2714e1e29fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505294615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1505294615
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3538905696
Short name T957
Test name
Test status
Simulation time 81946466 ps
CPU time 1.55 seconds
Started Jun 04 01:31:09 PM PDT 24
Finished Jun 04 01:31:12 PM PDT 24
Peak memory 213932 kb
Host smart-100d7ce6-a13b-4109-b007-5f59b728b79c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538905696 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3538905696
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1845467561
Short name T159
Test name
Test status
Simulation time 58038121 ps
CPU time 1.08 seconds
Started Jun 04 01:31:11 PM PDT 24
Finished Jun 04 01:31:14 PM PDT 24
Peak memory 205704 kb
Host smart-eff62648-f295-45e9-afab-5e9d4165734e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845467561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1845467561
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1993398841
Short name T973
Test name
Test status
Simulation time 44182317 ps
CPU time 0.72 seconds
Started Jun 04 01:31:11 PM PDT 24
Finished Jun 04 01:31:13 PM PDT 24
Peak memory 205384 kb
Host smart-fee884ee-f825-4b2a-9aee-89d7ff4e0bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993398841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1993398841
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1079963992
Short name T163
Test name
Test status
Simulation time 46159104 ps
CPU time 2 seconds
Started Jun 04 01:31:09 PM PDT 24
Finished Jun 04 01:31:12 PM PDT 24
Peak memory 205684 kb
Host smart-3afc8342-bc15-4c3a-bf26-e34f60a066ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079963992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1079963992
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2661668412
Short name T996
Test name
Test status
Simulation time 129090027 ps
CPU time 1.93 seconds
Started Jun 04 01:31:16 PM PDT 24
Finished Jun 04 01:31:19 PM PDT 24
Peak memory 214192 kb
Host smart-3a4eff5d-c9fd-43a6-a2f2-48eb9b300246
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661668412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2661668412
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2910197263
Short name T1051
Test name
Test status
Simulation time 1025374419 ps
CPU time 12.79 seconds
Started Jun 04 01:31:11 PM PDT 24
Finished Jun 04 01:31:26 PM PDT 24
Peak memory 214220 kb
Host smart-741deb55-8179-4979-8b55-035133187f34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910197263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2910197263
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2659452320
Short name T991
Test name
Test status
Simulation time 231054413 ps
CPU time 2.75 seconds
Started Jun 04 01:31:15 PM PDT 24
Finished Jun 04 01:31:19 PM PDT 24
Peak memory 213820 kb
Host smart-88de9c4e-e08f-48e3-840d-f8ec7670a7f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659452320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2659452320
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3069296195
Short name T196
Test name
Test status
Simulation time 34385647 ps
CPU time 1.06 seconds
Started Jun 04 01:31:16 PM PDT 24
Finished Jun 04 01:31:18 PM PDT 24
Peak memory 205604 kb
Host smart-e008781d-57c5-4f47-944c-e4980eff9b17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069296195 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3069296195
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1279412938
Short name T949
Test name
Test status
Simulation time 124153107 ps
CPU time 1.26 seconds
Started Jun 04 01:31:16 PM PDT 24
Finished Jun 04 01:31:18 PM PDT 24
Peak memory 205652 kb
Host smart-14d4068b-0dda-47fc-bee8-812924661fed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279412938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1279412938
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2316490443
Short name T1020
Test name
Test status
Simulation time 40178199 ps
CPU time 0.83 seconds
Started Jun 04 01:31:15 PM PDT 24
Finished Jun 04 01:31:16 PM PDT 24
Peak memory 205312 kb
Host smart-49bdf0a5-153f-4852-a952-79c3b05d067c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316490443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2316490443
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2526384083
Short name T1040
Test name
Test status
Simulation time 37056057 ps
CPU time 1.47 seconds
Started Jun 04 01:31:09 PM PDT 24
Finished Jun 04 01:31:12 PM PDT 24
Peak memory 205684 kb
Host smart-d3b2ae86-2169-40bf-911e-5a30f6904626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526384083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2526384083
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3104062785
Short name T1061
Test name
Test status
Simulation time 209289729 ps
CPU time 1.35 seconds
Started Jun 04 01:31:11 PM PDT 24
Finished Jun 04 01:31:14 PM PDT 24
Peak memory 214192 kb
Host smart-9a4cbc34-ff8d-4da4-be78-75600cb48251
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104062785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3104062785
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3274312541
Short name T1071
Test name
Test status
Simulation time 263132835 ps
CPU time 3.74 seconds
Started Jun 04 01:31:12 PM PDT 24
Finished Jun 04 01:31:17 PM PDT 24
Peak memory 222416 kb
Host smart-ee1fe96e-5b7d-49f8-8243-d2fcce061aa8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274312541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3274312541
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1162923160
Short name T1068
Test name
Test status
Simulation time 53232179 ps
CPU time 3.63 seconds
Started Jun 04 01:31:13 PM PDT 24
Finished Jun 04 01:31:18 PM PDT 24
Peak memory 213816 kb
Host smart-1e647584-cdcd-4227-bc7a-ad56338b193d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162923160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1162923160
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.290339345
Short name T907
Test name
Test status
Simulation time 54835658 ps
CPU time 3.16 seconds
Started Jun 04 01:31:12 PM PDT 24
Finished Jun 04 01:31:17 PM PDT 24
Peak memory 213848 kb
Host smart-3ced8fd2-ca58-4760-93d1-42c7a2c28f73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290339345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.290339345
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.11273109
Short name T926
Test name
Test status
Simulation time 67572603 ps
CPU time 1.89 seconds
Started Jun 04 01:31:09 PM PDT 24
Finished Jun 04 01:31:12 PM PDT 24
Peak memory 213960 kb
Host smart-5f74c17b-bf8e-48a4-843f-8ab79c9b3c9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11273109 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.11273109
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.463554566
Short name T1041
Test name
Test status
Simulation time 108823631 ps
CPU time 1.45 seconds
Started Jun 04 01:31:09 PM PDT 24
Finished Jun 04 01:31:11 PM PDT 24
Peak memory 205492 kb
Host smart-cecdf2ff-a785-4851-98f6-13478ec26ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463554566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.463554566
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.690293452
Short name T997
Test name
Test status
Simulation time 9819417 ps
CPU time 0.81 seconds
Started Jun 04 01:31:10 PM PDT 24
Finished Jun 04 01:31:13 PM PDT 24
Peak memory 205392 kb
Host smart-cfaf9267-15f3-4315-899d-0551e87f1576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690293452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.690293452
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3200502093
Short name T1075
Test name
Test status
Simulation time 95635262 ps
CPU time 2.67 seconds
Started Jun 04 01:31:15 PM PDT 24
Finished Jun 04 01:31:18 PM PDT 24
Peak memory 205616 kb
Host smart-1f1032b1-a7bb-48cc-8c3d-1b0e8a6b5e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200502093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3200502093
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2640408155
Short name T135
Test name
Test status
Simulation time 174665929 ps
CPU time 1.95 seconds
Started Jun 04 01:31:09 PM PDT 24
Finished Jun 04 01:31:12 PM PDT 24
Peak memory 214244 kb
Host smart-3ce16ff6-87a5-45e7-ad0e-2316da8b5470
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640408155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2640408155
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1463612855
Short name T978
Test name
Test status
Simulation time 543271512 ps
CPU time 6.65 seconds
Started Jun 04 01:31:11 PM PDT 24
Finished Jun 04 01:31:19 PM PDT 24
Peak memory 214284 kb
Host smart-acd2df09-0e0d-458b-84a5-b9996aaf89af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463612855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1463612855
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.161136516
Short name T975
Test name
Test status
Simulation time 133895866 ps
CPU time 2.66 seconds
Started Jun 04 01:31:12 PM PDT 24
Finished Jun 04 01:31:16 PM PDT 24
Peak memory 213892 kb
Host smart-c6613d90-8911-46ec-9658-94eb03035470
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161136516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.161136516
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2597986597
Short name T925
Test name
Test status
Simulation time 88514660 ps
CPU time 1.51 seconds
Started Jun 04 01:31:17 PM PDT 24
Finished Jun 04 01:31:20 PM PDT 24
Peak memory 213936 kb
Host smart-4b696d49-219e-4eac-900d-0bbe0f8056fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597986597 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2597986597
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.248236604
Short name T1070
Test name
Test status
Simulation time 54275062 ps
CPU time 1.07 seconds
Started Jun 04 01:31:18 PM PDT 24
Finished Jun 04 01:31:21 PM PDT 24
Peak memory 205612 kb
Host smart-a7fc3486-ca0f-416e-be6e-bf204f90f3e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248236604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.248236604
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2736962119
Short name T985
Test name
Test status
Simulation time 24557561 ps
CPU time 0.74 seconds
Started Jun 04 01:31:19 PM PDT 24
Finished Jun 04 01:31:21 PM PDT 24
Peak memory 205372 kb
Host smart-78bac48e-2ab3-4859-98b2-5560f522a1e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736962119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2736962119
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3776918365
Short name T964
Test name
Test status
Simulation time 134516212 ps
CPU time 2.53 seconds
Started Jun 04 01:31:21 PM PDT 24
Finished Jun 04 01:31:24 PM PDT 24
Peak memory 205756 kb
Host smart-35a4d7ea-ef40-4142-a9b0-d9afaa407ce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776918365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3776918365
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3508918644
Short name T969
Test name
Test status
Simulation time 332620004 ps
CPU time 4.75 seconds
Started Jun 04 01:31:11 PM PDT 24
Finished Jun 04 01:31:18 PM PDT 24
Peak memory 214248 kb
Host smart-5b2617dc-0d75-44db-af72-75b1bdc9397d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508918644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3508918644
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3387175574
Short name T1033
Test name
Test status
Simulation time 32206443 ps
CPU time 1.8 seconds
Started Jun 04 01:31:22 PM PDT 24
Finished Jun 04 01:31:25 PM PDT 24
Peak memory 213852 kb
Host smart-408a580e-b9f0-4033-ad7d-74e6ed0b6f6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387175574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3387175574
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.867896764
Short name T1022
Test name
Test status
Simulation time 273778565 ps
CPU time 4.82 seconds
Started Jun 04 01:31:18 PM PDT 24
Finished Jun 04 01:31:24 PM PDT 24
Peak memory 213984 kb
Host smart-1d6926e3-a08b-4b2c-a9d2-73d477521361
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867896764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.867896764
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.241483067
Short name T974
Test name
Test status
Simulation time 117277815 ps
CPU time 2.16 seconds
Started Jun 04 01:31:23 PM PDT 24
Finished Jun 04 01:31:26 PM PDT 24
Peak memory 219336 kb
Host smart-80457f5e-dff2-47af-a907-b9c854377362
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241483067 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.241483067
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4098519891
Short name T1059
Test name
Test status
Simulation time 91092396 ps
CPU time 1.11 seconds
Started Jun 04 01:31:22 PM PDT 24
Finished Jun 04 01:31:24 PM PDT 24
Peak memory 205560 kb
Host smart-24defea0-e89d-407f-ab6e-565ea23dd655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098519891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.4098519891
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3661347410
Short name T967
Test name
Test status
Simulation time 18990975 ps
CPU time 0.73 seconds
Started Jun 04 01:31:17 PM PDT 24
Finished Jun 04 01:31:19 PM PDT 24
Peak memory 205324 kb
Host smart-b5f53a98-1800-42e5-9709-56f5823b8aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661347410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3661347410
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2379952703
Short name T1024
Test name
Test status
Simulation time 132958845 ps
CPU time 2.29 seconds
Started Jun 04 01:31:22 PM PDT 24
Finished Jun 04 01:31:25 PM PDT 24
Peak memory 213848 kb
Host smart-08cc3177-d247-4d64-9496-411e21d76a05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379952703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2379952703
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.997492970
Short name T129
Test name
Test status
Simulation time 223773747 ps
CPU time 3.14 seconds
Started Jun 04 01:31:22 PM PDT 24
Finished Jun 04 01:31:26 PM PDT 24
Peak memory 214196 kb
Host smart-607a118c-dbfb-4908-9d34-aa74afd3ba4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997492970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.997492970
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2962580102
Short name T1006
Test name
Test status
Simulation time 215849073 ps
CPU time 7.08 seconds
Started Jun 04 01:31:18 PM PDT 24
Finished Jun 04 01:31:26 PM PDT 24
Peak memory 220716 kb
Host smart-44bbd726-9319-40c7-b745-b7ed84658fec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962580102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2962580102
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.161395771
Short name T1010
Test name
Test status
Simulation time 94920248 ps
CPU time 3.46 seconds
Started Jun 04 01:31:18 PM PDT 24
Finished Jun 04 01:31:23 PM PDT 24
Peak memory 213924 kb
Host smart-d344ca4c-2886-4f31-a2fc-62cb2ae68d71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161395771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.161395771
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.801598741
Short name T912
Test name
Test status
Simulation time 17415008 ps
CPU time 1.35 seconds
Started Jun 04 01:31:28 PM PDT 24
Finished Jun 04 01:31:31 PM PDT 24
Peak memory 205624 kb
Host smart-4cf6b279-6bb0-4071-8d41-03a268e38fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801598741 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.801598741
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1367840841
Short name T942
Test name
Test status
Simulation time 25159408 ps
CPU time 1.08 seconds
Started Jun 04 01:31:18 PM PDT 24
Finished Jun 04 01:31:21 PM PDT 24
Peak memory 205588 kb
Host smart-dddda54d-ff22-4747-ad5b-f3f2e4c65170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367840841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1367840841
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2106293247
Short name T961
Test name
Test status
Simulation time 14108443 ps
CPU time 0.91 seconds
Started Jun 04 01:31:20 PM PDT 24
Finished Jun 04 01:31:22 PM PDT 24
Peak memory 205524 kb
Host smart-9eb8d423-75af-4011-9f2b-78bdc1b1b37c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106293247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2106293247
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4010974868
Short name T935
Test name
Test status
Simulation time 96032096 ps
CPU time 1.45 seconds
Started Jun 04 01:31:20 PM PDT 24
Finished Jun 04 01:31:22 PM PDT 24
Peak memory 205712 kb
Host smart-6956a62b-74ce-497b-ac7b-bbf852a1248e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010974868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.4010974868
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2910706902
Short name T1047
Test name
Test status
Simulation time 33395554 ps
CPU time 1.35 seconds
Started Jun 04 01:31:18 PM PDT 24
Finished Jun 04 01:31:20 PM PDT 24
Peak memory 214340 kb
Host smart-7c0f6eda-792f-4d6d-b00f-79de48264901
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910706902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2910706902
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1690867875
Short name T953
Test name
Test status
Simulation time 275908307 ps
CPU time 7.61 seconds
Started Jun 04 01:31:20 PM PDT 24
Finished Jun 04 01:31:29 PM PDT 24
Peak memory 220192 kb
Host smart-d20e75bb-d0e4-414b-a442-19642fcaac5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690867875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1690867875
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3855197410
Short name T1007
Test name
Test status
Simulation time 1305851252 ps
CPU time 4.62 seconds
Started Jun 04 01:31:19 PM PDT 24
Finished Jun 04 01:31:25 PM PDT 24
Peak memory 216940 kb
Host smart-e5224779-c3cf-4e42-9cc6-b378ab84e603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855197410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3855197410
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2476851405
Short name T175
Test name
Test status
Simulation time 1148261260 ps
CPU time 4.95 seconds
Started Jun 04 01:31:19 PM PDT 24
Finished Jun 04 01:31:25 PM PDT 24
Peak memory 213972 kb
Host smart-29a93c68-5e0b-4d2d-bd44-0d887bba03a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476851405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2476851405
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2770852883
Short name T1023
Test name
Test status
Simulation time 22043533 ps
CPU time 1.4 seconds
Started Jun 04 01:31:26 PM PDT 24
Finished Jun 04 01:31:28 PM PDT 24
Peak memory 213924 kb
Host smart-a5c70fce-9177-4527-b366-73dfeb3b8f3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770852883 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2770852883
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2058522324
Short name T923
Test name
Test status
Simulation time 37722813 ps
CPU time 0.93 seconds
Started Jun 04 01:31:25 PM PDT 24
Finished Jun 04 01:31:26 PM PDT 24
Peak memory 205452 kb
Host smart-b7075cb0-2687-4bec-9153-8054d24731d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058522324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2058522324
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2311397160
Short name T931
Test name
Test status
Simulation time 14052343 ps
CPU time 0.75 seconds
Started Jun 04 01:31:28 PM PDT 24
Finished Jun 04 01:31:29 PM PDT 24
Peak memory 205372 kb
Host smart-52ff6fa6-176b-45c8-a996-833af1dfdbf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311397160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2311397160
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1149022961
Short name T1064
Test name
Test status
Simulation time 206936742 ps
CPU time 1.63 seconds
Started Jun 04 01:31:31 PM PDT 24
Finished Jun 04 01:31:33 PM PDT 24
Peak memory 205608 kb
Host smart-9a37f230-7a25-40d3-b7d4-5751e79e9ef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149022961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1149022961
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3751128223
Short name T133
Test name
Test status
Simulation time 557019887 ps
CPU time 4.7 seconds
Started Jun 04 01:31:28 PM PDT 24
Finished Jun 04 01:31:34 PM PDT 24
Peak memory 214184 kb
Host smart-844f900f-56c7-4c3c-89e9-34f375f200ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751128223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3751128223
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1826262086
Short name T1004
Test name
Test status
Simulation time 341314657 ps
CPU time 4.82 seconds
Started Jun 04 01:31:27 PM PDT 24
Finished Jun 04 01:31:33 PM PDT 24
Peak memory 214264 kb
Host smart-48a883bc-53df-4073-87dd-42411218ad2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826262086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1826262086
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.9998303
Short name T948
Test name
Test status
Simulation time 576890934 ps
CPU time 3.79 seconds
Started Jun 04 01:31:34 PM PDT 24
Finished Jun 04 01:31:38 PM PDT 24
Peak memory 213848 kb
Host smart-65b97358-e758-47f0-a744-037566881a29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9998303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.9998303
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2451523532
Short name T976
Test name
Test status
Simulation time 72385776 ps
CPU time 1.32 seconds
Started Jun 04 01:31:27 PM PDT 24
Finished Jun 04 01:31:29 PM PDT 24
Peak memory 216932 kb
Host smart-90dd7eb2-d63b-488f-ac86-9d6187c730c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451523532 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2451523532
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1407819525
Short name T161
Test name
Test status
Simulation time 79530707 ps
CPU time 1.11 seconds
Started Jun 04 01:31:30 PM PDT 24
Finished Jun 04 01:31:31 PM PDT 24
Peak memory 205636 kb
Host smart-61126ede-e7be-4164-9f9b-688802cfbb22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407819525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1407819525
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1737299726
Short name T951
Test name
Test status
Simulation time 16186967 ps
CPU time 0.78 seconds
Started Jun 04 01:31:31 PM PDT 24
Finished Jun 04 01:31:33 PM PDT 24
Peak memory 205304 kb
Host smart-ce2df112-aebe-453e-8152-12736e4f6156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737299726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1737299726
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.539492915
Short name T1034
Test name
Test status
Simulation time 169346294 ps
CPU time 3.56 seconds
Started Jun 04 01:31:28 PM PDT 24
Finished Jun 04 01:31:33 PM PDT 24
Peak memory 205680 kb
Host smart-2a31042d-53d7-4242-bf76-4454af8d950c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539492915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.539492915
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1966288362
Short name T992
Test name
Test status
Simulation time 333146436 ps
CPU time 3.63 seconds
Started Jun 04 01:31:29 PM PDT 24
Finished Jun 04 01:31:33 PM PDT 24
Peak memory 214192 kb
Host smart-258a0900-6fc9-4fb0-a05e-1de29fb27826
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966288362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1966288362
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2718243016
Short name T128
Test name
Test status
Simulation time 362731131 ps
CPU time 13.65 seconds
Started Jun 04 01:31:27 PM PDT 24
Finished Jun 04 01:31:42 PM PDT 24
Peak memory 214156 kb
Host smart-cbcc1c55-82f0-4f5b-be5b-608148b20fcf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718243016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2718243016
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.4208089551
Short name T941
Test name
Test status
Simulation time 82053634 ps
CPU time 1.65 seconds
Started Jun 04 01:31:25 PM PDT 24
Finished Jun 04 01:31:28 PM PDT 24
Peak memory 221636 kb
Host smart-2513036c-bbb0-4f8b-a98c-d1b423d4ea9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208089551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.4208089551
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3088952038
Short name T968
Test name
Test status
Simulation time 30688635 ps
CPU time 1.94 seconds
Started Jun 04 01:31:28 PM PDT 24
Finished Jun 04 01:31:30 PM PDT 24
Peak memory 213852 kb
Host smart-4a270590-7698-4d8d-ac2d-f68572d2adbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088952038 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3088952038
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.597420713
Short name T1042
Test name
Test status
Simulation time 134797031 ps
CPU time 1.66 seconds
Started Jun 04 01:31:27 PM PDT 24
Finished Jun 04 01:31:29 PM PDT 24
Peak memory 205652 kb
Host smart-37905c77-0739-4d5c-a902-46358367ef3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597420713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.597420713
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3828495879
Short name T958
Test name
Test status
Simulation time 11645803 ps
CPU time 0.91 seconds
Started Jun 04 01:31:26 PM PDT 24
Finished Jun 04 01:31:28 PM PDT 24
Peak memory 205384 kb
Host smart-9cd2d184-c449-451e-9bd0-35c1ee9edd89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828495879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3828495879
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3514780422
Short name T160
Test name
Test status
Simulation time 36201407 ps
CPU time 1.29 seconds
Started Jun 04 01:31:28 PM PDT 24
Finished Jun 04 01:31:31 PM PDT 24
Peak memory 205712 kb
Host smart-5b2e78bf-872c-4a91-807e-377e3a8125c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514780422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3514780422
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2194090937
Short name T938
Test name
Test status
Simulation time 144285874 ps
CPU time 2.74 seconds
Started Jun 04 01:31:25 PM PDT 24
Finished Jun 04 01:31:28 PM PDT 24
Peak memory 214188 kb
Host smart-836d7f8d-135c-4d3e-a84b-e366a43f8589
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194090937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2194090937
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.137930505
Short name T1027
Test name
Test status
Simulation time 383913475 ps
CPU time 13.99 seconds
Started Jun 04 01:31:27 PM PDT 24
Finished Jun 04 01:31:42 PM PDT 24
Peak memory 214160 kb
Host smart-f1880c81-e304-43c2-a5e3-d094acab8240
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137930505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.137930505
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3894149996
Short name T987
Test name
Test status
Simulation time 184008010 ps
CPU time 3.9 seconds
Started Jun 04 01:31:29 PM PDT 24
Finished Jun 04 01:31:34 PM PDT 24
Peak memory 213840 kb
Host smart-18c9a6d0-eee0-401f-b183-b0eb10cccb4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894149996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3894149996
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.627084566
Short name T943
Test name
Test status
Simulation time 371473532 ps
CPU time 14.54 seconds
Started Jun 04 01:30:33 PM PDT 24
Finished Jun 04 01:30:48 PM PDT 24
Peak memory 205616 kb
Host smart-c04c000a-4c23-488c-82ac-3de90e6af6b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627084566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.627084566
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3098695885
Short name T909
Test name
Test status
Simulation time 3579772730 ps
CPU time 26.33 seconds
Started Jun 04 01:30:35 PM PDT 24
Finished Jun 04 01:31:02 PM PDT 24
Peak memory 205676 kb
Host smart-8f574112-bc21-4747-b17c-61ee65798cda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098695885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
098695885
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.748627777
Short name T988
Test name
Test status
Simulation time 33838768 ps
CPU time 0.96 seconds
Started Jun 04 01:30:35 PM PDT 24
Finished Jun 04 01:30:37 PM PDT 24
Peak memory 205364 kb
Host smart-b68f5d0e-e116-4d3c-83b6-cbdc7f00c18e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748627777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.748627777
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3844174812
Short name T944
Test name
Test status
Simulation time 23024979 ps
CPU time 1.13 seconds
Started Jun 04 01:30:35 PM PDT 24
Finished Jun 04 01:30:37 PM PDT 24
Peak memory 205748 kb
Host smart-b5891ea7-a145-419e-8fc6-fac7e5db5f74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844174812 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3844174812
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3159721624
Short name T156
Test name
Test status
Simulation time 28257506 ps
CPU time 1.08 seconds
Started Jun 04 01:30:35 PM PDT 24
Finished Jun 04 01:30:36 PM PDT 24
Peak memory 205664 kb
Host smart-15decb63-2027-4c23-bad4-41fbf45cb5ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159721624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3159721624
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3277885714
Short name T914
Test name
Test status
Simulation time 14522732 ps
CPU time 0.87 seconds
Started Jun 04 01:30:33 PM PDT 24
Finished Jun 04 01:30:35 PM PDT 24
Peak memory 205572 kb
Host smart-54757a70-ae5f-49b6-8367-00c701ec9f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277885714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3277885714
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3641268064
Short name T158
Test name
Test status
Simulation time 58137267 ps
CPU time 1.52 seconds
Started Jun 04 01:30:33 PM PDT 24
Finished Jun 04 01:30:35 PM PDT 24
Peak memory 205640 kb
Host smart-eef84098-7bfb-4cd6-a97d-67940d2d78e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641268064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3641268064
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.935193433
Short name T989
Test name
Test status
Simulation time 122154746 ps
CPU time 2.31 seconds
Started Jun 04 01:30:25 PM PDT 24
Finished Jun 04 01:30:28 PM PDT 24
Peak memory 214136 kb
Host smart-d856cf42-0918-418e-afad-44d66951ee0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935193433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.935193433
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3634426849
Short name T1021
Test name
Test status
Simulation time 73954676 ps
CPU time 3.79 seconds
Started Jun 04 01:30:25 PM PDT 24
Finished Jun 04 01:30:30 PM PDT 24
Peak memory 214176 kb
Host smart-06ff6a7f-f53d-4b95-bb3d-4e904cdcfd36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634426849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3634426849
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3057277960
Short name T1013
Test name
Test status
Simulation time 312757419 ps
CPU time 2.5 seconds
Started Jun 04 01:30:32 PM PDT 24
Finished Jun 04 01:30:35 PM PDT 24
Peak memory 215868 kb
Host smart-45aa3a57-5a03-4bb7-9aeb-f2d252295725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057277960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3057277960
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3297247622
Short name T182
Test name
Test status
Simulation time 380607247 ps
CPU time 3.81 seconds
Started Jun 04 01:30:34 PM PDT 24
Finished Jun 04 01:30:39 PM PDT 24
Peak memory 205736 kb
Host smart-80fedf4a-73a2-4676-b280-ffccb370c51b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297247622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3297247622
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.465314371
Short name T1062
Test name
Test status
Simulation time 12533773 ps
CPU time 0.76 seconds
Started Jun 04 01:31:27 PM PDT 24
Finished Jun 04 01:31:29 PM PDT 24
Peak memory 205308 kb
Host smart-6463d39f-fc53-41ec-a6c6-13baea4d29e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465314371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.465314371
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1846185689
Short name T977
Test name
Test status
Simulation time 26990570 ps
CPU time 0.76 seconds
Started Jun 04 01:31:26 PM PDT 24
Finished Jun 04 01:31:28 PM PDT 24
Peak memory 205300 kb
Host smart-d8d3ae9b-0fc9-4ea6-bb09-86953b99d5cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846185689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1846185689
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1228276957
Short name T908
Test name
Test status
Simulation time 117191602 ps
CPU time 0.72 seconds
Started Jun 04 01:31:26 PM PDT 24
Finished Jun 04 01:31:27 PM PDT 24
Peak memory 205452 kb
Host smart-a64332a9-a9f7-45d8-9c46-bdc9e67b83ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228276957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1228276957
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.791780924
Short name T1067
Test name
Test status
Simulation time 103558239 ps
CPU time 0.81 seconds
Started Jun 04 01:31:31 PM PDT 24
Finished Jun 04 01:31:32 PM PDT 24
Peak memory 205304 kb
Host smart-0a8ea574-2c05-450f-a02d-b9c0f5ec270d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791780924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.791780924
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1964405953
Short name T1008
Test name
Test status
Simulation time 35570856 ps
CPU time 0.85 seconds
Started Jun 04 01:31:29 PM PDT 24
Finished Jun 04 01:31:30 PM PDT 24
Peak memory 205340 kb
Host smart-1de388ae-849e-4d7f-b425-151e28826033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964405953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1964405953
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3970133315
Short name T933
Test name
Test status
Simulation time 35946294 ps
CPU time 0.73 seconds
Started Jun 04 01:31:27 PM PDT 24
Finished Jun 04 01:31:29 PM PDT 24
Peak memory 205288 kb
Host smart-3f710513-58b7-46ad-8d80-cf244a85e572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970133315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3970133315
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1499738455
Short name T913
Test name
Test status
Simulation time 27720643 ps
CPU time 0.76 seconds
Started Jun 04 01:31:28 PM PDT 24
Finished Jun 04 01:31:30 PM PDT 24
Peak memory 205364 kb
Host smart-bca9c549-b971-4515-a594-0b5390c71cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499738455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1499738455
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2908750979
Short name T940
Test name
Test status
Simulation time 17602203 ps
CPU time 0.85 seconds
Started Jun 04 01:31:35 PM PDT 24
Finished Jun 04 01:31:36 PM PDT 24
Peak memory 205360 kb
Host smart-a1fdba53-b5d7-44ce-84f1-b71d6b6c4c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908750979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2908750979
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4120875750
Short name T981
Test name
Test status
Simulation time 13059624 ps
CPU time 0.75 seconds
Started Jun 04 01:31:35 PM PDT 24
Finished Jun 04 01:31:37 PM PDT 24
Peak memory 205332 kb
Host smart-ee2be136-5704-4776-b7b1-da16699f187c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120875750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.4120875750
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.307632789
Short name T1036
Test name
Test status
Simulation time 9312705 ps
CPU time 0.82 seconds
Started Jun 04 01:31:34 PM PDT 24
Finished Jun 04 01:31:35 PM PDT 24
Peak memory 205364 kb
Host smart-c82adb46-ce60-4d61-825f-5ba6d8a907d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307632789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.307632789
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2008560103
Short name T1063
Test name
Test status
Simulation time 1028360504 ps
CPU time 17.87 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:31:00 PM PDT 24
Peak memory 205740 kb
Host smart-7c3dc296-93e0-4d9e-a175-adbe92c0dff9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008560103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
008560103
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3335723493
Short name T960
Test name
Test status
Simulation time 829491073 ps
CPU time 10.34 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:30:52 PM PDT 24
Peak memory 205716 kb
Host smart-e6535022-662f-4be0-bef3-092e67432cdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335723493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
335723493
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1342681553
Short name T1016
Test name
Test status
Simulation time 111143850 ps
CPU time 1.25 seconds
Started Jun 04 01:30:34 PM PDT 24
Finished Jun 04 01:30:36 PM PDT 24
Peak memory 205724 kb
Host smart-e2ffedc8-cca8-4ab6-9b03-386521dcb6fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342681553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
342681553
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2753167984
Short name T906
Test name
Test status
Simulation time 18818663 ps
CPU time 1.28 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:30:43 PM PDT 24
Peak memory 213876 kb
Host smart-ffccc475-f7d5-4b35-b022-6c0ae3e0d150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753167984 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2753167984
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1897792131
Short name T1055
Test name
Test status
Simulation time 35446255 ps
CPU time 1.08 seconds
Started Jun 04 01:30:35 PM PDT 24
Finished Jun 04 01:30:37 PM PDT 24
Peak memory 205616 kb
Host smart-d1ad1490-763c-4731-b14d-8ee163cea63e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897792131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1897792131
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3404649904
Short name T1053
Test name
Test status
Simulation time 114265072 ps
CPU time 0.7 seconds
Started Jun 04 01:30:34 PM PDT 24
Finished Jun 04 01:30:35 PM PDT 24
Peak memory 205268 kb
Host smart-e0c1f322-2851-4944-ae2f-071aee9f9e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404649904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3404649904
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2720270217
Short name T999
Test name
Test status
Simulation time 147919375 ps
CPU time 2.5 seconds
Started Jun 04 01:30:42 PM PDT 24
Finished Jun 04 01:30:46 PM PDT 24
Peak memory 205684 kb
Host smart-9aec0c69-3eda-4195-831a-a03e2e12d68a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720270217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2720270217
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1497386939
Short name T1003
Test name
Test status
Simulation time 146449930 ps
CPU time 2.56 seconds
Started Jun 04 01:30:35 PM PDT 24
Finished Jun 04 01:30:39 PM PDT 24
Peak memory 214264 kb
Host smart-1dc2ee56-fcea-43ab-9aaf-add11b5a95b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497386939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1497386939
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.9128999
Short name T134
Test name
Test status
Simulation time 363219825 ps
CPU time 9.15 seconds
Started Jun 04 01:30:34 PM PDT 24
Finished Jun 04 01:30:44 PM PDT 24
Peak memory 214236 kb
Host smart-ece94f8e-2d13-4734-8f18-627e8c18c0e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9128999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_S
EQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.key
mgr_shadow_reg_errors_with_csr_rw.9128999
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.73860428
Short name T911
Test name
Test status
Simulation time 355781027 ps
CPU time 1.9 seconds
Started Jun 04 01:30:34 PM PDT 24
Finished Jun 04 01:30:37 PM PDT 24
Peak memory 213780 kb
Host smart-8b5bbbc2-bf9f-4369-9f6e-b91dc84f3f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73860428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.73860428
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.395607818
Short name T178
Test name
Test status
Simulation time 419696932 ps
CPU time 9.75 seconds
Started Jun 04 01:30:34 PM PDT 24
Finished Jun 04 01:30:44 PM PDT 24
Peak memory 205536 kb
Host smart-4c67feab-5271-4bec-b568-f8ed89904cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395607818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
395607818
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2286420581
Short name T1066
Test name
Test status
Simulation time 45021539 ps
CPU time 0.84 seconds
Started Jun 04 01:31:37 PM PDT 24
Finished Jun 04 01:31:38 PM PDT 24
Peak memory 205376 kb
Host smart-d411f13b-9c61-41b1-ba61-f72859cc8700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286420581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2286420581
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2436234326
Short name T1060
Test name
Test status
Simulation time 12828631 ps
CPU time 0.73 seconds
Started Jun 04 01:31:35 PM PDT 24
Finished Jun 04 01:31:36 PM PDT 24
Peak memory 205292 kb
Host smart-52652045-1eef-4617-8f8f-1a552355c25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436234326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2436234326
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2199140559
Short name T970
Test name
Test status
Simulation time 9257697 ps
CPU time 0.73 seconds
Started Jun 04 01:31:35 PM PDT 24
Finished Jun 04 01:31:37 PM PDT 24
Peak memory 205384 kb
Host smart-b2a7f746-f4b2-422a-9021-30c4b0e27382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199140559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2199140559
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3625440542
Short name T1046
Test name
Test status
Simulation time 7837625 ps
CPU time 0.72 seconds
Started Jun 04 01:31:37 PM PDT 24
Finished Jun 04 01:31:38 PM PDT 24
Peak memory 205296 kb
Host smart-ad5ce52f-02d8-4703-bcc0-ffdffeccbe57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625440542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3625440542
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4095773816
Short name T1043
Test name
Test status
Simulation time 10933741 ps
CPU time 0.81 seconds
Started Jun 04 01:31:36 PM PDT 24
Finished Jun 04 01:31:38 PM PDT 24
Peak memory 205384 kb
Host smart-8452de98-201a-45e5-8b13-754fdd472f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095773816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.4095773816
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1657895248
Short name T965
Test name
Test status
Simulation time 48500573 ps
CPU time 0.7 seconds
Started Jun 04 01:31:38 PM PDT 24
Finished Jun 04 01:31:39 PM PDT 24
Peak memory 205364 kb
Host smart-3a9a5441-1984-40c8-a892-796744bb7ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657895248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1657895248
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3557252426
Short name T962
Test name
Test status
Simulation time 11628227 ps
CPU time 0.68 seconds
Started Jun 04 01:31:35 PM PDT 24
Finished Jun 04 01:31:37 PM PDT 24
Peak memory 205336 kb
Host smart-c11de89c-8654-4423-b95f-8d884d701037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557252426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3557252426
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2477357594
Short name T998
Test name
Test status
Simulation time 13442795 ps
CPU time 0.76 seconds
Started Jun 04 01:31:39 PM PDT 24
Finished Jun 04 01:31:40 PM PDT 24
Peak memory 205380 kb
Host smart-dea77149-849e-4283-a518-48d0937ebdbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477357594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2477357594
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2518757210
Short name T918
Test name
Test status
Simulation time 56935280 ps
CPU time 0.84 seconds
Started Jun 04 01:31:36 PM PDT 24
Finished Jun 04 01:31:38 PM PDT 24
Peak memory 205292 kb
Host smart-1f913501-4f51-4b47-aca4-fe07a6d9bf2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518757210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2518757210
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1329095210
Short name T1001
Test name
Test status
Simulation time 26049169 ps
CPU time 0.72 seconds
Started Jun 04 01:31:37 PM PDT 24
Finished Jun 04 01:31:38 PM PDT 24
Peak memory 205316 kb
Host smart-90a898d8-053b-4606-ba28-fdae48ba3829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329095210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1329095210
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2780211727
Short name T980
Test name
Test status
Simulation time 842780287 ps
CPU time 5.62 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:30:48 PM PDT 24
Peak memory 205708 kb
Host smart-c4a3ccb6-126d-4495-bc42-65020bfd63e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780211727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
780211727
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1183516038
Short name T932
Test name
Test status
Simulation time 255330578 ps
CPU time 12.21 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:30:55 PM PDT 24
Peak memory 205628 kb
Host smart-a521931f-27ac-4903-b12b-6ec965fa335a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183516038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
183516038
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2631571814
Short name T1019
Test name
Test status
Simulation time 260744338 ps
CPU time 1.59 seconds
Started Jun 04 01:30:40 PM PDT 24
Finished Jun 04 01:30:43 PM PDT 24
Peak memory 205608 kb
Host smart-26fc2203-47d5-4c0a-98b7-4118f329726d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631571814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
631571814
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3878177195
Short name T930
Test name
Test status
Simulation time 145222200 ps
CPU time 1.54 seconds
Started Jun 04 01:30:42 PM PDT 24
Finished Jun 04 01:30:45 PM PDT 24
Peak memory 213948 kb
Host smart-19baa17d-0ad5-4616-924b-cb11bb1b121b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878177195 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3878177195
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3106161489
Short name T1026
Test name
Test status
Simulation time 118172599 ps
CPU time 1.44 seconds
Started Jun 04 01:30:42 PM PDT 24
Finished Jun 04 01:30:45 PM PDT 24
Peak memory 205656 kb
Host smart-d9a98c7a-2b1c-4e81-b2b7-53146e534a34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106161489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3106161489
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1890041481
Short name T1025
Test name
Test status
Simulation time 23110488 ps
CPU time 0.82 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:30:44 PM PDT 24
Peak memory 205368 kb
Host smart-0ec4d207-f950-4704-85e4-54466c7d51b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890041481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1890041481
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.89781074
Short name T1000
Test name
Test status
Simulation time 312125047 ps
CPU time 1.34 seconds
Started Jun 04 01:30:42 PM PDT 24
Finished Jun 04 01:30:44 PM PDT 24
Peak memory 205720 kb
Host smart-af8c9f62-3818-44eb-b5e1-b835a4f411d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89781074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same
_csr_outstanding.89781074
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3849953561
Short name T1028
Test name
Test status
Simulation time 76918035 ps
CPU time 2.6 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:30:45 PM PDT 24
Peak memory 214264 kb
Host smart-e1e4fb51-b0ba-4a37-a8ac-cdd0c9c27809
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849953561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3849953561
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2513209285
Short name T1014
Test name
Test status
Simulation time 237672741 ps
CPU time 8.23 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:30:50 PM PDT 24
Peak memory 214332 kb
Host smart-d46d0f87-b9dd-4a85-998d-d810c6dbf48a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513209285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2513209285
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1214379342
Short name T1044
Test name
Test status
Simulation time 260352116 ps
CPU time 2.91 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:30:45 PM PDT 24
Peak memory 213784 kb
Host smart-684a3662-dde2-43ad-b34b-04a4aabf4aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214379342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1214379342
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1221162651
Short name T187
Test name
Test status
Simulation time 170465808 ps
CPU time 2.52 seconds
Started Jun 04 01:30:43 PM PDT 24
Finished Jun 04 01:30:46 PM PDT 24
Peak memory 205612 kb
Host smart-a90e3897-4f34-4e60-8555-d9050c58c634
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221162651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1221162651
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.774171243
Short name T966
Test name
Test status
Simulation time 19939094 ps
CPU time 0.73 seconds
Started Jun 04 01:31:36 PM PDT 24
Finished Jun 04 01:31:38 PM PDT 24
Peak memory 205368 kb
Host smart-43945c38-6626-4493-82ba-ed242a6c301e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774171243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.774171243
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2546206355
Short name T1009
Test name
Test status
Simulation time 29514189 ps
CPU time 0.72 seconds
Started Jun 04 01:31:35 PM PDT 24
Finished Jun 04 01:31:37 PM PDT 24
Peak memory 205376 kb
Host smart-3127d1a3-cfce-4d99-8a09-deee85715655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546206355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2546206355
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1051593448
Short name T1056
Test name
Test status
Simulation time 13835930 ps
CPU time 0.9 seconds
Started Jun 04 01:31:37 PM PDT 24
Finished Jun 04 01:31:39 PM PDT 24
Peak memory 205532 kb
Host smart-c3a025fa-ab1a-45bc-a7c5-c97abc08b3a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051593448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1051593448
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1427060755
Short name T910
Test name
Test status
Simulation time 13887712 ps
CPU time 0.72 seconds
Started Jun 04 01:31:37 PM PDT 24
Finished Jun 04 01:31:39 PM PDT 24
Peak memory 205332 kb
Host smart-8f0327ad-9ffb-4891-bd05-5fb5a12f5fac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427060755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1427060755
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1132579369
Short name T936
Test name
Test status
Simulation time 44855554 ps
CPU time 0.73 seconds
Started Jun 04 01:31:35 PM PDT 24
Finished Jun 04 01:31:37 PM PDT 24
Peak memory 205224 kb
Host smart-859cd671-697f-4be2-ba34-1ea8f9bfcd6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132579369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1132579369
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1480460937
Short name T955
Test name
Test status
Simulation time 12113488 ps
CPU time 0.79 seconds
Started Jun 04 01:31:37 PM PDT 24
Finished Jun 04 01:31:39 PM PDT 24
Peak memory 205308 kb
Host smart-8a2d6cef-cbbd-4f1e-92df-7114b412952c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480460937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1480460937
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.188422219
Short name T1005
Test name
Test status
Simulation time 12255411 ps
CPU time 0.91 seconds
Started Jun 04 01:31:35 PM PDT 24
Finished Jun 04 01:31:36 PM PDT 24
Peak memory 205384 kb
Host smart-61f25b02-4a52-4afb-a306-9d3c5187009d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188422219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.188422219
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1994349367
Short name T1032
Test name
Test status
Simulation time 14498787 ps
CPU time 0.73 seconds
Started Jun 04 01:31:39 PM PDT 24
Finished Jun 04 01:31:41 PM PDT 24
Peak memory 205304 kb
Host smart-ba922ff4-054f-4006-9f59-913703d7a6c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994349367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1994349367
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1201277946
Short name T928
Test name
Test status
Simulation time 44209457 ps
CPU time 0.71 seconds
Started Jun 04 01:31:34 PM PDT 24
Finished Jun 04 01:31:36 PM PDT 24
Peak memory 205356 kb
Host smart-190e46ba-fbe1-4af2-bdde-0e018562826e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201277946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1201277946
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3997579696
Short name T1054
Test name
Test status
Simulation time 27100730 ps
CPU time 0.81 seconds
Started Jun 04 01:31:36 PM PDT 24
Finished Jun 04 01:31:38 PM PDT 24
Peak memory 205388 kb
Host smart-7752012c-c39a-4c53-9ae9-7d8da133d895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997579696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3997579696
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1983647535
Short name T982
Test name
Test status
Simulation time 49914021 ps
CPU time 2.84 seconds
Started Jun 04 01:30:43 PM PDT 24
Finished Jun 04 01:30:47 PM PDT 24
Peak memory 213908 kb
Host smart-44208351-d9a8-46bf-a2b0-5a45f3eee18d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983647535 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1983647535
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3833755049
Short name T1049
Test name
Test status
Simulation time 82900158 ps
CPU time 1.3 seconds
Started Jun 04 01:30:42 PM PDT 24
Finished Jun 04 01:30:44 PM PDT 24
Peak memory 205756 kb
Host smart-fb5b3f7a-9e13-4674-b97a-3d35b69f2c92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833755049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3833755049
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.76920473
Short name T920
Test name
Test status
Simulation time 9709754 ps
CPU time 0.82 seconds
Started Jun 04 01:30:43 PM PDT 24
Finished Jun 04 01:30:45 PM PDT 24
Peak memory 205380 kb
Host smart-07016b10-631e-408b-8b7a-430ebe60f13b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76920473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.76920473
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.892591545
Short name T921
Test name
Test status
Simulation time 66744841 ps
CPU time 2.45 seconds
Started Jun 04 01:30:43 PM PDT 24
Finished Jun 04 01:30:47 PM PDT 24
Peak memory 205604 kb
Host smart-b1a44c75-46e3-453b-9b41-0c1dacca08a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892591545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.892591545
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2029567617
Short name T983
Test name
Test status
Simulation time 43361629 ps
CPU time 1.98 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:30:44 PM PDT 24
Peak memory 214188 kb
Host smart-61319192-da81-4773-8905-1185f54ebc2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029567617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2029567617
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1023760244
Short name T1045
Test name
Test status
Simulation time 679825730 ps
CPU time 4.59 seconds
Started Jun 04 01:30:42 PM PDT 24
Finished Jun 04 01:30:48 PM PDT 24
Peak memory 214108 kb
Host smart-bab41ac8-d0b9-43a3-bb8c-ec36c4196652
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023760244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1023760244
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.776632113
Short name T952
Test name
Test status
Simulation time 69876172 ps
CPU time 1.52 seconds
Started Jun 04 01:30:41 PM PDT 24
Finished Jun 04 01:30:44 PM PDT 24
Peak memory 205696 kb
Host smart-657b69df-d872-4882-9e49-a7c2c21b33af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776632113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.776632113
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.893812275
Short name T937
Test name
Test status
Simulation time 116959364 ps
CPU time 2.25 seconds
Started Jun 04 01:30:52 PM PDT 24
Finished Jun 04 01:30:55 PM PDT 24
Peak memory 214000 kb
Host smart-c95944af-3212-41b3-bdf5-7b2fbafd6041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893812275 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.893812275
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3259962486
Short name T950
Test name
Test status
Simulation time 22276612 ps
CPU time 0.99 seconds
Started Jun 04 01:30:50 PM PDT 24
Finished Jun 04 01:30:51 PM PDT 24
Peak memory 205512 kb
Host smart-86902b4d-c003-407d-9cbf-5b22856dddd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259962486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3259962486
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3893279255
Short name T1018
Test name
Test status
Simulation time 9748371 ps
CPU time 0.73 seconds
Started Jun 04 01:30:50 PM PDT 24
Finished Jun 04 01:30:52 PM PDT 24
Peak memory 205388 kb
Host smart-f9af637e-2ab1-42a3-b795-50dc5be19879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893279255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3893279255
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.448030867
Short name T934
Test name
Test status
Simulation time 109338718 ps
CPU time 2.3 seconds
Started Jun 04 01:30:52 PM PDT 24
Finished Jun 04 01:30:55 PM PDT 24
Peak memory 205632 kb
Host smart-86c21885-d49c-443f-b9b7-34c9cee441a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448030867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.448030867
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3698938111
Short name T1048
Test name
Test status
Simulation time 561250273 ps
CPU time 4.56 seconds
Started Jun 04 01:30:52 PM PDT 24
Finished Jun 04 01:30:58 PM PDT 24
Peak memory 214176 kb
Host smart-f6b590a5-fe73-4b36-9d71-c1724a1087c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698938111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3698938111
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3042621062
Short name T995
Test name
Test status
Simulation time 965278327 ps
CPU time 5.3 seconds
Started Jun 04 01:30:50 PM PDT 24
Finished Jun 04 01:30:56 PM PDT 24
Peak memory 222488 kb
Host smart-4f228eff-6671-4889-b701-35ac5b42e230
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042621062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3042621062
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2617670188
Short name T927
Test name
Test status
Simulation time 115286290 ps
CPU time 1.97 seconds
Started Jun 04 01:30:52 PM PDT 24
Finished Jun 04 01:30:55 PM PDT 24
Peak memory 213928 kb
Host smart-22a63dd0-60f8-4772-9a13-adeda7c06f79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617670188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2617670188
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2066918918
Short name T189
Test name
Test status
Simulation time 403542020 ps
CPU time 4.47 seconds
Started Jun 04 01:30:50 PM PDT 24
Finished Jun 04 01:30:55 PM PDT 24
Peak memory 205796 kb
Host smart-b4fed30c-bb7f-423b-992b-648b088f1c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066918918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2066918918
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3188409748
Short name T1058
Test name
Test status
Simulation time 175853610 ps
CPU time 1.75 seconds
Started Jun 04 01:30:49 PM PDT 24
Finished Jun 04 01:30:52 PM PDT 24
Peak memory 213880 kb
Host smart-5078a7a5-31b5-4da0-bd1e-4838b96fa8ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188409748 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3188409748
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2148576305
Short name T1073
Test name
Test status
Simulation time 101076636 ps
CPU time 1.19 seconds
Started Jun 04 01:30:49 PM PDT 24
Finished Jun 04 01:30:51 PM PDT 24
Peak memory 205684 kb
Host smart-e9f66652-1f9c-4a35-a030-d2f775845803
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148576305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2148576305
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.887924430
Short name T915
Test name
Test status
Simulation time 41682188 ps
CPU time 0.85 seconds
Started Jun 04 01:30:51 PM PDT 24
Finished Jun 04 01:30:53 PM PDT 24
Peak memory 205344 kb
Host smart-c3746800-ffa8-4fc5-98c7-85efc9d91aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887924430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.887924430
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2563544949
Short name T954
Test name
Test status
Simulation time 60790948 ps
CPU time 1.67 seconds
Started Jun 04 01:30:50 PM PDT 24
Finished Jun 04 01:30:52 PM PDT 24
Peak memory 205552 kb
Host smart-5fd155b0-44b1-4447-bb57-a3757bcde63f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563544949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2563544949
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1472939756
Short name T984
Test name
Test status
Simulation time 86847195 ps
CPU time 3.32 seconds
Started Jun 04 01:30:52 PM PDT 24
Finished Jun 04 01:30:56 PM PDT 24
Peak memory 214240 kb
Host smart-bb1d43b1-0476-4610-9ff7-fedb6dbf1929
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472939756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1472939756
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.970214163
Short name T1057
Test name
Test status
Simulation time 803001143 ps
CPU time 6.13 seconds
Started Jun 04 01:30:53 PM PDT 24
Finished Jun 04 01:30:59 PM PDT 24
Peak memory 214196 kb
Host smart-4a886a64-36b9-4648-894c-73cd7da6dbd5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970214163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.970214163
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3625782396
Short name T919
Test name
Test status
Simulation time 135594235 ps
CPU time 2.1 seconds
Started Jun 04 01:30:49 PM PDT 24
Finished Jun 04 01:30:52 PM PDT 24
Peak memory 213812 kb
Host smart-1bb06c56-34b0-490a-b398-0133409896d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625782396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3625782396
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1675854146
Short name T917
Test name
Test status
Simulation time 128443004 ps
CPU time 2.52 seconds
Started Jun 04 01:31:01 PM PDT 24
Finished Jun 04 01:31:05 PM PDT 24
Peak memory 213856 kb
Host smart-e043babf-fb74-4c96-8504-243b0b5ada4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675854146 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1675854146
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1263888402
Short name T1052
Test name
Test status
Simulation time 113692845 ps
CPU time 1.19 seconds
Started Jun 04 01:31:00 PM PDT 24
Finished Jun 04 01:31:02 PM PDT 24
Peak memory 205720 kb
Host smart-3eb9450e-803a-44d8-aba4-4ee4303d391b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263888402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1263888402
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4113427714
Short name T1035
Test name
Test status
Simulation time 36451007 ps
CPU time 0.76 seconds
Started Jun 04 01:31:02 PM PDT 24
Finished Jun 04 01:31:03 PM PDT 24
Peak memory 205212 kb
Host smart-993d04e4-d5f0-431b-8915-323ab8ed69a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113427714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4113427714
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2546374305
Short name T1031
Test name
Test status
Simulation time 32003871 ps
CPU time 2.1 seconds
Started Jun 04 01:31:02 PM PDT 24
Finished Jun 04 01:31:05 PM PDT 24
Peak memory 205612 kb
Host smart-64c6bd9d-f670-4a41-b29b-46709a195fd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546374305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2546374305
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1875283800
Short name T1039
Test name
Test status
Simulation time 142811919 ps
CPU time 1.37 seconds
Started Jun 04 01:30:50 PM PDT 24
Finished Jun 04 01:30:52 PM PDT 24
Peak memory 214180 kb
Host smart-603b6102-35a3-4caa-af4a-228c7067da67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875283800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1875283800
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1795833325
Short name T1011
Test name
Test status
Simulation time 332275086 ps
CPU time 3.55 seconds
Started Jun 04 01:30:51 PM PDT 24
Finished Jun 04 01:30:55 PM PDT 24
Peak memory 220312 kb
Host smart-cb1d3145-b3fb-45fd-a979-338d5ec5fedc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795833325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1795833325
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3341263140
Short name T939
Test name
Test status
Simulation time 96144123 ps
CPU time 1.66 seconds
Started Jun 04 01:30:50 PM PDT 24
Finished Jun 04 01:30:53 PM PDT 24
Peak memory 213752 kb
Host smart-6ec430ed-3e0f-4cee-b60c-47dd5745b9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341263140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3341263140
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4106527102
Short name T1038
Test name
Test status
Simulation time 144818592 ps
CPU time 1.62 seconds
Started Jun 04 01:31:00 PM PDT 24
Finished Jun 04 01:31:03 PM PDT 24
Peak memory 213972 kb
Host smart-86ae1bc7-0e2a-4220-88f5-0928e6cc70e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106527102 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4106527102
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.125669340
Short name T157
Test name
Test status
Simulation time 22729817 ps
CPU time 1.22 seconds
Started Jun 04 01:31:03 PM PDT 24
Finished Jun 04 01:31:05 PM PDT 24
Peak memory 205804 kb
Host smart-270d1173-601a-4277-9546-7cdfaab62138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125669340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.125669340
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2085066416
Short name T916
Test name
Test status
Simulation time 25021698 ps
CPU time 0.82 seconds
Started Jun 04 01:31:04 PM PDT 24
Finished Jun 04 01:31:06 PM PDT 24
Peak memory 205380 kb
Host smart-13f34b0f-917e-4d0c-8511-aaf693fa2afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085066416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2085066416
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4155657777
Short name T945
Test name
Test status
Simulation time 131930806 ps
CPU time 4.23 seconds
Started Jun 04 01:31:02 PM PDT 24
Finished Jun 04 01:31:06 PM PDT 24
Peak memory 205768 kb
Host smart-ab840838-cbb3-4fb0-93a8-aac518fdb015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155657777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4155657777
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3348710838
Short name T1074
Test name
Test status
Simulation time 42882490 ps
CPU time 1.35 seconds
Started Jun 04 01:31:04 PM PDT 24
Finished Jun 04 01:31:06 PM PDT 24
Peak memory 214268 kb
Host smart-e6e87feb-bdce-4bca-83cb-36ade51ada41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348710838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3348710838
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2131985646
Short name T1015
Test name
Test status
Simulation time 1401423150 ps
CPU time 5.04 seconds
Started Jun 04 01:31:02 PM PDT 24
Finished Jun 04 01:31:08 PM PDT 24
Peak memory 214420 kb
Host smart-e6761421-6d01-4b31-aae3-3e1d2ee7b459
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131985646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2131985646
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1977696044
Short name T993
Test name
Test status
Simulation time 140697896 ps
CPU time 3.16 seconds
Started Jun 04 01:31:00 PM PDT 24
Finished Jun 04 01:31:04 PM PDT 24
Peak memory 213896 kb
Host smart-e904f883-121b-4074-9df1-5cbd33485853
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977696044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1977696044
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1093197943
Short name T463
Test name
Test status
Simulation time 17738420 ps
CPU time 0.95 seconds
Started Jun 04 01:57:09 PM PDT 24
Finished Jun 04 01:57:11 PM PDT 24
Peak memory 206104 kb
Host smart-3175b659-8676-4bc8-9dde-aaaa1ea29a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093197943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1093197943
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2366748941
Short name T76
Test name
Test status
Simulation time 749664779 ps
CPU time 9.8 seconds
Started Jun 04 01:57:09 PM PDT 24
Finished Jun 04 01:57:20 PM PDT 24
Peak memory 214528 kb
Host smart-50ab2a1d-032b-42a6-9de7-05e346c2fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366748941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2366748941
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.828481813
Short name T555
Test name
Test status
Simulation time 181312354 ps
CPU time 3.1 seconds
Started Jun 04 01:57:01 PM PDT 24
Finished Jun 04 01:57:05 PM PDT 24
Peak memory 214324 kb
Host smart-9598f8f0-5353-4789-a8b9-4763d4c57080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828481813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.828481813
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1073085221
Short name T690
Test name
Test status
Simulation time 95737325 ps
CPU time 1.89 seconds
Started Jun 04 01:57:10 PM PDT 24
Finished Jun 04 01:57:13 PM PDT 24
Peak memory 214332 kb
Host smart-32ce33fc-9586-4e06-a499-bf99bea5d3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073085221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1073085221
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1842048872
Short name T717
Test name
Test status
Simulation time 218228696 ps
CPU time 3.92 seconds
Started Jun 04 01:57:03 PM PDT 24
Finished Jun 04 01:57:07 PM PDT 24
Peak memory 208408 kb
Host smart-2c3c8ad8-2878-4fec-bf78-963b362c0e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842048872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1842048872
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.251080969
Short name T452
Test name
Test status
Simulation time 545696493 ps
CPU time 4.65 seconds
Started Jun 04 01:57:02 PM PDT 24
Finished Jun 04 01:57:08 PM PDT 24
Peak memory 208676 kb
Host smart-8679426e-937d-4015-8dc3-d9a8ef92bc82
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251080969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.251080969
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1553634162
Short name T397
Test name
Test status
Simulation time 350646939 ps
CPU time 2.41 seconds
Started Jun 04 01:57:04 PM PDT 24
Finished Jun 04 01:57:07 PM PDT 24
Peak memory 209204 kb
Host smart-c413a6da-edf0-4eb5-941c-471da5c26308
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553634162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1553634162
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3412582369
Short name T522
Test name
Test status
Simulation time 306332777 ps
CPU time 4.78 seconds
Started Jun 04 01:57:01 PM PDT 24
Finished Jun 04 01:57:06 PM PDT 24
Peak memory 208968 kb
Host smart-fe7eae41-c3f0-487a-a67b-180b121ab9a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412582369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3412582369
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2358098699
Short name T483
Test name
Test status
Simulation time 139894226 ps
CPU time 2.18 seconds
Started Jun 04 01:57:03 PM PDT 24
Finished Jun 04 01:57:06 PM PDT 24
Peak memory 206692 kb
Host smart-ee84453d-562f-4df9-a8de-4502f708f4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358098699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2358098699
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3328128266
Short name T270
Test name
Test status
Simulation time 573502195 ps
CPU time 15.97 seconds
Started Jun 04 01:57:10 PM PDT 24
Finished Jun 04 01:57:27 PM PDT 24
Peak memory 217204 kb
Host smart-43509086-0617-4a68-83fb-9b5e07365cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328128266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3328128266
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2652362750
Short name T119
Test name
Test status
Simulation time 300297274 ps
CPU time 12.71 seconds
Started Jun 04 01:57:09 PM PDT 24
Finished Jun 04 01:57:23 PM PDT 24
Peak memory 222580 kb
Host smart-fe952ef0-0565-44d2-9105-468ca0b540c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652362750 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2652362750
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1691612017
Short name T895
Test name
Test status
Simulation time 142728688 ps
CPU time 5.16 seconds
Started Jun 04 01:57:10 PM PDT 24
Finished Jun 04 01:57:16 PM PDT 24
Peak memory 218316 kb
Host smart-f82f18e4-8dba-42c0-8e60-9490cb1dc5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691612017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1691612017
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1339473950
Short name T389
Test name
Test status
Simulation time 97723420 ps
CPU time 1.89 seconds
Started Jun 04 01:57:09 PM PDT 24
Finished Jun 04 01:57:13 PM PDT 24
Peak memory 209760 kb
Host smart-e0522d7d-f8f5-4a1f-8d81-047a13b942eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339473950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1339473950
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1618506554
Short name T469
Test name
Test status
Simulation time 20066384 ps
CPU time 0.75 seconds
Started Jun 04 01:57:29 PM PDT 24
Finished Jun 04 01:57:30 PM PDT 24
Peak memory 205956 kb
Host smart-214a92f9-f0da-4d5a-8391-96d301f64272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618506554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1618506554
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2417036210
Short name T541
Test name
Test status
Simulation time 69357868 ps
CPU time 2.59 seconds
Started Jun 04 01:57:18 PM PDT 24
Finished Jun 04 01:57:21 PM PDT 24
Peak memory 214236 kb
Host smart-319bbd2c-def1-466f-911b-e1925722678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417036210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2417036210
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3731344563
Short name T284
Test name
Test status
Simulation time 332342322 ps
CPU time 5.23 seconds
Started Jun 04 01:57:18 PM PDT 24
Finished Jun 04 01:57:24 PM PDT 24
Peak memory 207924 kb
Host smart-a21ac5fc-df58-49e3-88e8-62e86f2047d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731344563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3731344563
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4225108602
Short name T354
Test name
Test status
Simulation time 369549970 ps
CPU time 4.7 seconds
Started Jun 04 01:57:16 PM PDT 24
Finished Jun 04 01:57:22 PM PDT 24
Peak memory 222468 kb
Host smart-1cadb8da-f52d-4817-9433-d2b95b87b181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225108602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4225108602
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2278214633
Short name T238
Test name
Test status
Simulation time 207230012 ps
CPU time 3.46 seconds
Started Jun 04 01:57:19 PM PDT 24
Finished Jun 04 01:57:23 PM PDT 24
Peak memory 210268 kb
Host smart-4ea0dbf3-02bb-403b-bb7b-7f0cdc1caf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278214633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2278214633
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.597140388
Short name T658
Test name
Test status
Simulation time 117055506 ps
CPU time 2.37 seconds
Started Jun 04 01:57:16 PM PDT 24
Finished Jun 04 01:57:19 PM PDT 24
Peak memory 207548 kb
Host smart-f3814ad7-12f8-42d8-b55a-ed81e5857759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597140388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.597140388
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.758633695
Short name T13
Test name
Test status
Simulation time 226957662 ps
CPU time 5.29 seconds
Started Jun 04 01:57:29 PM PDT 24
Finished Jun 04 01:57:35 PM PDT 24
Peak memory 237440 kb
Host smart-d581b55b-6ed5-42e8-874a-f1a0da8b809a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758633695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.758633695
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2072363295
Short name T761
Test name
Test status
Simulation time 64710516 ps
CPU time 2.39 seconds
Started Jun 04 01:57:18 PM PDT 24
Finished Jun 04 01:57:21 PM PDT 24
Peak memory 206820 kb
Host smart-10918ed6-835d-489a-8c12-b48408cc6d20
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072363295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2072363295
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2143995070
Short name T772
Test name
Test status
Simulation time 5882007805 ps
CPU time 29.16 seconds
Started Jun 04 01:57:17 PM PDT 24
Finished Jun 04 01:57:47 PM PDT 24
Peak memory 208796 kb
Host smart-011a673d-c49d-4c56-9e4c-077d004463d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143995070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2143995070
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.288614090
Short name T259
Test name
Test status
Simulation time 241471593 ps
CPU time 3.23 seconds
Started Jun 04 01:57:17 PM PDT 24
Finished Jun 04 01:57:21 PM PDT 24
Peak memory 208756 kb
Host smart-ef507bf5-6c9d-4576-83f1-2af21cd15d47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288614090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.288614090
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1696512236
Short name T813
Test name
Test status
Simulation time 345486112 ps
CPU time 3.99 seconds
Started Jun 04 01:57:33 PM PDT 24
Finished Jun 04 01:57:38 PM PDT 24
Peak memory 209516 kb
Host smart-958a46d4-4119-4de7-997e-6c58f4ccc541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696512236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1696512236
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3173630946
Short name T905
Test name
Test status
Simulation time 86596181 ps
CPU time 1.91 seconds
Started Jun 04 01:57:08 PM PDT 24
Finished Jun 04 01:57:11 PM PDT 24
Peak memory 208644 kb
Host smart-86bc615d-a95c-4890-8d7d-1b35e0740f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173630946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3173630946
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1681453624
Short name T276
Test name
Test status
Simulation time 1144035613 ps
CPU time 6 seconds
Started Jun 04 01:57:17 PM PDT 24
Finished Jun 04 01:57:24 PM PDT 24
Peak memory 209788 kb
Host smart-3e6eeb4c-4d25-41b7-a92a-b2a77bcce8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681453624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1681453624
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3787063532
Short name T184
Test name
Test status
Simulation time 226604675 ps
CPU time 1.98 seconds
Started Jun 04 01:57:33 PM PDT 24
Finished Jun 04 01:57:36 PM PDT 24
Peak memory 210016 kb
Host smart-c10881f7-9e52-4832-b2c6-f1bd496728e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787063532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3787063532
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1476415686
Short name T768
Test name
Test status
Simulation time 42282997 ps
CPU time 0.83 seconds
Started Jun 04 01:58:36 PM PDT 24
Finished Jun 04 01:58:38 PM PDT 24
Peak memory 205952 kb
Host smart-7dae23c8-77cc-47e8-b552-1f912a7b83a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476415686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1476415686
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2101638442
Short name T34
Test name
Test status
Simulation time 501900166 ps
CPU time 4.87 seconds
Started Jun 04 01:58:38 PM PDT 24
Finished Jun 04 01:58:44 PM PDT 24
Peak memory 209880 kb
Host smart-7662ef41-2d60-45fc-b06a-cd964a4609be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101638442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2101638442
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2115784290
Short name T580
Test name
Test status
Simulation time 955780578 ps
CPU time 5.69 seconds
Started Jun 04 01:58:27 PM PDT 24
Finished Jun 04 01:58:34 PM PDT 24
Peak memory 214344 kb
Host smart-60588768-b69c-4299-8d5d-f9ffd4ff70f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115784290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2115784290
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.501193885
Short name T107
Test name
Test status
Simulation time 94195671 ps
CPU time 4.53 seconds
Started Jun 04 01:58:36 PM PDT 24
Finished Jun 04 01:58:41 PM PDT 24
Peak memory 214360 kb
Host smart-79e97358-db95-486e-9a5f-734eb0e6c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501193885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.501193885
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1578660518
Short name T111
Test name
Test status
Simulation time 90047462 ps
CPU time 2.03 seconds
Started Jun 04 01:58:39 PM PDT 24
Finished Jun 04 01:58:42 PM PDT 24
Peak memory 220120 kb
Host smart-9ebcb710-1bd2-4e3c-b117-03f3be759106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578660518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1578660518
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2930693504
Short name T840
Test name
Test status
Simulation time 118000744 ps
CPU time 3.17 seconds
Started Jun 04 01:58:27 PM PDT 24
Finished Jun 04 01:58:32 PM PDT 24
Peak memory 206096 kb
Host smart-e7fbe990-60e4-494c-b87f-2235c2923ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930693504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2930693504
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2247776056
Short name T745
Test name
Test status
Simulation time 368903863 ps
CPU time 4.34 seconds
Started Jun 04 01:58:33 PM PDT 24
Finished Jun 04 01:58:38 PM PDT 24
Peak memory 219272 kb
Host smart-6430960b-ff61-4313-adc3-93f966a7922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247776056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2247776056
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2625833469
Short name T614
Test name
Test status
Simulation time 521005479 ps
CPU time 3.83 seconds
Started Jun 04 01:58:27 PM PDT 24
Finished Jun 04 01:58:32 PM PDT 24
Peak memory 208000 kb
Host smart-ae0fada5-d74e-4232-b573-fd7242b5dc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625833469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2625833469
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3362878377
Short name T381
Test name
Test status
Simulation time 187542642 ps
CPU time 2.57 seconds
Started Jun 04 01:58:27 PM PDT 24
Finished Jun 04 01:58:31 PM PDT 24
Peak memory 208920 kb
Host smart-b5f1994c-118b-4f30-b6ea-46b72b889153
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362878377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3362878377
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.608661225
Short name T495
Test name
Test status
Simulation time 63318625 ps
CPU time 3.38 seconds
Started Jun 04 01:58:28 PM PDT 24
Finished Jun 04 01:58:32 PM PDT 24
Peak memory 208948 kb
Host smart-bf8435a3-ab24-4329-aed8-8b6dffe3055a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608661225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.608661225
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.842442390
Short name T91
Test name
Test status
Simulation time 161337136 ps
CPU time 2.32 seconds
Started Jun 04 01:58:33 PM PDT 24
Finished Jun 04 01:58:35 PM PDT 24
Peak memory 206980 kb
Host smart-bbc414e9-edda-4c17-833a-fab9c6aae19d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842442390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.842442390
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_smoke.35644496
Short name T505
Test name
Test status
Simulation time 183639398 ps
CPU time 2.63 seconds
Started Jun 04 01:58:34 PM PDT 24
Finished Jun 04 01:58:37 PM PDT 24
Peak memory 208280 kb
Host smart-49e9b7dd-1115-4c98-b063-1ef771ad0f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35644496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.35644496
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3725216436
Short name T620
Test name
Test status
Simulation time 794092525 ps
CPU time 9.05 seconds
Started Jun 04 01:58:29 PM PDT 24
Finished Jun 04 01:58:39 PM PDT 24
Peak memory 219652 kb
Host smart-29850379-963a-4f78-9943-dfb2b7af4513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725216436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3725216436
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.4236366705
Short name T752
Test name
Test status
Simulation time 36648893 ps
CPU time 1.96 seconds
Started Jun 04 01:58:37 PM PDT 24
Finished Jun 04 01:58:40 PM PDT 24
Peak memory 210072 kb
Host smart-999b18c8-6bd5-46dc-bd18-4229e2f4f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236366705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.4236366705
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2334488345
Short name T488
Test name
Test status
Simulation time 15396375 ps
CPU time 0.87 seconds
Started Jun 04 01:58:44 PM PDT 24
Finished Jun 04 01:58:46 PM PDT 24
Peak memory 205936 kb
Host smart-0f39f50f-3231-41f7-96ba-7be3846c4a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334488345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2334488345
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3518093203
Short name T412
Test name
Test status
Simulation time 6046133079 ps
CPU time 103.81 seconds
Started Jun 04 01:58:36 PM PDT 24
Finished Jun 04 02:00:20 PM PDT 24
Peak memory 214448 kb
Host smart-88d04ed6-32ca-4dff-80d9-df9d902fdb98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518093203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3518093203
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2325595445
Short name T458
Test name
Test status
Simulation time 253223180 ps
CPU time 3.02 seconds
Started Jun 04 01:58:37 PM PDT 24
Finished Jun 04 01:58:41 PM PDT 24
Peak memory 207624 kb
Host smart-2a734501-e168-45f9-b539-7a974ce65de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325595445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2325595445
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1175136462
Short name T385
Test name
Test status
Simulation time 285993057 ps
CPU time 4.48 seconds
Started Jun 04 01:58:45 PM PDT 24
Finished Jun 04 01:58:51 PM PDT 24
Peak memory 214324 kb
Host smart-88546668-2685-4071-9144-d800789c6850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175136462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1175136462
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1102543660
Short name T694
Test name
Test status
Simulation time 404963769 ps
CPU time 3.15 seconds
Started Jun 04 01:58:45 PM PDT 24
Finished Jun 04 01:58:49 PM PDT 24
Peak memory 214280 kb
Host smart-21907955-5f31-4256-9616-f7f557752c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102543660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1102543660
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_random.2136710676
Short name T144
Test name
Test status
Simulation time 49609994 ps
CPU time 2.94 seconds
Started Jun 04 01:58:36 PM PDT 24
Finished Jun 04 01:58:39 PM PDT 24
Peak memory 209688 kb
Host smart-a7bf29de-f8f3-457f-9e86-1939478b4dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136710676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2136710676
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2663673400
Short name T712
Test name
Test status
Simulation time 61447818 ps
CPU time 2.12 seconds
Started Jun 04 01:58:36 PM PDT 24
Finished Jun 04 01:58:39 PM PDT 24
Peak memory 206888 kb
Host smart-1b5ca461-ae21-480c-ab7e-8ffe7a5dfcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663673400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2663673400
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2318979810
Short name T704
Test name
Test status
Simulation time 272107443 ps
CPU time 2.87 seconds
Started Jun 04 01:58:38 PM PDT 24
Finished Jun 04 01:58:42 PM PDT 24
Peak memory 207324 kb
Host smart-b9c18004-9273-47fc-bb84-bea1e283da0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318979810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2318979810
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2802195268
Short name T862
Test name
Test status
Simulation time 207062389 ps
CPU time 2.93 seconds
Started Jun 04 01:58:37 PM PDT 24
Finished Jun 04 01:58:40 PM PDT 24
Peak memory 207528 kb
Host smart-6acb29d3-a8a3-450d-8570-6568f8a2054b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802195268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2802195268
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1970009683
Short name T197
Test name
Test status
Simulation time 209910358 ps
CPU time 5.93 seconds
Started Jun 04 01:58:37 PM PDT 24
Finished Jun 04 01:58:44 PM PDT 24
Peak memory 208804 kb
Host smart-fe6ce6ed-5db4-4171-b50a-7f9fee63c186
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970009683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1970009683
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.942467385
Short name T784
Test name
Test status
Simulation time 160629228 ps
CPU time 2.56 seconds
Started Jun 04 01:58:43 PM PDT 24
Finished Jun 04 01:58:47 PM PDT 24
Peak memory 214364 kb
Host smart-28e2fc94-e6c4-4834-9c99-2938b5f20b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942467385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.942467385
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2356331958
Short name T652
Test name
Test status
Simulation time 154000591 ps
CPU time 2.13 seconds
Started Jun 04 01:58:35 PM PDT 24
Finished Jun 04 01:58:38 PM PDT 24
Peak memory 206764 kb
Host smart-e7db90a5-ffe3-434c-8b53-c94e11b5ecdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356331958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2356331958
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2124116973
Short name T264
Test name
Test status
Simulation time 428979579 ps
CPU time 4.77 seconds
Started Jun 04 01:58:43 PM PDT 24
Finished Jun 04 01:58:48 PM PDT 24
Peak memory 209460 kb
Host smart-79608ad9-658c-4219-ab09-4ae5b39f832a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124116973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2124116973
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2594624887
Short name T844
Test name
Test status
Simulation time 91166060 ps
CPU time 5.82 seconds
Started Jun 04 01:58:43 PM PDT 24
Finished Jun 04 01:58:49 PM PDT 24
Peak memory 221844 kb
Host smart-5b172a33-6451-4155-a774-137e25d18648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594624887 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2594624887
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3294117782
Short name T116
Test name
Test status
Simulation time 95903306 ps
CPU time 2.77 seconds
Started Jun 04 01:58:36 PM PDT 24
Finished Jun 04 01:58:39 PM PDT 24
Peak memory 207792 kb
Host smart-552cbdc1-d0ed-4f8c-9263-d8bc962ae2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294117782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3294117782
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2557799018
Short name T827
Test name
Test status
Simulation time 156208627 ps
CPU time 2.48 seconds
Started Jun 04 01:58:48 PM PDT 24
Finished Jun 04 01:58:52 PM PDT 24
Peak memory 210324 kb
Host smart-b4d69244-7c5b-4ada-9f3e-aad127742983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557799018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2557799018
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.4165314582
Short name T471
Test name
Test status
Simulation time 14354679 ps
CPU time 0.76 seconds
Started Jun 04 01:58:44 PM PDT 24
Finished Jun 04 01:58:46 PM PDT 24
Peak memory 205976 kb
Host smart-8b0f09b2-76a6-4a85-b1d3-6adccfa50a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165314582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.4165314582
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1110731428
Short name T427
Test name
Test status
Simulation time 123636959 ps
CPU time 6.91 seconds
Started Jun 04 01:58:43 PM PDT 24
Finished Jun 04 01:58:51 PM PDT 24
Peak memory 222344 kb
Host smart-b20daec9-0851-4695-b897-a6c1ec75ba54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110731428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1110731428
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1477450119
Short name T21
Test name
Test status
Simulation time 28154205 ps
CPU time 1.51 seconds
Started Jun 04 01:58:45 PM PDT 24
Finished Jun 04 01:58:47 PM PDT 24
Peak memory 217136 kb
Host smart-340d46c9-478d-4776-8aa7-afda6e412429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477450119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1477450119
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3283219892
Short name T807
Test name
Test status
Simulation time 78429640 ps
CPU time 2.64 seconds
Started Jun 04 01:58:43 PM PDT 24
Finished Jun 04 01:58:46 PM PDT 24
Peak memory 218248 kb
Host smart-8e2aa83f-c288-454f-ae92-be8c4775701c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283219892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3283219892
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2469414935
Short name T530
Test name
Test status
Simulation time 29209312 ps
CPU time 2.35 seconds
Started Jun 04 01:58:49 PM PDT 24
Finished Jun 04 01:58:53 PM PDT 24
Peak memory 214464 kb
Host smart-c5a80c06-cd3e-480c-be1a-a917de7acd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469414935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2469414935
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.761308123
Short name T693
Test name
Test status
Simulation time 358741881 ps
CPU time 3.2 seconds
Started Jun 04 01:58:44 PM PDT 24
Finished Jun 04 01:58:48 PM PDT 24
Peak memory 222436 kb
Host smart-836218da-4209-4e4f-8974-6bb29e587f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761308123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.761308123
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.977413337
Short name T417
Test name
Test status
Simulation time 81440129 ps
CPU time 3.23 seconds
Started Jun 04 01:58:45 PM PDT 24
Finished Jun 04 01:58:49 PM PDT 24
Peak memory 218892 kb
Host smart-1681fb48-b565-4e25-8cfd-02bb30546104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977413337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.977413337
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.578540574
Short name T651
Test name
Test status
Simulation time 395347001 ps
CPU time 10.21 seconds
Started Jun 04 01:58:49 PM PDT 24
Finished Jun 04 01:59:00 PM PDT 24
Peak memory 214432 kb
Host smart-eb5fe4cb-52be-440d-a5ef-9b70ff2491fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578540574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.578540574
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3499226449
Short name T632
Test name
Test status
Simulation time 377347902 ps
CPU time 4.02 seconds
Started Jun 04 01:58:45 PM PDT 24
Finished Jun 04 01:58:50 PM PDT 24
Peak memory 208576 kb
Host smart-3fed652d-2170-4ca2-a7d3-b712cfc38a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499226449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3499226449
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2381684172
Short name T507
Test name
Test status
Simulation time 961615285 ps
CPU time 16.7 seconds
Started Jun 04 01:58:46 PM PDT 24
Finished Jun 04 01:59:04 PM PDT 24
Peak memory 208344 kb
Host smart-bb80a90f-cd0f-4c91-aa71-106d13bae1b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381684172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2381684172
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.817533256
Short name T713
Test name
Test status
Simulation time 857759633 ps
CPU time 3.16 seconds
Started Jun 04 01:58:43 PM PDT 24
Finished Jun 04 01:58:47 PM PDT 24
Peak memory 206968 kb
Host smart-2abc1bb9-2170-4258-9d68-99937e8aed9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817533256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.817533256
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.193177648
Short name T815
Test name
Test status
Simulation time 395112032 ps
CPU time 6.02 seconds
Started Jun 04 01:58:41 PM PDT 24
Finished Jun 04 01:58:48 PM PDT 24
Peak memory 208096 kb
Host smart-cf843e78-4b4b-4d56-a344-3612729e808b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193177648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.193177648
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1408496842
Short name T199
Test name
Test status
Simulation time 244562678 ps
CPU time 3.06 seconds
Started Jun 04 01:58:43 PM PDT 24
Finished Jun 04 01:58:47 PM PDT 24
Peak memory 208184 kb
Host smart-432e91ea-cff4-4b88-b0c2-506898234399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408496842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1408496842
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1361084015
Short name T721
Test name
Test status
Simulation time 873894586 ps
CPU time 6.37 seconds
Started Jun 04 01:58:44 PM PDT 24
Finished Jun 04 01:58:52 PM PDT 24
Peak memory 207964 kb
Host smart-21c8cc23-a749-4c16-abee-38ab5e66a2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361084015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1361084015
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1594591676
Short name T596
Test name
Test status
Simulation time 1231934359 ps
CPU time 14.18 seconds
Started Jun 04 01:58:43 PM PDT 24
Finished Jun 04 01:58:57 PM PDT 24
Peak memory 221376 kb
Host smart-99fdca9b-cf3d-499f-b953-378914e7c9f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594591676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1594591676
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1901847378
Short name T760
Test name
Test status
Simulation time 1371286258 ps
CPU time 7.84 seconds
Started Jun 04 01:58:42 PM PDT 24
Finished Jun 04 01:58:51 PM PDT 24
Peak memory 208700 kb
Host smart-1fe71249-4402-4938-b5cb-81ea90fb893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901847378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1901847378
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3033128581
Short name T173
Test name
Test status
Simulation time 106720527 ps
CPU time 2.65 seconds
Started Jun 04 01:58:44 PM PDT 24
Finished Jun 04 01:58:48 PM PDT 24
Peak memory 210184 kb
Host smart-9c4f85d0-1e24-4825-b74c-4982643d4b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033128581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3033128581
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3003810721
Short name T556
Test name
Test status
Simulation time 14239800 ps
CPU time 0.8 seconds
Started Jun 04 01:58:53 PM PDT 24
Finished Jun 04 01:58:54 PM PDT 24
Peak memory 205968 kb
Host smart-2ab8a8d2-04c6-4d9e-8488-cdfb67841868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003810721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3003810721
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1929630106
Short name T248
Test name
Test status
Simulation time 159346665 ps
CPU time 4.87 seconds
Started Jun 04 01:58:44 PM PDT 24
Finished Jun 04 01:58:50 PM PDT 24
Peak memory 214448 kb
Host smart-8ee6c3e8-def1-47ac-8f47-263db79b20c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929630106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1929630106
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2299481286
Short name T687
Test name
Test status
Simulation time 51422215 ps
CPU time 2.52 seconds
Started Jun 04 01:58:53 PM PDT 24
Finished Jun 04 01:58:56 PM PDT 24
Peak memory 221164 kb
Host smart-9e5d6276-56ad-4cd1-8143-1629e5575168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299481286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2299481286
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3986029463
Short name T817
Test name
Test status
Simulation time 26453784 ps
CPU time 1.53 seconds
Started Jun 04 01:58:50 PM PDT 24
Finished Jun 04 01:58:53 PM PDT 24
Peak memory 207520 kb
Host smart-510032d0-cafd-43bf-8130-13da42d698aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986029463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3986029463
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.963695262
Short name T331
Test name
Test status
Simulation time 412121849 ps
CPU time 3.45 seconds
Started Jun 04 01:58:52 PM PDT 24
Finished Jun 04 01:58:56 PM PDT 24
Peak memory 214252 kb
Host smart-48ed3d53-f12b-4650-a54f-daf30ff2a9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963695262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.963695262
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.668440346
Short name T245
Test name
Test status
Simulation time 210065721 ps
CPU time 3.89 seconds
Started Jun 04 01:58:52 PM PDT 24
Finished Jun 04 01:58:57 PM PDT 24
Peak memory 220244 kb
Host smart-d167deca-b107-4cc9-9dbb-4781abc5d6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668440346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.668440346
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3548912162
Short name T214
Test name
Test status
Simulation time 256361416 ps
CPU time 5.03 seconds
Started Jun 04 01:58:44 PM PDT 24
Finished Jun 04 01:58:50 PM PDT 24
Peak memory 208092 kb
Host smart-cd6bfcc1-7d4f-4ffd-96a7-b3f8ff9624c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548912162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3548912162
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.889380970
Short name T146
Test name
Test status
Simulation time 1269633717 ps
CPU time 2.81 seconds
Started Jun 04 01:58:44 PM PDT 24
Finished Jun 04 01:58:48 PM PDT 24
Peak memory 206716 kb
Host smart-a098112d-824d-45cd-9181-fa790dd371d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889380970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.889380970
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1626714244
Short name T608
Test name
Test status
Simulation time 74541089 ps
CPU time 1.73 seconds
Started Jun 04 01:58:44 PM PDT 24
Finished Jun 04 01:58:47 PM PDT 24
Peak memory 206900 kb
Host smart-c3777541-9eba-471f-9081-104bea60dfc1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626714244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1626714244
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1835826417
Short name T787
Test name
Test status
Simulation time 40976394 ps
CPU time 3.05 seconds
Started Jun 04 01:58:49 PM PDT 24
Finished Jun 04 01:58:53 PM PDT 24
Peak memory 209196 kb
Host smart-1fabe32d-c733-4aa7-ba9f-1302827daa61
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835826417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1835826417
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1008916286
Short name T546
Test name
Test status
Simulation time 1189646730 ps
CPU time 3.47 seconds
Started Jun 04 01:58:43 PM PDT 24
Finished Jun 04 01:58:48 PM PDT 24
Peak memory 206776 kb
Host smart-c8289c7b-dbbb-4780-8fce-48ae1455d14a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008916286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1008916286
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1514995297
Short name T572
Test name
Test status
Simulation time 91844791 ps
CPU time 2.21 seconds
Started Jun 04 01:58:53 PM PDT 24
Finished Jun 04 01:58:56 PM PDT 24
Peak memory 214368 kb
Host smart-d8dc5bde-d791-45a8-9ab2-0a798a757109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514995297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1514995297
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.938149137
Short name T832
Test name
Test status
Simulation time 567224380 ps
CPU time 3.42 seconds
Started Jun 04 01:58:45 PM PDT 24
Finished Jun 04 01:58:49 PM PDT 24
Peak memory 208120 kb
Host smart-260c9c3a-6c21-4418-969d-6868ad89c550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938149137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.938149137
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.912297648
Short name T63
Test name
Test status
Simulation time 69953919 ps
CPU time 2.62 seconds
Started Jun 04 01:58:49 PM PDT 24
Finished Jun 04 01:58:52 PM PDT 24
Peak memory 209968 kb
Host smart-0732958c-5a4a-4d23-8378-b58ae0b9f925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912297648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.912297648
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.761063890
Short name T843
Test name
Test status
Simulation time 16167346 ps
CPU time 0.96 seconds
Started Jun 04 01:59:03 PM PDT 24
Finished Jun 04 01:59:04 PM PDT 24
Peak memory 206112 kb
Host smart-4e1890aa-d120-43f1-b494-cc58e5eb9443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761063890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.761063890
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.4067955408
Short name T155
Test name
Test status
Simulation time 65049049 ps
CPU time 4.37 seconds
Started Jun 04 01:58:50 PM PDT 24
Finished Jun 04 01:58:56 PM PDT 24
Peak memory 214356 kb
Host smart-34ca22d4-ca31-47a0-9206-27e0902fbdf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067955408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.4067955408
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1144275928
Short name T234
Test name
Test status
Simulation time 272260654 ps
CPU time 3.35 seconds
Started Jun 04 01:58:59 PM PDT 24
Finished Jun 04 01:59:03 PM PDT 24
Peak memory 208484 kb
Host smart-4909ab07-6035-42a5-ae22-9623e53e190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144275928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1144275928
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2360915180
Short name T85
Test name
Test status
Simulation time 509778975 ps
CPU time 4.78 seconds
Started Jun 04 01:58:51 PM PDT 24
Finished Jun 04 01:58:57 PM PDT 24
Peak memory 207684 kb
Host smart-52b7f91f-0104-41f0-ad4c-d8056cdbbdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360915180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2360915180
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2499128376
Short name T630
Test name
Test status
Simulation time 222097119 ps
CPU time 3.62 seconds
Started Jun 04 01:59:00 PM PDT 24
Finished Jun 04 01:59:04 PM PDT 24
Peak memory 221956 kb
Host smart-2716c1c6-079d-4159-955d-c414876b1684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499128376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2499128376
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4026849350
Short name T754
Test name
Test status
Simulation time 127439279 ps
CPU time 2.34 seconds
Started Jun 04 01:59:00 PM PDT 24
Finished Jun 04 01:59:03 PM PDT 24
Peak memory 214292 kb
Host smart-0dbf3cf1-4c37-49d1-8d2a-78921ecc73c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026849350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4026849350
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2248105000
Short name T679
Test name
Test status
Simulation time 147227419 ps
CPU time 2.69 seconds
Started Jun 04 01:58:59 PM PDT 24
Finished Jun 04 01:59:03 PM PDT 24
Peak memory 208008 kb
Host smart-bdafbdd2-aa21-4e50-b539-e1ae36becaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248105000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2248105000
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3922650019
Short name T320
Test name
Test status
Simulation time 872549948 ps
CPU time 6.44 seconds
Started Jun 04 01:58:52 PM PDT 24
Finished Jun 04 01:58:59 PM PDT 24
Peak memory 214308 kb
Host smart-b2da3bd4-3535-4230-874d-944e65d597a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922650019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3922650019
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.270084525
Short name T699
Test name
Test status
Simulation time 80096149 ps
CPU time 3.31 seconds
Started Jun 04 01:58:51 PM PDT 24
Finished Jun 04 01:58:55 PM PDT 24
Peak memory 208492 kb
Host smart-16fa2b6a-814c-4828-942c-49b47ab0f4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270084525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.270084525
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2815289380
Short name T562
Test name
Test status
Simulation time 108066233 ps
CPU time 2.95 seconds
Started Jun 04 01:58:51 PM PDT 24
Finished Jun 04 01:58:54 PM PDT 24
Peak memory 207380 kb
Host smart-aa1b5af0-13f2-4cdf-a256-b6346c5792b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815289380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2815289380
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.204828592
Short name T550
Test name
Test status
Simulation time 2354695771 ps
CPU time 22.96 seconds
Started Jun 04 01:58:52 PM PDT 24
Finished Jun 04 01:59:15 PM PDT 24
Peak memory 208392 kb
Host smart-cf8efa7e-fc5d-4b02-8fbc-350bae3aec65
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204828592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.204828592
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1363297241
Short name T777
Test name
Test status
Simulation time 298589032 ps
CPU time 3.9 seconds
Started Jun 04 01:58:51 PM PDT 24
Finished Jun 04 01:58:55 PM PDT 24
Peak memory 208772 kb
Host smart-a1fb8e2e-2d83-4409-8391-d2e8e1771ed4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363297241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1363297241
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3926327190
Short name T763
Test name
Test status
Simulation time 157780500 ps
CPU time 2.69 seconds
Started Jun 04 01:59:01 PM PDT 24
Finished Jun 04 01:59:04 PM PDT 24
Peak memory 218312 kb
Host smart-093afca7-0314-4d1f-a6db-731fa5a30e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926327190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3926327190
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2493545253
Short name T645
Test name
Test status
Simulation time 148129177 ps
CPU time 2.84 seconds
Started Jun 04 01:58:49 PM PDT 24
Finished Jun 04 01:58:53 PM PDT 24
Peak memory 206812 kb
Host smart-bde5cc3c-55b8-43af-943a-f4d69a896f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493545253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2493545253
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1888022990
Short name T56
Test name
Test status
Simulation time 1178614189 ps
CPU time 31.79 seconds
Started Jun 04 01:58:59 PM PDT 24
Finished Jun 04 01:59:32 PM PDT 24
Peak memory 216796 kb
Host smart-0cd8c4c2-58e9-4bc0-b8cb-66947fc93cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888022990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1888022990
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2244834124
Short name T324
Test name
Test status
Simulation time 2417785806 ps
CPU time 24.61 seconds
Started Jun 04 01:58:59 PM PDT 24
Finished Jun 04 01:59:24 PM PDT 24
Peak memory 220760 kb
Host smart-579e2f4c-2fbe-459e-8243-45e731e6fcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244834124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2244834124
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3385254172
Short name T180
Test name
Test status
Simulation time 52856515 ps
CPU time 2.23 seconds
Started Jun 04 01:59:00 PM PDT 24
Finished Jun 04 01:59:03 PM PDT 24
Peak memory 210192 kb
Host smart-82d4885e-320f-4925-bc92-92427a4227ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385254172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3385254172
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1697995023
Short name T746
Test name
Test status
Simulation time 35332543 ps
CPU time 0.92 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:12 PM PDT 24
Peak memory 206108 kb
Host smart-1fb67ba7-3836-4742-9856-368e69216f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697995023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1697995023
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2340300364
Short name T413
Test name
Test status
Simulation time 306534990 ps
CPU time 16.2 seconds
Started Jun 04 01:58:59 PM PDT 24
Finished Jun 04 01:59:16 PM PDT 24
Peak memory 214356 kb
Host smart-9e81c504-a19c-4c1f-afd5-ce69e98b7efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340300364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2340300364
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1819814377
Short name T41
Test name
Test status
Simulation time 498049659 ps
CPU time 3.69 seconds
Started Jun 04 01:59:07 PM PDT 24
Finished Jun 04 01:59:12 PM PDT 24
Peak memory 208608 kb
Host smart-05349b87-73e7-4efe-b396-e1b468edd554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819814377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1819814377
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.377836159
Short name T362
Test name
Test status
Simulation time 1160897496 ps
CPU time 5.26 seconds
Started Jun 04 01:59:01 PM PDT 24
Finished Jun 04 01:59:07 PM PDT 24
Peak memory 218332 kb
Host smart-f18a2025-b62c-4216-9f68-e6145edcf0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377836159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.377836159
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3864959781
Short name T775
Test name
Test status
Simulation time 71343603 ps
CPU time 1.72 seconds
Started Jun 04 01:59:08 PM PDT 24
Finished Jun 04 01:59:11 PM PDT 24
Peak memory 214248 kb
Host smart-890ae77f-fd04-4e06-ac76-36d106ff86a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864959781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3864959781
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1365040576
Short name T279
Test name
Test status
Simulation time 114764413 ps
CPU time 3.87 seconds
Started Jun 04 01:59:00 PM PDT 24
Finished Jun 04 01:59:05 PM PDT 24
Peak memory 222284 kb
Host smart-9d8316b1-f2a4-4df8-bec6-e0ace8fa3ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365040576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1365040576
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.347863267
Short name T205
Test name
Test status
Simulation time 171617750 ps
CPU time 4.48 seconds
Started Jun 04 01:58:58 PM PDT 24
Finished Jun 04 01:59:03 PM PDT 24
Peak memory 206972 kb
Host smart-788868ce-9737-4241-8f64-b254d66e25bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347863267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.347863267
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2907167392
Short name T839
Test name
Test status
Simulation time 279504067 ps
CPU time 2.68 seconds
Started Jun 04 01:59:01 PM PDT 24
Finished Jun 04 01:59:04 PM PDT 24
Peak memory 206896 kb
Host smart-97ee4450-2966-45e6-bf54-0100d3dfad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907167392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2907167392
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3030774878
Short name T461
Test name
Test status
Simulation time 1301508944 ps
CPU time 4.81 seconds
Started Jun 04 01:59:00 PM PDT 24
Finished Jun 04 01:59:06 PM PDT 24
Peak memory 208600 kb
Host smart-b2391237-663b-4410-86cd-5ceb0d7fa50f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030774878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3030774878
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2995023353
Short name T526
Test name
Test status
Simulation time 40661045 ps
CPU time 2.27 seconds
Started Jun 04 01:59:00 PM PDT 24
Finished Jun 04 01:59:03 PM PDT 24
Peak memory 206956 kb
Host smart-66702e83-e270-4410-a3de-507ee0926182
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995023353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2995023353
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2135533265
Short name T714
Test name
Test status
Simulation time 1023117862 ps
CPU time 3.89 seconds
Started Jun 04 01:59:02 PM PDT 24
Finished Jun 04 01:59:06 PM PDT 24
Peak memory 208776 kb
Host smart-0f620380-8341-4f5b-96a7-9ac08c8d0e9a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135533265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2135533265
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3113070869
Short name T653
Test name
Test status
Simulation time 47824622 ps
CPU time 1.37 seconds
Started Jun 04 01:59:08 PM PDT 24
Finished Jun 04 01:59:10 PM PDT 24
Peak memory 215312 kb
Host smart-44337e74-9a44-4c2a-bf38-8d3dd700a5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113070869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3113070869
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.655206943
Short name T894
Test name
Test status
Simulation time 339939485 ps
CPU time 4.1 seconds
Started Jun 04 01:58:59 PM PDT 24
Finished Jun 04 01:59:04 PM PDT 24
Peak memory 208524 kb
Host smart-a8e4cf6b-993f-4edf-8bb3-ee8ad6a995dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655206943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.655206943
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3703831204
Short name T77
Test name
Test status
Simulation time 155210899 ps
CPU time 3.12 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 207320 kb
Host smart-d4f075f5-1493-4bca-bf81-389521e21d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703831204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3703831204
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2907772412
Short name T568
Test name
Test status
Simulation time 523616766 ps
CPU time 22.37 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:33 PM PDT 24
Peak memory 222508 kb
Host smart-83fcc9ec-c871-4ef0-84bd-8030285d988a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907772412 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2907772412
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1606680833
Short name T818
Test name
Test status
Simulation time 58628293 ps
CPU time 2.17 seconds
Started Jun 04 01:58:55 PM PDT 24
Finished Jun 04 01:58:58 PM PDT 24
Peak memory 214348 kb
Host smart-10eb0854-32a4-4b07-9611-8af9a7accf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606680833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1606680833
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1959015900
Short name T565
Test name
Test status
Simulation time 342955427 ps
CPU time 10.47 seconds
Started Jun 04 01:59:07 PM PDT 24
Finished Jun 04 01:59:19 PM PDT 24
Peak memory 211180 kb
Host smart-cef2b02a-1a80-4f78-8929-b5eae0f6f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959015900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1959015900
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.159018592
Short name T881
Test name
Test status
Simulation time 11247252 ps
CPU time 0.86 seconds
Started Jun 04 01:59:06 PM PDT 24
Finished Jun 04 01:59:08 PM PDT 24
Peak memory 205896 kb
Host smart-e78d8278-76bd-4a8e-8dc6-7bc40f6a40b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159018592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.159018592
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1189361023
Short name T359
Test name
Test status
Simulation time 778666752 ps
CPU time 10.99 seconds
Started Jun 04 01:59:08 PM PDT 24
Finished Jun 04 01:59:20 PM PDT 24
Peak memory 215388 kb
Host smart-6678b219-7b49-4462-88e2-d4a0d573d0ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1189361023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1189361023
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.4166532857
Short name T240
Test name
Test status
Simulation time 473194397 ps
CPU time 3.85 seconds
Started Jun 04 01:59:08 PM PDT 24
Finished Jun 04 01:59:13 PM PDT 24
Peak memory 214656 kb
Host smart-cb0c80c4-3ebe-4f6a-b09f-84e307c519fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166532857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.4166532857
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1395545054
Short name T731
Test name
Test status
Simulation time 133582498 ps
CPU time 1.9 seconds
Started Jun 04 01:59:08 PM PDT 24
Finished Jun 04 01:59:12 PM PDT 24
Peak memory 218392 kb
Host smart-39359084-8468-4c62-8252-21321eddd63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395545054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1395545054
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.108294644
Short name T301
Test name
Test status
Simulation time 143187563 ps
CPU time 5.31 seconds
Started Jun 04 01:59:07 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 219108 kb
Host smart-2780a676-e315-4b85-96b5-baee22f10b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108294644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.108294644
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2251539266
Short name T256
Test name
Test status
Simulation time 217286418 ps
CPU time 3.54 seconds
Started Jun 04 01:59:07 PM PDT 24
Finished Jun 04 01:59:12 PM PDT 24
Peak memory 214512 kb
Host smart-aafeb18c-4dd3-4d82-accf-0b513bed0f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251539266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2251539266
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2318658029
Short name T828
Test name
Test status
Simulation time 277209737 ps
CPU time 2.56 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 209588 kb
Host smart-19cfc6e1-fa76-481f-952f-4067503cc0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318658029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2318658029
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.661037403
Short name T275
Test name
Test status
Simulation time 98424309 ps
CPU time 3.56 seconds
Started Jun 04 01:59:06 PM PDT 24
Finished Jun 04 01:59:10 PM PDT 24
Peak memory 218472 kb
Host smart-2d5f1d57-5fff-4ba9-b6df-f2148deea1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661037403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.661037403
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.150777066
Short name T265
Test name
Test status
Simulation time 341060710 ps
CPU time 4.41 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:15 PM PDT 24
Peak memory 208644 kb
Host smart-fa4cb1f9-e6dd-467d-b2ce-02ebbabab510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150777066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.150777066
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1720031030
Short name T897
Test name
Test status
Simulation time 38560591 ps
CPU time 2.27 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 206756 kb
Host smart-8f0a1a75-0b90-4b30-ab82-c27a589eb2e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720031030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1720031030
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1568168786
Short name T792
Test name
Test status
Simulation time 4085881105 ps
CPU time 11.21 seconds
Started Jun 04 01:59:08 PM PDT 24
Finished Jun 04 01:59:21 PM PDT 24
Peak memory 206948 kb
Host smart-014a7dc8-bc6c-409d-92bf-4c8afeb20caa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568168786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1568168786
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1342403264
Short name T729
Test name
Test status
Simulation time 146180749 ps
CPU time 2.79 seconds
Started Jun 04 01:59:07 PM PDT 24
Finished Jun 04 01:59:11 PM PDT 24
Peak memory 208428 kb
Host smart-936a26d7-98fa-4d17-b889-d6aa5ae6fe14
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342403264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1342403264
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.123382535
Short name T733
Test name
Test status
Simulation time 145627760 ps
CPU time 1.99 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:13 PM PDT 24
Peak memory 207976 kb
Host smart-475a15fe-37e1-4fe9-939d-a302bdabab79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123382535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.123382535
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.101665641
Short name T120
Test name
Test status
Simulation time 120189033 ps
CPU time 2.43 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 208328 kb
Host smart-b7d67d33-710c-4ddf-8905-c8a44aa2ba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101665641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.101665641
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.618922338
Short name T358
Test name
Test status
Simulation time 1980174613 ps
CPU time 24.64 seconds
Started Jun 04 01:59:07 PM PDT 24
Finished Jun 04 01:59:33 PM PDT 24
Peak memory 222504 kb
Host smart-8a356fe3-22f9-4252-8f70-fc4c8272ebf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618922338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.618922338
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2747191663
Short name T346
Test name
Test status
Simulation time 255411605 ps
CPU time 7.65 seconds
Started Jun 04 01:59:07 PM PDT 24
Finished Jun 04 01:59:16 PM PDT 24
Peak memory 207640 kb
Host smart-348f0e5c-0b7f-4726-ba51-c32ae1237478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747191663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2747191663
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1993760895
Short name T667
Test name
Test status
Simulation time 119387417 ps
CPU time 1.33 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:12 PM PDT 24
Peak memory 209520 kb
Host smart-bec7dba4-cfbb-4841-9644-3241ecdd384f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993760895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1993760895
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.309162074
Short name T3
Test name
Test status
Simulation time 14448856 ps
CPU time 0.77 seconds
Started Jun 04 01:59:08 PM PDT 24
Finished Jun 04 01:59:10 PM PDT 24
Peak memory 205960 kb
Host smart-176a49c2-0e75-4162-af7c-c6ef87ad7feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309162074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.309162074
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2172276140
Short name T280
Test name
Test status
Simulation time 80815455 ps
CPU time 2.85 seconds
Started Jun 04 01:59:08 PM PDT 24
Finished Jun 04 01:59:12 PM PDT 24
Peak memory 214348 kb
Host smart-8000fedd-8be3-4629-8d82-d3313cbbcd0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172276140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2172276140
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4046188492
Short name T605
Test name
Test status
Simulation time 101294500 ps
CPU time 2.58 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 209572 kb
Host smart-e04a07fb-8a49-4396-b408-82a0a88c44c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046188492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4046188492
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1756386392
Short name T870
Test name
Test status
Simulation time 72847267 ps
CPU time 3.03 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 207640 kb
Host smart-9a7ba550-e0d2-4790-9621-9c33252699e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756386392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1756386392
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.4107230228
Short name T709
Test name
Test status
Simulation time 1257492731 ps
CPU time 25.41 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:36 PM PDT 24
Peak memory 214300 kb
Host smart-94fec4d2-ad9c-45f3-9415-30ca0145ac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107230228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.4107230228
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2985541719
Short name T305
Test name
Test status
Simulation time 582531121 ps
CPU time 4.03 seconds
Started Jun 04 01:59:10 PM PDT 24
Finished Jun 04 01:59:16 PM PDT 24
Peak memory 221680 kb
Host smart-633a9e4c-0792-47fc-a300-198af2ca40a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985541719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2985541719
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1973835235
Short name T296
Test name
Test status
Simulation time 68177535 ps
CPU time 4.24 seconds
Started Jun 04 01:59:11 PM PDT 24
Finished Jun 04 01:59:17 PM PDT 24
Peak memory 214412 kb
Host smart-7836a4c8-58a8-4104-bb9a-0069f6b85fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973835235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1973835235
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3316418161
Short name T89
Test name
Test status
Simulation time 222157574 ps
CPU time 3.65 seconds
Started Jun 04 01:59:08 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 218156 kb
Host smart-1b679c10-c4c4-4dca-8868-4bc23dfb3653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316418161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3316418161
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.43070274
Short name T470
Test name
Test status
Simulation time 250944834 ps
CPU time 4.35 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:15 PM PDT 24
Peak memory 208740 kb
Host smart-8ce577c6-25a0-46f9-8b03-1a5950787552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43070274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.43070274
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2192758868
Short name T773
Test name
Test status
Simulation time 292290122 ps
CPU time 5.91 seconds
Started Jun 04 01:59:07 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 208188 kb
Host smart-0296173c-54aa-4d88-bc03-b13090e00bcd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192758868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2192758868
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3565787427
Short name T485
Test name
Test status
Simulation time 197531816 ps
CPU time 4.74 seconds
Started Jun 04 01:59:07 PM PDT 24
Finished Jun 04 01:59:12 PM PDT 24
Peak memory 208780 kb
Host smart-75a314a4-7d2d-44da-9a58-62e42176113e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565787427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3565787427
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2715433343
Short name T800
Test name
Test status
Simulation time 55916826 ps
CPU time 2.73 seconds
Started Jun 04 01:59:12 PM PDT 24
Finished Jun 04 01:59:16 PM PDT 24
Peak memory 208052 kb
Host smart-0678f5e1-ed01-4e02-8b72-d7a26d4b0c82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715433343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2715433343
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2439053833
Short name T899
Test name
Test status
Simulation time 198980760 ps
CPU time 2.57 seconds
Started Jun 04 01:59:09 PM PDT 24
Finished Jun 04 01:59:13 PM PDT 24
Peak memory 209852 kb
Host smart-af7dd310-a17b-4399-a57d-2e364ecb93ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439053833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2439053833
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1563806898
Short name T706
Test name
Test status
Simulation time 205333868 ps
CPU time 2.62 seconds
Started Jun 04 01:59:10 PM PDT 24
Finished Jun 04 01:59:15 PM PDT 24
Peak memory 208640 kb
Host smart-7de70d54-40f5-4199-8874-dd5ac8179d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563806898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1563806898
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3835393924
Short name T321
Test name
Test status
Simulation time 1803572180 ps
CPU time 24.62 seconds
Started Jun 04 01:59:08 PM PDT 24
Finished Jun 04 01:59:34 PM PDT 24
Peak memory 215000 kb
Host smart-1e100704-0a40-430c-bfc5-25cbabb17898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835393924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3835393924
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3050914883
Short name T432
Test name
Test status
Simulation time 10290071040 ps
CPU time 59.66 seconds
Started Jun 04 01:59:07 PM PDT 24
Finished Jun 04 02:00:08 PM PDT 24
Peak memory 221568 kb
Host smart-190e7229-b0ee-4c8c-978f-8804f3a500e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050914883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3050914883
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2482152789
Short name T503
Test name
Test status
Simulation time 288239059 ps
CPU time 2.13 seconds
Started Jun 04 01:59:11 PM PDT 24
Finished Jun 04 01:59:15 PM PDT 24
Peak memory 209836 kb
Host smart-25d1be36-7cbd-4bcd-9757-b5434ecd0b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482152789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2482152789
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.922813536
Short name T825
Test name
Test status
Simulation time 12501297 ps
CPU time 0.86 seconds
Started Jun 04 01:59:15 PM PDT 24
Finished Jun 04 01:59:16 PM PDT 24
Peak memory 205956 kb
Host smart-203dd905-d34b-4fc7-b80b-db82fd3c6501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922813536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.922813536
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3681593056
Short name T408
Test name
Test status
Simulation time 162900952 ps
CPU time 8.69 seconds
Started Jun 04 01:59:14 PM PDT 24
Finished Jun 04 01:59:24 PM PDT 24
Peak memory 214324 kb
Host smart-b5ed989f-c5ce-4bf8-9559-c21e8ced5de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681593056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3681593056
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2192167804
Short name T10
Test name
Test status
Simulation time 297723117 ps
CPU time 2.31 seconds
Started Jun 04 01:59:19 PM PDT 24
Finished Jun 04 01:59:22 PM PDT 24
Peak memory 219096 kb
Host smart-4f709ce8-6e84-4d81-a08a-8de871f25b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192167804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2192167804
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2911033847
Short name T79
Test name
Test status
Simulation time 287977271 ps
CPU time 2.29 seconds
Started Jun 04 01:59:14 PM PDT 24
Finished Jun 04 01:59:17 PM PDT 24
Peak memory 208288 kb
Host smart-bef6c45f-76fc-4b96-bbe6-70e7b360221c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911033847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2911033847
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3889478815
Short name T781
Test name
Test status
Simulation time 118455869 ps
CPU time 2.59 seconds
Started Jun 04 01:59:16 PM PDT 24
Finished Jun 04 01:59:20 PM PDT 24
Peak memory 208372 kb
Host smart-74d29aef-2942-46f3-a158-5bea5f5398a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889478815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3889478815
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2630164763
Short name T613
Test name
Test status
Simulation time 131007735 ps
CPU time 4.42 seconds
Started Jun 04 01:59:16 PM PDT 24
Finished Jun 04 01:59:22 PM PDT 24
Peak memory 214264 kb
Host smart-009ff430-f810-4609-9767-f6a0f96983a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630164763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2630164763
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2862883702
Short name T480
Test name
Test status
Simulation time 53339860 ps
CPU time 2.04 seconds
Started Jun 04 01:59:17 PM PDT 24
Finished Jun 04 01:59:20 PM PDT 24
Peak memory 214300 kb
Host smart-d247c587-c64c-4754-bd10-609ca5af3f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862883702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2862883702
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1531558820
Short name T583
Test name
Test status
Simulation time 64789026 ps
CPU time 3.66 seconds
Started Jun 04 01:59:16 PM PDT 24
Finished Jun 04 01:59:21 PM PDT 24
Peak memory 209448 kb
Host smart-3851de7b-bd26-45a4-ada2-9c56ff90d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531558820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1531558820
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3385114208
Short name T513
Test name
Test status
Simulation time 308180324 ps
CPU time 2.39 seconds
Started Jun 04 01:59:15 PM PDT 24
Finished Jun 04 01:59:18 PM PDT 24
Peak memory 206892 kb
Host smart-a34d3bb5-ce40-4456-b578-fcc2d56871ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385114208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3385114208
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.790856793
Short name T347
Test name
Test status
Simulation time 105947103 ps
CPU time 4.08 seconds
Started Jun 04 01:59:17 PM PDT 24
Finished Jun 04 01:59:22 PM PDT 24
Peak memory 206904 kb
Host smart-2dd106e7-7fc3-46e3-8caa-868eb93549e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790856793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.790856793
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4123101962
Short name T663
Test name
Test status
Simulation time 108329633 ps
CPU time 3.23 seconds
Started Jun 04 01:59:17 PM PDT 24
Finished Jun 04 01:59:21 PM PDT 24
Peak memory 208356 kb
Host smart-a6fbac35-c2b7-4e53-b80c-16918f984dd3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123101962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4123101962
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2957046657
Short name T786
Test name
Test status
Simulation time 1600262642 ps
CPU time 8.19 seconds
Started Jun 04 01:59:18 PM PDT 24
Finished Jun 04 01:59:27 PM PDT 24
Peak memory 208232 kb
Host smart-93526605-5ca3-429b-b518-4c62401bf6fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957046657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2957046657
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3469098065
Short name T876
Test name
Test status
Simulation time 21578422 ps
CPU time 1.38 seconds
Started Jun 04 01:59:17 PM PDT 24
Finished Jun 04 01:59:19 PM PDT 24
Peak memory 206936 kb
Host smart-8477e5ca-b286-4084-84ad-c106da51a9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469098065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3469098065
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2664921155
Short name T636
Test name
Test status
Simulation time 3955585719 ps
CPU time 17.89 seconds
Started Jun 04 01:59:18 PM PDT 24
Finished Jun 04 01:59:37 PM PDT 24
Peak memory 208000 kb
Host smart-22a033b8-20b8-4a08-ac5e-a70c23a677c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664921155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2664921155
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2892099556
Short name T220
Test name
Test status
Simulation time 434426664 ps
CPU time 5.29 seconds
Started Jun 04 01:59:17 PM PDT 24
Finished Jun 04 01:59:23 PM PDT 24
Peak memory 207624 kb
Host smart-dd43bd6e-a074-4c46-aacc-bbedb915c19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892099556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2892099556
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.276805841
Short name T661
Test name
Test status
Simulation time 89468745 ps
CPU time 2.25 seconds
Started Jun 04 01:59:17 PM PDT 24
Finished Jun 04 01:59:20 PM PDT 24
Peak memory 210252 kb
Host smart-2970d969-d1d7-42a9-a158-871c39ac6050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276805841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.276805841
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2998422259
Short name T896
Test name
Test status
Simulation time 20090328 ps
CPU time 0.86 seconds
Started Jun 04 01:59:24 PM PDT 24
Finished Jun 04 01:59:26 PM PDT 24
Peak memory 205892 kb
Host smart-b9ae877c-5298-4d6e-960e-09ada31cf668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998422259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2998422259
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.822789545
Short name T338
Test name
Test status
Simulation time 110826370 ps
CPU time 3.85 seconds
Started Jun 04 01:59:16 PM PDT 24
Finished Jun 04 01:59:21 PM PDT 24
Peak memory 214376 kb
Host smart-bf856ad5-06d4-43e9-8301-9c3f78a3447b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822789545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.822789545
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3377183327
Short name T624
Test name
Test status
Simulation time 376210311 ps
CPU time 2.9 seconds
Started Jun 04 01:59:26 PM PDT 24
Finished Jun 04 01:59:30 PM PDT 24
Peak memory 218376 kb
Host smart-fdc2bbd0-d4a6-47b0-a17e-ce36d16a6eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377183327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3377183327
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1305426252
Short name T330
Test name
Test status
Simulation time 428006151 ps
CPU time 4.75 seconds
Started Jun 04 01:59:23 PM PDT 24
Finished Jun 04 01:59:28 PM PDT 24
Peak memory 214620 kb
Host smart-ec742534-4ead-4af9-87fe-c20aee4affef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305426252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1305426252
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2470071192
Short name T290
Test name
Test status
Simulation time 51344128 ps
CPU time 3.08 seconds
Started Jun 04 01:59:23 PM PDT 24
Finished Jun 04 01:59:27 PM PDT 24
Peak memory 214516 kb
Host smart-3501d00a-be3d-4412-9f45-8d749077ca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470071192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2470071192
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.849620658
Short name T798
Test name
Test status
Simulation time 53818208 ps
CPU time 3.49 seconds
Started Jun 04 01:59:23 PM PDT 24
Finished Jun 04 01:59:28 PM PDT 24
Peak memory 218636 kb
Host smart-faedb4a0-05a3-4521-ab3a-d5cedf5b23b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849620658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.849620658
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.898056832
Short name T743
Test name
Test status
Simulation time 194310340 ps
CPU time 5.48 seconds
Started Jun 04 01:59:14 PM PDT 24
Finished Jun 04 01:59:21 PM PDT 24
Peak memory 208252 kb
Host smart-0cc09b23-72d9-40b0-afde-fb0bf7241721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898056832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.898056832
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.296400889
Short name T361
Test name
Test status
Simulation time 1011206889 ps
CPU time 18.95 seconds
Started Jun 04 01:59:19 PM PDT 24
Finished Jun 04 01:59:38 PM PDT 24
Peak memory 208184 kb
Host smart-86888191-ee46-4346-a0d0-d0e954874592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296400889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.296400889
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1469972589
Short name T821
Test name
Test status
Simulation time 421283301 ps
CPU time 3.5 seconds
Started Jun 04 01:59:18 PM PDT 24
Finished Jun 04 01:59:23 PM PDT 24
Peak memory 206896 kb
Host smart-3d6cbed3-5f99-4218-8150-70d004d6e584
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469972589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1469972589
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1327375014
Short name T734
Test name
Test status
Simulation time 3335754496 ps
CPU time 37.34 seconds
Started Jun 04 01:59:17 PM PDT 24
Finished Jun 04 01:59:56 PM PDT 24
Peak memory 208516 kb
Host smart-7823aa06-eafd-49a8-acbb-58ade34fb4d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327375014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1327375014
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1917355398
Short name T864
Test name
Test status
Simulation time 233128783 ps
CPU time 3.37 seconds
Started Jun 04 01:59:17 PM PDT 24
Finished Jun 04 01:59:21 PM PDT 24
Peak memory 206412 kb
Host smart-5a5bed74-1196-4c24-b4af-2963c298ad21
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917355398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1917355398
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1995287019
Short name T764
Test name
Test status
Simulation time 61987141 ps
CPU time 1.51 seconds
Started Jun 04 01:59:24 PM PDT 24
Finished Jun 04 01:59:27 PM PDT 24
Peak memory 208168 kb
Host smart-1acfc1e9-312a-4b39-a72b-82cb56cc30dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995287019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1995287019
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.187630342
Short name T629
Test name
Test status
Simulation time 519796768 ps
CPU time 3.76 seconds
Started Jun 04 01:59:18 PM PDT 24
Finished Jun 04 01:59:23 PM PDT 24
Peak memory 208672 kb
Host smart-747e6fff-f346-4bb8-a118-e5349045f3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187630342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.187630342
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1007067101
Short name T887
Test name
Test status
Simulation time 108383216 ps
CPU time 3.35 seconds
Started Jun 04 01:59:22 PM PDT 24
Finished Jun 04 01:59:27 PM PDT 24
Peak memory 209952 kb
Host smart-b53e73b5-12cc-4800-95b6-a868028a131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007067101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1007067101
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2736425925
Short name T573
Test name
Test status
Simulation time 14215487 ps
CPU time 0.73 seconds
Started Jun 04 01:57:34 PM PDT 24
Finished Jun 04 01:57:35 PM PDT 24
Peak memory 205964 kb
Host smart-7ddc684a-8701-431c-b97f-048c4faaba8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736425925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2736425925
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2511181698
Short name T426
Test name
Test status
Simulation time 58087476 ps
CPU time 2.47 seconds
Started Jun 04 01:57:34 PM PDT 24
Finished Jun 04 01:57:37 PM PDT 24
Peak memory 214324 kb
Host smart-273701ff-d5ca-46e8-9696-7788338eb8dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511181698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2511181698
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3193367665
Short name T622
Test name
Test status
Simulation time 91590971 ps
CPU time 4.44 seconds
Started Jun 04 01:57:35 PM PDT 24
Finished Jun 04 01:57:40 PM PDT 24
Peak memory 218384 kb
Host smart-a6119108-d907-4f6f-a03e-9a96414201b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193367665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3193367665
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.550056019
Short name T814
Test name
Test status
Simulation time 171690786 ps
CPU time 3.41 seconds
Started Jun 04 01:57:32 PM PDT 24
Finished Jun 04 01:57:36 PM PDT 24
Peak memory 209504 kb
Host smart-ceb850c2-cf7f-4da1-9a17-56fdc55177d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550056019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.550056019
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3805955643
Short name T26
Test name
Test status
Simulation time 263392308 ps
CPU time 7.37 seconds
Started Jun 04 01:57:34 PM PDT 24
Finished Jun 04 01:57:43 PM PDT 24
Peak memory 214228 kb
Host smart-9c596353-5a79-4e96-b074-6a44b229e142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805955643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3805955643
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3441850741
Short name T200
Test name
Test status
Simulation time 109613126 ps
CPU time 1.86 seconds
Started Jun 04 01:57:34 PM PDT 24
Finished Jun 04 01:57:37 PM PDT 24
Peak memory 214220 kb
Host smart-c9805354-7d3e-408d-a0f7-65c4fcf54bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441850741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3441850741
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2283669698
Short name T194
Test name
Test status
Simulation time 677839527 ps
CPU time 6.52 seconds
Started Jun 04 01:57:35 PM PDT 24
Finished Jun 04 01:57:42 PM PDT 24
Peak memory 218860 kb
Host smart-cd1c3ad8-3fbb-4d73-9d35-fab79cac2f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283669698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2283669698
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3330380990
Short name T831
Test name
Test status
Simulation time 277565220 ps
CPU time 5.54 seconds
Started Jun 04 01:57:32 PM PDT 24
Finished Jun 04 01:57:38 PM PDT 24
Peak memory 209704 kb
Host smart-8e2d1678-1721-47c5-a04e-056e5e3d5cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330380990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3330380990
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2889965691
Short name T12
Test name
Test status
Simulation time 2420333135 ps
CPU time 5.12 seconds
Started Jun 04 01:57:34 PM PDT 24
Finished Jun 04 01:57:41 PM PDT 24
Peak memory 233424 kb
Host smart-21dea6d3-79aa-4ee7-be41-38f50b9fc917
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889965691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2889965691
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2690807971
Short name T317
Test name
Test status
Simulation time 6398254247 ps
CPU time 45.38 seconds
Started Jun 04 01:57:28 PM PDT 24
Finished Jun 04 01:58:15 PM PDT 24
Peak memory 208840 kb
Host smart-871eeeee-6f47-4e2c-b2bd-f13eaf4eec17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690807971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2690807971
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4054367169
Short name T683
Test name
Test status
Simulation time 112826044 ps
CPU time 3.1 seconds
Started Jun 04 01:57:29 PM PDT 24
Finished Jun 04 01:57:32 PM PDT 24
Peak memory 208760 kb
Host smart-09ca1bb0-2112-40b1-9b6c-05f5c617e5ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054367169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4054367169
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3292027863
Short name T435
Test name
Test status
Simulation time 210231193 ps
CPU time 6.79 seconds
Started Jun 04 01:57:29 PM PDT 24
Finished Jun 04 01:57:36 PM PDT 24
Peak memory 207952 kb
Host smart-9cdea6aa-cdb9-454f-8d33-7f5258504d89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292027863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3292027863
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1291169709
Short name T569
Test name
Test status
Simulation time 319925647 ps
CPU time 3.81 seconds
Started Jun 04 01:57:34 PM PDT 24
Finished Jun 04 01:57:39 PM PDT 24
Peak memory 215860 kb
Host smart-f2e5873d-55d7-461d-ba35-ba530d0711ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291169709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1291169709
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2991742852
Short name T903
Test name
Test status
Simulation time 94543708 ps
CPU time 2.26 seconds
Started Jun 04 01:57:29 PM PDT 24
Finished Jun 04 01:57:32 PM PDT 24
Peak memory 206772 kb
Host smart-7ffe73d5-3171-4035-9a7f-fb6336813229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991742852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2991742852
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3070637365
Short name T855
Test name
Test status
Simulation time 1844010569 ps
CPU time 17.39 seconds
Started Jun 04 01:57:34 PM PDT 24
Finished Jun 04 01:57:53 PM PDT 24
Peak memory 218836 kb
Host smart-d589e286-842e-471b-b096-e9ca35495090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070637365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3070637365
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.168837874
Short name T478
Test name
Test status
Simulation time 48053102 ps
CPU time 2.85 seconds
Started Jun 04 01:57:34 PM PDT 24
Finished Jun 04 01:57:37 PM PDT 24
Peak memory 208048 kb
Host smart-a04d42c6-f56d-4de7-a1c8-923b23f7222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168837874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.168837874
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.617086735
Short name T142
Test name
Test status
Simulation time 977595127 ps
CPU time 7.83 seconds
Started Jun 04 01:57:34 PM PDT 24
Finished Jun 04 01:57:43 PM PDT 24
Peak memory 209768 kb
Host smart-ef170ff7-c885-48f7-b099-9908c8bea50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617086735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.617086735
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2229539316
Short name T782
Test name
Test status
Simulation time 16810161 ps
CPU time 0.91 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:34 PM PDT 24
Peak memory 206032 kb
Host smart-5ca0aa90-9aa0-415e-b5d1-af1d063b2996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229539316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2229539316
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1687998412
Short name T31
Test name
Test status
Simulation time 112833952 ps
CPU time 4.36 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:37 PM PDT 24
Peak memory 210404 kb
Host smart-eb0b3991-17a1-4763-b633-eab9f59546d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687998412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1687998412
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1679337215
Short name T285
Test name
Test status
Simulation time 638973200 ps
CPU time 8.36 seconds
Started Jun 04 01:59:23 PM PDT 24
Finished Jun 04 01:59:33 PM PDT 24
Peak memory 219692 kb
Host smart-d0c26e2e-0c09-4576-b9ab-1823eeb49785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679337215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1679337215
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3248975262
Short name T303
Test name
Test status
Simulation time 109977349 ps
CPU time 4.12 seconds
Started Jun 04 01:59:25 PM PDT 24
Finished Jun 04 01:59:30 PM PDT 24
Peak memory 214304 kb
Host smart-e073b36e-df40-42c5-8000-19d73678f975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248975262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3248975262
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1272602566
Short name T282
Test name
Test status
Simulation time 198623822 ps
CPU time 3.51 seconds
Started Jun 04 01:59:24 PM PDT 24
Finished Jun 04 01:59:28 PM PDT 24
Peak memory 214316 kb
Host smart-4631ce22-3380-4fa2-85ef-066acfd3ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272602566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1272602566
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.718832978
Short name T508
Test name
Test status
Simulation time 1235533490 ps
CPU time 8.56 seconds
Started Jun 04 01:59:27 PM PDT 24
Finished Jun 04 01:59:36 PM PDT 24
Peak memory 218180 kb
Host smart-540df8ce-28f9-4438-951a-910ba784fcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718832978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.718832978
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.4245559233
Short name T95
Test name
Test status
Simulation time 273387880 ps
CPU time 3.27 seconds
Started Jun 04 01:59:23 PM PDT 24
Finished Jun 04 01:59:27 PM PDT 24
Peak memory 208820 kb
Host smart-760b09fd-02fc-47c0-a56d-7ef633890cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245559233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.4245559233
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3231868
Short name T710
Test name
Test status
Simulation time 470221806 ps
CPU time 3.73 seconds
Started Jun 04 01:59:24 PM PDT 24
Finished Jun 04 01:59:29 PM PDT 24
Peak memory 206948 kb
Host smart-d9da80fb-fd50-48c0-9101-4130f9b9f031
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3231868
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3105559486
Short name T708
Test name
Test status
Simulation time 157627012 ps
CPU time 3.95 seconds
Started Jun 04 01:59:25 PM PDT 24
Finished Jun 04 01:59:30 PM PDT 24
Peak memory 208712 kb
Host smart-eefca7a7-3ab2-4c45-87f1-40bc837a6094
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105559486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3105559486
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1245307063
Short name T491
Test name
Test status
Simulation time 179578801 ps
CPU time 2.73 seconds
Started Jun 04 01:59:26 PM PDT 24
Finished Jun 04 01:59:30 PM PDT 24
Peak memory 206908 kb
Host smart-e7c5ef0b-ba20-4407-818a-fcbfa5b83f8c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245307063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1245307063
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2312554351
Short name T611
Test name
Test status
Simulation time 15792488 ps
CPU time 1.49 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:35 PM PDT 24
Peak memory 214412 kb
Host smart-9048ee61-bc99-4c3e-97ec-51ecd47b4762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312554351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2312554351
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.114514220
Short name T845
Test name
Test status
Simulation time 396766827 ps
CPU time 3.98 seconds
Started Jun 04 01:59:23 PM PDT 24
Finished Jun 04 01:59:28 PM PDT 24
Peak memory 208096 kb
Host smart-5f7e49ae-8021-4c24-a9b5-69e3da73dfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114514220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.114514220
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.4174293059
Short name T858
Test name
Test status
Simulation time 991990355 ps
CPU time 12.86 seconds
Started Jun 04 01:59:35 PM PDT 24
Finished Jun 04 01:59:49 PM PDT 24
Peak memory 216280 kb
Host smart-60682967-f164-4a17-bfed-f5ef81cc2cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174293059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.4174293059
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3233948209
Short name T212
Test name
Test status
Simulation time 139699919 ps
CPU time 3.12 seconds
Started Jun 04 01:59:26 PM PDT 24
Finished Jun 04 01:59:29 PM PDT 24
Peak memory 218692 kb
Host smart-43f16c40-52dc-40cf-a5ba-37981d4d9157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233948209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3233948209
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3425971163
Short name T659
Test name
Test status
Simulation time 78120728 ps
CPU time 2.35 seconds
Started Jun 04 01:59:37 PM PDT 24
Finished Jun 04 01:59:40 PM PDT 24
Peak memory 210452 kb
Host smart-98786bd2-c71b-4cd1-ae02-9ce7c3028fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425971163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3425971163
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.135536693
Short name T501
Test name
Test status
Simulation time 62222863 ps
CPU time 0.76 seconds
Started Jun 04 01:59:33 PM PDT 24
Finished Jun 04 01:59:34 PM PDT 24
Peak memory 205972 kb
Host smart-d2a8f0be-cf3c-450e-8a49-0e5bd755963c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135536693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.135536693
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2704953615
Short name T393
Test name
Test status
Simulation time 239542844 ps
CPU time 12.08 seconds
Started Jun 04 01:59:33 PM PDT 24
Finished Jun 04 01:59:46 PM PDT 24
Peak memory 214300 kb
Host smart-1c75ef2b-6260-4baf-89e7-c0adc5a4feda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704953615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2704953615
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1060677399
Short name T382
Test name
Test status
Simulation time 57715189 ps
CPU time 2.35 seconds
Started Jun 04 01:59:33 PM PDT 24
Finished Jun 04 01:59:36 PM PDT 24
Peak memory 214232 kb
Host smart-9805916f-e346-4cb3-88b2-df17971eed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060677399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1060677399
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1019470177
Short name T112
Test name
Test status
Simulation time 1180227016 ps
CPU time 12.35 seconds
Started Jun 04 01:59:31 PM PDT 24
Finished Jun 04 01:59:45 PM PDT 24
Peak memory 221876 kb
Host smart-f5ea0bdc-a489-4b41-a355-bc2d9687a5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019470177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1019470177
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.721242547
Short name T739
Test name
Test status
Simulation time 308651746 ps
CPU time 5.27 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:38 PM PDT 24
Peak memory 222516 kb
Host smart-11d964ae-4869-4471-91e2-3e1658e17e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721242547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.721242547
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1565439340
Short name T494
Test name
Test status
Simulation time 176000590 ps
CPU time 2.85 seconds
Started Jun 04 01:59:34 PM PDT 24
Finished Jun 04 01:59:38 PM PDT 24
Peak memory 222428 kb
Host smart-04db9065-a298-4091-bea6-960457e39560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565439340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1565439340
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.4146968486
Short name T591
Test name
Test status
Simulation time 1255779023 ps
CPU time 5.17 seconds
Started Jun 04 01:59:31 PM PDT 24
Finished Jun 04 01:59:37 PM PDT 24
Peak memory 209076 kb
Host smart-59e00e46-baf8-4086-a90b-452e1db501f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146968486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.4146968486
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2776493312
Short name T493
Test name
Test status
Simulation time 83131796 ps
CPU time 2.26 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:35 PM PDT 24
Peak memory 208300 kb
Host smart-21e8212a-dcf3-4b7b-9f89-adf7f380a1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776493312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2776493312
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1218208365
Short name T518
Test name
Test status
Simulation time 324791529 ps
CPU time 3.03 seconds
Started Jun 04 01:59:35 PM PDT 24
Finished Jun 04 01:59:39 PM PDT 24
Peak memory 206940 kb
Host smart-f0145f3c-a252-436d-93e3-29adf9e41468
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218208365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1218208365
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.4006932452
Short name T370
Test name
Test status
Simulation time 35527445 ps
CPU time 2.39 seconds
Started Jun 04 01:59:34 PM PDT 24
Finished Jun 04 01:59:37 PM PDT 24
Peak memory 208720 kb
Host smart-2001ebae-3618-4f6d-bcdb-ff6bffd87c38
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006932452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.4006932452
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1388557483
Short name T251
Test name
Test status
Simulation time 817006280 ps
CPU time 17.96 seconds
Started Jun 04 01:59:33 PM PDT 24
Finished Jun 04 01:59:52 PM PDT 24
Peak memory 208184 kb
Host smart-11e39314-10f1-4780-9070-1da351d05455
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388557483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1388557483
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1115186933
Short name T164
Test name
Test status
Simulation time 521729609 ps
CPU time 4.4 seconds
Started Jun 04 01:59:31 PM PDT 24
Finished Jun 04 01:59:36 PM PDT 24
Peak memory 218204 kb
Host smart-a073f679-4674-4a11-8722-1dee88893eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115186933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1115186933
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.843756954
Short name T527
Test name
Test status
Simulation time 51815211 ps
CPU time 2.55 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:36 PM PDT 24
Peak memory 206776 kb
Host smart-a658aed5-b4fe-4744-8240-4fc5416d422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843756954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.843756954
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1292487931
Short name T207
Test name
Test status
Simulation time 1417723383 ps
CPU time 32.3 seconds
Started Jun 04 01:59:37 PM PDT 24
Finished Jun 04 02:00:10 PM PDT 24
Peak memory 216140 kb
Host smart-ea3a1834-8b98-4529-8e0c-868f058758f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292487931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1292487931
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2019931684
Short name T685
Test name
Test status
Simulation time 255565643 ps
CPU time 6.69 seconds
Started Jun 04 01:59:36 PM PDT 24
Finished Jun 04 01:59:44 PM PDT 24
Peak memory 222656 kb
Host smart-91fa92ba-0327-4cd5-98a5-68d910f51e04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019931684 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2019931684
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2540919695
Short name T274
Test name
Test status
Simulation time 459028763 ps
CPU time 4.94 seconds
Started Jun 04 01:59:34 PM PDT 24
Finished Jun 04 01:59:40 PM PDT 24
Peak memory 214416 kb
Host smart-1ffc4864-dba1-441a-9933-f04a1032bcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540919695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2540919695
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3731435694
Short name T655
Test name
Test status
Simulation time 272494223 ps
CPU time 2.13 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:35 PM PDT 24
Peak memory 210372 kb
Host smart-4c0747c1-bc12-41e4-93a2-d912ff0b93c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731435694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3731435694
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3354736609
Short name T789
Test name
Test status
Simulation time 11211751 ps
CPU time 0.72 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 01:59:44 PM PDT 24
Peak memory 205952 kb
Host smart-9c94d49e-6eab-4b6d-9cbe-4e8e1782a9f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354736609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3354736609
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2262319453
Short name T425
Test name
Test status
Simulation time 71317450 ps
CPU time 4.66 seconds
Started Jun 04 01:59:34 PM PDT 24
Finished Jun 04 01:59:40 PM PDT 24
Peak memory 215268 kb
Host smart-80caf466-501b-48c2-8813-dbceed86d017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262319453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2262319453
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2368933309
Short name T231
Test name
Test status
Simulation time 271171065 ps
CPU time 2.51 seconds
Started Jun 04 01:59:31 PM PDT 24
Finished Jun 04 01:59:34 PM PDT 24
Peak memory 208912 kb
Host smart-79b01a67-4c01-42d2-88ee-1cf87c89c879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368933309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2368933309
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.416680762
Short name T869
Test name
Test status
Simulation time 93602169 ps
CPU time 2.01 seconds
Started Jun 04 01:59:36 PM PDT 24
Finished Jun 04 01:59:39 PM PDT 24
Peak memory 207320 kb
Host smart-05469dd6-70c9-42f4-b43e-03b858f4dda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416680762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.416680762
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2652593489
Short name T681
Test name
Test status
Simulation time 116055657 ps
CPU time 3.05 seconds
Started Jun 04 01:59:31 PM PDT 24
Finished Jun 04 01:59:35 PM PDT 24
Peak memory 208640 kb
Host smart-a2accd82-afe2-4240-b169-1456e49794cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652593489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2652593489
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.4180338521
Short name T669
Test name
Test status
Simulation time 95351381 ps
CPU time 4.08 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:37 PM PDT 24
Peak memory 209848 kb
Host smart-407c42a6-f6fe-4f34-8e3e-0f2a3f825ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180338521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.4180338521
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.4131329922
Short name T670
Test name
Test status
Simulation time 223691503 ps
CPU time 6.57 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:39 PM PDT 24
Peak memory 214328 kb
Host smart-84d53322-ba0f-404f-852a-30f2bbb99c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131329922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.4131329922
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1334747288
Short name T595
Test name
Test status
Simulation time 3785894750 ps
CPU time 28.44 seconds
Started Jun 04 01:59:31 PM PDT 24
Finished Jun 04 02:00:00 PM PDT 24
Peak memory 208428 kb
Host smart-45cae4bc-712a-42db-9a98-1209cb4d12ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334747288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1334747288
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1277015029
Short name T571
Test name
Test status
Simulation time 7660132912 ps
CPU time 44.94 seconds
Started Jun 04 01:59:35 PM PDT 24
Finished Jun 04 02:00:21 PM PDT 24
Peak memory 208628 kb
Host smart-68703c4f-5969-4bf1-90e9-b0f19c1cca69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277015029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1277015029
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3111919004
Short name T770
Test name
Test status
Simulation time 2803654073 ps
CPU time 37.28 seconds
Started Jun 04 01:59:36 PM PDT 24
Finished Jun 04 02:00:15 PM PDT 24
Peak memory 208116 kb
Host smart-8c37ba63-eff6-4bc3-96d5-7c5b9726ae88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111919004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3111919004
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1568180223
Short name T499
Test name
Test status
Simulation time 476204222 ps
CPU time 11.39 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:45 PM PDT 24
Peak memory 208036 kb
Host smart-79af5052-b367-47d1-b5c7-e80b951fc867
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568180223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1568180223
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1110103788
Short name T883
Test name
Test status
Simulation time 40909178 ps
CPU time 2.34 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:35 PM PDT 24
Peak memory 218584 kb
Host smart-4c92fa06-8041-44bb-ac44-80b59d045052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110103788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1110103788
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1851265498
Short name T533
Test name
Test status
Simulation time 168950099 ps
CPU time 3.87 seconds
Started Jun 04 01:59:32 PM PDT 24
Finished Jun 04 01:59:37 PM PDT 24
Peak memory 208112 kb
Host smart-134e7ab6-242d-4da0-9dbe-6d3825b654e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851265498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1851265498
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1620471970
Short name T149
Test name
Test status
Simulation time 3790511593 ps
CPU time 45.59 seconds
Started Jun 04 01:59:31 PM PDT 24
Finished Jun 04 02:00:18 PM PDT 24
Peak memory 208392 kb
Host smart-e4fc3795-97d7-434d-b7f2-4b41690b2a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620471970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1620471970
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.4293935768
Short name T139
Test name
Test status
Simulation time 1262960237 ps
CPU time 25.37 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 02:00:08 PM PDT 24
Peak memory 222656 kb
Host smart-6a467cbb-a30d-496c-93e6-bfc15852d122
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293935768 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.4293935768
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2405509459
Short name T575
Test name
Test status
Simulation time 1453356217 ps
CPU time 5.65 seconds
Started Jun 04 01:59:35 PM PDT 24
Finished Jun 04 01:59:41 PM PDT 24
Peak memory 214476 kb
Host smart-f0078b6f-6b03-4ada-bc0b-27b4722fedf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405509459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2405509459
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.357382274
Short name T174
Test name
Test status
Simulation time 102960004 ps
CPU time 2.57 seconds
Started Jun 04 01:59:34 PM PDT 24
Finished Jun 04 01:59:38 PM PDT 24
Peak memory 210220 kb
Host smart-1607f131-03e9-490e-9243-af5eb26a6b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357382274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.357382274
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3036175879
Short name T793
Test name
Test status
Simulation time 31973485 ps
CPU time 0.72 seconds
Started Jun 04 01:59:44 PM PDT 24
Finished Jun 04 01:59:46 PM PDT 24
Peak memory 205940 kb
Host smart-34917508-b346-481b-aec6-c0062ea4d931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036175879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3036175879
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3848389310
Short name T740
Test name
Test status
Simulation time 72454972 ps
CPU time 2.78 seconds
Started Jun 04 01:59:43 PM PDT 24
Finished Jun 04 01:59:48 PM PDT 24
Peak memory 215392 kb
Host smart-6ff70d7a-951b-441a-a669-ac2aab4866d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3848389310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3848389310
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2606507345
Short name T696
Test name
Test status
Simulation time 42656988 ps
CPU time 2.22 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 01:59:46 PM PDT 24
Peak memory 207692 kb
Host smart-c54faa94-50b3-4152-ba9c-cc4ff451e7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606507345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2606507345
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1617001323
Short name T662
Test name
Test status
Simulation time 207826447 ps
CPU time 6.67 seconds
Started Jun 04 01:59:47 PM PDT 24
Finished Jun 04 01:59:54 PM PDT 24
Peak memory 222588 kb
Host smart-aec02ad2-4504-477b-887f-5b654fcd66d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617001323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1617001323
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.667966945
Short name T17
Test name
Test status
Simulation time 108566752 ps
CPU time 2.27 seconds
Started Jun 04 01:59:47 PM PDT 24
Finished Jun 04 01:59:50 PM PDT 24
Peak memory 222564 kb
Host smart-cd063a90-d3cf-4cd6-a0b7-0c56a6f230db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667966945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.667966945
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.418668785
Short name T70
Test name
Test status
Simulation time 98773034 ps
CPU time 4.12 seconds
Started Jun 04 01:59:40 PM PDT 24
Finished Jun 04 01:59:45 PM PDT 24
Peak memory 219736 kb
Host smart-4f737339-c078-4cc8-b1b6-fe7e0a4ab68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418668785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.418668785
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.771236547
Short name T292
Test name
Test status
Simulation time 68816437 ps
CPU time 2.63 seconds
Started Jun 04 01:59:43 PM PDT 24
Finished Jun 04 01:59:47 PM PDT 24
Peak memory 218476 kb
Host smart-094f1c93-9292-41d4-a332-3899cbd4ff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771236547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.771236547
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.157684622
Short name T871
Test name
Test status
Simulation time 178306272 ps
CPU time 3.31 seconds
Started Jun 04 01:59:41 PM PDT 24
Finished Jun 04 01:59:44 PM PDT 24
Peak memory 207292 kb
Host smart-dbf19339-6327-4b36-9603-3b905cc389f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157684622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.157684622
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1257414818
Short name T838
Test name
Test status
Simulation time 1224678473 ps
CPU time 8.08 seconds
Started Jun 04 01:59:43 PM PDT 24
Finished Jun 04 01:59:52 PM PDT 24
Peak memory 207936 kb
Host smart-72947107-6d5d-4c42-bce2-56f28d0bf5eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257414818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1257414818
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1736499945
Short name T548
Test name
Test status
Simulation time 3234779918 ps
CPU time 54.66 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 02:00:38 PM PDT 24
Peak memory 208384 kb
Host smart-8e2d592d-6f42-419c-a5ac-98435f95582d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736499945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1736499945
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3609024412
Short name T779
Test name
Test status
Simulation time 435385980 ps
CPU time 3.99 seconds
Started Jun 04 01:59:44 PM PDT 24
Finished Jun 04 01:59:49 PM PDT 24
Peak memory 208836 kb
Host smart-681c732e-dfb7-4355-a193-9f6699dc9d0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609024412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3609024412
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.4144080802
Short name T647
Test name
Test status
Simulation time 237985658 ps
CPU time 3.26 seconds
Started Jun 04 01:59:40 PM PDT 24
Finished Jun 04 01:59:44 PM PDT 24
Peak memory 208152 kb
Host smart-5ee95498-ea5d-415f-8bbc-a5c792f01505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144080802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4144080802
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1518557668
Short name T445
Test name
Test status
Simulation time 74733021 ps
CPU time 3.08 seconds
Started Jun 04 01:59:40 PM PDT 24
Finished Jun 04 01:59:44 PM PDT 24
Peak memory 206116 kb
Host smart-c07a3b36-c2f5-4dee-b1c4-4aab9e605a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518557668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1518557668
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4105360598
Short name T666
Test name
Test status
Simulation time 749752678 ps
CPU time 10.64 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 01:59:53 PM PDT 24
Peak memory 216844 kb
Host smart-77b681b3-46c0-4561-9486-ccf3bff62bc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105360598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4105360598
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1261803612
Short name T421
Test name
Test status
Simulation time 94529807 ps
CPU time 3.3 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 01:59:47 PM PDT 24
Peak memory 218428 kb
Host smart-38bf2388-556b-4902-b018-7d48c9355238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261803612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1261803612
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.205795268
Short name T703
Test name
Test status
Simulation time 94588532 ps
CPU time 2.48 seconds
Started Jun 04 01:59:44 PM PDT 24
Finished Jun 04 01:59:48 PM PDT 24
Peak memory 210716 kb
Host smart-428133a0-55ca-4e7c-914d-c21412225084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205795268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.205795268
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3934037905
Short name T528
Test name
Test status
Simulation time 50478152 ps
CPU time 0.81 seconds
Started Jun 04 01:59:45 PM PDT 24
Finished Jun 04 01:59:47 PM PDT 24
Peak memory 205944 kb
Host smart-ca7a9397-3dfb-4283-9b81-f0282039324b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934037905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3934037905
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4229592018
Short name T765
Test name
Test status
Simulation time 85106798 ps
CPU time 3.53 seconds
Started Jun 04 01:59:46 PM PDT 24
Finished Jun 04 01:59:51 PM PDT 24
Peak memory 209236 kb
Host smart-0233bf24-503c-474f-b8ea-95bdcc99ec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229592018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4229592018
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2271178525
Short name T757
Test name
Test status
Simulation time 319719858 ps
CPU time 3.56 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 01:59:47 PM PDT 24
Peak memory 214456 kb
Host smart-44091ff6-4700-4b3c-914e-85525de1a675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271178525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2271178525
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2494272791
Short name T108
Test name
Test status
Simulation time 173060318 ps
CPU time 4.21 seconds
Started Jun 04 01:59:43 PM PDT 24
Finished Jun 04 01:59:49 PM PDT 24
Peak memory 222496 kb
Host smart-edb33a4d-2747-44f1-b90f-58bddc92ea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494272791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2494272791
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.43747626
Short name T27
Test name
Test status
Simulation time 151625776 ps
CPU time 4.88 seconds
Started Jun 04 01:59:40 PM PDT 24
Finished Jun 04 01:59:46 PM PDT 24
Peak memory 221076 kb
Host smart-cb5ca1f2-c6d1-4be7-82ef-444e4b873425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43747626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.43747626
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.11163158
Short name T59
Test name
Test status
Simulation time 59437547 ps
CPU time 3.01 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 01:59:46 PM PDT 24
Peak memory 214420 kb
Host smart-5a5f160e-213f-4141-8a17-e9c3f5c61151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11163158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.11163158
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2272006919
Short name T374
Test name
Test status
Simulation time 385147510 ps
CPU time 5.21 seconds
Started Jun 04 01:59:43 PM PDT 24
Finished Jun 04 01:59:50 PM PDT 24
Peak memory 214324 kb
Host smart-cfb4f866-0817-483c-8326-b703000187e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272006919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2272006919
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3554586684
Short name T673
Test name
Test status
Simulation time 69428836 ps
CPU time 2.35 seconds
Started Jun 04 01:59:43 PM PDT 24
Finished Jun 04 01:59:47 PM PDT 24
Peak memory 207148 kb
Host smart-0edf6e13-acfd-4d2c-b2ca-7b98ca885fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554586684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3554586684
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.177516208
Short name T618
Test name
Test status
Simulation time 223124989 ps
CPU time 6 seconds
Started Jun 04 01:59:44 PM PDT 24
Finished Jun 04 01:59:51 PM PDT 24
Peak memory 208544 kb
Host smart-8e0c58ff-5dbb-49b3-aed2-dfa6522b7f24
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177516208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.177516208
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2636729358
Short name T766
Test name
Test status
Simulation time 77456863 ps
CPU time 2.88 seconds
Started Jun 04 01:59:40 PM PDT 24
Finished Jun 04 01:59:44 PM PDT 24
Peak memory 208852 kb
Host smart-530161da-2024-499f-919d-62303ea4e9c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636729358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2636729358
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1595090953
Short name T689
Test name
Test status
Simulation time 441521334 ps
CPU time 13.95 seconds
Started Jun 04 01:59:44 PM PDT 24
Finished Jun 04 02:00:00 PM PDT 24
Peak memory 208024 kb
Host smart-30445086-8133-45a2-8f0a-ebb36f36de6e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595090953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1595090953
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2898268069
Short name T603
Test name
Test status
Simulation time 16170654 ps
CPU time 1.52 seconds
Started Jun 04 01:59:44 PM PDT 24
Finished Jun 04 01:59:47 PM PDT 24
Peak memory 206924 kb
Host smart-3e36fee3-c4b5-4b6c-9135-f3b6765ea934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898268069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2898268069
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1330357879
Short name T650
Test name
Test status
Simulation time 158807016 ps
CPU time 3.31 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 01:59:47 PM PDT 24
Peak memory 208460 kb
Host smart-4ca1be12-89d4-4ab3-84ec-f30566a1d4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330357879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1330357879
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1627888328
Short name T742
Test name
Test status
Simulation time 95602820 ps
CPU time 0.75 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:52 PM PDT 24
Peak memory 205904 kb
Host smart-1a44cef5-3248-493d-95fc-8dfd3f2f1ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627888328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1627888328
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1956441407
Short name T606
Test name
Test status
Simulation time 74538098 ps
CPU time 3.7 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:54 PM PDT 24
Peak memory 214608 kb
Host smart-849ae8a7-aa5e-441a-a818-08023bb26943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956441407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1956441407
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3747760155
Short name T852
Test name
Test status
Simulation time 88341300 ps
CPU time 3.2 seconds
Started Jun 04 01:59:48 PM PDT 24
Finished Jun 04 01:59:52 PM PDT 24
Peak memory 208620 kb
Host smart-b8e87880-b44e-45a2-b1d8-4127ac8f5c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747760155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3747760155
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3665983681
Short name T218
Test name
Test status
Simulation time 136159532 ps
CPU time 3.8 seconds
Started Jun 04 01:59:51 PM PDT 24
Finished Jun 04 01:59:57 PM PDT 24
Peak memory 214340 kb
Host smart-fd161327-1697-4b99-a95b-ed0e3bcaff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665983681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3665983681
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1648654630
Short name T774
Test name
Test status
Simulation time 535541989 ps
CPU time 6.12 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:56 PM PDT 24
Peak memory 218444 kb
Host smart-2be70f0f-69bc-4156-b839-effd91a99473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648654630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1648654630
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3623640464
Short name T332
Test name
Test status
Simulation time 25839635 ps
CPU time 2.04 seconds
Started Jun 04 01:59:43 PM PDT 24
Finished Jun 04 01:59:46 PM PDT 24
Peak memory 208652 kb
Host smart-ad9cea6b-65ff-4f2d-9227-6c431368690a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623640464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3623640464
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2377705134
Short name T557
Test name
Test status
Simulation time 497403475 ps
CPU time 8.66 seconds
Started Jun 04 01:59:42 PM PDT 24
Finished Jun 04 01:59:51 PM PDT 24
Peak memory 206796 kb
Host smart-e04fe7f4-a62d-4cab-bae7-23ad83f19dfa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377705134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2377705134
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1480891662
Short name T715
Test name
Test status
Simulation time 44679210 ps
CPU time 2.59 seconds
Started Jun 04 01:59:45 PM PDT 24
Finished Jun 04 01:59:49 PM PDT 24
Peak memory 207436 kb
Host smart-4e249fb4-d40f-49c3-9ecb-1573b3fbea08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480891662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1480891662
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3295325087
Short name T1
Test name
Test status
Simulation time 308164087 ps
CPU time 2.95 seconds
Started Jun 04 01:59:50 PM PDT 24
Finished Jun 04 01:59:55 PM PDT 24
Peak memory 208432 kb
Host smart-4b3ec441-3f10-4c1e-b93d-6ad7f42e290b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295325087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3295325087
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3548604432
Short name T747
Test name
Test status
Simulation time 72173733 ps
CPU time 1.81 seconds
Started Jun 04 01:59:48 PM PDT 24
Finished Jun 04 01:59:50 PM PDT 24
Peak memory 215492 kb
Host smart-bd01e35e-3971-4c75-8b1e-0fc591f97f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548604432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3548604432
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3149013155
Short name T121
Test name
Test status
Simulation time 278831628 ps
CPU time 1.91 seconds
Started Jun 04 01:59:43 PM PDT 24
Finished Jun 04 01:59:47 PM PDT 24
Peak memory 208576 kb
Host smart-48098a1c-9685-4df9-b753-38b4f96eb1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149013155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3149013155
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.4154951228
Short name T675
Test name
Test status
Simulation time 262522545 ps
CPU time 5.86 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:56 PM PDT 24
Peak memory 208152 kb
Host smart-76f1f34c-2b92-48db-a99e-da0e6fc547f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154951228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.4154951228
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2069768186
Short name T892
Test name
Test status
Simulation time 214921258 ps
CPU time 2.47 seconds
Started Jun 04 01:59:50 PM PDT 24
Finished Jun 04 01:59:55 PM PDT 24
Peak memory 210116 kb
Host smart-10821a33-a751-4528-9b9a-4633001b62a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069768186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2069768186
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.825489088
Short name T433
Test name
Test status
Simulation time 18803854 ps
CPU time 0.75 seconds
Started Jun 04 01:59:57 PM PDT 24
Finished Jun 04 01:59:59 PM PDT 24
Peak memory 205904 kb
Host smart-4701f049-f512-43f2-97b0-6255e4aaf472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825489088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.825489088
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.338424926
Short name T153
Test name
Test status
Simulation time 185269184 ps
CPU time 5.55 seconds
Started Jun 04 01:59:56 PM PDT 24
Finished Jun 04 02:00:03 PM PDT 24
Peak memory 214336 kb
Host smart-ab1c2cf0-3aa8-4835-8749-ac9c46ee98dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338424926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.338424926
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2377903220
Short name T23
Test name
Test status
Simulation time 48006380 ps
CPU time 3.04 seconds
Started Jun 04 01:59:48 PM PDT 24
Finished Jun 04 01:59:52 PM PDT 24
Peak memory 217976 kb
Host smart-d0fbeb7e-658d-4473-bc14-5cc6fa4acc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377903220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2377903220
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2467829529
Short name T660
Test name
Test status
Simulation time 329802853 ps
CPU time 2.31 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:52 PM PDT 24
Peak memory 208768 kb
Host smart-95ab1e88-0874-467c-943c-dff557c769c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467829529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2467829529
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1488780930
Short name T54
Test name
Test status
Simulation time 49459914 ps
CPU time 2.84 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:53 PM PDT 24
Peak memory 214276 kb
Host smart-c6d17ebc-d4e4-46bf-9d2e-bee405415b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488780930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1488780930
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1426572041
Short name T58
Test name
Test status
Simulation time 108267057 ps
CPU time 2.98 seconds
Started Jun 04 01:59:55 PM PDT 24
Finished Jun 04 01:59:59 PM PDT 24
Peak memory 209552 kb
Host smart-b8f23020-daf8-421a-8090-6ee743999fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426572041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1426572041
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3492242379
Short name T419
Test name
Test status
Simulation time 92032319 ps
CPU time 4.97 seconds
Started Jun 04 01:59:55 PM PDT 24
Finished Jun 04 02:00:01 PM PDT 24
Peak memory 207268 kb
Host smart-2d3679cd-b6a9-420a-9450-43c636ac1898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492242379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3492242379
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.432018747
Short name T642
Test name
Test status
Simulation time 42124001 ps
CPU time 2.19 seconds
Started Jun 04 01:59:48 PM PDT 24
Finished Jun 04 01:59:51 PM PDT 24
Peak memory 206856 kb
Host smart-eaea5dfa-edf8-4c73-b4de-18fbda039813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432018747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.432018747
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2628053752
Short name T767
Test name
Test status
Simulation time 32573918 ps
CPU time 2 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:53 PM PDT 24
Peak memory 208732 kb
Host smart-b3915aec-4a8c-4d44-b122-62cf503ddd94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628053752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2628053752
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2429898715
Short name T649
Test name
Test status
Simulation time 3655317197 ps
CPU time 25.32 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 02:00:16 PM PDT 24
Peak memory 208640 kb
Host smart-605b2b2f-c38c-470b-9efa-19108430dd25
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429898715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2429898715
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3879077080
Short name T489
Test name
Test status
Simulation time 654695878 ps
CPU time 7.77 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:58 PM PDT 24
Peak memory 206972 kb
Host smart-8057805e-89e3-4251-b72d-6cf9b744c556
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879077080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3879077080
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3640536855
Short name T578
Test name
Test status
Simulation time 831892584 ps
CPU time 5.25 seconds
Started Jun 04 01:59:50 PM PDT 24
Finished Jun 04 01:59:57 PM PDT 24
Peak memory 208824 kb
Host smart-0dfec221-1bdc-476e-bbbb-f29a7d7e8059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640536855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3640536855
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2685382131
Short name T497
Test name
Test status
Simulation time 252847751 ps
CPU time 2.97 seconds
Started Jun 04 01:59:51 PM PDT 24
Finished Jun 04 01:59:56 PM PDT 24
Peak memory 206824 kb
Host smart-62bdb8a4-be1c-4384-9f6d-0e87e87333e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685382131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2685382131
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.79002680
Short name T502
Test name
Test status
Simulation time 211759839 ps
CPU time 8.63 seconds
Started Jun 04 01:59:50 PM PDT 24
Finished Jun 04 02:00:00 PM PDT 24
Peak memory 220776 kb
Host smart-c6c1edd8-6454-430d-80be-180ec1f09afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79002680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.79002680
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3574136017
Short name T300
Test name
Test status
Simulation time 108219437 ps
CPU time 4.9 seconds
Started Jun 04 01:59:50 PM PDT 24
Finished Jun 04 01:59:57 PM PDT 24
Peak memory 208948 kb
Host smart-bdc882fd-4fd4-4589-ac83-d29aa1b6f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574136017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3574136017
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.98961456
Short name T407
Test name
Test status
Simulation time 271871017 ps
CPU time 2.7 seconds
Started Jun 04 01:59:49 PM PDT 24
Finished Jun 04 01:59:53 PM PDT 24
Peak memory 210284 kb
Host smart-39f41720-7cc3-4b88-94c4-64c8d866d3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98961456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.98961456
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.299412915
Short name T723
Test name
Test status
Simulation time 47822280 ps
CPU time 0.89 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:01 PM PDT 24
Peak memory 205968 kb
Host smart-17ed3e29-7bb2-4c9f-9a52-8d0d1492556b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299412915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.299412915
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2977640298
Short name T394
Test name
Test status
Simulation time 65441162 ps
CPU time 4.49 seconds
Started Jun 04 02:00:00 PM PDT 24
Finished Jun 04 02:00:05 PM PDT 24
Peak memory 214980 kb
Host smart-ef97d47a-c37d-453e-84fd-94330a0db99e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977640298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2977640298
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3759763177
Short name T233
Test name
Test status
Simulation time 330216801 ps
CPU time 3.51 seconds
Started Jun 04 01:59:57 PM PDT 24
Finished Jun 04 02:00:02 PM PDT 24
Peak memory 209596 kb
Host smart-0e28580e-2cbd-4725-9109-f0d13364a9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759763177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3759763177
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3962814239
Short name T82
Test name
Test status
Simulation time 103944985 ps
CPU time 1.97 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:02 PM PDT 24
Peak memory 207700 kb
Host smart-79372c46-9ec7-4bac-9110-5b0f5163df45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962814239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3962814239
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2114090288
Short name T306
Test name
Test status
Simulation time 139153370 ps
CPU time 1.79 seconds
Started Jun 04 01:59:58 PM PDT 24
Finished Jun 04 02:00:01 PM PDT 24
Peak memory 214292 kb
Host smart-905c9e4e-ccb5-49e4-9359-5387cdd674df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114090288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2114090288
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2293569244
Short name T820
Test name
Test status
Simulation time 69963477 ps
CPU time 1.98 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:03 PM PDT 24
Peak memory 213724 kb
Host smart-1b131c3b-478e-45b5-a8c4-15b7e6a3cfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293569244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2293569244
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_random.3394663564
Short name T888
Test name
Test status
Simulation time 1269946346 ps
CPU time 21.02 seconds
Started Jun 04 01:59:56 PM PDT 24
Finished Jun 04 02:00:18 PM PDT 24
Peak memory 214308 kb
Host smart-3d56980f-1cc1-443d-bf98-48ffc7d5ca7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394663564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3394663564
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3473962539
Short name T628
Test name
Test status
Simulation time 60383160 ps
CPU time 3.1 seconds
Started Jun 04 01:59:57 PM PDT 24
Finished Jun 04 02:00:02 PM PDT 24
Peak memory 206884 kb
Host smart-9f992716-a036-4ad8-a947-a9c0c00f64fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473962539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3473962539
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1906223241
Short name T318
Test name
Test status
Simulation time 153862474 ps
CPU time 3.7 seconds
Started Jun 04 02:00:00 PM PDT 24
Finished Jun 04 02:00:05 PM PDT 24
Peak memory 208348 kb
Host smart-d66381b5-5936-45c3-a7d8-05e6a2aa4918
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906223241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1906223241
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3126238827
Short name T697
Test name
Test status
Simulation time 384061774 ps
CPU time 3.35 seconds
Started Jun 04 01:59:57 PM PDT 24
Finished Jun 04 02:00:01 PM PDT 24
Peak memory 208632 kb
Host smart-bbfd25b5-e200-4768-8b75-002ac844f283
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126238827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3126238827
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1664673185
Short name T885
Test name
Test status
Simulation time 53217476 ps
CPU time 2.53 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:03 PM PDT 24
Peak memory 207000 kb
Host smart-61f525cf-77a0-44a3-adca-affafbf21617
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664673185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1664673185
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3910913167
Short name T826
Test name
Test status
Simulation time 195442472 ps
CPU time 1.9 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:02 PM PDT 24
Peak memory 207248 kb
Host smart-d5dead39-765b-4543-a400-02450235e158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910913167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3910913167
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.853144932
Short name T735
Test name
Test status
Simulation time 382344899 ps
CPU time 3.83 seconds
Started Jun 04 02:00:00 PM PDT 24
Finished Jun 04 02:00:05 PM PDT 24
Peak memory 208392 kb
Host smart-06b65f7f-1849-464f-b895-9f2cdef39d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853144932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.853144932
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3677740839
Short name T857
Test name
Test status
Simulation time 785484985 ps
CPU time 12.49 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:12 PM PDT 24
Peak memory 207820 kb
Host smart-e9d0df00-193f-435f-9b57-4be282538a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677740839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3677740839
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3187354774
Short name T216
Test name
Test status
Simulation time 265015118 ps
CPU time 3.03 seconds
Started Jun 04 02:00:01 PM PDT 24
Finished Jun 04 02:00:05 PM PDT 24
Peak memory 210472 kb
Host smart-5f370fa7-a100-40c4-b2ef-deef71703282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187354774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3187354774
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2363238880
Short name T641
Test name
Test status
Simulation time 12098297 ps
CPU time 0.84 seconds
Started Jun 04 01:59:58 PM PDT 24
Finished Jun 04 02:00:00 PM PDT 24
Peak memory 205940 kb
Host smart-77c8631c-5000-4240-85fc-d227e717a019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363238880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2363238880
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3466756930
Short name T396
Test name
Test status
Simulation time 3110708723 ps
CPU time 55.6 seconds
Started Jun 04 01:59:57 PM PDT 24
Finished Jun 04 02:00:54 PM PDT 24
Peak memory 214764 kb
Host smart-34422738-fd46-48a5-9036-83ed480249a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466756930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3466756930
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2813199007
Short name T607
Test name
Test status
Simulation time 101030410 ps
CPU time 2.72 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:03 PM PDT 24
Peak memory 208200 kb
Host smart-5f9ffe7f-3d7e-4293-8ce9-46bbacff7498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813199007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2813199007
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3418072310
Short name T384
Test name
Test status
Simulation time 119489653 ps
CPU time 3.71 seconds
Started Jun 04 01:59:57 PM PDT 24
Finished Jun 04 02:00:02 PM PDT 24
Peak memory 214288 kb
Host smart-08b28e21-c200-4641-b3e8-88a39d489434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418072310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3418072310
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3760796726
Short name T7
Test name
Test status
Simulation time 198979754 ps
CPU time 3.62 seconds
Started Jun 04 02:00:02 PM PDT 24
Finished Jun 04 02:00:07 PM PDT 24
Peak memory 209552 kb
Host smart-92fdd407-79c6-4796-9786-f8a1168561a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760796726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3760796726
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3136729830
Short name T281
Test name
Test status
Simulation time 54998932 ps
CPU time 3.55 seconds
Started Jun 04 01:59:57 PM PDT 24
Finished Jun 04 02:00:02 PM PDT 24
Peak memory 207128 kb
Host smart-4d7ffde5-2ab9-4d93-9746-f39d1e779e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136729830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3136729830
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2339545318
Short name T554
Test name
Test status
Simulation time 100884719 ps
CPU time 3.48 seconds
Started Jun 04 01:59:56 PM PDT 24
Finished Jun 04 02:00:01 PM PDT 24
Peak memory 208432 kb
Host smart-828a4ef9-cc91-450c-b343-1a8e2f715eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339545318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2339545318
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2276460770
Short name T878
Test name
Test status
Simulation time 39031027 ps
CPU time 2.43 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:03 PM PDT 24
Peak memory 208028 kb
Host smart-22fb3619-e8dd-4b97-baf2-71ae4121b945
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276460770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2276460770
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1927370380
Short name T576
Test name
Test status
Simulation time 223084545 ps
CPU time 6.46 seconds
Started Jun 04 02:00:02 PM PDT 24
Finished Jun 04 02:00:10 PM PDT 24
Peak memory 208716 kb
Host smart-7b413ffc-bd84-4d64-98eb-9ee55b1018a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927370380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1927370380
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.603182157
Short name T198
Test name
Test status
Simulation time 529415183 ps
CPU time 8.66 seconds
Started Jun 04 01:59:57 PM PDT 24
Finished Jun 04 02:00:07 PM PDT 24
Peak memory 208140 kb
Host smart-c02db883-fa08-4fdc-9188-1463f950412a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603182157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.603182157
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4053624845
Short name T795
Test name
Test status
Simulation time 38668694 ps
CPU time 1.62 seconds
Started Jun 04 01:59:57 PM PDT 24
Finished Jun 04 02:00:00 PM PDT 24
Peak memory 207128 kb
Host smart-088c8311-98cf-4a03-82a3-eb0c3b498d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053624845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4053624845
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3217976197
Short name T676
Test name
Test status
Simulation time 864055298 ps
CPU time 3.65 seconds
Started Jun 04 02:00:01 PM PDT 24
Finished Jun 04 02:00:06 PM PDT 24
Peak memory 208900 kb
Host smart-6b2aa129-df2c-4b8d-80f0-7ca133cf6958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217976197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3217976197
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.4109277990
Short name T230
Test name
Test status
Simulation time 3887489780 ps
CPU time 42.28 seconds
Started Jun 04 01:59:57 PM PDT 24
Finished Jun 04 02:00:40 PM PDT 24
Peak memory 216732 kb
Host smart-507b9c5a-0494-4c65-814d-baaf3150cac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109277990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.4109277990
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2762549044
Short name T124
Test name
Test status
Simulation time 187091843 ps
CPU time 7.38 seconds
Started Jun 04 01:59:58 PM PDT 24
Finished Jun 04 02:00:07 PM PDT 24
Peak memory 222580 kb
Host smart-c6c9ec03-51f3-4d82-ad66-69336e705b9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762549044 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2762549044
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2766288273
Short name T342
Test name
Test status
Simulation time 285165330 ps
CPU time 4.26 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:05 PM PDT 24
Peak memory 207696 kb
Host smart-17188cb9-0b2a-4c71-8d47-967c3ca28c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766288273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2766288273
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2050591199
Short name T125
Test name
Test status
Simulation time 326920431 ps
CPU time 1.74 seconds
Started Jun 04 02:00:02 PM PDT 24
Finished Jun 04 02:00:05 PM PDT 24
Peak memory 210116 kb
Host smart-1544452f-2764-43f3-a1b1-c8ec2e4bee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050591199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2050591199
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2197842927
Short name T863
Test name
Test status
Simulation time 27056899 ps
CPU time 0.79 seconds
Started Jun 04 02:00:05 PM PDT 24
Finished Jun 04 02:00:07 PM PDT 24
Peak memory 205916 kb
Host smart-35d4607f-40e5-40d8-b5ec-446839174c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197842927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2197842927
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1658721332
Short name T431
Test name
Test status
Simulation time 139812754 ps
CPU time 3.23 seconds
Started Jun 04 02:00:07 PM PDT 24
Finished Jun 04 02:00:12 PM PDT 24
Peak memory 215296 kb
Host smart-edf133bc-5761-4457-9c75-0a90848ba2b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1658721332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1658721332
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3279022750
Short name T243
Test name
Test status
Simulation time 91878886 ps
CPU time 3.84 seconds
Started Jun 04 02:00:08 PM PDT 24
Finished Jun 04 02:00:14 PM PDT 24
Peak memory 209824 kb
Host smart-89a4af71-a758-44d6-98d8-219107342361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279022750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3279022750
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1608643663
Short name T585
Test name
Test status
Simulation time 841878659 ps
CPU time 20.17 seconds
Started Jun 04 02:00:05 PM PDT 24
Finished Jun 04 02:00:26 PM PDT 24
Peak memory 209588 kb
Host smart-a718c4e0-3bef-434a-840f-e9d7ea68e9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608643663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1608643663
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2040730611
Short name T816
Test name
Test status
Simulation time 32997391 ps
CPU time 2.47 seconds
Started Jun 04 02:00:06 PM PDT 24
Finished Jun 04 02:00:11 PM PDT 24
Peak memory 214264 kb
Host smart-ebbf2e16-b132-4223-976f-f63e6a85ac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040730611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2040730611
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3468119853
Short name T873
Test name
Test status
Simulation time 149310285 ps
CPU time 6.13 seconds
Started Jun 04 02:00:10 PM PDT 24
Finished Jun 04 02:00:19 PM PDT 24
Peak memory 222516 kb
Host smart-b2a247ce-83eb-4511-8f87-6638fd7fc49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468119853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3468119853
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.4179792898
Short name T621
Test name
Test status
Simulation time 260908229 ps
CPU time 3.97 seconds
Started Jun 04 02:00:06 PM PDT 24
Finished Jun 04 02:00:11 PM PDT 24
Peak memory 214384 kb
Host smart-62517af3-8045-43fd-9878-daf8ce5a543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179792898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.4179792898
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3160692354
Short name T514
Test name
Test status
Simulation time 706896195 ps
CPU time 5.51 seconds
Started Jun 04 02:00:07 PM PDT 24
Finished Jun 04 02:00:14 PM PDT 24
Peak memory 218196 kb
Host smart-e7e2cd8e-ef55-4181-ac1f-0bde86627179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160692354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3160692354
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.303125507
Short name T727
Test name
Test status
Simulation time 130174258 ps
CPU time 2.5 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:03 PM PDT 24
Peak memory 208736 kb
Host smart-01609eca-2528-430f-aad9-8e60cbf441bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303125507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.303125507
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3666689824
Short name T405
Test name
Test status
Simulation time 163536769 ps
CPU time 3.81 seconds
Started Jun 04 01:59:59 PM PDT 24
Finished Jun 04 02:00:04 PM PDT 24
Peak memory 208796 kb
Host smart-c95d4a8c-7a1e-4d4f-8332-694bdef6e94d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666689824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3666689824
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.481571075
Short name T671
Test name
Test status
Simulation time 196536966 ps
CPU time 4.18 seconds
Started Jun 04 01:59:55 PM PDT 24
Finished Jun 04 02:00:01 PM PDT 24
Peak memory 208660 kb
Host smart-f85968b3-b199-4052-ae0b-ebd714f1814b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481571075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.481571075
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2632943799
Short name T646
Test name
Test status
Simulation time 102367397 ps
CPU time 3.4 seconds
Started Jun 04 02:00:07 PM PDT 24
Finished Jun 04 02:00:13 PM PDT 24
Peak memory 208816 kb
Host smart-84d63aa1-c23e-4a5d-9c44-4bbbed532da7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632943799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2632943799
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.587712160
Short name T477
Test name
Test status
Simulation time 2525359233 ps
CPU time 7.12 seconds
Started Jun 04 02:00:04 PM PDT 24
Finished Jun 04 02:00:12 PM PDT 24
Peak memory 208836 kb
Host smart-9855e1f8-a4ec-4981-a601-7b87da6f7a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587712160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.587712160
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1247411333
Short name T678
Test name
Test status
Simulation time 224744605 ps
CPU time 4.84 seconds
Started Jun 04 02:00:02 PM PDT 24
Finished Jun 04 02:00:08 PM PDT 24
Peak memory 206948 kb
Host smart-f3d3a1d1-7ae6-469a-a964-78bfe293d78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247411333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1247411333
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1986380990
Short name T294
Test name
Test status
Simulation time 6102078097 ps
CPU time 178.46 seconds
Started Jun 04 02:00:04 PM PDT 24
Finished Jun 04 02:03:04 PM PDT 24
Peak memory 218432 kb
Host smart-bc905d7a-e5c5-464c-933b-ce82c405b503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986380990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1986380990
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.279954410
Short name T521
Test name
Test status
Simulation time 183298630 ps
CPU time 3.91 seconds
Started Jun 04 02:00:04 PM PDT 24
Finished Jun 04 02:00:09 PM PDT 24
Peak memory 218320 kb
Host smart-678441ec-96b0-405a-b891-91fa4c7a35ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279954410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.279954410
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.608128390
Short name T388
Test name
Test status
Simulation time 74464554 ps
CPU time 3.06 seconds
Started Jun 04 02:00:10 PM PDT 24
Finished Jun 04 02:00:14 PM PDT 24
Peak memory 210244 kb
Host smart-b8fd9239-bdf8-4266-a3f6-5cacb379fde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608128390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.608128390
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2832223630
Short name T441
Test name
Test status
Simulation time 64232237 ps
CPU time 0.91 seconds
Started Jun 04 01:57:51 PM PDT 24
Finished Jun 04 01:57:52 PM PDT 24
Peak memory 205948 kb
Host smart-22f77df4-8eb7-4352-977f-1908d3aef7b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832223630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2832223630
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2529459289
Short name T473
Test name
Test status
Simulation time 553978343 ps
CPU time 6.04 seconds
Started Jun 04 01:57:41 PM PDT 24
Finished Jun 04 01:57:48 PM PDT 24
Peak memory 214432 kb
Host smart-aa7de23f-210a-4c51-ba87-22698c3984b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529459289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2529459289
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3992550511
Short name T698
Test name
Test status
Simulation time 543805202 ps
CPU time 8.02 seconds
Started Jun 04 01:57:42 PM PDT 24
Finished Jun 04 01:57:52 PM PDT 24
Peak memory 214312 kb
Host smart-c75c5e66-6617-499b-954b-8a89de8c62a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992550511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3992550511
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2635537333
Short name T75
Test name
Test status
Simulation time 162157119 ps
CPU time 2.64 seconds
Started Jun 04 01:57:40 PM PDT 24
Finished Jun 04 01:57:43 PM PDT 24
Peak memory 210028 kb
Host smart-10f60c2e-200e-4f8c-a12c-2095191cc58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635537333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2635537333
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.492082885
Short name T824
Test name
Test status
Simulation time 2710951401 ps
CPU time 14.54 seconds
Started Jun 04 01:57:39 PM PDT 24
Finished Jun 04 01:57:54 PM PDT 24
Peak memory 209056 kb
Host smart-bdf348cc-9527-4c3d-9bc7-413c902470db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492082885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.492082885
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.185292084
Short name T114
Test name
Test status
Simulation time 488245550 ps
CPU time 6.07 seconds
Started Jun 04 01:57:46 PM PDT 24
Finished Jun 04 01:57:54 PM PDT 24
Peak memory 229228 kb
Host smart-96779823-85bb-4554-b47c-d448d2ce212d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185292084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.185292084
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4156315617
Short name T267
Test name
Test status
Simulation time 764642726 ps
CPU time 5.73 seconds
Started Jun 04 01:57:41 PM PDT 24
Finished Jun 04 01:57:48 PM PDT 24
Peak memory 208544 kb
Host smart-3c633829-1733-4d56-b121-22c3441a9369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156315617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4156315617
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1805874070
Short name T893
Test name
Test status
Simulation time 282404320 ps
CPU time 4.16 seconds
Started Jun 04 01:57:40 PM PDT 24
Finished Jun 04 01:57:45 PM PDT 24
Peak memory 208568 kb
Host smart-9489b693-e37c-4b83-b1d0-4250fc818c7c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805874070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1805874070
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1368867981
Short name T619
Test name
Test status
Simulation time 750663986 ps
CPU time 4.64 seconds
Started Jun 04 01:57:39 PM PDT 24
Finished Jun 04 01:57:44 PM PDT 24
Peak memory 208936 kb
Host smart-7ebd87b0-3b24-425f-8a6a-5dc288a21dca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368867981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1368867981
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.686400084
Short name T457
Test name
Test status
Simulation time 105361471 ps
CPU time 3.96 seconds
Started Jun 04 01:57:39 PM PDT 24
Finished Jun 04 01:57:43 PM PDT 24
Peak memory 207000 kb
Host smart-8aa88ce4-e8b5-4f67-bfdd-4af723405753
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686400084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.686400084
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2265050031
Short name T4
Test name
Test status
Simulation time 1596063129 ps
CPU time 19.06 seconds
Started Jun 04 01:57:49 PM PDT 24
Finished Jun 04 01:58:09 PM PDT 24
Peak memory 209880 kb
Host smart-d9e891ba-8430-4829-800f-968ca6bb1608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265050031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2265050031
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1345491386
Short name T481
Test name
Test status
Simulation time 418200378 ps
CPU time 3.01 seconds
Started Jun 04 01:57:34 PM PDT 24
Finished Jun 04 01:57:38 PM PDT 24
Peak memory 208144 kb
Host smart-21a0db27-be3e-4d9f-a495-b09e8da6c7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345491386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1345491386
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1143006141
Short name T254
Test name
Test status
Simulation time 507298474 ps
CPU time 12.92 seconds
Started Jun 04 01:57:47 PM PDT 24
Finished Jun 04 01:58:01 PM PDT 24
Peak memory 218452 kb
Host smart-ac37de0c-c721-4959-a342-127f63d8237f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143006141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1143006141
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2862749065
Short name T755
Test name
Test status
Simulation time 718231799 ps
CPU time 21.25 seconds
Started Jun 04 01:57:47 PM PDT 24
Finished Jun 04 01:58:09 PM PDT 24
Peak memory 221164 kb
Host smart-26761b22-4671-4718-8402-6f1bfa2ad6e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862749065 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2862749065
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2246779512
Short name T277
Test name
Test status
Simulation time 96119556 ps
CPU time 4.32 seconds
Started Jun 04 01:57:43 PM PDT 24
Finished Jun 04 01:57:48 PM PDT 24
Peak memory 209108 kb
Host smart-a9d52569-024a-4cf9-8ed6-c2197c119a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246779512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2246779512
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.709986049
Short name T519
Test name
Test status
Simulation time 232636794 ps
CPU time 2.45 seconds
Started Jun 04 01:57:48 PM PDT 24
Finished Jun 04 01:57:51 PM PDT 24
Peak memory 210308 kb
Host smart-00ce424f-a84c-48d5-8688-5cf47c855b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709986049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.709986049
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3859642395
Short name T598
Test name
Test status
Simulation time 40858632 ps
CPU time 0.85 seconds
Started Jun 04 02:00:05 PM PDT 24
Finished Jun 04 02:00:07 PM PDT 24
Peak memory 205960 kb
Host smart-4bee5260-e03a-42d4-a598-22679d75ce18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859642395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3859642395
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1869376261
Short name T203
Test name
Test status
Simulation time 50013512 ps
CPU time 2.06 seconds
Started Jun 04 02:00:07 PM PDT 24
Finished Jun 04 02:00:10 PM PDT 24
Peak memory 218896 kb
Host smart-b668e2bb-6ca5-4bd8-b7b4-44498e85cc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869376261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1869376261
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3642425608
Short name T366
Test name
Test status
Simulation time 86096129 ps
CPU time 2.38 seconds
Started Jun 04 02:00:07 PM PDT 24
Finished Jun 04 02:00:12 PM PDT 24
Peak memory 210140 kb
Host smart-38b53449-de9d-42fb-b55d-8e1b1a2bf59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642425608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3642425608
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2937368598
Short name T902
Test name
Test status
Simulation time 175962765 ps
CPU time 3.94 seconds
Started Jun 04 02:00:06 PM PDT 24
Finished Jun 04 02:00:12 PM PDT 24
Peak memory 222396 kb
Host smart-6984c83a-88dc-4ca0-9228-8baf800de4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937368598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2937368598
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2729120966
Short name T258
Test name
Test status
Simulation time 404581254 ps
CPU time 4.97 seconds
Started Jun 04 02:00:08 PM PDT 24
Finished Jun 04 02:00:15 PM PDT 24
Peak memory 221804 kb
Host smart-86839efa-0921-4579-b5c7-f32f544bc6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729120966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2729120966
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3270389626
Short name T623
Test name
Test status
Simulation time 33373861 ps
CPU time 2.06 seconds
Started Jun 04 02:00:07 PM PDT 24
Finished Jun 04 02:00:11 PM PDT 24
Peak memory 215352 kb
Host smart-f0be8be8-64d0-492a-828e-4714e84d7f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270389626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3270389626
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3038304235
Short name T877
Test name
Test status
Simulation time 481740416 ps
CPU time 4.37 seconds
Started Jun 04 02:00:08 PM PDT 24
Finished Jun 04 02:00:14 PM PDT 24
Peak memory 219096 kb
Host smart-d7530f05-5d88-4ffe-a96a-9a2952f89c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038304235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3038304235
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3579907608
Short name T633
Test name
Test status
Simulation time 197045477 ps
CPU time 2.68 seconds
Started Jun 04 02:00:09 PM PDT 24
Finished Jun 04 02:00:13 PM PDT 24
Peak memory 206984 kb
Host smart-8887b757-6990-4777-a95c-cbe39d63b0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579907608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3579907608
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.135435378
Short name T695
Test name
Test status
Simulation time 478075918 ps
CPU time 4.1 seconds
Started Jun 04 02:00:07 PM PDT 24
Finished Jun 04 02:00:13 PM PDT 24
Peak memory 208480 kb
Host smart-7219d497-7f86-4735-b7ed-fa75843cf9ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135435378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.135435378
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2829085088
Short name T38
Test name
Test status
Simulation time 305316682 ps
CPU time 6.08 seconds
Started Jun 04 02:00:06 PM PDT 24
Finished Jun 04 02:00:14 PM PDT 24
Peak memory 208548 kb
Host smart-3c47fce7-c1b6-47aa-84df-66e218a72c0b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829085088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2829085088
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3897495325
Short name T355
Test name
Test status
Simulation time 42706728 ps
CPU time 3.13 seconds
Started Jun 04 02:00:11 PM PDT 24
Finished Jun 04 02:00:16 PM PDT 24
Peak memory 208600 kb
Host smart-24ae62c2-eb90-48dc-b8f6-a38b6ef41ab7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897495325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3897495325
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3875894106
Short name T559
Test name
Test status
Simulation time 77264285 ps
CPU time 2.15 seconds
Started Jun 04 02:00:09 PM PDT 24
Finished Jun 04 02:00:13 PM PDT 24
Peak memory 208900 kb
Host smart-d31a2e91-c577-44aa-a5df-aa26dc7ac317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875894106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3875894106
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3261567862
Short name T592
Test name
Test status
Simulation time 521544299 ps
CPU time 4.12 seconds
Started Jun 04 02:00:03 PM PDT 24
Finished Jun 04 02:00:09 PM PDT 24
Peak memory 206900 kb
Host smart-cfaa276e-52a6-4ff6-919d-85aa07df15fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261567862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3261567862
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2172883837
Short name T853
Test name
Test status
Simulation time 3001430461 ps
CPU time 27.12 seconds
Started Jun 04 02:00:04 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 222572 kb
Host smart-f6866f45-7a44-4d38-9ba7-fee48ceb7f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172883837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2172883837
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1400412745
Short name T604
Test name
Test status
Simulation time 1064159350 ps
CPU time 14.39 seconds
Started Jun 04 02:00:10 PM PDT 24
Finished Jun 04 02:00:26 PM PDT 24
Peak memory 214356 kb
Host smart-8b58ff37-2e2e-48e2-a90c-f88c96c98573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400412745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1400412745
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.595261648
Short name T392
Test name
Test status
Simulation time 80757673 ps
CPU time 3.11 seconds
Started Jun 04 02:00:05 PM PDT 24
Finished Jun 04 02:00:09 PM PDT 24
Peak memory 210508 kb
Host smart-6a553e85-b566-46cc-9c24-12be8b31e79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595261648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.595261648
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2773728034
Short name T590
Test name
Test status
Simulation time 15800198 ps
CPU time 0.93 seconds
Started Jun 04 02:00:17 PM PDT 24
Finished Jun 04 02:00:19 PM PDT 24
Peak memory 206140 kb
Host smart-fe774411-87c0-46a8-a01f-23d825d95a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773728034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2773728034
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3409545967
Short name T430
Test name
Test status
Simulation time 42999531 ps
CPU time 3.13 seconds
Started Jun 04 02:00:08 PM PDT 24
Finished Jun 04 02:00:13 PM PDT 24
Peak memory 214336 kb
Host smart-5712c1ad-d3fa-4a20-b3fa-e82a2a7a2ce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409545967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3409545967
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2311427521
Short name T520
Test name
Test status
Simulation time 69155157 ps
CPU time 2.01 seconds
Started Jun 04 02:00:07 PM PDT 24
Finished Jun 04 02:00:11 PM PDT 24
Peak memory 207464 kb
Host smart-8f048004-48a4-4123-b79a-3247c8acee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311427521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2311427521
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1055632552
Short name T791
Test name
Test status
Simulation time 280428068 ps
CPU time 3.49 seconds
Started Jun 04 02:00:16 PM PDT 24
Finished Jun 04 02:00:20 PM PDT 24
Peak memory 214384 kb
Host smart-6302c2be-56c1-4b8e-a2f5-6ad23c3e6469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055632552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1055632552
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3125454179
Short name T288
Test name
Test status
Simulation time 163645201 ps
CPU time 3.06 seconds
Started Jun 04 02:00:15 PM PDT 24
Finished Jun 04 02:00:19 PM PDT 24
Peak memory 214232 kb
Host smart-65102829-e2fb-400b-aeef-f7ddac5826f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125454179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3125454179
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_random.1314677455
Short name T500
Test name
Test status
Simulation time 747141520 ps
CPU time 9.89 seconds
Started Jun 04 02:00:08 PM PDT 24
Finished Jun 04 02:00:20 PM PDT 24
Peak memory 209380 kb
Host smart-8ff68096-b074-4188-bcdf-7b51338a6471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314677455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1314677455
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.252897191
Short name T448
Test name
Test status
Simulation time 69587407 ps
CPU time 3.05 seconds
Started Jun 04 02:00:10 PM PDT 24
Finished Jun 04 02:00:15 PM PDT 24
Peak memory 207004 kb
Host smart-28efe455-30bd-45a8-89fb-b0f25674d928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252897191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.252897191
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.707581797
Short name T460
Test name
Test status
Simulation time 285918168 ps
CPU time 2.59 seconds
Started Jun 04 02:00:08 PM PDT 24
Finished Jun 04 02:00:13 PM PDT 24
Peak memory 206896 kb
Host smart-f6c0d696-da2e-4893-b42b-80c370a33bc8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707581797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.707581797
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.919455063
Short name T498
Test name
Test status
Simulation time 136265525 ps
CPU time 3.4 seconds
Started Jun 04 02:00:09 PM PDT 24
Finished Jun 04 02:00:14 PM PDT 24
Peak memory 208332 kb
Host smart-41658f6b-65cd-4101-8849-075b85928a9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919455063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.919455063
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2706329546
Short name T319
Test name
Test status
Simulation time 252007545 ps
CPU time 3.26 seconds
Started Jun 04 02:00:11 PM PDT 24
Finished Jun 04 02:00:16 PM PDT 24
Peak memory 208828 kb
Host smart-9ec3304a-ab73-49f4-ab9b-49edd91b6279
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706329546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2706329546
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3615667361
Short name T726
Test name
Test status
Simulation time 699876076 ps
CPU time 5.53 seconds
Started Jun 04 02:00:20 PM PDT 24
Finished Jun 04 02:00:26 PM PDT 24
Peak memory 216256 kb
Host smart-86e12123-446d-4e1c-9e25-13a9917d0367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615667361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3615667361
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1608088923
Short name T886
Test name
Test status
Simulation time 293288923 ps
CPU time 2.28 seconds
Started Jun 04 02:00:04 PM PDT 24
Finished Jun 04 02:00:07 PM PDT 24
Peak memory 208320 kb
Host smart-e9aa650d-cca3-4851-9396-7d8ef785647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608088923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1608088923
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3586805640
Short name T371
Test name
Test status
Simulation time 385155272 ps
CPU time 15.3 seconds
Started Jun 04 02:00:15 PM PDT 24
Finished Jun 04 02:00:31 PM PDT 24
Peak memory 220884 kb
Host smart-b1371bff-ed4a-4ea4-95ef-536283266bd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586805640 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3586805640
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1154150014
Short name T846
Test name
Test status
Simulation time 555817927 ps
CPU time 5.48 seconds
Started Jun 04 02:00:18 PM PDT 24
Finished Jun 04 02:00:25 PM PDT 24
Peak memory 218284 kb
Host smart-4845e900-e303-4cc1-8bdc-3cd971fc1460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154150014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1154150014
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.734319890
Short name T737
Test name
Test status
Simulation time 73665196 ps
CPU time 2.45 seconds
Started Jun 04 02:00:20 PM PDT 24
Finished Jun 04 02:00:23 PM PDT 24
Peak memory 210132 kb
Host smart-0d6d3e02-e48a-47d8-ac40-0682e9a99403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734319890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.734319890
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.150172299
Short name T447
Test name
Test status
Simulation time 48069130 ps
CPU time 0.8 seconds
Started Jun 04 02:00:15 PM PDT 24
Finished Jun 04 02:00:17 PM PDT 24
Peak memory 205936 kb
Host smart-289f93e9-3ba4-47a9-810e-9feca43ee5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150172299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.150172299
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.4145231770
Short name T395
Test name
Test status
Simulation time 41540589 ps
CPU time 2.84 seconds
Started Jun 04 02:00:17 PM PDT 24
Finished Jun 04 02:00:21 PM PDT 24
Peak memory 215056 kb
Host smart-c6cc6612-bb98-4cfe-b0ad-8f1bb35cb61f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145231770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.4145231770
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3568672912
Short name T516
Test name
Test status
Simulation time 1293252972 ps
CPU time 11.07 seconds
Started Jun 04 02:00:18 PM PDT 24
Finished Jun 04 02:00:30 PM PDT 24
Peak memory 218728 kb
Host smart-86050d6b-b689-4df9-8c88-2601ffa3f912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568672912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3568672912
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3117043985
Short name T400
Test name
Test status
Simulation time 57583396 ps
CPU time 2.03 seconds
Started Jun 04 02:00:16 PM PDT 24
Finished Jun 04 02:00:18 PM PDT 24
Peak memory 207816 kb
Host smart-eee5c0f3-4c7f-42a3-826d-6330e92451b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117043985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3117043985
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3742897183
Short name T268
Test name
Test status
Simulation time 73610545 ps
CPU time 3.66 seconds
Started Jun 04 02:00:18 PM PDT 24
Finished Jun 04 02:00:23 PM PDT 24
Peak memory 214332 kb
Host smart-ea1a8e4c-6a15-478a-a6aa-20bb5846c398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742897183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3742897183
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.970046208
Short name T788
Test name
Test status
Simulation time 243767949 ps
CPU time 3.09 seconds
Started Jun 04 02:00:19 PM PDT 24
Finished Jun 04 02:00:23 PM PDT 24
Peak memory 210680 kb
Host smart-88d29b3c-d946-421c-9093-8ff47688afc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970046208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.970046208
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.4065803292
Short name T686
Test name
Test status
Simulation time 289169306 ps
CPU time 5.12 seconds
Started Jun 04 02:00:18 PM PDT 24
Finished Jun 04 02:00:25 PM PDT 24
Peak memory 214368 kb
Host smart-00590a4f-bb81-4ede-bf48-cd809da920c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065803292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.4065803292
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3304755591
Short name T904
Test name
Test status
Simulation time 182960338 ps
CPU time 3.88 seconds
Started Jun 04 02:00:17 PM PDT 24
Finished Jun 04 02:00:22 PM PDT 24
Peak memory 207492 kb
Host smart-40d0c36c-c1b3-4092-b75a-820f7e1174b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304755591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3304755591
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2929871608
Short name T96
Test name
Test status
Simulation time 115695707 ps
CPU time 2.13 seconds
Started Jun 04 02:00:19 PM PDT 24
Finished Jun 04 02:00:23 PM PDT 24
Peak memory 206744 kb
Host smart-d000fad4-3ce6-43e7-87fa-996dbc580a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929871608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2929871608
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3855817324
Short name T836
Test name
Test status
Simulation time 1762992939 ps
CPU time 4.39 seconds
Started Jun 04 02:00:18 PM PDT 24
Finished Jun 04 02:00:23 PM PDT 24
Peak memory 206960 kb
Host smart-eeed43fe-3599-4055-acc9-d17d8d22b70d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855817324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3855817324
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3661086852
Short name T872
Test name
Test status
Simulation time 81479952 ps
CPU time 3.43 seconds
Started Jun 04 02:00:18 PM PDT 24
Finished Jun 04 02:00:23 PM PDT 24
Peak memory 208628 kb
Host smart-2a6011c2-a455-4a35-b70c-a663efb35a36
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661086852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3661086852
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.998396962
Short name T551
Test name
Test status
Simulation time 99634302 ps
CPU time 3.43 seconds
Started Jun 04 02:00:17 PM PDT 24
Finished Jun 04 02:00:21 PM PDT 24
Peak memory 208900 kb
Host smart-cab04686-d13f-4d41-8629-659f75fd6ca4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998396962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.998396962
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.901794503
Short name T875
Test name
Test status
Simulation time 156077613 ps
CPU time 2.51 seconds
Started Jun 04 02:00:18 PM PDT 24
Finished Jun 04 02:00:22 PM PDT 24
Peak memory 208236 kb
Host smart-1a6b5778-a6a7-4db8-8421-7df2e662ddec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901794503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.901794503
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4124907416
Short name T92
Test name
Test status
Simulation time 1358125768 ps
CPU time 27.01 seconds
Started Jun 04 02:00:17 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 208788 kb
Host smart-8e9d3548-26e2-48ff-bc05-f5321c9e5dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124907416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4124907416
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1831006585
Short name T627
Test name
Test status
Simulation time 1582158759 ps
CPU time 18.15 seconds
Started Jun 04 02:00:16 PM PDT 24
Finished Jun 04 02:00:35 PM PDT 24
Peak memory 214960 kb
Host smart-93d3054e-4c9c-4ac6-946d-626d5918de7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831006585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1831006585
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.4182536115
Short name T801
Test name
Test status
Simulation time 2097727562 ps
CPU time 20.93 seconds
Started Jun 04 02:00:20 PM PDT 24
Finished Jun 04 02:00:42 PM PDT 24
Peak memory 222656 kb
Host smart-cb763204-9bba-41db-b312-881ae5cfd897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182536115 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.4182536115
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1502372935
Short name T309
Test name
Test status
Simulation time 313628277 ps
CPU time 9.15 seconds
Started Jun 04 02:00:19 PM PDT 24
Finished Jun 04 02:00:29 PM PDT 24
Peak memory 214336 kb
Host smart-99bca08a-4a75-4d64-b91e-4a014e2fc0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502372935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1502372935
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1186872384
Short name T610
Test name
Test status
Simulation time 23360824 ps
CPU time 0.7 seconds
Started Jun 04 02:00:24 PM PDT 24
Finished Jun 04 02:00:25 PM PDT 24
Peak memory 205952 kb
Host smart-97883b9e-c0ff-42e2-9f48-825e1b1c4dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186872384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1186872384
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.210454223
Short name T422
Test name
Test status
Simulation time 179260369 ps
CPU time 9.29 seconds
Started Jun 04 02:00:18 PM PDT 24
Finished Jun 04 02:00:28 PM PDT 24
Peak memory 214724 kb
Host smart-fa71db6a-1b45-47ad-a431-0d5eed70d5db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=210454223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.210454223
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2737823049
Short name T29
Test name
Test status
Simulation time 570106591 ps
CPU time 5.75 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:35 PM PDT 24
Peak memory 210412 kb
Host smart-1c88d05e-b9ec-4b07-9e56-217f3c5987fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737823049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2737823049
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3913513274
Short name T543
Test name
Test status
Simulation time 596235322 ps
CPU time 4.12 seconds
Started Jun 04 02:00:17 PM PDT 24
Finished Jun 04 02:00:22 PM PDT 24
Peak memory 218280 kb
Host smart-b5f915af-8076-4d8e-85b8-c7bb3d5ec9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913513274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3913513274
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3005773289
Short name T104
Test name
Test status
Simulation time 198755405 ps
CPU time 3.42 seconds
Started Jun 04 02:00:18 PM PDT 24
Finished Jun 04 02:00:22 PM PDT 24
Peak memory 209404 kb
Host smart-a719388a-854c-4fdd-9362-627a93ef1683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005773289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3005773289
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1957571466
Short name T474
Test name
Test status
Simulation time 42380632 ps
CPU time 1.79 seconds
Started Jun 04 02:00:25 PM PDT 24
Finished Jun 04 02:00:28 PM PDT 24
Peak memory 214220 kb
Host smart-9c404842-3531-4998-bc99-41aa07c6489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957571466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1957571466
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4152114549
Short name T648
Test name
Test status
Simulation time 78058842 ps
CPU time 3.99 seconds
Started Jun 04 02:00:17 PM PDT 24
Finished Jun 04 02:00:21 PM PDT 24
Peak memory 222380 kb
Host smart-6765d151-f582-40e7-855a-484bdc89a5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152114549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4152114549
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3960647113
Short name T725
Test name
Test status
Simulation time 414440242 ps
CPU time 3.28 seconds
Started Jun 04 02:00:17 PM PDT 24
Finished Jun 04 02:00:21 PM PDT 24
Peak memory 207028 kb
Host smart-52d2f28a-f0c4-428e-9ba2-6b7f24e68c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960647113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3960647113
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1733937724
Short name T476
Test name
Test status
Simulation time 174317017 ps
CPU time 2.6 seconds
Started Jun 04 02:00:16 PM PDT 24
Finished Jun 04 02:00:20 PM PDT 24
Peak memory 206108 kb
Host smart-3d82f696-e586-43bc-81f1-d77130e7bf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733937724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1733937724
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2410154992
Short name T589
Test name
Test status
Simulation time 237554796 ps
CPU time 6.24 seconds
Started Jun 04 02:00:15 PM PDT 24
Finished Jun 04 02:00:22 PM PDT 24
Peak memory 208756 kb
Host smart-09f3e6e1-5711-4409-8cb7-9c0b71704c94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410154992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2410154992
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.372897372
Short name T602
Test name
Test status
Simulation time 109229848 ps
CPU time 4.7 seconds
Started Jun 04 02:00:19 PM PDT 24
Finished Jun 04 02:00:25 PM PDT 24
Peak memory 208880 kb
Host smart-e2486df3-f5fd-405a-b048-f17b9b490a7d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372897372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.372897372
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4062540740
Short name T834
Test name
Test status
Simulation time 22632969 ps
CPU time 1.81 seconds
Started Jun 04 02:00:16 PM PDT 24
Finished Jun 04 02:00:19 PM PDT 24
Peak memory 207468 kb
Host smart-3e973537-9a4e-47f8-b8a8-a888db3eca03
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062540740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4062540740
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2805725963
Short name T36
Test name
Test status
Simulation time 262677984 ps
CPU time 3.64 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 216008 kb
Host smart-4a9690b5-d829-4348-9e63-996a64d6041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805725963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2805725963
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2897842185
Short name T564
Test name
Test status
Simulation time 879718623 ps
CPU time 4.7 seconds
Started Jun 04 02:00:16 PM PDT 24
Finished Jun 04 02:00:22 PM PDT 24
Peak memory 208580 kb
Host smart-cf996d6d-96fb-4e7f-bc86-c7d7961c4703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897842185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2897842185
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2933180706
Short name T209
Test name
Test status
Simulation time 9724431013 ps
CPU time 52.63 seconds
Started Jun 04 02:00:29 PM PDT 24
Finished Jun 04 02:01:23 PM PDT 24
Peak memory 216444 kb
Host smart-df7385c3-cbc6-48f7-9f36-1ea88d286c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933180706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2933180706
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1020416987
Short name T141
Test name
Test status
Simulation time 1423427158 ps
CPU time 18.96 seconds
Started Jun 04 02:00:25 PM PDT 24
Finished Jun 04 02:00:46 PM PDT 24
Peak memory 222648 kb
Host smart-ebf05ca1-687c-4e18-8cc1-1237bc525098
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020416987 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1020416987
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1511438
Short name T810
Test name
Test status
Simulation time 306155431 ps
CPU time 3.62 seconds
Started Jun 04 02:00:19 PM PDT 24
Finished Jun 04 02:00:24 PM PDT 24
Peak memory 207684 kb
Host smart-d0c96a15-8f5b-41a3-88b7-d8b7929f7d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1511438
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3177629036
Short name T188
Test name
Test status
Simulation time 395731035 ps
CPU time 4.17 seconds
Started Jun 04 02:00:28 PM PDT 24
Finished Jun 04 02:00:34 PM PDT 24
Peak memory 210148 kb
Host smart-a878bb8b-c719-4765-aeab-07141545d747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177629036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3177629036
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1096035560
Short name T221
Test name
Test status
Simulation time 72533198 ps
CPU time 0.76 seconds
Started Jun 04 02:00:25 PM PDT 24
Finished Jun 04 02:00:27 PM PDT 24
Peak memory 205964 kb
Host smart-56dfcb37-2620-4e55-8049-26eef57ce2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096035560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1096035560
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3483450552
Short name T295
Test name
Test status
Simulation time 172643027 ps
CPU time 4.35 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 218280 kb
Host smart-b227a188-23da-4710-b2c6-b9958e92645b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483450552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3483450552
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1748009951
Short name T854
Test name
Test status
Simulation time 41880503 ps
CPU time 2.83 seconds
Started Jun 04 02:00:24 PM PDT 24
Finished Jun 04 02:00:28 PM PDT 24
Peak memory 208484 kb
Host smart-0c3bd8d0-4b9e-4b8e-be97-0ff49d329821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748009951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1748009951
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1651134467
Short name T349
Test name
Test status
Simulation time 53296675 ps
CPU time 1.66 seconds
Started Jun 04 02:00:25 PM PDT 24
Finished Jun 04 02:00:28 PM PDT 24
Peak memory 214212 kb
Host smart-89b8f54e-da8a-48fa-afc7-36176a34330f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651134467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1651134467
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.471463316
Short name T66
Test name
Test status
Simulation time 98628158 ps
CPU time 3.85 seconds
Started Jun 04 02:00:29 PM PDT 24
Finished Jun 04 02:00:34 PM PDT 24
Peak memory 209368 kb
Host smart-cd685177-75ca-4008-afc7-771c908e04e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471463316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.471463316
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2730409731
Short name T312
Test name
Test status
Simulation time 44874847 ps
CPU time 2.95 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:31 PM PDT 24
Peak memory 209492 kb
Host smart-62c68cbf-a5a2-4548-a119-8b4f149a3c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730409731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2730409731
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2226457487
Short name T561
Test name
Test status
Simulation time 421424442 ps
CPU time 2.54 seconds
Started Jun 04 02:00:29 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 206904 kb
Host smart-13e374d1-56eb-4cf3-b320-d74aa29cbeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226457487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2226457487
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.122589175
Short name T434
Test name
Test status
Simulation time 4602439494 ps
CPU time 33.9 seconds
Started Jun 04 02:00:29 PM PDT 24
Finished Jun 04 02:01:05 PM PDT 24
Peak memory 208148 kb
Host smart-9e915f04-cd68-4df8-98f8-d610fb046db9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122589175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.122589175
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4251617980
Short name T581
Test name
Test status
Simulation time 1306967065 ps
CPU time 3.55 seconds
Started Jun 04 02:00:29 PM PDT 24
Finished Jun 04 02:00:34 PM PDT 24
Peak memory 207016 kb
Host smart-7fa761ad-c933-4768-9c34-9681ae86b6de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251617980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4251617980
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.4275416133
Short name T15
Test name
Test status
Simulation time 1091394859 ps
CPU time 27.06 seconds
Started Jun 04 02:00:25 PM PDT 24
Finished Jun 04 02:00:53 PM PDT 24
Peak memory 208424 kb
Host smart-fc53412a-9390-4aa9-b0dd-73136cf4740f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275416133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.4275416133
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2417558445
Short name T340
Test name
Test status
Simulation time 214876403 ps
CPU time 3.01 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:31 PM PDT 24
Peak memory 209164 kb
Host smart-4a675d69-49f7-41d5-be4a-5fd191290e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417558445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2417558445
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1686656726
Short name T626
Test name
Test status
Simulation time 80287112 ps
CPU time 1.83 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:29 PM PDT 24
Peak memory 208552 kb
Host smart-89f76cb7-37ae-4b7a-b316-2b1a100b5f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686656726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1686656726
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2906650578
Short name T242
Test name
Test status
Simulation time 420226771 ps
CPU time 16.16 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:44 PM PDT 24
Peak memory 222496 kb
Host smart-c25ba897-7a61-4b59-8baa-6c40ded552a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906650578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2906650578
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2868695816
Short name T195
Test name
Test status
Simulation time 2907268850 ps
CPU time 25.65 seconds
Started Jun 04 02:00:24 PM PDT 24
Finished Jun 04 02:00:51 PM PDT 24
Peak memory 222636 kb
Host smart-d9288c2e-0b97-453b-a3de-a8345d46fd53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868695816 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2868695816
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1976653731
Short name T597
Test name
Test status
Simulation time 310063009 ps
CPU time 4.2 seconds
Started Jun 04 02:00:24 PM PDT 24
Finished Jun 04 02:00:30 PM PDT 24
Peak memory 207632 kb
Host smart-aac2d404-5e89-44b0-91cb-03ac3852290f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976653731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1976653731
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1425277898
Short name T601
Test name
Test status
Simulation time 56536343 ps
CPU time 0.92 seconds
Started Jun 04 02:00:25 PM PDT 24
Finished Jun 04 02:00:28 PM PDT 24
Peak memory 206076 kb
Host smart-57ac4b86-ea42-4fe9-9a5b-c722af1a03e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425277898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1425277898
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2920417511
Short name T776
Test name
Test status
Simulation time 34389152 ps
CPU time 2.76 seconds
Started Jun 04 02:00:25 PM PDT 24
Finished Jun 04 02:00:28 PM PDT 24
Peak memory 214344 kb
Host smart-0fb9410e-f4cd-490d-b2a8-a908eb3325fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920417511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2920417511
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3354739932
Short name T80
Test name
Test status
Simulation time 57669480 ps
CPU time 1.81 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:30 PM PDT 24
Peak memory 206120 kb
Host smart-69a3dab5-5a72-4d05-9c09-f8333aa147c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354739932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3354739932
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1198878924
Short name T805
Test name
Test status
Simulation time 418513173 ps
CPU time 3.83 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 214360 kb
Host smart-fc32a90d-03d7-49b9-a266-b17cddbd5b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198878924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1198878924
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.970470097
Short name T635
Test name
Test status
Simulation time 85355436 ps
CPU time 3.52 seconds
Started Jun 04 02:00:29 PM PDT 24
Finished Jun 04 02:00:34 PM PDT 24
Peak memory 214372 kb
Host smart-d9523a1b-b672-4887-af8f-34fd5c8d79b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970470097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.970470097
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3158437744
Short name T517
Test name
Test status
Simulation time 155195730 ps
CPU time 2.29 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:29 PM PDT 24
Peak memory 215240 kb
Host smart-04e0607f-e209-463a-9bb8-9cd28b017012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158437744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3158437744
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3670686356
Short name T326
Test name
Test status
Simulation time 168933315 ps
CPU time 2.91 seconds
Started Jun 04 02:00:29 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 207748 kb
Host smart-03281546-964e-4a38-b9c6-3a5d2a02946f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670686356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3670686356
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2882059990
Short name T373
Test name
Test status
Simulation time 80654336 ps
CPU time 1.89 seconds
Started Jun 04 02:00:28 PM PDT 24
Finished Jun 04 02:00:32 PM PDT 24
Peak memory 207320 kb
Host smart-0668a25f-6df3-433c-adb0-de61bdff3210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882059990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2882059990
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4053199253
Short name T315
Test name
Test status
Simulation time 471984363 ps
CPU time 5.1 seconds
Started Jun 04 02:00:24 PM PDT 24
Finished Jun 04 02:00:30 PM PDT 24
Peak memory 207120 kb
Host smart-f6f7f575-48f2-4740-b863-3416dbd03f40
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053199253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4053199253
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.4275783276
Short name T879
Test name
Test status
Simulation time 147363115 ps
CPU time 2.83 seconds
Started Jun 04 02:00:28 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 206908 kb
Host smart-7c00cf85-388f-46e2-8e17-b1b5e7f16400
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275783276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.4275783276
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2889179745
Short name T758
Test name
Test status
Simulation time 93696150 ps
CPU time 3.73 seconds
Started Jun 04 02:00:28 PM PDT 24
Finished Jun 04 02:00:34 PM PDT 24
Peak memory 208948 kb
Host smart-4e629cf8-cefc-4257-b666-94381a50623f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889179745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2889179745
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1451214384
Short name T438
Test name
Test status
Simulation time 198775256 ps
CPU time 4.42 seconds
Started Jun 04 02:00:24 PM PDT 24
Finished Jun 04 02:00:30 PM PDT 24
Peak memory 208388 kb
Host smart-15d38baa-38d7-48a8-99b8-258eb31d1fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451214384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1451214384
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2003160383
Short name T383
Test name
Test status
Simulation time 823002442 ps
CPU time 13.74 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:43 PM PDT 24
Peak memory 222556 kb
Host smart-fbb830d1-a404-4f55-a02c-4349a1ea1c7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003160383 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2003160383
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1823123196
Short name T204
Test name
Test status
Simulation time 2039248728 ps
CPU time 49.23 seconds
Started Jun 04 02:00:30 PM PDT 24
Finished Jun 04 02:01:20 PM PDT 24
Peak memory 210428 kb
Host smart-5e27bf8f-63b1-4a63-955f-e53ffb29b968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823123196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1823123196
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3972297190
Short name T884
Test name
Test status
Simulation time 51254471 ps
CPU time 2.5 seconds
Started Jun 04 02:00:25 PM PDT 24
Finished Jun 04 02:00:29 PM PDT 24
Peak memory 210160 kb
Host smart-5ccd987a-9c70-43f1-8694-ff64289ce226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972297190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3972297190
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3526684982
Short name T841
Test name
Test status
Simulation time 7833883 ps
CPU time 0.68 seconds
Started Jun 04 02:00:33 PM PDT 24
Finished Jun 04 02:00:35 PM PDT 24
Peak memory 205964 kb
Host smart-c94a4516-3b89-4ef0-90c4-75d1c1e1fb84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526684982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3526684982
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1496922381
Short name T414
Test name
Test status
Simulation time 918688346 ps
CPU time 48.06 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:01:16 PM PDT 24
Peak memory 214660 kb
Host smart-fe22f7dc-13d7-49b1-8ddb-18dd84ba8646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496922381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1496922381
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.366124938
Short name T20
Test name
Test status
Simulation time 1334696398 ps
CPU time 5.81 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 222728 kb
Host smart-dd964489-c69b-44fa-a6b3-d70e155a2823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366124938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.366124938
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.353293966
Short name T808
Test name
Test status
Simulation time 122790766 ps
CPU time 3.81 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 209940 kb
Host smart-3e799850-8cf9-45a5-865a-c4d094a5d7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353293966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.353293966
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2290677211
Short name T225
Test name
Test status
Simulation time 658965469 ps
CPU time 8.27 seconds
Started Jun 04 02:00:28 PM PDT 24
Finished Jun 04 02:00:38 PM PDT 24
Peak memory 214428 kb
Host smart-115f7552-194e-4a04-b9b9-24c87bfe3085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290677211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2290677211
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.808685495
Short name T271
Test name
Test status
Simulation time 40102978 ps
CPU time 2.47 seconds
Started Jun 04 02:00:25 PM PDT 24
Finished Jun 04 02:00:28 PM PDT 24
Peak memory 214312 kb
Host smart-b51bca39-eb3f-41b6-b751-0cdc73c464f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808685495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.808685495
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1170093384
Short name T771
Test name
Test status
Simulation time 686337789 ps
CPU time 5.45 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:35 PM PDT 24
Peak memory 222424 kb
Host smart-34dd7068-5dde-4513-8292-c6e5bc90474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170093384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1170093384
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1461371962
Short name T402
Test name
Test status
Simulation time 273639416 ps
CPU time 4 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:34 PM PDT 24
Peak memory 218132 kb
Host smart-5cc640a8-7950-4c09-a9e2-c9b5ed8723cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461371962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1461371962
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.595746772
Short name T387
Test name
Test status
Simulation time 115070855 ps
CPU time 2.91 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:31 PM PDT 24
Peak memory 206760 kb
Host smart-cc799058-2ee2-4867-9786-fe3d17aede47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595746772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.595746772
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2122953566
Short name T123
Test name
Test status
Simulation time 1893354578 ps
CPU time 38.23 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:01:06 PM PDT 24
Peak memory 208508 kb
Host smart-387d9823-96ad-4a89-834b-81389f878e3a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122953566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2122953566
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1624019492
Short name T722
Test name
Test status
Simulation time 366407375 ps
CPU time 7.49 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:37 PM PDT 24
Peak memory 208028 kb
Host smart-7109e6bf-52e2-494d-8d9c-735592aa4a2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624019492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1624019492
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.642499499
Short name T664
Test name
Test status
Simulation time 87658801 ps
CPU time 2.95 seconds
Started Jun 04 02:00:24 PM PDT 24
Finished Jun 04 02:00:28 PM PDT 24
Peak memory 206780 kb
Host smart-723c8a64-67ca-4a07-9ee8-7fd6ee00ec32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642499499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.642499499
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.944408667
Short name T487
Test name
Test status
Simulation time 93720744 ps
CPU time 1.69 seconds
Started Jun 04 02:00:29 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 215852 kb
Host smart-6a05f2be-7aba-42ec-93db-95e4d21b2c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944408667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.944408667
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2462623789
Short name T443
Test name
Test status
Simulation time 1267041102 ps
CPU time 5.31 seconds
Started Jun 04 02:00:28 PM PDT 24
Finished Jun 04 02:00:35 PM PDT 24
Peak memory 207132 kb
Host smart-c3e9039d-b84e-48cc-af6f-70470deac059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462623789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2462623789
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.494233854
Short name T360
Test name
Test status
Simulation time 221447428 ps
CPU time 9.31 seconds
Started Jun 04 02:00:30 PM PDT 24
Finished Jun 04 02:00:41 PM PDT 24
Peak memory 215076 kb
Host smart-e8d8f877-e54d-4f8a-9081-ac72c4fef542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494233854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.494233854
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.4014855748
Short name T558
Test name
Test status
Simulation time 171075609 ps
CPU time 10.56 seconds
Started Jun 04 02:00:29 PM PDT 24
Finished Jun 04 02:00:41 PM PDT 24
Peak memory 220588 kb
Host smart-02a9c737-cd1c-46e3-8c1b-74737b46a63e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014855748 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.4014855748
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1560518495
Short name T631
Test name
Test status
Simulation time 770993998 ps
CPU time 5.87 seconds
Started Jun 04 02:00:26 PM PDT 24
Finished Jun 04 02:00:34 PM PDT 24
Peak memory 214344 kb
Host smart-e7e2f2ae-29ff-46fd-8aaa-d805c32b45bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560518495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1560518495
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2168314670
Short name T391
Test name
Test status
Simulation time 126161363 ps
CPU time 3.87 seconds
Started Jun 04 02:00:27 PM PDT 24
Finished Jun 04 02:00:34 PM PDT 24
Peak memory 210112 kb
Host smart-6220ee21-9d56-4457-a8ee-545882c1c51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168314670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2168314670
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3004499908
Short name T16
Test name
Test status
Simulation time 24037796 ps
CPU time 0.84 seconds
Started Jun 04 02:00:33 PM PDT 24
Finished Jun 04 02:00:36 PM PDT 24
Peak memory 205960 kb
Host smart-682acd22-0154-4ea1-8289-da9688834744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004499908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3004499908
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.4131855296
Short name T574
Test name
Test status
Simulation time 261795971 ps
CPU time 4.11 seconds
Started Jun 04 02:00:33 PM PDT 24
Finished Jun 04 02:00:38 PM PDT 24
Peak memory 209388 kb
Host smart-1917ecaf-0efd-4006-8bbf-2122e3ce5f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131855296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.4131855296
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4073919131
Short name T796
Test name
Test status
Simulation time 248885552 ps
CPU time 2.17 seconds
Started Jun 04 02:00:32 PM PDT 24
Finished Jun 04 02:00:36 PM PDT 24
Peak memory 214320 kb
Host smart-9fadb55b-8edc-44a6-827b-e831011490fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073919131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4073919131
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.823193041
Short name T287
Test name
Test status
Simulation time 687433524 ps
CPU time 3.19 seconds
Started Jun 04 02:00:31 PM PDT 24
Finished Jun 04 02:00:35 PM PDT 24
Peak memory 214228 kb
Host smart-040b6228-967d-4ccc-9fee-2632503e67ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823193041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.823193041
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.4075067863
Short name T579
Test name
Test status
Simulation time 148444257 ps
CPU time 3.18 seconds
Started Jun 04 02:00:35 PM PDT 24
Finished Jun 04 02:00:39 PM PDT 24
Peak memory 214228 kb
Host smart-97e07383-8cf9-402a-957d-ee6c385723ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075067863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.4075067863
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.647092395
Short name T625
Test name
Test status
Simulation time 422554993 ps
CPU time 7.16 seconds
Started Jun 04 02:00:33 PM PDT 24
Finished Jun 04 02:00:42 PM PDT 24
Peak memory 218460 kb
Host smart-4c29acc4-061e-475b-bb7a-d3fb7ad8b5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647092395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.647092395
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1650019146
Short name T376
Test name
Test status
Simulation time 42793286 ps
CPU time 2.18 seconds
Started Jun 04 02:00:34 PM PDT 24
Finished Jun 04 02:00:37 PM PDT 24
Peak memory 208028 kb
Host smart-b0a4d0f6-f696-44b8-9890-ac5ef2b9f71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650019146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1650019146
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.830666230
Short name T449
Test name
Test status
Simulation time 7129423797 ps
CPU time 72.34 seconds
Started Jun 04 02:00:34 PM PDT 24
Finished Jun 04 02:01:48 PM PDT 24
Peak memory 208300 kb
Host smart-37280579-bd9e-41cf-a1c3-494f5d0ad903
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830666230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.830666230
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2542885748
Short name T809
Test name
Test status
Simulation time 52200966 ps
CPU time 2.84 seconds
Started Jun 04 02:00:34 PM PDT 24
Finished Jun 04 02:00:38 PM PDT 24
Peak memory 208744 kb
Host smart-6c0c9564-f027-44e0-8b3b-2b85cf0548aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542885748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2542885748
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2887027420
Short name T802
Test name
Test status
Simulation time 597352024 ps
CPU time 4.66 seconds
Started Jun 04 02:00:37 PM PDT 24
Finished Jun 04 02:00:42 PM PDT 24
Peak memory 208612 kb
Host smart-f4c0bf81-d39b-4568-a104-951cdbf27cf1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887027420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2887027420
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2033336865
Short name T901
Test name
Test status
Simulation time 70923303 ps
CPU time 3.1 seconds
Started Jun 04 02:00:35 PM PDT 24
Finished Jun 04 02:00:39 PM PDT 24
Peak memory 213868 kb
Host smart-f949133c-83c2-46a0-8492-7f5adc85f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033336865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2033336865
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3060758804
Short name T436
Test name
Test status
Simulation time 435469727 ps
CPU time 9.61 seconds
Started Jun 04 02:00:34 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 207908 kb
Host smart-585b40fb-14ce-4907-b7a8-ff3f75c98d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060758804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3060758804
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1566317841
Short name T269
Test name
Test status
Simulation time 459442567 ps
CPU time 5.07 seconds
Started Jun 04 02:00:35 PM PDT 24
Finished Jun 04 02:00:41 PM PDT 24
Peak memory 207656 kb
Host smart-ddc9e701-6a3d-4265-b80e-2d5e60363cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566317841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1566317841
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.4007799346
Short name T542
Test name
Test status
Simulation time 25214570 ps
CPU time 1.57 seconds
Started Jun 04 02:00:37 PM PDT 24
Finished Jun 04 02:00:40 PM PDT 24
Peak memory 209612 kb
Host smart-f0f7e392-a47d-4cc9-bb10-5138ddea0f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007799346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.4007799346
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2829786642
Short name T466
Test name
Test status
Simulation time 49975976 ps
CPU time 0.77 seconds
Started Jun 04 02:00:33 PM PDT 24
Finished Jun 04 02:00:35 PM PDT 24
Peak memory 205936 kb
Host smart-00feaecc-77b4-499f-9694-fa2b66bfcf88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829786642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2829786642
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1272876777
Short name T380
Test name
Test status
Simulation time 350742707 ps
CPU time 6.25 seconds
Started Jun 04 02:00:34 PM PDT 24
Finished Jun 04 02:00:42 PM PDT 24
Peak memory 214420 kb
Host smart-a33919ee-8e4d-4094-bd0f-6c10db591599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272876777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1272876777
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2550955418
Short name T644
Test name
Test status
Simulation time 179559207 ps
CPU time 6.84 seconds
Started Jun 04 02:00:34 PM PDT 24
Finished Jun 04 02:00:42 PM PDT 24
Peak memory 214300 kb
Host smart-d017b747-5569-4a0f-ab86-3b97a74c30b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550955418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2550955418
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1231970643
Short name T348
Test name
Test status
Simulation time 56034497 ps
CPU time 2.51 seconds
Started Jun 04 02:00:35 PM PDT 24
Finished Jun 04 02:00:39 PM PDT 24
Peak memory 208324 kb
Host smart-3e358693-1cee-4d79-ae13-2b548a2d219f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231970643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1231970643
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2623044161
Short name T25
Test name
Test status
Simulation time 1544972351 ps
CPU time 17.6 seconds
Started Jun 04 02:00:34 PM PDT 24
Finished Jun 04 02:00:53 PM PDT 24
Peak memory 220412 kb
Host smart-6cf7e8f1-fe71-40ca-94ab-17844e89b25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623044161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2623044161
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.39064812
Short name T496
Test name
Test status
Simulation time 118442301 ps
CPU time 3.37 seconds
Started Jun 04 02:00:37 PM PDT 24
Finished Jun 04 02:00:42 PM PDT 24
Peak memory 214304 kb
Host smart-f2adff55-a4ee-4e02-9088-eb28bf0724af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39064812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.39064812
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1685912346
Short name T50
Test name
Test status
Simulation time 87752909 ps
CPU time 3.25 seconds
Started Jun 04 02:00:33 PM PDT 24
Finished Jun 04 02:00:38 PM PDT 24
Peak memory 222504 kb
Host smart-21f333c8-66bd-4067-badd-922fd5b91e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685912346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1685912346
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.4113979241
Short name T680
Test name
Test status
Simulation time 438231453 ps
CPU time 4.8 seconds
Started Jun 04 02:00:36 PM PDT 24
Finished Jun 04 02:00:41 PM PDT 24
Peak memory 209568 kb
Host smart-5f723907-bb3b-4d29-b6d5-95a284818547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113979241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.4113979241
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3120344548
Short name T657
Test name
Test status
Simulation time 113560842 ps
CPU time 2.39 seconds
Started Jun 04 02:00:37 PM PDT 24
Finished Jun 04 02:00:40 PM PDT 24
Peak memory 206864 kb
Host smart-6b703dd3-18af-4200-989b-7d4515b1f0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120344548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3120344548
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2589174564
Short name T584
Test name
Test status
Simulation time 669669627 ps
CPU time 21.8 seconds
Started Jun 04 02:00:33 PM PDT 24
Finished Jun 04 02:00:56 PM PDT 24
Peak memory 208860 kb
Host smart-ba1f6933-472a-462f-adf6-7e7028a2dd87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589174564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2589174564
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2527430293
Short name T316
Test name
Test status
Simulation time 352588563 ps
CPU time 4.5 seconds
Started Jun 04 02:00:34 PM PDT 24
Finished Jun 04 02:00:40 PM PDT 24
Peak memory 208592 kb
Host smart-422ef58f-d831-45fd-bb34-4fa82044b06a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527430293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2527430293
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1368949227
Short name T684
Test name
Test status
Simulation time 455646865 ps
CPU time 5.18 seconds
Started Jun 04 02:00:32 PM PDT 24
Finished Jun 04 02:00:38 PM PDT 24
Peak memory 208412 kb
Host smart-8491e936-f1af-4674-af36-20f0a013b608
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368949227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1368949227
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.95043091
Short name T398
Test name
Test status
Simulation time 31453395 ps
CPU time 2.05 seconds
Started Jun 04 02:00:33 PM PDT 24
Finished Jun 04 02:00:36 PM PDT 24
Peak memory 214384 kb
Host smart-d117865a-a44c-4106-b9eb-ad7275493e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95043091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.95043091
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3385036085
Short name T539
Test name
Test status
Simulation time 397491143 ps
CPU time 2.74 seconds
Started Jun 04 02:00:33 PM PDT 24
Finished Jun 04 02:00:37 PM PDT 24
Peak memory 206876 kb
Host smart-91a07f17-6d1c-4605-a57a-05783d51f6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385036085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3385036085
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2692017288
Short name T851
Test name
Test status
Simulation time 62092237 ps
CPU time 2.32 seconds
Started Jun 04 02:00:35 PM PDT 24
Finished Jun 04 02:00:39 PM PDT 24
Peak memory 206816 kb
Host smart-33d9ac60-0911-4f3e-811e-7a8c4f85dd66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692017288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2692017288
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2398314055
Short name T532
Test name
Test status
Simulation time 367119191 ps
CPU time 5.12 seconds
Started Jun 04 02:00:34 PM PDT 24
Finished Jun 04 02:00:40 PM PDT 24
Peak memory 214348 kb
Host smart-9d930224-6edd-4cdc-88f5-57fc98cf3eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398314055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2398314055
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3035099763
Short name T62
Test name
Test status
Simulation time 248239668 ps
CPU time 1.95 seconds
Started Jun 04 02:00:32 PM PDT 24
Finished Jun 04 02:00:35 PM PDT 24
Peak memory 210356 kb
Host smart-9b8afee1-799b-4540-b86a-55e0b9b79dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035099763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3035099763
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1107325537
Short name T446
Test name
Test status
Simulation time 14883023 ps
CPU time 0.72 seconds
Started Jun 04 02:00:41 PM PDT 24
Finished Jun 04 02:00:44 PM PDT 24
Peak memory 205936 kb
Host smart-8a9b5174-d1d5-45d3-9f6a-1d0882ffe029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107325537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1107325537
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3713898825
Short name T232
Test name
Test status
Simulation time 304268729 ps
CPU time 6.76 seconds
Started Jun 04 02:00:41 PM PDT 24
Finished Jun 04 02:00:50 PM PDT 24
Peak memory 209824 kb
Host smart-ed1a6273-46e6-4db8-bbc2-af14ce704b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713898825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3713898825
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.773920775
Short name T867
Test name
Test status
Simulation time 110449324 ps
CPU time 2.63 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:44 PM PDT 24
Peak memory 214396 kb
Host smart-8fa5edea-79f3-44a5-b86b-87a5df428939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773920775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.773920775
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.783770640
Short name T99
Test name
Test status
Simulation time 3796819525 ps
CPU time 6.4 seconds
Started Jun 04 02:00:44 PM PDT 24
Finished Jun 04 02:00:51 PM PDT 24
Peak memory 211504 kb
Host smart-e674ecd9-b196-4020-98f9-b35075bcaf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783770640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.783770640
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.358204315
Short name T202
Test name
Test status
Simulation time 49914687 ps
CPU time 2.05 seconds
Started Jun 04 02:00:42 PM PDT 24
Finished Jun 04 02:00:46 PM PDT 24
Peak memory 214256 kb
Host smart-9fde812a-ece4-4e60-b600-2ed30ab20cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358204315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.358204315
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.4208846033
Short name T769
Test name
Test status
Simulation time 62349526 ps
CPU time 2.57 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 206076 kb
Host smart-e4abcb4f-5fbd-4f9a-98e6-50e780d66deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208846033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.4208846033
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3613683596
Short name T250
Test name
Test status
Simulation time 79726696 ps
CPU time 4.04 seconds
Started Jun 04 02:00:39 PM PDT 24
Finished Jun 04 02:00:43 PM PDT 24
Peak memory 209524 kb
Host smart-b1d1db8c-e20e-4cda-ae40-dd54644dc88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613683596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3613683596
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1798794962
Short name T46
Test name
Test status
Simulation time 26291974 ps
CPU time 1.93 seconds
Started Jun 04 02:00:39 PM PDT 24
Finished Jun 04 02:00:42 PM PDT 24
Peak memory 208488 kb
Host smart-dfe2aac6-e151-40d1-b4af-5917d6759fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798794962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1798794962
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.342432678
Short name T682
Test name
Test status
Simulation time 39773620 ps
CPU time 1.68 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:43 PM PDT 24
Peak memory 206836 kb
Host smart-c894edb2-67c6-41ee-94ad-8326d3ce0fbb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342432678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.342432678
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.812933776
Short name T459
Test name
Test status
Simulation time 206827928 ps
CPU time 2.3 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:43 PM PDT 24
Peak memory 207020 kb
Host smart-d7cab784-2356-4794-a0a4-c69d93dbf69b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812933776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.812933776
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.4107189730
Short name T799
Test name
Test status
Simulation time 40562951 ps
CPU time 1.82 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:44 PM PDT 24
Peak memory 206852 kb
Host smart-64db9a53-afa3-48dd-abd1-e0a7d43e0ca0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107189730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4107189730
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2371651063
Short name T849
Test name
Test status
Simulation time 26320586 ps
CPU time 1.7 seconds
Started Jun 04 02:00:39 PM PDT 24
Finished Jun 04 02:00:42 PM PDT 24
Peak memory 215876 kb
Host smart-eaeb4062-e34b-443a-a69a-75d95f3283ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371651063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2371651063
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1731773077
Short name T401
Test name
Test status
Simulation time 215005433 ps
CPU time 2.8 seconds
Started Jun 04 02:00:42 PM PDT 24
Finished Jun 04 02:00:47 PM PDT 24
Peak memory 208668 kb
Host smart-cef59049-e4dd-45fc-8d20-5c8af6925ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731773077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1731773077
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.862892468
Short name T716
Test name
Test status
Simulation time 968497308 ps
CPU time 32.13 seconds
Started Jun 04 02:00:43 PM PDT 24
Finished Jun 04 02:01:16 PM PDT 24
Peak memory 217076 kb
Host smart-c18c099b-1f3f-4b3b-ab1e-4be9b1a92ea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862892468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.862892468
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.972458868
Short name T616
Test name
Test status
Simulation time 257209715 ps
CPU time 5.97 seconds
Started Jun 04 02:00:42 PM PDT 24
Finished Jun 04 02:00:50 PM PDT 24
Peak memory 209216 kb
Host smart-dff834fe-8154-4aba-b286-68060cf4d3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972458868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.972458868
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1307073111
Short name T615
Test name
Test status
Simulation time 26865599 ps
CPU time 1.09 seconds
Started Jun 04 01:57:57 PM PDT 24
Finished Jun 04 01:57:59 PM PDT 24
Peak memory 206096 kb
Host smart-75bd240b-7367-4499-b2c9-f1e96fcd3812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307073111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1307073111
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1023120040
Short name T252
Test name
Test status
Simulation time 165331966 ps
CPU time 3.33 seconds
Started Jun 04 01:57:48 PM PDT 24
Finished Jun 04 01:57:52 PM PDT 24
Peak memory 214384 kb
Host smart-539fca66-ea97-44cd-8001-4b26a4547a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023120040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1023120040
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2619212073
Short name T540
Test name
Test status
Simulation time 91500835 ps
CPU time 3.34 seconds
Started Jun 04 01:57:58 PM PDT 24
Finished Jun 04 01:58:02 PM PDT 24
Peak memory 220932 kb
Host smart-3be15c26-4f1b-4c29-bbef-33e5e3c64a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619212073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2619212073
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3502584495
Short name T823
Test name
Test status
Simulation time 84898436 ps
CPU time 1.87 seconds
Started Jun 04 01:57:54 PM PDT 24
Finished Jun 04 01:57:57 PM PDT 24
Peak memory 207604 kb
Host smart-f6909722-c8f2-4eef-b5fa-99154fca1ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502584495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3502584495
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1170832009
Short name T741
Test name
Test status
Simulation time 912442465 ps
CPU time 6.14 seconds
Started Jun 04 01:57:57 PM PDT 24
Finished Jun 04 01:58:04 PM PDT 24
Peak memory 209672 kb
Host smart-136380d4-8ab3-4d8d-ab1f-3892114fa5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170832009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1170832009
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3009052947
Short name T356
Test name
Test status
Simulation time 73113189 ps
CPU time 3.73 seconds
Started Jun 04 01:57:55 PM PDT 24
Finished Jun 04 01:57:59 PM PDT 24
Peak memory 214900 kb
Host smart-a9e87cd3-a78d-4c19-bf0b-bb7a64ec2137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009052947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3009052947
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2501468203
Short name T404
Test name
Test status
Simulation time 52151826 ps
CPU time 3.04 seconds
Started Jun 04 01:57:55 PM PDT 24
Finished Jun 04 01:57:58 PM PDT 24
Peak memory 209980 kb
Host smart-526682c7-461b-4785-b4e7-b208d568de2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501468203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2501468203
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2668302290
Short name T334
Test name
Test status
Simulation time 539028865 ps
CPU time 2.84 seconds
Started Jun 04 01:57:48 PM PDT 24
Finished Jun 04 01:57:52 PM PDT 24
Peak memory 218544 kb
Host smart-51b00140-853e-48f6-be01-e472ff53df14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668302290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2668302290
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2886882235
Short name T45
Test name
Test status
Simulation time 1978679089 ps
CPU time 10.25 seconds
Started Jun 04 01:57:56 PM PDT 24
Finished Jun 04 01:58:07 PM PDT 24
Peak memory 238168 kb
Host smart-6df8e8a5-b098-4a43-8312-ed850dfa35d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886882235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2886882235
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1428951833
Short name T492
Test name
Test status
Simulation time 147081904 ps
CPU time 3.45 seconds
Started Jun 04 01:57:46 PM PDT 24
Finished Jun 04 01:57:51 PM PDT 24
Peak memory 208392 kb
Host smart-b85362c0-7c97-4571-8135-2367c6b3dd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428951833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1428951833
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2547655426
Short name T442
Test name
Test status
Simulation time 19592703 ps
CPU time 1.7 seconds
Started Jun 04 01:57:50 PM PDT 24
Finished Jun 04 01:57:53 PM PDT 24
Peak memory 206608 kb
Host smart-6a953d29-6228-4507-85f9-7d9b2f81c421
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547655426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2547655426
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.546011191
Short name T90
Test name
Test status
Simulation time 114441874 ps
CPU time 2.41 seconds
Started Jun 04 01:57:54 PM PDT 24
Finished Jun 04 01:57:57 PM PDT 24
Peak memory 208964 kb
Host smart-9fb63836-64c4-4955-9b56-36d5c52b71f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546011191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.546011191
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3456914134
Short name T753
Test name
Test status
Simulation time 237278307 ps
CPU time 2.99 seconds
Started Jun 04 01:57:48 PM PDT 24
Finished Jun 04 01:57:52 PM PDT 24
Peak memory 206892 kb
Host smart-75e640c9-3e3d-4dc4-bd71-a04b3352edfa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456914134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3456914134
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1077284001
Short name T665
Test name
Test status
Simulation time 342467951 ps
CPU time 5.53 seconds
Started Jun 04 01:57:57 PM PDT 24
Finished Jun 04 01:58:04 PM PDT 24
Peak memory 215836 kb
Host smart-4052d5b6-bea7-496e-b12b-1b2457e745ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077284001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1077284001
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.421351606
Short name T490
Test name
Test status
Simulation time 46304267 ps
CPU time 2.3 seconds
Started Jun 04 01:57:54 PM PDT 24
Finished Jun 04 01:57:57 PM PDT 24
Peak memory 206940 kb
Host smart-8ec0799c-aa80-4f95-bda8-729f1720ba13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421351606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.421351606
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3461725966
Short name T900
Test name
Test status
Simulation time 197598124 ps
CPU time 3.39 seconds
Started Jun 04 01:57:57 PM PDT 24
Finished Jun 04 01:58:01 PM PDT 24
Peak memory 210544 kb
Host smart-c7072a85-98ed-49f2-896d-4f819e013c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461725966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3461725966
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3952976886
Short name T830
Test name
Test status
Simulation time 231861851 ps
CPU time 1.46 seconds
Started Jun 04 01:57:56 PM PDT 24
Finished Jun 04 01:57:58 PM PDT 24
Peak memory 208468 kb
Host smart-1315ad46-11de-4a2d-9983-615d91d6dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952976886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3952976886
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.30954888
Short name T454
Test name
Test status
Simulation time 15653563 ps
CPU time 1.03 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:48 PM PDT 24
Peak memory 206088 kb
Host smart-ad3fc4b0-1276-4f49-810b-87f242a8ef88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30954888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.30954888
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2152868576
Short name T882
Test name
Test status
Simulation time 118608566 ps
CPU time 6.2 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:48 PM PDT 24
Peak memory 214344 kb
Host smart-b38ffeaa-8563-415d-8803-71319388ad08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152868576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2152868576
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1931506641
Short name T718
Test name
Test status
Simulation time 82544010 ps
CPU time 1.54 seconds
Started Jun 04 02:00:42 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 214264 kb
Host smart-dbe0dc83-50c5-4434-9a8d-a93545814a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931506641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1931506641
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2244697170
Short name T822
Test name
Test status
Simulation time 169322852 ps
CPU time 2.34 seconds
Started Jun 04 02:00:43 PM PDT 24
Finished Jun 04 02:00:47 PM PDT 24
Peak memory 209644 kb
Host smart-9eedf801-930e-4657-880c-dd6407fb3b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244697170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2244697170
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.588556794
Short name T547
Test name
Test status
Simulation time 91690178 ps
CPU time 3.16 seconds
Started Jun 04 02:00:44 PM PDT 24
Finished Jun 04 02:00:49 PM PDT 24
Peak memory 214376 kb
Host smart-d8bb53de-d1fa-4252-9736-59d9a2229056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588556794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.588556794
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3258432391
Short name T8
Test name
Test status
Simulation time 304800359 ps
CPU time 3.83 seconds
Started Jun 04 02:00:44 PM PDT 24
Finished Jun 04 02:00:49 PM PDT 24
Peak memory 210700 kb
Host smart-da14a4a8-beb2-4811-ae84-58469b516ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258432391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3258432391
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2807843210
Short name T475
Test name
Test status
Simulation time 92740212 ps
CPU time 4.39 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:46 PM PDT 24
Peak memory 207428 kb
Host smart-5573f15a-46ca-42d8-8243-3c6a9dea16db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807843210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2807843210
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3702061717
Short name T874
Test name
Test status
Simulation time 85749165 ps
CPU time 3.74 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 208720 kb
Host smart-28eb5522-463c-46f2-8d72-f0277f56770f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702061717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3702061717
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1332557878
Short name T453
Test name
Test status
Simulation time 1180868322 ps
CPU time 6.85 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:49 PM PDT 24
Peak memory 208760 kb
Host smart-758d3ba8-da18-47c3-ae3e-44af04376a6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332557878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1332557878
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1739278812
Short name T97
Test name
Test status
Simulation time 87762498 ps
CPU time 3.06 seconds
Started Jun 04 02:00:44 PM PDT 24
Finished Jun 04 02:00:48 PM PDT 24
Peak memory 206936 kb
Host smart-e0403bad-e07d-4af6-a79f-750b9981b824
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739278812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1739278812
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.358151237
Short name T850
Test name
Test status
Simulation time 69135832 ps
CPU time 3.12 seconds
Started Jun 04 02:00:41 PM PDT 24
Finished Jun 04 02:00:46 PM PDT 24
Peak memory 207016 kb
Host smart-fda64351-2a51-4195-ab52-ac8fd3b6522d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358151237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.358151237
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2416392770
Short name T783
Test name
Test status
Simulation time 96017277 ps
CPU time 4.15 seconds
Started Jun 04 02:00:43 PM PDT 24
Finished Jun 04 02:00:49 PM PDT 24
Peak memory 209828 kb
Host smart-258b7e33-4109-4ff2-8686-cc2e676a7cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416392770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2416392770
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2797183590
Short name T637
Test name
Test status
Simulation time 84703129 ps
CPU time 1.77 seconds
Started Jun 04 02:00:41 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 207324 kb
Host smart-fbbe7ecd-4297-42d7-a008-3b772236d233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797183590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2797183590
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.559496026
Short name T674
Test name
Test status
Simulation time 1097333207 ps
CPU time 10.89 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:53 PM PDT 24
Peak memory 214372 kb
Host smart-2d82bd3a-dd04-47d4-a6ad-777c69b28e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559496026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.559496026
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.629569407
Short name T804
Test name
Test status
Simulation time 1431225012 ps
CPU time 4.19 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:46 PM PDT 24
Peak memory 211012 kb
Host smart-4523e3c3-f8ae-4f54-8e86-36650a120e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629569407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.629569407
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2587009013
Short name T544
Test name
Test status
Simulation time 59188290 ps
CPU time 0.92 seconds
Started Jun 04 02:00:54 PM PDT 24
Finished Jun 04 02:00:55 PM PDT 24
Peak memory 206140 kb
Host smart-fc2ca408-18aa-42fd-9bc6-f7d67c305db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587009013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2587009013
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2135710393
Short name T424
Test name
Test status
Simulation time 56326443 ps
CPU time 3.6 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:51 PM PDT 24
Peak memory 222488 kb
Host smart-f2600e1d-1965-431e-a2f5-14f117bce8cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135710393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2135710393
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2566918228
Short name T439
Test name
Test status
Simulation time 27325957 ps
CPU time 1.99 seconds
Started Jun 04 02:00:42 PM PDT 24
Finished Jun 04 02:00:46 PM PDT 24
Peak memory 207812 kb
Host smart-bfd0a190-7447-470b-a065-fec54e27fc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566918228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2566918228
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2784507911
Short name T692
Test name
Test status
Simulation time 178052470 ps
CPU time 2.15 seconds
Started Jun 04 02:00:48 PM PDT 24
Finished Jun 04 02:00:51 PM PDT 24
Peak memory 214348 kb
Host smart-7d61f97e-7573-47be-b67a-cd5870909698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784507911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2784507911
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.45510272
Short name T609
Test name
Test status
Simulation time 274812293 ps
CPU time 5.15 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:52 PM PDT 24
Peak memory 222372 kb
Host smart-3f24c3c4-4f22-47d7-9e99-6aebabbe768f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45510272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.45510272
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3862397028
Short name T724
Test name
Test status
Simulation time 24071914 ps
CPU time 1.16 seconds
Started Jun 04 02:00:43 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 206164 kb
Host smart-bad0cf00-f3a4-4d9a-9bca-f5176e4411e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862397028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3862397028
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.144764816
Short name T545
Test name
Test status
Simulation time 375822384 ps
CPU time 4.31 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:51 PM PDT 24
Peak memory 207172 kb
Host smart-b962c85f-a4c2-499f-8ac7-fd0a7d317383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144764816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.144764816
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3115391194
Short name T378
Test name
Test status
Simulation time 1094423707 ps
CPU time 4.82 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:51 PM PDT 24
Peak memory 207148 kb
Host smart-254698f0-6553-4201-9ab0-53a187c4f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115391194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3115391194
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1987841873
Short name T811
Test name
Test status
Simulation time 107631446 ps
CPU time 1.79 seconds
Started Jun 04 02:00:42 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 206900 kb
Host smart-6bd404e1-10c8-4e9c-8f1c-078f1ce2b75d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987841873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1987841873
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3520291457
Short name T455
Test name
Test status
Simulation time 1510777043 ps
CPU time 4.14 seconds
Started Jun 04 02:00:40 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 206984 kb
Host smart-570e9f8a-db66-494f-b93f-e488c6c5977d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520291457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3520291457
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3671442383
Short name T861
Test name
Test status
Simulation time 51601180 ps
CPU time 2.87 seconds
Started Jun 04 02:00:41 PM PDT 24
Finished Jun 04 02:00:45 PM PDT 24
Peak memory 208892 kb
Host smart-39df8813-d939-491d-882a-cf08b6d11a09
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671442383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3671442383
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.24012035
Short name T587
Test name
Test status
Simulation time 128887626 ps
CPU time 4.38 seconds
Started Jun 04 02:00:49 PM PDT 24
Finished Jun 04 02:00:54 PM PDT 24
Peak memory 214400 kb
Host smart-8002bdf1-2255-471c-9c14-a2bdb93e6b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24012035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.24012035
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2730373767
Short name T511
Test name
Test status
Simulation time 1043510099 ps
CPU time 9.99 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:57 PM PDT 24
Peak memory 208380 kb
Host smart-e5401c73-6a38-4a59-bd99-5c08baece597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730373767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2730373767
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2186162889
Short name T86
Test name
Test status
Simulation time 50980345358 ps
CPU time 436.05 seconds
Started Jun 04 02:00:47 PM PDT 24
Finished Jun 04 02:08:04 PM PDT 24
Peak memory 218476 kb
Host smart-998012b6-9117-435a-9885-adbb8622d1cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186162889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2186162889
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1826209265
Short name T143
Test name
Test status
Simulation time 791916730 ps
CPU time 11.34 seconds
Started Jun 04 02:00:47 PM PDT 24
Finished Jun 04 02:00:59 PM PDT 24
Peak memory 222552 kb
Host smart-2f299e3f-cced-468d-bf9b-347b26e3f72d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826209265 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1826209265
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.4179479703
Short name T472
Test name
Test status
Simulation time 1354081816 ps
CPU time 8.7 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:56 PM PDT 24
Peak memory 208076 kb
Host smart-7ad38958-19f2-47c9-92ce-953f42bab733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179479703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.4179479703
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.269119722
Short name T44
Test name
Test status
Simulation time 75458357 ps
CPU time 1.89 seconds
Started Jun 04 02:00:50 PM PDT 24
Finished Jun 04 02:00:53 PM PDT 24
Peak memory 210072 kb
Host smart-3515816c-845c-47d8-8a6a-5849ded51342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269119722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.269119722
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3258363358
Short name T898
Test name
Test status
Simulation time 13019453 ps
CPU time 0.73 seconds
Started Jun 04 02:00:53 PM PDT 24
Finished Jun 04 02:00:55 PM PDT 24
Peak memory 205964 kb
Host smart-083c2aba-ca33-4a6e-8980-265c4e4e8748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258363358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3258363358
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2536830493
Short name T379
Test name
Test status
Simulation time 8748480308 ps
CPU time 113.97 seconds
Started Jun 04 02:00:49 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 215336 kb
Host smart-6632f1ea-5169-41d2-ba27-0027f18bbba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2536830493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2536830493
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1253056887
Short name T570
Test name
Test status
Simulation time 210538641 ps
CPU time 6.36 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:54 PM PDT 24
Peak memory 209416 kb
Host smart-bcd4cfc4-0a92-4066-9c36-a493a2d61143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253056887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1253056887
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.317888965
Short name T291
Test name
Test status
Simulation time 110435285 ps
CPU time 2.82 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:49 PM PDT 24
Peak memory 210128 kb
Host smart-aacc204d-758a-4d8b-bd96-9b1d5b981aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317888965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.317888965
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1581157825
Short name T750
Test name
Test status
Simulation time 76933856 ps
CPU time 2.86 seconds
Started Jun 04 02:00:47 PM PDT 24
Finished Jun 04 02:00:51 PM PDT 24
Peak memory 214252 kb
Host smart-ac1c2a8a-f464-46d1-9a95-9ea420d4cc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581157825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1581157825
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2447936763
Short name T246
Test name
Test status
Simulation time 202586649 ps
CPU time 2.52 seconds
Started Jun 04 02:00:50 PM PDT 24
Finished Jun 04 02:00:53 PM PDT 24
Peak memory 208776 kb
Host smart-1b1597d7-46b7-4750-8b1b-13e76dd972b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447936763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2447936763
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1028633769
Short name T266
Test name
Test status
Simulation time 33269293 ps
CPU time 2.38 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:50 PM PDT 24
Peak memory 208268 kb
Host smart-e0373e7d-883f-4638-916a-b352495bf263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028633769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1028633769
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3043261726
Short name T812
Test name
Test status
Simulation time 962350210 ps
CPU time 3.15 seconds
Started Jun 04 02:00:48 PM PDT 24
Finished Jun 04 02:00:52 PM PDT 24
Peak memory 208632 kb
Host smart-c0cdb616-a61c-4e9b-9b06-db4294107658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043261726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3043261726
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3804989564
Short name T719
Test name
Test status
Simulation time 47090770 ps
CPU time 2.13 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:49 PM PDT 24
Peak memory 208864 kb
Host smart-3ade6191-6ccb-48f1-babd-83dc7f3325a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804989564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3804989564
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2483982492
Short name T482
Test name
Test status
Simulation time 337078469 ps
CPU time 3.4 seconds
Started Jun 04 02:00:47 PM PDT 24
Finished Jun 04 02:00:51 PM PDT 24
Peak memory 208588 kb
Host smart-d1ec410e-7bd2-48d4-b0ef-d5eb4fe99d11
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483982492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2483982492
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2572713051
Short name T859
Test name
Test status
Simulation time 98212096 ps
CPU time 2.66 seconds
Started Jun 04 02:00:44 PM PDT 24
Finished Jun 04 02:00:48 PM PDT 24
Peak memory 206972 kb
Host smart-d3ee596b-9386-4fb0-9250-bd141cfcf9e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572713051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2572713051
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3211975204
Short name T337
Test name
Test status
Simulation time 189969180 ps
CPU time 5.62 seconds
Started Jun 04 02:00:51 PM PDT 24
Finished Jun 04 02:00:58 PM PDT 24
Peak memory 208888 kb
Host smart-9c150fa4-20d7-4f03-ac4c-e3d87340d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211975204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3211975204
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3682125916
Short name T117
Test name
Test status
Simulation time 156315745 ps
CPU time 4.07 seconds
Started Jun 04 02:00:47 PM PDT 24
Finished Jun 04 02:00:52 PM PDT 24
Peak memory 206804 kb
Host smart-97028a90-ce64-4442-be09-7269fa1e0395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682125916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3682125916
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3196700270
Short name T78
Test name
Test status
Simulation time 1419419934 ps
CPU time 17.76 seconds
Started Jun 04 02:00:49 PM PDT 24
Finished Jun 04 02:01:08 PM PDT 24
Peak memory 222532 kb
Host smart-ba4c0f50-be64-4ef2-bdfe-eb6ab7a842b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196700270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3196700270
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1402409457
Short name T797
Test name
Test status
Simulation time 278876583 ps
CPU time 8.85 seconds
Started Jun 04 02:00:47 PM PDT 24
Finished Jun 04 02:00:56 PM PDT 24
Peak memory 220356 kb
Host smart-a062b1bf-aba0-4ab2-a8a0-47cf356fb365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402409457 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1402409457
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1567105728
Short name T298
Test name
Test status
Simulation time 635493696 ps
CPU time 5.79 seconds
Started Jun 04 02:00:48 PM PDT 24
Finished Jun 04 02:00:55 PM PDT 24
Peak memory 222456 kb
Host smart-78f5d31d-c9c7-4a27-afac-0a0228a36629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567105728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1567105728
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.744329862
Short name T711
Test name
Test status
Simulation time 117596950 ps
CPU time 2.54 seconds
Started Jun 04 02:00:49 PM PDT 24
Finished Jun 04 02:00:53 PM PDT 24
Peak memory 210320 kb
Host smart-ddc7287c-8948-408f-9602-4d3aaba33075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744329862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.744329862
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2012605563
Short name T450
Test name
Test status
Simulation time 157362781 ps
CPU time 0.74 seconds
Started Jun 04 02:00:57 PM PDT 24
Finished Jun 04 02:01:00 PM PDT 24
Peak memory 205856 kb
Host smart-bc62ab19-d3eb-42bd-aa8e-1e26264edfa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012605563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2012605563
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3460563141
Short name T32
Test name
Test status
Simulation time 73692776 ps
CPU time 2.17 seconds
Started Jun 04 02:01:00 PM PDT 24
Finished Jun 04 02:01:03 PM PDT 24
Peak memory 208788 kb
Host smart-ed33cf26-18e6-4eaa-b79d-2ec7330e3433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460563141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3460563141
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1183575536
Short name T535
Test name
Test status
Simulation time 95959208 ps
CPU time 2.72 seconds
Started Jun 04 02:00:51 PM PDT 24
Finished Jun 04 02:00:55 PM PDT 24
Peak memory 209988 kb
Host smart-8dbb62db-be7e-4d5d-8ead-fdef2589aa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183575536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1183575536
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3391858685
Short name T549
Test name
Test status
Simulation time 426388229 ps
CPU time 4.04 seconds
Started Jun 04 02:00:49 PM PDT 24
Finished Jun 04 02:00:55 PM PDT 24
Peak memory 214340 kb
Host smart-61d9b888-e54c-4f22-9828-25de8e3c32f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391858685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3391858685
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2705548365
Short name T219
Test name
Test status
Simulation time 85354840 ps
CPU time 2.46 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:02 PM PDT 24
Peak memory 214260 kb
Host smart-92670cde-09b9-4520-886d-748a7eb99eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705548365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2705548365
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3618594838
Short name T227
Test name
Test status
Simulation time 362830795 ps
CPU time 3.57 seconds
Started Jun 04 02:00:50 PM PDT 24
Finished Jun 04 02:00:55 PM PDT 24
Peak memory 220324 kb
Host smart-710d2926-6d1a-4f5e-9bb6-b3021a354fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618594838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3618594838
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1395119864
Short name T668
Test name
Test status
Simulation time 114199595 ps
CPU time 4.62 seconds
Started Jun 04 02:00:52 PM PDT 24
Finished Jun 04 02:00:57 PM PDT 24
Peak memory 214328 kb
Host smart-22272816-b1c0-4a9b-9210-d7242b4e6288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395119864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1395119864
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2859955944
Short name T656
Test name
Test status
Simulation time 276704137 ps
CPU time 3.62 seconds
Started Jun 04 02:00:49 PM PDT 24
Finished Jun 04 02:00:54 PM PDT 24
Peak memory 206752 kb
Host smart-488f4242-801c-43e9-a29b-341ef7af6f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859955944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2859955944
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1625522061
Short name T594
Test name
Test status
Simulation time 910568500 ps
CPU time 12.45 seconds
Started Jun 04 02:00:46 PM PDT 24
Finished Jun 04 02:00:59 PM PDT 24
Peak memory 208184 kb
Host smart-c6efbdb9-5b74-4f3b-b181-ca337648f929
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625522061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1625522061
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.758468583
Short name T829
Test name
Test status
Simulation time 1104486796 ps
CPU time 7.73 seconds
Started Jun 04 02:00:47 PM PDT 24
Finished Jun 04 02:00:56 PM PDT 24
Peak memory 208780 kb
Host smart-ad207916-0821-4ec1-a7f5-6f41df5b9d3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758468583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.758468583
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1402747769
Short name T736
Test name
Test status
Simulation time 103897936 ps
CPU time 4.77 seconds
Started Jun 04 02:00:51 PM PDT 24
Finished Jun 04 02:00:57 PM PDT 24
Peak memory 208624 kb
Host smart-ebbdf3e6-e40d-44b6-b362-f0c7f0b2d487
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402747769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1402747769
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2893070387
Short name T363
Test name
Test status
Simulation time 113073649 ps
CPU time 3.25 seconds
Started Jun 04 02:00:55 PM PDT 24
Finished Jun 04 02:00:59 PM PDT 24
Peak memory 208052 kb
Host smart-222d3ba5-3b71-4451-b692-e6f655928ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893070387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2893070387
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3973072596
Short name T819
Test name
Test status
Simulation time 381069223 ps
CPU time 4.42 seconds
Started Jun 04 02:00:49 PM PDT 24
Finished Jun 04 02:00:54 PM PDT 24
Peak memory 208144 kb
Host smart-0d140258-cea2-4cf9-b064-8a1f23073491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973072596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3973072596
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.581847727
Short name T208
Test name
Test status
Simulation time 2099320421 ps
CPU time 17.8 seconds
Started Jun 04 02:00:54 PM PDT 24
Finished Jun 04 02:01:13 PM PDT 24
Peak memory 216876 kb
Host smart-dcd9e2e0-a25b-475f-946a-37371be78fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581847727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.581847727
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1356297507
Short name T217
Test name
Test status
Simulation time 376838387 ps
CPU time 5.72 seconds
Started Jun 04 02:00:52 PM PDT 24
Finished Jun 04 02:00:59 PM PDT 24
Peak memory 208112 kb
Host smart-45c3bf1b-114c-4921-ae6c-e2cf9b353d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356297507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1356297507
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1710179729
Short name T552
Test name
Test status
Simulation time 189978493 ps
CPU time 2.23 seconds
Started Jun 04 02:00:56 PM PDT 24
Finished Jun 04 02:00:59 PM PDT 24
Peak memory 210816 kb
Host smart-5fb56459-c1dc-4576-824e-15a2cdb19d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710179729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1710179729
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.220309932
Short name T524
Test name
Test status
Simulation time 47100393 ps
CPU time 0.81 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:00 PM PDT 24
Peak memory 205920 kb
Host smart-b88e0da5-c63e-403a-96d8-7b5e0b4ae407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220309932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.220309932
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2757766647
Short name T152
Test name
Test status
Simulation time 294016055 ps
CPU time 5.01 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:05 PM PDT 24
Peak memory 214456 kb
Host smart-708f6fd7-b5e4-485a-91a0-e8908ad445d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757766647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2757766647
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1045211387
Short name T403
Test name
Test status
Simulation time 193366620 ps
CPU time 2.76 seconds
Started Jun 04 02:00:57 PM PDT 24
Finished Jun 04 02:01:01 PM PDT 24
Peak memory 207808 kb
Host smart-11e15897-9e80-41fc-be20-407fe128c43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045211387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1045211387
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2139009000
Short name T744
Test name
Test status
Simulation time 467165430 ps
CPU time 2 seconds
Started Jun 04 02:00:53 PM PDT 24
Finished Jun 04 02:00:56 PM PDT 24
Peak memory 207768 kb
Host smart-e232cde1-cb57-489b-b6ac-967209535874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139009000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2139009000
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3899903063
Short name T386
Test name
Test status
Simulation time 121652422 ps
CPU time 2.24 seconds
Started Jun 04 02:00:57 PM PDT 24
Finished Jun 04 02:01:01 PM PDT 24
Peak memory 214344 kb
Host smart-0b8ddf68-f9ce-4b0f-8c01-854d9d83c494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899903063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3899903063
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.893804293
Short name T865
Test name
Test status
Simulation time 601541802 ps
CPU time 9.5 seconds
Started Jun 04 02:00:55 PM PDT 24
Finished Jun 04 02:01:05 PM PDT 24
Peak memory 214256 kb
Host smart-a46d6de6-18da-47de-8274-8f80ab974c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893804293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.893804293
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.270154022
Short name T241
Test name
Test status
Simulation time 179053711 ps
CPU time 2.56 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:02 PM PDT 24
Peak memory 208272 kb
Host smart-2e190ce4-8179-4a92-9229-106e3b63f060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270154022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.270154022
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3978014047
Short name T201
Test name
Test status
Simulation time 177869750 ps
CPU time 7.21 seconds
Started Jun 04 02:00:57 PM PDT 24
Finished Jun 04 02:01:05 PM PDT 24
Peak memory 214292 kb
Host smart-a71ccccc-d812-418a-8f2c-5f3512c2c6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978014047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3978014047
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1791950274
Short name T364
Test name
Test status
Simulation time 150203995 ps
CPU time 4.54 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:04 PM PDT 24
Peak memory 206780 kb
Host smart-1db28857-db69-4a6f-b3c7-074615819ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791950274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1791950274
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3557571546
Short name T785
Test name
Test status
Simulation time 847115722 ps
CPU time 5.8 seconds
Started Jun 04 02:00:59 PM PDT 24
Finished Jun 04 02:01:06 PM PDT 24
Peak memory 208656 kb
Host smart-6dcb7d2f-95a6-47ed-92c5-2d91b1f5ca03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557571546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3557571546
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1915032934
Short name T856
Test name
Test status
Simulation time 33035327 ps
CPU time 2.29 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:08 PM PDT 24
Peak memory 206768 kb
Host smart-1aa89d60-d669-4173-a055-bf7f5aacee7f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915032934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1915032934
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.75020801
Short name T484
Test name
Test status
Simulation time 25604926 ps
CPU time 2.02 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:07 PM PDT 24
Peak memory 208472 kb
Host smart-d1d922a8-1206-4930-82bc-1ec060d108a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75020801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.75020801
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.218451328
Short name T211
Test name
Test status
Simulation time 527773146 ps
CPU time 11.63 seconds
Started Jun 04 02:00:57 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 218304 kb
Host smart-d8013545-8927-49e1-8381-3358118d28a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218451328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.218451328
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.51849436
Short name T599
Test name
Test status
Simulation time 60642425 ps
CPU time 3 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:03 PM PDT 24
Peak memory 208644 kb
Host smart-c75fd449-9ce9-4d07-b596-e8be0d1feee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51849436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.51849436
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.94525377
Short name T639
Test name
Test status
Simulation time 2698840935 ps
CPU time 37.18 seconds
Started Jun 04 02:00:57 PM PDT 24
Finished Jun 04 02:01:35 PM PDT 24
Peak memory 208884 kb
Host smart-e92ddc52-629d-4681-ae5d-266af5b75b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94525377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.94525377
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2631031228
Short name T186
Test name
Test status
Simulation time 66373980 ps
CPU time 2.29 seconds
Started Jun 04 02:00:57 PM PDT 24
Finished Jun 04 02:01:01 PM PDT 24
Peak memory 210040 kb
Host smart-46ca7876-3d04-4dad-a0d3-631e93f18f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631031228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2631031228
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.962993084
Short name T506
Test name
Test status
Simulation time 11462235 ps
CPU time 0.73 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:06 PM PDT 24
Peak memory 205912 kb
Host smart-893fba63-5690-455f-a6e6-396a2c8cafa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962993084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.962993084
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2926071520
Short name T420
Test name
Test status
Simulation time 141662249 ps
CPU time 2.76 seconds
Started Jun 04 02:00:57 PM PDT 24
Finished Jun 04 02:01:01 PM PDT 24
Peak memory 214296 kb
Host smart-2d3cb60a-29f2-48f8-af19-f1428de468fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926071520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2926071520
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3583223162
Short name T563
Test name
Test status
Simulation time 228448805 ps
CPU time 5.42 seconds
Started Jun 04 02:00:54 PM PDT 24
Finished Jun 04 02:01:00 PM PDT 24
Peak memory 219696 kb
Host smart-b1b044b3-f641-4fc9-9dc7-793125bbd1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583223162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3583223162
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.319828860
Short name T353
Test name
Test status
Simulation time 76589676 ps
CPU time 2.66 seconds
Started Jun 04 02:00:59 PM PDT 24
Finished Jun 04 02:01:03 PM PDT 24
Peak memory 222604 kb
Host smart-74d88132-98d7-4604-b855-c53ce708e185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319828860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.319828860
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1921014383
Short name T272
Test name
Test status
Simulation time 31559245 ps
CPU time 1.91 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:02 PM PDT 24
Peak memory 214256 kb
Host smart-3bb158a0-b159-4f8e-947c-dcd066e4c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921014383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1921014383
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_random.1743529970
Short name T253
Test name
Test status
Simulation time 755759374 ps
CPU time 5.56 seconds
Started Jun 04 02:00:56 PM PDT 24
Finished Jun 04 02:01:02 PM PDT 24
Peak memory 208524 kb
Host smart-f4529cb7-d4bf-44a4-8727-39d817cc5738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743529970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1743529970
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3729515338
Short name T224
Test name
Test status
Simulation time 113945322 ps
CPU time 2.91 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:03 PM PDT 24
Peak memory 206832 kb
Host smart-5d929cba-1b7c-4e6a-9600-cfc13b2b3d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729515338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3729515338
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2427743734
Short name T47
Test name
Test status
Simulation time 112536590 ps
CPU time 2.3 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:02 PM PDT 24
Peak memory 207376 kb
Host smart-019baea2-7403-4351-920b-bdb1e8eb9876
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427743734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2427743734
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1447781079
Short name T440
Test name
Test status
Simulation time 2532035567 ps
CPU time 9.35 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:09 PM PDT 24
Peak memory 208236 kb
Host smart-c12a5750-3708-4945-bdf0-cec4fa2db40c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447781079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1447781079
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1270357079
Short name T534
Test name
Test status
Simulation time 1020640166 ps
CPU time 36.62 seconds
Started Jun 04 02:00:57 PM PDT 24
Finished Jun 04 02:01:36 PM PDT 24
Peak memory 209116 kb
Host smart-65a60304-833d-44ac-ab5a-13caebd512c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270357079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1270357079
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1936027413
Short name T416
Test name
Test status
Simulation time 649397690 ps
CPU time 3.83 seconds
Started Jun 04 02:01:02 PM PDT 24
Finished Jun 04 02:01:09 PM PDT 24
Peak memory 209740 kb
Host smart-b3f82e74-7b8c-4a84-9479-672f890a3065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936027413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1936027413
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.4111548396
Short name T444
Test name
Test status
Simulation time 878887060 ps
CPU time 9.24 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:09 PM PDT 24
Peak memory 208416 kb
Host smart-1aa6416a-3660-47f3-bf56-8e925bf5d368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111548396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.4111548396
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3789829343
Short name T357
Test name
Test status
Simulation time 415182209 ps
CPU time 17.05 seconds
Started Jun 04 02:01:01 PM PDT 24
Finished Jun 04 02:01:19 PM PDT 24
Peak memory 222100 kb
Host smart-d848a3a9-d524-42db-b423-17788800cc1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789829343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3789829343
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2923730108
Short name T868
Test name
Test status
Simulation time 19285133329 ps
CPU time 48.65 seconds
Started Jun 04 02:00:58 PM PDT 24
Finished Jun 04 02:01:49 PM PDT 24
Peak memory 214464 kb
Host smart-8d88ae76-8c1a-4ee4-a208-bced0ac58d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923730108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2923730108
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1482088933
Short name T780
Test name
Test status
Simulation time 164422235 ps
CPU time 4.44 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 209908 kb
Host smart-9a84b796-4023-4c76-8abf-5ead9d067919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482088933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1482088933
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1271836291
Short name T889
Test name
Test status
Simulation time 15137054 ps
CPU time 0.76 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:07 PM PDT 24
Peak memory 205896 kb
Host smart-24ca04d5-f4df-4adf-890f-84c2b3000eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271836291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1271836291
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3814638983
Short name T423
Test name
Test status
Simulation time 452550090 ps
CPU time 10.46 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:17 PM PDT 24
Peak memory 215816 kb
Host smart-0cf6423c-7047-4901-91c5-99ae8ba22770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814638983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3814638983
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3887242617
Short name T19
Test name
Test status
Simulation time 106323433 ps
CPU time 2.55 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:09 PM PDT 24
Peak memory 210348 kb
Host smart-ca60a9cf-c75d-48d3-9681-848c6ac703ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887242617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3887242617
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2937351846
Short name T84
Test name
Test status
Simulation time 54468534 ps
CPU time 2.17 seconds
Started Jun 04 02:01:06 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 207264 kb
Host smart-34f9344b-49ce-499c-ac62-b87ff2c829f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937351846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2937351846
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1219581223
Short name T257
Test name
Test status
Simulation time 176494811 ps
CPU time 3.88 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 214260 kb
Host smart-c78915d7-1179-41af-bdf8-8363ce93458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219581223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1219581223
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2401782704
Short name T49
Test name
Test status
Simulation time 62611078 ps
CPU time 2.93 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 214308 kb
Host smart-e8764bc7-84ce-4948-8bf3-7c7decce60da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401782704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2401782704
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2318868336
Short name T531
Test name
Test status
Simulation time 448454605 ps
CPU time 4.64 seconds
Started Jun 04 02:01:07 PM PDT 24
Finished Jun 04 02:01:13 PM PDT 24
Peak memory 214316 kb
Host smart-a80b57a5-10e9-4d25-8c93-d5faa6236936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318868336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2318868336
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1047081133
Short name T617
Test name
Test status
Simulation time 2502284523 ps
CPU time 29.64 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 208064 kb
Host smart-06f33c48-f81b-4934-9549-e710a83fa5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047081133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1047081133
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3238702334
Short name T643
Test name
Test status
Simulation time 266370206 ps
CPU time 8.68 seconds
Started Jun 04 02:01:04 PM PDT 24
Finished Jun 04 02:01:15 PM PDT 24
Peak memory 207928 kb
Host smart-d1703445-1507-4cde-9a9b-f4c0227e8a2a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238702334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3238702334
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3169792363
Short name T510
Test name
Test status
Simulation time 380596422 ps
CPU time 2.67 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:08 PM PDT 24
Peak memory 206816 kb
Host smart-0140e8e0-e71e-454b-9a42-ebb530fd84cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169792363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3169792363
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2653345066
Short name T464
Test name
Test status
Simulation time 5119087791 ps
CPU time 33.85 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:39 PM PDT 24
Peak memory 208748 kb
Host smart-b25c13d0-c149-40f7-8ec1-2d592322342f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653345066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2653345066
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2202860373
Short name T147
Test name
Test status
Simulation time 254382613 ps
CPU time 2.83 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 209076 kb
Host smart-4a2d126c-fff6-4b25-9d24-3408f785c9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202860373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2202860373
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2130838128
Short name T437
Test name
Test status
Simulation time 90234453 ps
CPU time 2.3 seconds
Started Jun 04 02:01:06 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 206824 kb
Host smart-2bd0efe3-3d7d-4f6c-8b30-b0ace39ac06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130838128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2130838128
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.869041559
Short name T418
Test name
Test status
Simulation time 425070828 ps
CPU time 4.86 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:12 PM PDT 24
Peak memory 209168 kb
Host smart-a8a93d1b-41c7-4aaa-a1a3-6134a46e084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869041559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.869041559
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1952150619
Short name T691
Test name
Test status
Simulation time 131923917 ps
CPU time 2.4 seconds
Started Jun 04 02:01:06 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 210384 kb
Host smart-9f18b487-f3d2-4635-8b5b-590de97cfaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952150619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1952150619
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.462189205
Short name T654
Test name
Test status
Simulation time 53955697 ps
CPU time 0.75 seconds
Started Jun 04 02:01:06 PM PDT 24
Finished Jun 04 02:01:09 PM PDT 24
Peak memory 205856 kb
Host smart-afae6598-1a6c-43ae-a23a-ea242a3e27a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462189205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.462189205
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.986103167
Short name T35
Test name
Test status
Simulation time 386233093 ps
CPU time 2.95 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:09 PM PDT 24
Peak memory 221216 kb
Host smart-e299bf1b-1482-4a45-8396-8d068790127b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986103167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.986103167
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2509473308
Short name T88
Test name
Test status
Simulation time 1413046963 ps
CPU time 4.82 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 214336 kb
Host smart-dfd49343-163d-4abc-b4f2-a0f2a9ae197d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509473308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2509473308
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.4279474459
Short name T462
Test name
Test status
Simulation time 1176855287 ps
CPU time 8.4 seconds
Started Jun 04 02:01:04 PM PDT 24
Finished Jun 04 02:01:15 PM PDT 24
Peak memory 209060 kb
Host smart-f165495d-4355-4e08-8ede-123e5a807673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279474459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.4279474459
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4204694857
Short name T368
Test name
Test status
Simulation time 226451193 ps
CPU time 5.62 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:13 PM PDT 24
Peak memory 222380 kb
Host smart-28b3727b-c2c4-44bf-8ef6-c97f38d7aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204694857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4204694857
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_random.1422669790
Short name T790
Test name
Test status
Simulation time 150977302 ps
CPU time 6.25 seconds
Started Jun 04 02:01:04 PM PDT 24
Finished Jun 04 02:01:13 PM PDT 24
Peak memory 214356 kb
Host smart-78621c77-6a9f-4ca8-803f-390ea48b72a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422669790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1422669790
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1017475406
Short name T806
Test name
Test status
Simulation time 154520087 ps
CPU time 5.61 seconds
Started Jun 04 02:01:02 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 206744 kb
Host smart-d0c94c06-65e2-4f04-a398-6e3d1b975991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017475406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1017475406
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2016070581
Short name T345
Test name
Test status
Simulation time 252307111 ps
CPU time 2.72 seconds
Started Jun 04 02:01:02 PM PDT 24
Finished Jun 04 02:01:08 PM PDT 24
Peak memory 207036 kb
Host smart-26c4b3d7-7950-432c-865b-a90139b85ea7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016070581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2016070581
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.372593904
Short name T890
Test name
Test status
Simulation time 56083399 ps
CPU time 2.89 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 207052 kb
Host smart-3825d663-a4c2-4b4f-b727-9628d188259b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372593904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.372593904
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3714287862
Short name T467
Test name
Test status
Simulation time 124177235 ps
CPU time 3.77 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:11 PM PDT 24
Peak memory 208620 kb
Host smart-7b9b942b-b631-478a-bfd6-ff9243b98781
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714287862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3714287862
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.419477471
Short name T837
Test name
Test status
Simulation time 809336531 ps
CPU time 8.25 seconds
Started Jun 04 02:01:04 PM PDT 24
Finished Jun 04 02:01:15 PM PDT 24
Peak memory 218312 kb
Host smart-f7e5a69d-756b-4d89-98a1-d8152f297989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419477471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.419477471
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1176060928
Short name T122
Test name
Test status
Simulation time 532156874 ps
CPU time 3.21 seconds
Started Jun 04 02:01:02 PM PDT 24
Finished Jun 04 02:01:07 PM PDT 24
Peak memory 208504 kb
Host smart-3d27129a-c192-4519-b2cf-5d9778b31359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176060928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1176060928
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1098805747
Short name T87
Test name
Test status
Simulation time 2473088591 ps
CPU time 41.54 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:48 PM PDT 24
Peak memory 214412 kb
Host smart-571ee0da-f7c9-46cd-9e8d-0dc70402650b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098805747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1098805747
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.359527655
Short name T538
Test name
Test status
Simulation time 391024739 ps
CPU time 13.44 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:21 PM PDT 24
Peak memory 222748 kb
Host smart-3b751ddb-40e1-4c37-84da-39811ffbafc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359527655 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.359527655
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4176813607
Short name T486
Test name
Test status
Simulation time 38075200 ps
CPU time 3.02 seconds
Started Jun 04 02:01:05 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 207688 kb
Host smart-6403ddcd-2886-4101-9498-dafb45674018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176813607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4176813607
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3998688999
Short name T390
Test name
Test status
Simulation time 1301698998 ps
CPU time 11.59 seconds
Started Jun 04 02:01:07 PM PDT 24
Finished Jun 04 02:01:20 PM PDT 24
Peak memory 210732 kb
Host smart-15b0e369-23b4-4e7f-9881-b6c4396465a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998688999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3998688999
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1911382156
Short name T582
Test name
Test status
Simulation time 330241952 ps
CPU time 0.79 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:21 PM PDT 24
Peak memory 205636 kb
Host smart-e4bce5d2-3c22-486b-bc5e-277c67c9b39f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911382156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1911382156
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1641599969
Short name T341
Test name
Test status
Simulation time 222180909 ps
CPU time 3.46 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:22 PM PDT 24
Peak memory 214320 kb
Host smart-fe9ab32d-5038-41ca-a74a-f2d39fa1f9f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1641599969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1641599969
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4035607926
Short name T700
Test name
Test status
Simulation time 61628785 ps
CPU time 2.69 seconds
Started Jun 04 02:01:15 PM PDT 24
Finished Jun 04 02:01:18 PM PDT 24
Peak memory 214300 kb
Host smart-3168b38a-fa4a-44d1-a263-b816fcca394c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035607926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4035607926
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.4155142963
Short name T351
Test name
Test status
Simulation time 124846445 ps
CPU time 2.45 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:22 PM PDT 24
Peak memory 214352 kb
Host smart-7ef794e5-e0ec-43e5-8f5b-7206183a4886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155142963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.4155142963
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.609435398
Short name T255
Test name
Test status
Simulation time 278522879 ps
CPU time 3.82 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:25 PM PDT 24
Peak memory 206116 kb
Host smart-51e5c54f-3d99-4154-813a-c67b5dc4336f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609435398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.609435398
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.545062806
Short name T705
Test name
Test status
Simulation time 329598899 ps
CPU time 2.6 seconds
Started Jun 04 02:01:16 PM PDT 24
Finished Jun 04 02:01:19 PM PDT 24
Peak memory 214380 kb
Host smart-d1e2fb58-7e54-40c4-be8b-c3e1c5db6e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545062806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.545062806
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1296137118
Short name T343
Test name
Test status
Simulation time 663194552 ps
CPU time 17.36 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:35 PM PDT 24
Peak memory 218560 kb
Host smart-b0c96875-6605-49bd-8750-99daf237c4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296137118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1296137118
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1799681898
Short name T866
Test name
Test status
Simulation time 401672357 ps
CPU time 6.19 seconds
Started Jun 04 02:01:07 PM PDT 24
Finished Jun 04 02:01:14 PM PDT 24
Peak memory 208596 kb
Host smart-adbca062-8d6f-4775-99fe-8ceadf5440d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799681898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1799681898
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1653326062
Short name T314
Test name
Test status
Simulation time 78459419 ps
CPU time 2.61 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:22 PM PDT 24
Peak memory 207080 kb
Host smart-bc17d073-16b8-43e5-9ceb-6f53cb878bf1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653326062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1653326062
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3154229582
Short name T325
Test name
Test status
Simulation time 72460049 ps
CPU time 1.64 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:19 PM PDT 24
Peak memory 206780 kb
Host smart-8723ce0d-424e-49aa-88ce-5e15825404a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154229582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3154229582
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2855195902
Short name T880
Test name
Test status
Simulation time 40388364 ps
CPU time 2.38 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:22 PM PDT 24
Peak memory 207420 kb
Host smart-adf1008d-721a-4749-8057-c692f20fae61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855195902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2855195902
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2326711055
Short name T835
Test name
Test status
Simulation time 354899664 ps
CPU time 3.06 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:21 PM PDT 24
Peak memory 207968 kb
Host smart-e34ddf47-0999-4e7d-b4a7-9610c9988c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326711055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2326711055
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2861487206
Short name T688
Test name
Test status
Simulation time 312383153 ps
CPU time 3.45 seconds
Started Jun 04 02:01:03 PM PDT 24
Finished Jun 04 02:01:09 PM PDT 24
Peak memory 208048 kb
Host smart-ced2b0eb-9c9e-4249-8ba6-fb634657b92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861487206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2861487206
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3931380960
Short name T239
Test name
Test status
Simulation time 7775063248 ps
CPU time 26.34 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:48 PM PDT 24
Peak memory 216908 kb
Host smart-a966bcd3-9965-478e-a286-f9d9b440aa33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931380960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3931380960
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2009678631
Short name T728
Test name
Test status
Simulation time 1585980443 ps
CPU time 19.8 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:41 PM PDT 24
Peak memory 222976 kb
Host smart-5d767355-9027-48f9-b282-2589a2848788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009678631 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2009678631
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1608459924
Short name T577
Test name
Test status
Simulation time 108655599 ps
CPU time 4.81 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:23 PM PDT 24
Peak memory 210316 kb
Host smart-9a218c66-8c2a-45ca-80af-f20bf648f494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608459924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1608459924
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.773198459
Short name T222
Test name
Test status
Simulation time 166074418 ps
CPU time 1.9 seconds
Started Jun 04 02:01:15 PM PDT 24
Finished Jun 04 02:01:17 PM PDT 24
Peak memory 210104 kb
Host smart-1bcd5b93-b544-4c24-8ad9-c498de73b4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773198459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.773198459
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.342477266
Short name T720
Test name
Test status
Simulation time 50222288 ps
CPU time 0.72 seconds
Started Jun 04 02:01:15 PM PDT 24
Finished Jun 04 02:01:16 PM PDT 24
Peak memory 205892 kb
Host smart-f3554cb4-5077-47de-914d-3199b29b4512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342477266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.342477266
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.220654631
Short name T428
Test name
Test status
Simulation time 65912214 ps
CPU time 2.38 seconds
Started Jun 04 02:01:15 PM PDT 24
Finished Jun 04 02:01:18 PM PDT 24
Peak memory 215412 kb
Host smart-c387aad0-e7c2-47e1-9bde-8545f9f9947a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220654631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.220654631
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1979143949
Short name T748
Test name
Test status
Simulation time 128451200 ps
CPU time 4.2 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:22 PM PDT 24
Peak memory 207864 kb
Host smart-fe902689-ba68-4c75-916e-e38ae4391f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979143949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1979143949
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.505142059
Short name T103
Test name
Test status
Simulation time 53961959 ps
CPU time 2.32 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:20 PM PDT 24
Peak memory 221280 kb
Host smart-449a9b8c-a728-422a-940d-8a1ea05fe826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505142059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.505142059
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3955752726
Short name T57
Test name
Test status
Simulation time 148034257 ps
CPU time 3 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:22 PM PDT 24
Peak memory 207852 kb
Host smart-7cb0eebd-d5ba-43fa-a42c-bb10802bd771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955752726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3955752726
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2111941630
Short name T365
Test name
Test status
Simulation time 219211902 ps
CPU time 6.29 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:26 PM PDT 24
Peak memory 207364 kb
Host smart-5e8266d4-f8dc-4c17-8b6f-7adef97543bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111941630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2111941630
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.658739373
Short name T479
Test name
Test status
Simulation time 30004354 ps
CPU time 2.28 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:22 PM PDT 24
Peak memory 207272 kb
Host smart-a121133b-eabd-412c-896a-2800aafab8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658739373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.658739373
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.370232610
Short name T465
Test name
Test status
Simulation time 335335693 ps
CPU time 2.23 seconds
Started Jun 04 02:01:15 PM PDT 24
Finished Jun 04 02:01:18 PM PDT 24
Peak memory 209136 kb
Host smart-d56ab6b4-88c0-4af1-9640-4d529209a8a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370232610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.370232610
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.368506854
Short name T399
Test name
Test status
Simulation time 52878267 ps
CPU time 2.89 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:23 PM PDT 24
Peak memory 206452 kb
Host smart-c187ce26-b42a-445b-abd4-c9371d68712e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368506854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.368506854
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1542231365
Short name T456
Test name
Test status
Simulation time 228814479 ps
CPU time 4.62 seconds
Started Jun 04 02:01:15 PM PDT 24
Finished Jun 04 02:01:20 PM PDT 24
Peak memory 206748 kb
Host smart-dcab46d3-c48a-49f3-aaac-b6743adf4ab4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542231365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1542231365
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.794071791
Short name T213
Test name
Test status
Simulation time 210079039 ps
CPU time 3.12 seconds
Started Jun 04 02:01:15 PM PDT 24
Finished Jun 04 02:01:19 PM PDT 24
Peak memory 209636 kb
Host smart-cf38b2a2-1fee-47e7-ad7f-8d3f794122ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794071791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.794071791
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4170344955
Short name T600
Test name
Test status
Simulation time 50379607 ps
CPU time 2.01 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:21 PM PDT 24
Peak memory 208456 kb
Host smart-de104494-4547-4016-b5c4-886094013f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170344955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4170344955
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1872250659
Short name T263
Test name
Test status
Simulation time 641314964 ps
CPU time 4.98 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:25 PM PDT 24
Peak memory 214280 kb
Host smart-7d7881de-d7f9-4508-a515-fa6a3a7e33a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872250659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1872250659
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3379416422
Short name T171
Test name
Test status
Simulation time 175627789 ps
CPU time 2.35 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:22 PM PDT 24
Peak memory 209868 kb
Host smart-352c4fb4-9e62-489a-a47a-b24570c4731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379416422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3379416422
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.337175232
Short name T523
Test name
Test status
Simulation time 12075145 ps
CPU time 0.75 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:06 PM PDT 24
Peak memory 205944 kb
Host smart-f2c4cd8d-b394-4214-8a8c-a82c1505356f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337175232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.337175232
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.433784214
Short name T151
Test name
Test status
Simulation time 573240176 ps
CPU time 4.3 seconds
Started Jun 04 01:57:57 PM PDT 24
Finished Jun 04 01:58:02 PM PDT 24
Peak memory 214356 kb
Host smart-48c57dac-5ed1-4359-a78c-cc4466c17334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433784214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.433784214
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3631311244
Short name T24
Test name
Test status
Simulation time 51171658 ps
CPU time 1.72 seconds
Started Jun 04 01:58:05 PM PDT 24
Finished Jun 04 01:58:07 PM PDT 24
Peak memory 214580 kb
Host smart-4f2f87b0-e7e6-4749-9272-02328eab93a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631311244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3631311244
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.140274371
Short name T860
Test name
Test status
Simulation time 37945483 ps
CPU time 2.1 seconds
Started Jun 04 01:57:59 PM PDT 24
Finished Jun 04 01:58:02 PM PDT 24
Peak memory 208812 kb
Host smart-4398926c-150e-4f27-8fc9-72c1434b3d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140274371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.140274371
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4224593399
Short name T101
Test name
Test status
Simulation time 45164921 ps
CPU time 2.94 seconds
Started Jun 04 01:57:59 PM PDT 24
Finished Jun 04 01:58:03 PM PDT 24
Peak memory 209164 kb
Host smart-923886f3-f29c-4bca-b61f-869f592bbbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224593399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4224593399
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.234263324
Short name T794
Test name
Test status
Simulation time 324490830 ps
CPU time 2.8 seconds
Started Jun 04 01:57:58 PM PDT 24
Finished Jun 04 01:58:01 PM PDT 24
Peak memory 209428 kb
Host smart-83ef2102-e089-422d-9606-1fb5e4b3ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234263324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.234263324
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3944460515
Short name T593
Test name
Test status
Simulation time 429546510 ps
CPU time 4.86 seconds
Started Jun 04 01:57:58 PM PDT 24
Finished Jun 04 01:58:04 PM PDT 24
Peak memory 206804 kb
Host smart-b21432b3-9504-4c45-82a5-95c4a62e59fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944460515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3944460515
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1295006992
Short name T377
Test name
Test status
Simulation time 1508804935 ps
CPU time 9.12 seconds
Started Jun 04 01:57:56 PM PDT 24
Finished Jun 04 01:58:06 PM PDT 24
Peak memory 208124 kb
Host smart-c07f521d-16af-4618-9ec9-5880ebab0f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295006992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1295006992
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2636197877
Short name T344
Test name
Test status
Simulation time 86944441 ps
CPU time 1.82 seconds
Started Jun 04 01:57:58 PM PDT 24
Finished Jun 04 01:58:01 PM PDT 24
Peak memory 206852 kb
Host smart-dbf41c74-6908-43d4-9c00-8951d5f59c00
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636197877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2636197877
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2768274011
Short name T588
Test name
Test status
Simulation time 873483747 ps
CPU time 20.25 seconds
Started Jun 04 01:57:58 PM PDT 24
Finished Jun 04 01:58:19 PM PDT 24
Peak memory 207936 kb
Host smart-78d2d269-1f7d-4b5a-b8bc-048d65d67137
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768274011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2768274011
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2326884835
Short name T302
Test name
Test status
Simulation time 87397201 ps
CPU time 3.38 seconds
Started Jun 04 01:57:55 PM PDT 24
Finished Jun 04 01:57:59 PM PDT 24
Peak memory 208116 kb
Host smart-c213636f-b645-4a22-86f4-5d0640adfc7a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326884835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2326884835
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1742215930
Short name T537
Test name
Test status
Simulation time 47982812 ps
CPU time 2.92 seconds
Started Jun 04 01:58:02 PM PDT 24
Finished Jun 04 01:58:06 PM PDT 24
Peak memory 215924 kb
Host smart-30c33c59-50b6-4a3c-8638-7d52a1928abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742215930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1742215930
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1379703251
Short name T512
Test name
Test status
Simulation time 1037355895 ps
CPU time 14.39 seconds
Started Jun 04 01:57:54 PM PDT 24
Finished Jun 04 01:58:09 PM PDT 24
Peak memory 208776 kb
Host smart-10d2e6ae-689c-49ee-bd1c-d33b9033f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379703251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1379703251
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3778321415
Short name T74
Test name
Test status
Simulation time 1779920146 ps
CPU time 11.11 seconds
Started Jun 04 01:58:08 PM PDT 24
Finished Jun 04 01:58:19 PM PDT 24
Peak memory 220352 kb
Host smart-5ca6e956-d53d-4399-ae91-4c30efba2185
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778321415 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3778321415
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2413677951
Short name T759
Test name
Test status
Simulation time 399550795 ps
CPU time 4.89 seconds
Started Jun 04 01:57:58 PM PDT 24
Finished Jun 04 01:58:04 PM PDT 24
Peak memory 209480 kb
Host smart-23ec43b7-a491-4167-85fd-6dc703bfc7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413677951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2413677951
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1526937118
Short name T509
Test name
Test status
Simulation time 303398382 ps
CPU time 5.48 seconds
Started Jun 04 01:58:06 PM PDT 24
Finished Jun 04 01:58:12 PM PDT 24
Peak memory 210332 kb
Host smart-33d817d2-5883-4cc7-a1e1-c1011cdb6a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526937118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1526937118
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2756370447
Short name T451
Test name
Test status
Simulation time 285927099 ps
CPU time 0.95 seconds
Started Jun 04 01:58:15 PM PDT 24
Finished Jun 04 01:58:17 PM PDT 24
Peak memory 205976 kb
Host smart-9d9da79b-b7a5-4e91-910d-3263afadefe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756370447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2756370447
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3516452539
Short name T261
Test name
Test status
Simulation time 44901494 ps
CPU time 2.66 seconds
Started Jun 04 01:58:02 PM PDT 24
Finished Jun 04 01:58:05 PM PDT 24
Peak memory 214284 kb
Host smart-28b3be09-2e17-4edc-b3f4-684fd926360f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3516452539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3516452539
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1619244091
Short name T536
Test name
Test status
Simulation time 196355279 ps
CPU time 2.18 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:06 PM PDT 24
Peak memory 209004 kb
Host smart-182df662-cc49-44a6-9341-d43313f195e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619244091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1619244091
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3196701748
Short name T702
Test name
Test status
Simulation time 269490311 ps
CPU time 5.71 seconds
Started Jun 04 01:58:03 PM PDT 24
Finished Jun 04 01:58:09 PM PDT 24
Peak memory 209200 kb
Host smart-d7d8279f-faa6-4d06-9425-744149a0b0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196701748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3196701748
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2558012827
Short name T560
Test name
Test status
Simulation time 172274515 ps
CPU time 2.45 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:07 PM PDT 24
Peak memory 222360 kb
Host smart-532b4493-41d8-4a00-8ec6-28de74080ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558012827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2558012827
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2491029268
Short name T567
Test name
Test status
Simulation time 319335418 ps
CPU time 2.99 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:08 PM PDT 24
Peak memory 215668 kb
Host smart-b720ea54-3023-4602-a73d-36500139f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491029268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2491029268
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2404587285
Short name T262
Test name
Test status
Simulation time 256260953 ps
CPU time 6.54 seconds
Started Jun 04 01:58:05 PM PDT 24
Finished Jun 04 01:58:12 PM PDT 24
Peak memory 218372 kb
Host smart-77abc8e2-5b7c-4270-a1eb-be6c1d5f2d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404587285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2404587285
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.660270780
Short name T504
Test name
Test status
Simulation time 1309539761 ps
CPU time 40.27 seconds
Started Jun 04 01:58:03 PM PDT 24
Finished Jun 04 01:58:44 PM PDT 24
Peak memory 208592 kb
Host smart-bb80b760-b214-442d-bc85-248f438da65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660270780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.660270780
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4153097601
Short name T145
Test name
Test status
Simulation time 4472836136 ps
CPU time 28.74 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:34 PM PDT 24
Peak memory 209292 kb
Host smart-4b86a0a1-07a5-439d-a9d0-4c6e5b695688
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153097601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4153097601
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2147693026
Short name T701
Test name
Test status
Simulation time 10842396160 ps
CPU time 38.22 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:43 PM PDT 24
Peak memory 207976 kb
Host smart-f891fbff-890a-48ae-9a5b-be56429f45cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147693026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2147693026
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3929485306
Short name T803
Test name
Test status
Simulation time 853162969 ps
CPU time 8.76 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:14 PM PDT 24
Peak memory 208580 kb
Host smart-08d546a3-99ee-44ce-b49d-76cefe474a3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929485306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3929485306
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1198239278
Short name T762
Test name
Test status
Simulation time 25762411 ps
CPU time 1.86 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:07 PM PDT 24
Peak memory 207992 kb
Host smart-a5d0befc-9ef3-4637-ab04-55cddb0bf088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198239278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1198239278
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.4273200205
Short name T751
Test name
Test status
Simulation time 142214589 ps
CPU time 2.49 seconds
Started Jun 04 01:58:03 PM PDT 24
Finished Jun 04 01:58:07 PM PDT 24
Peak memory 208752 kb
Host smart-0e66fd22-3f73-4d1d-883d-cc2a724d8631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273200205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.4273200205
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1264998052
Short name T236
Test name
Test status
Simulation time 1795517416 ps
CPU time 24.46 seconds
Started Jun 04 01:58:13 PM PDT 24
Finished Jun 04 01:58:38 PM PDT 24
Peak memory 215296 kb
Host smart-dd0eac63-d5b1-421b-9530-8df81b6a94f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264998052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1264998052
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.573954745
Short name T310
Test name
Test status
Simulation time 209025696 ps
CPU time 4.9 seconds
Started Jun 04 01:58:06 PM PDT 24
Finished Jun 04 01:58:12 PM PDT 24
Peak memory 209624 kb
Host smart-af30a808-b4bb-43e7-8552-d35f7736d865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573954745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.573954745
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2404890229
Short name T72
Test name
Test status
Simulation time 1069353082 ps
CPU time 5.08 seconds
Started Jun 04 01:58:04 PM PDT 24
Finished Jun 04 01:58:09 PM PDT 24
Peak memory 211044 kb
Host smart-db7d85d5-12b2-4469-ae10-3f321b5e5e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404890229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2404890229
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.4082009884
Short name T42
Test name
Test status
Simulation time 1023559671 ps
CPU time 3.52 seconds
Started Jun 04 01:58:21 PM PDT 24
Finished Jun 04 01:58:25 PM PDT 24
Peak memory 208804 kb
Host smart-4671bebb-2a37-4675-9372-6f078ab7b732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082009884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.4082009884
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.643693943
Short name T566
Test name
Test status
Simulation time 32507062 ps
CPU time 1.97 seconds
Started Jun 04 01:58:14 PM PDT 24
Finished Jun 04 01:58:17 PM PDT 24
Peak memory 208204 kb
Host smart-297c516a-4656-4d0b-b0f8-b5a7ffb34da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643693943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.643693943
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3102695327
Short name T304
Test name
Test status
Simulation time 530942536 ps
CPU time 4.62 seconds
Started Jun 04 01:58:13 PM PDT 24
Finished Jun 04 01:58:19 PM PDT 24
Peak memory 215088 kb
Host smart-64b218d2-b4e4-43e1-81a3-278edee84432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102695327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3102695327
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1543428787
Short name T369
Test name
Test status
Simulation time 174169652 ps
CPU time 5.55 seconds
Started Jun 04 01:58:15 PM PDT 24
Finished Jun 04 01:58:21 PM PDT 24
Peak memory 222456 kb
Host smart-f103ae37-f4b8-4197-8920-e7ca76b3f915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543428787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1543428787
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2364408301
Short name T738
Test name
Test status
Simulation time 36447709 ps
CPU time 1.87 seconds
Started Jun 04 01:58:14 PM PDT 24
Finished Jun 04 01:58:17 PM PDT 24
Peak memory 222412 kb
Host smart-7e2273ae-2a14-4c43-b305-af33b7043470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364408301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2364408301
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.10320358
Short name T842
Test name
Test status
Simulation time 3963680861 ps
CPU time 40.48 seconds
Started Jun 04 01:58:13 PM PDT 24
Finished Jun 04 01:58:54 PM PDT 24
Peak memory 208928 kb
Host smart-b65ec484-2dfe-4df6-b0dc-b711bb72499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10320358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.10320358
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1149767578
Short name T640
Test name
Test status
Simulation time 126930798 ps
CPU time 3.2 seconds
Started Jun 04 01:58:13 PM PDT 24
Finished Jun 04 01:58:17 PM PDT 24
Peak memory 206680 kb
Host smart-726d0236-6e4c-4913-b53f-d58a0d36ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149767578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1149767578
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.683703255
Short name T612
Test name
Test status
Simulation time 93244997 ps
CPU time 2.56 seconds
Started Jun 04 01:58:14 PM PDT 24
Finished Jun 04 01:58:17 PM PDT 24
Peak memory 208612 kb
Host smart-6071583f-a8f2-40d2-99c1-6fcc7515a583
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683703255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.683703255
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1457036299
Short name T39
Test name
Test status
Simulation time 1896372774 ps
CPU time 47.1 seconds
Started Jun 04 01:58:13 PM PDT 24
Finished Jun 04 01:59:01 PM PDT 24
Peak memory 208084 kb
Host smart-3218a1cc-b9f3-4507-a53b-c5360251c117
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457036299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1457036299
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1260426628
Short name T749
Test name
Test status
Simulation time 2439556565 ps
CPU time 25.73 seconds
Started Jun 04 01:58:13 PM PDT 24
Finished Jun 04 01:58:40 PM PDT 24
Peak memory 208212 kb
Host smart-981c2d52-5458-4adb-94ba-f244d39750d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260426628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1260426628
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4038582299
Short name T313
Test name
Test status
Simulation time 34063047 ps
CPU time 2.44 seconds
Started Jun 04 01:58:21 PM PDT 24
Finished Jun 04 01:58:24 PM PDT 24
Peak memory 218284 kb
Host smart-6c9a5bd6-38d5-41d9-9bfd-72f68ae06c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038582299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4038582299
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.4108102316
Short name T468
Test name
Test status
Simulation time 124808572 ps
CPU time 2.19 seconds
Started Jun 04 01:58:14 PM PDT 24
Finished Jun 04 01:58:17 PM PDT 24
Peak memory 206772 kb
Host smart-ff5039c4-14db-4969-90a9-381e77dc0094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108102316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.4108102316
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.453064447
Short name T118
Test name
Test status
Simulation time 436813469 ps
CPU time 8.81 seconds
Started Jun 04 01:58:21 PM PDT 24
Finished Jun 04 01:58:31 PM PDT 24
Peak memory 219308 kb
Host smart-405e1ffd-bb91-43a2-869c-39043b18db1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453064447 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.453064447
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2997817086
Short name T93
Test name
Test status
Simulation time 746217739 ps
CPU time 9.57 seconds
Started Jun 04 01:58:12 PM PDT 24
Finished Jun 04 01:58:22 PM PDT 24
Peak memory 209164 kb
Host smart-ef3e19b8-7ad7-4138-8d54-9c8db7e56c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997817086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2997817086
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2577647156
Short name T206
Test name
Test status
Simulation time 321191861 ps
CPU time 2.29 seconds
Started Jun 04 01:58:21 PM PDT 24
Finished Jun 04 01:58:24 PM PDT 24
Peak memory 210276 kb
Host smart-602ae89c-09c1-4ff4-91ef-1b190d5191da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577647156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2577647156
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2903779446
Short name T707
Test name
Test status
Simulation time 37981807 ps
CPU time 0.77 seconds
Started Jun 04 01:58:20 PM PDT 24
Finished Jun 04 01:58:22 PM PDT 24
Peak memory 205956 kb
Host smart-67f01aed-5650-4d34-ba15-42fe3b1e2662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903779446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2903779446
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3269637158
Short name T52
Test name
Test status
Simulation time 717583539 ps
CPU time 9.09 seconds
Started Jun 04 01:58:20 PM PDT 24
Finished Jun 04 01:58:30 PM PDT 24
Peak memory 218116 kb
Host smart-adce7c25-861b-42dc-a18f-9532bb048e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269637158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3269637158
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4147847249
Short name T98
Test name
Test status
Simulation time 825447678 ps
CPU time 17.67 seconds
Started Jun 04 01:58:22 PM PDT 24
Finished Jun 04 01:58:40 PM PDT 24
Peak memory 214292 kb
Host smart-c0e87735-c89b-443a-8d9a-f60a529b1e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147847249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4147847249
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.867172099
Short name T53
Test name
Test status
Simulation time 38644684 ps
CPU time 2.01 seconds
Started Jun 04 01:58:24 PM PDT 24
Finished Jun 04 01:58:28 PM PDT 24
Peak memory 206020 kb
Host smart-cb78e1c7-9929-485e-b0e7-72dcbd66ab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867172099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.867172099
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3059934049
Short name T69
Test name
Test status
Simulation time 686486932 ps
CPU time 16.63 seconds
Started Jun 04 01:58:22 PM PDT 24
Finished Jun 04 01:58:39 PM PDT 24
Peak memory 209880 kb
Host smart-be5262ad-b8ae-4f13-846e-502322f466cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059934049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3059934049
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4288252837
Short name T525
Test name
Test status
Simulation time 990508850 ps
CPU time 8 seconds
Started Jun 04 01:58:19 PM PDT 24
Finished Jun 04 01:58:28 PM PDT 24
Peak memory 208108 kb
Host smart-04268211-b398-40e0-8242-8bd01d7072cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288252837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4288252837
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1292234968
Short name T833
Test name
Test status
Simulation time 131299846 ps
CPU time 3.69 seconds
Started Jun 04 01:58:21 PM PDT 24
Finished Jun 04 01:58:25 PM PDT 24
Peak memory 208552 kb
Host smart-907bc73f-7085-4e8d-b886-6f37db1632cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292234968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1292234968
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3741115705
Short name T94
Test name
Test status
Simulation time 372502820 ps
CPU time 3.9 seconds
Started Jun 04 01:58:24 PM PDT 24
Finished Jun 04 01:58:29 PM PDT 24
Peak memory 208784 kb
Host smart-7fb9661f-3c43-4fb4-bfca-8bea6eed78cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741115705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3741115705
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1720402447
Short name T148
Test name
Test status
Simulation time 95439814 ps
CPU time 3.11 seconds
Started Jun 04 01:58:22 PM PDT 24
Finished Jun 04 01:58:26 PM PDT 24
Peak memory 208564 kb
Host smart-bc5d7e31-7876-448d-b3d4-9888d3769cc9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720402447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1720402447
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2116988533
Short name T529
Test name
Test status
Simulation time 187924634 ps
CPU time 2.82 seconds
Started Jun 04 01:58:23 PM PDT 24
Finished Jun 04 01:58:26 PM PDT 24
Peak memory 206792 kb
Host smart-494d3a52-cbd5-4166-a70d-06b8f102d9e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116988533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2116988533
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.737871921
Short name T553
Test name
Test status
Simulation time 65020910 ps
CPU time 2.09 seconds
Started Jun 04 01:58:20 PM PDT 24
Finished Jun 04 01:58:23 PM PDT 24
Peak memory 208284 kb
Host smart-bd357a74-8141-4faa-9796-758184d5b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737871921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.737871921
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3900926786
Short name T406
Test name
Test status
Simulation time 68008118 ps
CPU time 2.28 seconds
Started Jun 04 01:58:24 PM PDT 24
Finished Jun 04 01:58:28 PM PDT 24
Peak memory 206632 kb
Host smart-475c0a1a-37fe-4f4f-b892-81d27ea0112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900926786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3900926786
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1011499299
Short name T638
Test name
Test status
Simulation time 62480811 ps
CPU time 3.08 seconds
Started Jun 04 01:58:21 PM PDT 24
Finished Jun 04 01:58:25 PM PDT 24
Peak memory 207936 kb
Host smart-b8737628-d214-40fe-b510-005af500dae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011499299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1011499299
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.129365319
Short name T778
Test name
Test status
Simulation time 687486100 ps
CPU time 2.81 seconds
Started Jun 04 01:58:23 PM PDT 24
Finished Jun 04 01:58:27 PM PDT 24
Peak memory 210328 kb
Host smart-091490be-d392-4a38-8ea2-f1b5524c2c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129365319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.129365319
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.275263486
Short name T515
Test name
Test status
Simulation time 42198728 ps
CPU time 0.8 seconds
Started Jun 04 01:58:31 PM PDT 24
Finished Jun 04 01:58:33 PM PDT 24
Peak memory 205904 kb
Host smart-bb03dbef-8a37-45a4-a741-be2772db411b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275263486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.275263486
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3737107978
Short name T297
Test name
Test status
Simulation time 56288781 ps
CPU time 3.51 seconds
Started Jun 04 01:58:21 PM PDT 24
Finished Jun 04 01:58:25 PM PDT 24
Peak memory 214404 kb
Host smart-6b23668a-70dd-4dbb-8cf3-f03b0e43e21f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737107978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3737107978
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.837948164
Short name T756
Test name
Test status
Simulation time 227382415 ps
CPU time 2.52 seconds
Started Jun 04 01:58:22 PM PDT 24
Finished Jun 04 01:58:26 PM PDT 24
Peak memory 207952 kb
Host smart-5ee84832-94d7-4b91-b936-5cd856d38921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837948164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.837948164
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2179724565
Short name T110
Test name
Test status
Simulation time 3780586466 ps
CPU time 27.36 seconds
Started Jun 04 01:58:22 PM PDT 24
Finished Jun 04 01:58:50 PM PDT 24
Peak memory 222344 kb
Host smart-950fb947-77da-42f9-b0b4-8d74c95953dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179724565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2179724565
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.572019093
Short name T677
Test name
Test status
Simulation time 183047112 ps
CPU time 3.93 seconds
Started Jun 04 01:58:24 PM PDT 24
Finished Jun 04 01:58:29 PM PDT 24
Peak memory 214992 kb
Host smart-3dd2caad-be0a-48ed-b6f9-715a34c28ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572019093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.572019093
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_random.3033932013
Short name T223
Test name
Test status
Simulation time 2062576292 ps
CPU time 10.44 seconds
Started Jun 04 01:58:23 PM PDT 24
Finished Jun 04 01:58:34 PM PDT 24
Peak memory 218400 kb
Host smart-7b23f080-f7e2-4fb4-b036-4c4ac1a2f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033932013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3033932013
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.289837934
Short name T278
Test name
Test status
Simulation time 47449652 ps
CPU time 2.57 seconds
Started Jun 04 01:58:21 PM PDT 24
Finished Jun 04 01:58:25 PM PDT 24
Peak memory 206876 kb
Host smart-5d2b0561-ad10-40a1-a8bb-4d92dbc97b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289837934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.289837934
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3173792293
Short name T336
Test name
Test status
Simulation time 57581545 ps
CPU time 2.68 seconds
Started Jun 04 01:58:21 PM PDT 24
Finished Jun 04 01:58:24 PM PDT 24
Peak memory 208308 kb
Host smart-aaa0ea70-9918-4eb6-b9eb-e5a8cb9ddcd7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173792293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3173792293
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2031057271
Short name T672
Test name
Test status
Simulation time 435066459 ps
CPU time 4.89 seconds
Started Jun 04 01:58:24 PM PDT 24
Finished Jun 04 01:58:30 PM PDT 24
Peak memory 208536 kb
Host smart-4ef85bea-d073-4f80-8bd1-af66179d3840
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031057271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2031057271
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2884086178
Short name T847
Test name
Test status
Simulation time 177636771 ps
CPU time 2.3 seconds
Started Jun 04 01:58:24 PM PDT 24
Finished Jun 04 01:58:28 PM PDT 24
Peak memory 208116 kb
Host smart-95fd667f-789c-4f06-8c23-f9489879049b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884086178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2884086178
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1345471402
Short name T730
Test name
Test status
Simulation time 34641740 ps
CPU time 2.46 seconds
Started Jun 04 01:58:32 PM PDT 24
Finished Jun 04 01:58:35 PM PDT 24
Peak memory 207948 kb
Host smart-af0933e0-6b35-4085-9215-34bfdf77a265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345471402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1345471402
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3283731289
Short name T848
Test name
Test status
Simulation time 66783444 ps
CPU time 3.06 seconds
Started Jun 04 01:58:20 PM PDT 24
Finished Jun 04 01:58:23 PM PDT 24
Peak memory 208692 kb
Host smart-51947299-834d-4716-b32c-5359b4c04013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283731289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3283731289
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2603914859
Short name T327
Test name
Test status
Simulation time 1581895558 ps
CPU time 10.76 seconds
Started Jun 04 01:58:29 PM PDT 24
Finished Jun 04 01:58:41 PM PDT 24
Peak memory 208152 kb
Host smart-b1f4ac20-56b5-44b4-b2e8-c4b43c72da15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603914859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2603914859
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2073172312
Short name T732
Test name
Test status
Simulation time 156487587 ps
CPU time 4.87 seconds
Started Jun 04 01:58:25 PM PDT 24
Finished Jun 04 01:58:31 PM PDT 24
Peak memory 207072 kb
Host smart-d824b025-21f5-46d5-817d-9fdcd7c83363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073172312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2073172312
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2263539722
Short name T136
Test name
Test status
Simulation time 140305850 ps
CPU time 1.51 seconds
Started Jun 04 01:58:27 PM PDT 24
Finished Jun 04 01:58:30 PM PDT 24
Peak memory 210036 kb
Host smart-09af8410-ad5c-4c56-9cd9-0ff835291f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263539722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2263539722
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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