Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
58364 |
1 |
|
|
T1 |
715 |
|
T2 |
61 |
|
T3 |
845 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
35476 |
1 |
|
|
T1 |
552 |
|
T2 |
14 |
|
T3 |
636 |
auto[1] |
22888 |
1 |
|
|
T1 |
163 |
|
T2 |
47 |
|
T3 |
209 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
29301 |
1 |
|
|
T1 |
406 |
|
T2 |
31 |
|
T3 |
441 |
auto[1] |
29063 |
1 |
|
|
T1 |
309 |
|
T2 |
30 |
|
T3 |
404 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
17653 |
1 |
|
|
T1 |
311 |
|
T2 |
7 |
|
T3 |
334 |
all_values[0] |
auto[0] |
auto[1] |
17823 |
1 |
|
|
T1 |
241 |
|
T2 |
7 |
|
T3 |
302 |
all_values[0] |
auto[1] |
auto[0] |
11648 |
1 |
|
|
T1 |
95 |
|
T2 |
24 |
|
T3 |
107 |
all_values[0] |
auto[1] |
auto[1] |
11240 |
1 |
|
|
T1 |
68 |
|
T2 |
23 |
|
T3 |
102 |