Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4899

1

T1

34

T2

4

T3

63

auto[1]

544

1

T1

4

T3

3

T15

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4899

1

T1

34

T2

4

T3

63

auto[1]

544

1

T1

4

T3

3

T15

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4881

1

T1

36

T2

3

T3

61

auto[1]

562

1

T1

2

T2

1

T3

5

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4881

1

T1

36

T2

3

T3

61

auto[1]

562

1

T1

2

T2

1

T3

5

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	437	1			T1	5		T2	1		T3	2
auto[OpGenId]	1190	1			T1	10		T2	1		T3	20
auto[OpGenSwOut]	1184	1			T1	10		T3	24		T16	2
auto[OpGenHwOut]	2555	1			T1	12		T2	2		T3	18
auto[OpDisable]	77	1			T1	1		T3	2		T62	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	437	1			T1	5		T2	1		T3	2
auto[OpGenId]	1190	1			T1	10		T2	1		T3	20
auto[OpGenSwOut]	1184	1			T1	10		T3	24		T16	2
auto[OpGenHwOut]	2555	1			T1	12		T2	2		T3	18
auto[OpDisable]	77	1			T1	1		T3	2		T62	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4901

1

T1

34

T2

3

T3

59

auto[1]

542

1

T1

4

T2

1

T3

7

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4901

1

T1

34

T2

3

T3

59

auto[1]

542

1

T1

4

T2

1

T3

7

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5104

1

T1

38

T2

4

T3

66

auto[1]

339

1

T104

2

T113

14

T143

1

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1867	1			T1	17		T2	2		T3	23
auto[1]	696	1			T1	3		T2	1		T3	8
auto[2]	683	1			T1	7		T3	4		T13	2
auto[3]	704	1			T1	1		T2	1		T3	13
auto[4]	408	1			T1	3		T3	3		T15	1
auto[5]	387	1			T1	1		T3	2		T13	3
auto[6]	390	1			T3	7		T13	1		T14	1
auto[7]	308	1			T1	6		T3	6		T13	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1493	1			T1	10		T3	18		T13	5
clear_one[1]	696	1			T1	3		T2	1		T3	8
clear_one[2]	683	1			T1	7		T3	4		T13	2
clear_one[3]	704	1			T1	1		T2	1		T3	13
clear_none	1867	1			T1	17		T2	2		T3	23

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1028	1			T1	13		T2	2		T3	11
auto[StInit]	653	1			T1	7		T3	7		T13	1
auto[StCreatorRootKey]	585	1			T1	1		T3	9		T13	1
auto[StOwnerIntKey]	512	1			T1	3		T2	1		T3	6
auto[StOwnerKey]	482	1			T1	2		T3	6		T13	1
auto[StDisabled]	1880	1			T1	12		T2	1		T3	27
auto[StInvalid]	303	1			T39	3		T49	5		T96	6

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1028	1			T1	13		T2	2		T3	11
auto[StInit]	653	1			T1	7		T3	7		T13	1
auto[StCreatorRootKey]	585	1			T1	1		T3	9		T13	1
auto[StOwnerIntKey]	512	1			T1	3		T2	1		T3	6
auto[StOwnerKey]	482	1			T1	2		T3	6		T13	1
auto[StDisabled]	1880	1			T1	12		T2	1		T3	27
auto[StInvalid]	303	1			T39	3		T49	5		T96	6

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T231	1		T232	1		T233	1
auto[0]	auto[StReset]	auto[OpGenId]	165	1			T1	4		T2	1		T3	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	177	1			T1	2		T3	5		T17	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	256	1			T1	2		T2	1		T3	1
auto[0]	auto[StInit]	auto[OpAdvance]	37	1			T1	1		T195	1		T197	1
auto[0]	auto[StInit]	auto[OpGenId]	79	1			T3	1		T48	1		T113	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	94	1			T1	1		T3	1		T208	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	188	1			T1	3		T3	2		T17	2
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T3	1		T208	1		T5	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	58	1			T3	1		T234	1		T52	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	42	1			T3	1		T52	1		T235	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	69	1			T3	1		T17	1		T46	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T208	1		T52	1		T236	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	33	1			T130	1		T68	1		T4	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T3	1		T52	1		T237	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	49	1			T1	1		T3	1		T238	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T1	1		T131	1		T81	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	35	1			T124	1		T200	1		T190	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T61	1		T239	1		T72	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T204	1		T52	1		T240	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	43	1			T1	1		T195	1		T6	1
auto[0]	auto[StDisabled]	auto[OpGenId]	56	1			T3	1		T17	1		T124	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	79	1			T3	1		T143	2		T131	2
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	169	1			T3	2		T13	1		T14	1
auto[0]	auto[StDisabled]	auto[OpDisable]	19	1			T1	1		T3	1		T52	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	16	1			T206	1		T82	1		T241	1
auto[0]	auto[StInvalid]	auto[OpGenId]	22	1			T49	1		T96	2		T242	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	29	1			T39	1		T96	1		T50	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	24	1			T96	1		T50	1		T206	1
auto[1]	auto[StReset]	auto[OpGenId]	13	1			T3	1		T17	1		T31	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	13	1			T199	1		T52	1		T243	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	31	1			T13	1		T244	1		T186	1
auto[1]	auto[StInit]	auto[OpAdvance]	9	1			T38	1		T199	1		T216	1
auto[1]	auto[StInit]	auto[OpGenId]	16	1			T3	1		T245	1		T246	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	8	1			T16	1		T85	1		T72	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	22	1			T205	1		T4	1		T186	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	14	1			T133	1		T134	1		T23	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T3	1		T247	1		T245	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T193	1		T248	1		T52	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T15	1		T205	1		T244	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T4	1		T133	1		T134	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	19	1			T17	1		T249	1		T210	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T247	1		T250	2		T120	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	32	1			T1	1		T204	1		T244	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T104	1		T130	1		T21	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T133	1		T234	1		T251	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T133	1		T134	1		T251	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T205	1		T197	1		T252	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	28	1			T52	1		T253	1		T254	4
auto[1]	auto[StDisabled]	auto[OpGenId]	49	1			T208	2		T193	1		T255	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	53	1			T1	2		T3	5		T134	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	144	1			T2	1		T13	1		T15	1
auto[1]	auto[StDisabled]	auto[OpDisable]	12	1			T72	2		T256	1		T177	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T49	1		T257	1		T258	1
auto[1]	auto[StInvalid]	auto[OpGenId]	14	1			T83	1		T259	1		T260	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	17	1			T39	2		T50	2		T206	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T82	1		T261	1		T262	1
auto[2]	auto[StReset]	auto[OpGenId]	25	1			T1	2		T50	1		T131	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	18	1			T263	1		T264	1		T81	2
auto[2]	auto[StReset]	auto[OpGenHwOut]	50	1			T13	1		T15	1		T68	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T4	1		T27	1		T265	1
auto[2]	auto[StInit]	auto[OpGenId]	8	1			T27	1		T266	1		T267	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	11	1			T268	1		T147	1		T269	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T14	1		T264	1		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T126	1		T271	1		T222	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T58	1		T272	1		T89	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T190	1		T273	1		T5	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T14	1		T204	1		T207	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T3	1		T274	1		T179	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T197	1		T192	1		T231	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T126	1		T196	1		T275	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T13	1		T207	1		T252	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T202	1		T239	2		T276	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	16	1			T67	1		T277	1		T85	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T192	1		T278	1		T52	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T15	1		T79	1		T194	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	23	1			T1	1		T130	1		T131	1
auto[2]	auto[StDisabled]	auto[OpGenId]	53	1			T3	1		T126	1		T193	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T1	4		T192	1		T130	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	166	1			T3	2		T15	2		T104	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T62	1		T4	1		T52	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T50	1		T83	1		T258	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T42	1		T241	1		T279	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T280	1		T257	1		T262	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T49	1		T96	1		T281	1
auto[3]	auto[StReset]	auto[OpGenId]	20	1			T3	1		T52	1		T5	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	23	1			T17	1		T190	1		T282	2
auto[3]	auto[StReset]	auto[OpGenHwOut]	41	1			T3	1		T14	1		T79	3
auto[3]	auto[StInit]	auto[OpAdvance]	5	1			T113	1		T32	1		T254	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T3	1		T194	1		T69	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	8	1			T119	1		T283	1		T284	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	20	1			T79	1		T285	1		T286	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T263	1		T287	1		T288	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T197	1		T210	2		T72	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	20	1			T3	1		T16	1		T113	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T3	1		T17	1		T79	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T2	1		T263	1		T289	2
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	26	1			T201	1		T290	1		T6	2
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T17	1		T193	1		T5	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T14	1		T291	1		T183	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T16	1		T264	1		T177	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	23	1			T1	1		T3	1		T144	3
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T4	1		T292	1		T61	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T195	1		T203	1		T186	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	16	1			T132	1		T5	1		T210	1
auto[3]	auto[StDisabled]	auto[OpGenId]	61	1			T3	3		T124	1		T194	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T3	3		T193	1		T52	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	143	1			T3	1		T17	1		T79	1
auto[3]	auto[StDisabled]	auto[OpDisable]	13	1			T52	1		T293	1		T210	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	9	1			T280	1		T260	1		T294	1
auto[3]	auto[StInvalid]	auto[OpGenId]	13	1			T50	1		T51	1		T259	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T82	1		T259	1		T279	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T260	1		T295	1		T296	1
auto[4]	auto[StReset]	auto[OpAdvance]	2	1			T297	2		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	5	1			T17	1		T298	1		T299	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	11	1			T30	2		T300	1		T25	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	19	1			T15	1		T17	1		T79	1
auto[4]	auto[StInit]	auto[OpAdvance]	6	1			T6	1		T26	1		T25	1
auto[4]	auto[StInit]	auto[OpGenId]	11	1			T131	1		T247	1		T5	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T27	1		T301	1		T302	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	15	1			T1	1		T74	1		T157	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T113	1		T67	1		T277	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T1	1		T3	1		T256	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T196	1		T67	1		T303	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T144	2		T292	1		T263	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T81	1		T304	1		T122	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T144	1		T305	1		T306	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T87	1		T307	1		T223	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T205	1		T61	1		T120	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T308	1		T309	3		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	8	1			T58	1		T310	1		T74	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T4	1		T6	1		T311	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T17	1		T113	2		T312	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T133	1		T67	1		T313	2
auto[4]	auto[StDisabled]	auto[OpGenId]	41	1			T3	1		T104	1		T113	5
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T3	1		T113	2		T68	3
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	90	1			T1	1		T204	1		T207	1
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T71	1		T314	1		T77	2
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T315	1		T316	1		T317	1
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T281	1		T318	1		T296	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T96	1		T319	1		T320	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T84	1		T42	1		T321	1
auto[5]	auto[StReset]	auto[OpGenId]	12	1			T104	1		T291	1		T248	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	13	1			T38	1		T243	1		T210	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	33	1			T205	1		T244	1		T131	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T1	1		T133	2		-	-
auto[5]	auto[StInit]	auto[OpGenId]	10	1			T291	1		T6	1		T322	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T23	1		T323	1		T324	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	8	1			T235	1		T243	1		T66	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T277	1		T233	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T48	1		T133	1		T6	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T5	1		T75	1		T267	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T13	1		T203	1		T210	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T255	1		T233	1		T324	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T195	1		T202	1		T325	2
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T184	1		T54	1		T325	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T15	1		T79	1		T4	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T263	1		T250	1		T306	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T3	1		T210	1		T326	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T210	1		T327	1		T91	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T143	1		T68	1		T328	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	15	1			T130	2		T144	1		T6	1
auto[5]	auto[StDisabled]	auto[OpGenId]	22	1			T16	1		T144	2		T134	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T3	1		T17	2		T197	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	86	1			T13	2		T14	1		T15	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T329	1		T330	1		T77	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	7	1			T241	1		T259	1		T279	2
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T331	1		T332	1		T333	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T82	1		T83	1		T262	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T49	1		T83	1		T280	2
auto[6]	auto[StReset]	auto[OpGenId]	13	1			T50	1		T255	1		T283	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	15	1			T190	1		T121	1		T295	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	25	1			T15	1		T203	1		T58	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T144	1		T334	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T210	1		T335	1		T164	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T58	1		T188	1		T336	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	15	1			T3	1		T13	1		T278	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T337	1		T305	1		T226	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T338	1		T339	1		T340	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T193	1		T52	1		T341	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T186	1		T6	1		T342	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T253	1		T343	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T62	1		T6	1		T209	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T3	1		T292	1		T344	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T186	1		T345	1		T346	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T253	1		T67	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	9	1			T3	1		T246	1		T210	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T52	1		T243	1		T127	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T3	1		T207	1		T347	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T144	1		T253	2		T231	1
auto[6]	auto[StDisabled]	auto[OpGenId]	32	1			T133	2		T52	1		T253	2
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T3	1		T291	1		T133	3
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	92	1			T3	1		T14	1		T79	3
auto[6]	auto[StDisabled]	auto[OpDisable]	9	1			T3	1		T348	1		T349	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	1	1			T350	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T279	1		T261	1		T316	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T296	1		T351	1		T352	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T49	1		T353	1		T320	1
auto[7]	auto[StReset]	auto[OpGenId]	9	1			T1	1		T52	1		T268	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	11	1			T61	1		T210	1		T282	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	25	1			T1	2		T183	1		T186	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T132	1		T354	1		T355	1
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T329	1		T356	1		T223	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T273	1		T210	1		T357	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	7	1			T15	1		T203	1		T358	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T329	1		T230	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T5	1		T359	1		T360	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T195	1		T361	1		T156	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T3	1		T278	1		T183	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T272	1		T157	1		T362	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T3	1		T72	1		T363	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T194	1		T210	1		T364	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T1	1		T3	1		T203	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T329	1		T127	1		T365	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T72	1		T88	1		T337	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T3	2		T69	1		T210	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T13	1		T14	1		T68	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	10	1			T132	1		T185	1		T6	1
auto[7]	auto[StDisabled]	auto[OpGenId]	20	1			T1	1		T201	1		T52	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T1	1		T194	1		T131	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	65	1			T3	1		T14	1		T17	1
auto[7]	auto[StDisabled]	auto[OpDisable]	2	1			T74	1		T77	1		-	-
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T366	1		T367	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	10	1			T206	1		T368	2		T369	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T80	1		T370	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T80	1		T370	1		T321	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1493

1

T1

10

T3

18

T13

5

clear_one[1]

auto[0]

auto[0]

auto[0]

392

1

T1

2

T3

5

T13

1

clear_one[1]

auto[0]

auto[0]

auto[1]

136

1

T3

3

T208

2

T193

1

clear_one[1]

auto[0]

auto[1]

auto[0]

130

1

T1

1

T13

1

T104

1

clear_one[1]

auto[0]

auto[1]

auto[1]

38

1

T2

1

T104

2

T21

1

clear_one[2]

auto[0]

auto[0]

auto[0]

397

1

T1

3

T3

3

T13

2

clear_one[2]

auto[0]

auto[0]

auto[1]

124

1

T1

1

T3

1

T207

3

clear_one[2]

auto[1]

auto[0]

auto[0]

124

1

T1

2

T15

3

T79

1

clear_one[2]

auto[1]

auto[0]

auto[1]

38

1

T1

1

T195

1

T192

4

clear_one[3]

auto[0]

auto[0]

auto[0]

433

1

T2

1

T3

9

T14

1

clear_one[3]

auto[0]

auto[1]

auto[0]

113

1

T3

2

T14

1

T205

1

clear_one[3]

auto[1]

auto[0]

auto[0]

122

1

T1

1

T3

2

T17

2

clear_one[3]

auto[1]

auto[1]

auto[0]

36

1

T124

1

T52

1

T134

1

clear_none

auto[0]

auto[0]

auto[0]

1344

1

T1

14

T2

2

T3

17

clear_none

auto[0]

auto[0]

auto[1]

116

1

T1

2

T3

2

T207

1

clear_none

auto[0]

auto[1]

auto[0]

132

1

T1

1

T3

3

T13

1

clear_none

auto[0]

auto[1]

auto[1]

51

1

T200

1

T371

1

T255

1

clear_none

auto[1]

auto[0]

auto[0]

141

1

T17

2

T194

1

T372

3

clear_none

auto[1]

auto[0]

auto[1]

21

1

T3

1

T185

1

T273

1

clear_none

auto[1]

auto[1]

auto[0]

44

1

T124

2

T46

1

T6

2

clear_none

auto[1]

auto[1]

auto[1]

18

1

T52

1

T5

1

T23

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1393	1			T1	10		T3	18		T13	5
clear_all	auto[1]	100	1			T113	13		T130	1		T144	8
clear_one[1]	auto[0]	618	1			T1	3		T2	1		T3	8
clear_one[1]	auto[1]	78	1			T104	2		T133	3		T253	4
clear_one[2]	auto[0]	652	1			T1	7		T3	4		T13	2
clear_one[2]	auto[1]	31	1			T130	1		T231	1		T263	1
clear_one[3]	auto[0]	661	1			T1	1		T2	1		T3	13
clear_one[3]	auto[1]	43	1			T113	1		T144	2		T263	2
clear_none	auto[0]	1780	1			T1	17		T2	2		T3	23
clear_none	auto[1]	87	1			T143	1		T130	1		T131	1