Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10970

1

T1

102

T2

16

T3

152

auto[Attestation]

7794

1

T1

137

T2

6

T3

126

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2783	1			T1	37		T2	4		T3	50
auto[Aes]	3394	1			T1	43		T2	3		T3	53
auto[Kmac]	3329	1			T1	42		T2	3		T3	41
auto[Otbn]	3334	1			T1	39		T2	3		T3	43

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7743	1			T1	65		T2	8		T3	121
auto[OpGenId]	5924	1			T1	78		T2	9		T3	91
auto[OpGenSwOut]	5939	1			T1	86		T2	5		T3	106
auto[OpGenHwOut]	6901	1			T1	75		T2	8		T3	81
auto[OpDisable]	153	1			T1	3		T3	2		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10690

1

T1

103

T2

12

T3

153

auto[OpDoneFail]

15970

1

T1

204

T2

18

T3

248

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6542	1			T1	91		T2	8		T3	76
auto[StInit]	3763	1			T1	40		T2	3		T3	45
auto[StCreatorRootKey]	3212	1			T1	27		T2	3		T3	41
auto[StOwnerIntKey]	2780	1			T1	28		T2	1		T3	42
auto[StOwnerKey]	2419	1			T1	27		T2	6		T3	42
auto[StDisabled]	7944	1			T1	94		T2	9		T3	155

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	355	1			T1	4		T3	9		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	108	1			T3	3		T17	2		T123	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	67	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	73	1			T3	1		T190	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	41	1			T191	1		T192	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	233	1			T1	1		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	337	1			T1	2		T2	1		T3	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	96	1			T193	1		T68	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	79	1			T2	1		T3	3		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	67	1			T3	1		T126	1		T144	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	51	1			T1	1		T3	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	224	1			T1	3		T3	10		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	321	1			T1	4		T3	3		T17	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	103	1			T1	3		T16	1		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T17	1		T125	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T17	2		T194	1		T113	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	50	1			T1	2		T124	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	229	1			T1	2		T3	5		T125	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	301	1			T1	2		T2	1		T3	5
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	99	1			T3	3		T196	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T1	2		T16	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	54	1			T1	1		T16	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	50	1			T3	1		T17	1		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	218	1			T1	5		T3	4		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	77	1			T1	5		T3	3		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	115	1			T1	3		T3	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	87	1			T1	1		T3	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	69	1			T3	1		T16	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T3	1		T125	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	233	1			T1	4		T3	5		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	91	1			T1	4		T3	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	103	1			T1	2		T16	1		T123	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	68	1			T3	2		T124	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	72	1			T3	3		T17	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	65	1			T17	2		T200	1		T193	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	251	1			T1	4		T3	9		T17	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	89	1			T1	5		T3	2		T17	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	95	1			T1	2		T3	2		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	89	1			T1	1		T3	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	71	1			T1	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	52	1			T1	3		T3	1		T104	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	226	1			T1	4		T3	7		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	106	1			T1	5		T3	3		T193	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	98	1			T1	2		T3	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	78	1			T1	2		T3	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	68	1			T1	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	63	1			T3	2		T200	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	201	1			T1	4		T3	2		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	283	1			T1	2		T2	1		T3	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	80	1			T17	1		T105	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	84	1			T1	1		T104	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	52	1			T1	1		T3	3		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T3	3		T17	2		T143	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	185	1			T1	2		T3	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	483	1			T3	3		T15	13		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	112	1			T3	3		T17	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	115	1			T1	1		T3	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	97	1			T1	3		T15	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	75	1			T1	1		T3	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	266	1			T1	5		T3	5		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	422	1			T3	2		T13	9		T14	6
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T1	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	104	1			T1	2		T3	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	102	1			T3	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	85	1			T2	1		T3	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	268	1			T1	3		T3	5		T13	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	474	1			T1	1		T2	1		T3	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T1	1		T17	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T3	3		T192	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	105	1			T1	3		T3	2		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	74	1			T3	2		T202	2		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	267	1			T1	3		T2	1		T3	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	52	1			T1	7		T3	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	99	1			T1	1		T3	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T37	1		T199	2		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	66	1			T3	2		T17	1		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T3	1		T200	1		T143	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	181	1			T1	4		T2	1		T3	5
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T1	4		T3	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	113	1			T1	5		T2	1		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	103	1			T15	1		T17	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	89	1			T1	1		T143	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	89	1			T1	3		T17	2		T123	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	291	1			T1	4		T3	5		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	72	1			T1	2		T3	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	118	1			T1	2		T3	1		T56	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T204	1		T46	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T1	2		T3	3		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	88	1			T2	2		T13	1		T123	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	265	1			T1	3		T3	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	53	1			T1	4		T17	3		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	139	1			T3	2		T39	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T207	1		T4	1		T52	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T1	2		T196	1		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	77	1			T1	1		T123	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	286	1			T3	7		T104	2		T208	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	170	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	707	1			T1	5		T2	1		T3	15
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	183	1			T1	1		T2	1		T3	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	671	1			T1	5		T2	1		T3	14
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	194	1			T1	1		T17	2		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	671	1			T1	10		T3	8		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	182	1			T1	3		T16	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	635	1			T1	7		T2	1		T3	13
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	196	1			T1	1		T3	4		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	444	1			T1	12		T3	9		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	192	1			T3	5		T17	3		T124	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	458	1			T1	10		T3	10		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	194	1			T1	5		T3	3		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	428	1			T1	11		T3	11		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T1	3		T3	3		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	421	1			T1	11		T3	6		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	184	1			T1	2		T3	6		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	560	1			T1	4		T2	1		T3	5
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	273	1			T1	4		T3	2		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	875	1			T1	6		T3	11		T15	15
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	272	1			T1	1		T2	1		T3	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	827	1			T1	5		T3	9		T13	13
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	279	1			T1	2		T3	6		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	865	1			T1	6		T2	2		T3	6
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	176	1			T3	3		T17	1		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	346	1			T1	12		T2	1		T3	7
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	263	1			T1	4		T15	1		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	479	1			T1	13		T2	1		T3	7
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	276	1			T1	2		T2	2		T3	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	467	1			T1	7		T3	6		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T1	3		T123	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	492	1			T1	4		T3	9		T17	3