Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32816

1

T1

342

T2

35

T3

461

auto[1]

289

1

T104

2

T113

13

T143

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32830	1			T1	342		T2	35		T3	461
auto[134217728:268435455]	8	1			T104	1		T143	1		T239	1
auto[268435456:402653183]	8	1			T130	1		T251	1		T289	1
auto[402653184:536870911]	9	1			T133	1		T379	1		T357	1
auto[536870912:671088639]	11	1			T113	2		T132	1		T344	1
auto[671088640:805306367]	9	1			T133	1		T263	1		T254	1
auto[805306368:939524095]	6	1			T131	1		T133	1		T254	1
auto[939524096:1073741823]	8	1			T133	1		T263	1		T254	1
auto[1073741824:1207959551]	4	1			T392	1		T393	1		T394	1
auto[1207959552:1342177279]	7	1			T133	1		T289	2		T395	1
auto[1342177280:1476395007]	15	1			T133	1		T253	1		T231	1
auto[1476395008:1610612735]	11	1			T130	1		T250	1		T239	2
auto[1610612736:1744830463]	6	1			T133	1		T253	1		T239	1
auto[1744830464:1879048191]	10	1			T113	2		T133	2		T250	1
auto[1879048192:2013265919]	5	1			T113	1		T132	1		T254	1
auto[2013265920:2147483647]	12	1			T144	2		T133	2		T231	1
auto[2147483648:2281701375]	10	1			T144	1		T251	1		T380	1
auto[2281701376:2415919103]	9	1			T130	1		T133	1		T253	1
auto[2415919104:2550136831]	11	1			T263	1		T239	3		T396	1
auto[2550136832:2684354559]	12	1			T254	1		T251	1		T287	1
auto[2684354560:2818572287]	6	1			T113	2		T231	1		T313	1
auto[2818572288:2952790015]	7	1			T113	1		T144	1		T253	1
auto[2952790016:3087007743]	18	1			T113	3		T133	1		T254	2
auto[3087007744:3221225471]	5	1			T239	1		T396	1		T289	1
auto[3221225472:3355443199]	5	1			T133	1		T263	1		T254	1
auto[3355443200:3489660927]	8	1			T253	1		T251	1		T239	1
auto[3489660928:3623878655]	6	1			T144	1		T133	1		T397	2
auto[3623878656:3758096383]	6	1			T104	1		T396	1		T398	1
auto[3758096384:3892314111]	14	1			T144	1		T131	2		T133	1
auto[3892314112:4026531839]	7	1			T287	1		T396	1		T313	1
auto[4026531840:4160749567]	9	1			T144	1		T133	2		T251	1
auto[4160749568:4294967295]	13	1			T144	1		T253	1		T250	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32816	1			T1	342		T2	35		T3	461
auto[0:134217727]	auto[1]	14	1			T113	2		T133	1		T253	1
auto[134217728:268435455]	auto[1]	8	1			T104	1		T143	1		T239	1
auto[268435456:402653183]	auto[1]	8	1			T130	1		T251	1		T289	1
auto[402653184:536870911]	auto[1]	9	1			T133	1		T379	1		T357	1
auto[536870912:671088639]	auto[1]	11	1			T113	2		T132	1		T344	1
auto[671088640:805306367]	auto[1]	9	1			T133	1		T263	1		T254	1
auto[805306368:939524095]	auto[1]	6	1			T131	1		T133	1		T254	1
auto[939524096:1073741823]	auto[1]	8	1			T133	1		T263	1		T254	1
auto[1073741824:1207959551]	auto[1]	4	1			T392	1		T393	1		T394	1
auto[1207959552:1342177279]	auto[1]	7	1			T133	1		T289	2		T395	1
auto[1342177280:1476395007]	auto[1]	15	1			T133	1		T253	1		T231	1
auto[1476395008:1610612735]	auto[1]	11	1			T130	1		T250	1		T239	2
auto[1610612736:1744830463]	auto[1]	6	1			T133	1		T253	1		T239	1
auto[1744830464:1879048191]	auto[1]	10	1			T113	2		T133	2		T250	1
auto[1879048192:2013265919]	auto[1]	5	1			T113	1		T132	1		T254	1
auto[2013265920:2147483647]	auto[1]	12	1			T144	2		T133	2		T231	1
auto[2147483648:2281701375]	auto[1]	10	1			T144	1		T251	1		T380	1
auto[2281701376:2415919103]	auto[1]	9	1			T130	1		T133	1		T253	1
auto[2415919104:2550136831]	auto[1]	11	1			T263	1		T239	3		T396	1
auto[2550136832:2684354559]	auto[1]	12	1			T254	1		T251	1		T287	1
auto[2684354560:2818572287]	auto[1]	6	1			T113	2		T231	1		T313	1
auto[2818572288:2952790015]	auto[1]	7	1			T113	1		T144	1		T253	1
auto[2952790016:3087007743]	auto[1]	18	1			T113	3		T133	1		T254	2
auto[3087007744:3221225471]	auto[1]	5	1			T239	1		T396	1		T289	1
auto[3221225472:3355443199]	auto[1]	5	1			T133	1		T263	1		T254	1
auto[3355443200:3489660927]	auto[1]	8	1			T253	1		T251	1		T239	1
auto[3489660928:3623878655]	auto[1]	6	1			T144	1		T133	1		T397	2
auto[3623878656:3758096383]	auto[1]	6	1			T104	1		T396	1		T398	1
auto[3758096384:3892314111]	auto[1]	14	1			T144	1		T131	2		T133	1
auto[3892314112:4026531839]	auto[1]	7	1			T287	1		T396	1		T313	1
auto[4026531840:4160749567]	auto[1]	9	1			T144	1		T133	2		T251	1
auto[4160749568:4294967295]	auto[1]	13	1			T144	1		T253	1		T250	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1680

1

T1

30

T2

3

T3

18

auto[1]

1753

1

T1

25

T2

2

T3

26

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T1	1		T17	1		T47	1
auto[134217728:268435455]	95	1			T2	1		T192	1		T47	1
auto[268435456:402653183]	116	1			T1	2		T3	1		T17	1
auto[402653184:536870911]	106	1			T1	3		T3	1		T202	2
auto[536870912:671088639]	121	1			T1	2		T3	2		T123	1
auto[671088640:805306367]	124	1			T2	1		T3	1		T31	1
auto[805306368:939524095]	112	1			T1	3		T3	2		T17	1
auto[939524096:1073741823]	123	1			T1	1		T3	3		T16	1
auto[1073741824:1207959551]	96	1			T1	6		T3	1		T17	1
auto[1207959552:1342177279]	93	1			T1	3		T16	1		T17	1
auto[1342177280:1476395007]	97	1			T1	2		T2	1		T3	1
auto[1476395008:1610612735]	100	1			T1	2		T126	1		T193	1
auto[1610612736:1744830463]	97	1			T1	1		T3	1		T104	1
auto[1744830464:1879048191]	110	1			T1	1		T3	1		T16	1
auto[1879048192:2013265919]	104	1			T1	2		T16	1		T38	1
auto[2013265920:2147483647]	104	1			T1	1		T3	2		T104	1
auto[2147483648:2281701375]	103	1			T3	2		T123	1		T38	1
auto[2281701376:2415919103]	89	1			T1	2		T2	1		T3	1
auto[2415919104:2550136831]	122	1			T1	4		T3	1		T39	2
auto[2550136832:2684354559]	118	1			T1	1		T17	1		T104	1
auto[2684354560:2818572287]	98	1			T1	2		T3	3		T123	1
auto[2818572288:2952790015]	106	1			T1	3		T3	2		T17	1
auto[2952790016:3087007743]	111	1			T1	1		T3	2		T208	1
auto[3087007744:3221225471]	103	1			T3	1		T208	1		T195	1
auto[3221225472:3355443199]	117	1			T1	1		T3	3		T124	1
auto[3355443200:3489660927]	116	1			T3	2		T208	1		T46	1
auto[3489660928:3623878655]	107	1			T1	1		T3	2		T47	1
auto[3623878656:3758096383]	120	1			T1	2		T3	1		T16	1
auto[3758096384:3892314111]	96	1			T1	2		T124	1		T46	1
auto[3892314112:4026531839]	99	1			T1	1		T3	1		T17	1
auto[4026531840:4160749567]	121	1			T1	3		T3	2		T193	1
auto[4160749568:4294967295]	98	1			T1	2		T2	1		T3	5

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T1	1		T17	1		T4	1
auto[0:134217727]	auto[1]	57	1			T47	1		T144	1		T206	1
auto[134217728:268435455]	auto[0]	47	1			T2	1		T49	2		T68	1
auto[134217728:268435455]	auto[1]	48	1			T192	1		T47	1		T5	1
auto[268435456:402653183]	auto[0]	55	1			T1	1		T17	1		T208	1
auto[268435456:402653183]	auto[1]	61	1			T1	1		T3	1		T197	1
auto[402653184:536870911]	auto[0]	43	1			T1	1		T3	1		T202	1
auto[402653184:536870911]	auto[1]	63	1			T1	2		T202	1		T131	1
auto[536870912:671088639]	auto[0]	64	1			T3	1		T123	1		T249	1
auto[536870912:671088639]	auto[1]	57	1			T1	2		T3	1		T48	1
auto[671088640:805306367]	auto[0]	59	1			T2	1		T31	1		T197	1
auto[671088640:805306367]	auto[1]	65	1			T3	1		T200	1		T68	1
auto[805306368:939524095]	auto[0]	55	1			T3	2		T17	1		T143	1
auto[805306368:939524095]	auto[1]	57	1			T1	3		T55	1		T51	1
auto[939524096:1073741823]	auto[0]	52	1			T3	1		T47	1		T49	1
auto[939524096:1073741823]	auto[1]	71	1			T1	1		T3	2		T16	1
auto[1073741824:1207959551]	auto[0]	38	1			T1	4		T17	1		T38	1
auto[1073741824:1207959551]	auto[1]	58	1			T1	2		T3	1		T47	1
auto[1207959552:1342177279]	auto[0]	45	1			T1	1		T38	1		T49	1
auto[1207959552:1342177279]	auto[1]	48	1			T1	2		T16	1		T17	1
auto[1342177280:1476395007]	auto[0]	44	1			T3	1		T124	1		T4	1
auto[1342177280:1476395007]	auto[1]	53	1			T1	2		T2	1		T104	1
auto[1476395008:1610612735]	auto[0]	52	1			T1	1		T193	1		T131	1
auto[1476395008:1610612735]	auto[1]	48	1			T1	1		T126	1		T371	1
auto[1610612736:1744830463]	auto[0]	51	1			T3	1		T193	1		T96	1
auto[1610612736:1744830463]	auto[1]	46	1			T1	1		T104	1		T39	1
auto[1744830464:1879048191]	auto[0]	56	1			T3	1		T4	2		T399	1
auto[1744830464:1879048191]	auto[1]	54	1			T1	1		T16	1		T126	1
auto[1879048192:2013265919]	auto[0]	51	1			T1	2		T47	1		T55	1
auto[1879048192:2013265919]	auto[1]	53	1			T16	1		T38	1		T143	1
auto[2013265920:2147483647]	auto[0]	54	1			T1	1		T3	1		T104	1
auto[2013265920:2147483647]	auto[1]	50	1			T3	1		T46	1		T195	1
auto[2147483648:2281701375]	auto[0]	53	1			T38	1		T200	1		T52	1
auto[2147483648:2281701375]	auto[1]	50	1			T3	2		T123	1		T68	1
auto[2281701376:2415919103]	auto[0]	44	1			T1	2		T2	1		T195	1
auto[2281701376:2415919103]	auto[1]	45	1			T3	1		T143	1		T4	1
auto[2415919104:2550136831]	auto[0]	56	1			T1	3		T39	2		T50	1
auto[2415919104:2550136831]	auto[1]	66	1			T1	1		T3	1		T49	1
auto[2550136832:2684354559]	auto[0]	61	1			T1	1		T17	1		T4	1
auto[2550136832:2684354559]	auto[1]	57	1			T104	1		T124	1		T200	1
auto[2684354560:2818572287]	auto[0]	44	1			T1	1		T199	1		T131	1
auto[2684354560:2818572287]	auto[1]	54	1			T1	1		T3	3		T123	1
auto[2818572288:2952790015]	auto[0]	53	1			T1	2		T3	1		T17	1
auto[2818572288:2952790015]	auto[1]	53	1			T1	1		T3	1		T126	1
auto[2952790016:3087007743]	auto[0]	52	1			T1	1		T3	1		T208	1
auto[2952790016:3087007743]	auto[1]	59	1			T3	1		T46	1		T195	1
auto[3087007744:3221225471]	auto[0]	57	1			T3	1		T208	1		T195	1
auto[3087007744:3221225471]	auto[1]	46	1			T193	1		T62	1		T4	1
auto[3221225472:3355443199]	auto[0]	51	1			T1	1		T3	1		T192	2
auto[3221225472:3355443199]	auto[1]	66	1			T3	2		T124	1		T195	1
auto[3355443200:3489660927]	auto[0]	66	1			T3	1		T199	1		T68	1
auto[3355443200:3489660927]	auto[1]	50	1			T3	1		T208	1		T46	1
auto[3489660928:3623878655]	auto[0]	54	1			T3	1		T199	1		T20	1
auto[3489660928:3623878655]	auto[1]	53	1			T1	1		T3	1		T47	1
auto[3623878656:3758096383]	auto[0]	64	1			T1	2		T50	1		T4	1
auto[3623878656:3758096383]	auto[1]	56	1			T3	1		T16	1		T126	1
auto[3758096384:3892314111]	auto[0]	49	1			T1	1		T46	1		T206	1
auto[3758096384:3892314111]	auto[1]	47	1			T1	1		T124	1		T249	1
auto[3892314112:4026531839]	auto[0]	48	1			T1	1		T31	1		T130	1
auto[3892314112:4026531839]	auto[1]	51	1			T3	1		T17	1		T104	1
auto[4026531840:4160749567]	auto[0]	60	1			T1	2		T3	1		T193	1
auto[4026531840:4160749567]	auto[1]	61	1			T1	1		T3	1		T55	1
auto[4160749568:4294967295]	auto[0]	48	1			T1	1		T3	2		T39	1
auto[4160749568:4294967295]	auto[1]	50	1			T1	1		T2	1		T3	3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1653

1

T1

29

T2

3

T3

12

auto[1]

1779

1

T1

26

T2

2

T3

32

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T1	3		T48	1		T38	1
auto[134217728:268435455]	93	1			T1	3		T3	1		T104	1
auto[268435456:402653183]	107	1			T1	2		T3	1		T46	1
auto[402653184:536870911]	120	1			T3	3		T208	1		T195	1
auto[536870912:671088639]	104	1			T1	1		T3	3		T16	1
auto[671088640:805306367]	94	1			T1	2		T2	1		T104	1
auto[805306368:939524095]	108	1			T3	1		T16	1		T17	1
auto[939524096:1073741823]	110	1			T1	3		T123	2		T31	1
auto[1073741824:1207959551]	108	1			T3	3		T208	1		T195	1
auto[1207959552:1342177279]	113	1			T1	3		T3	1		T195	1
auto[1342177280:1476395007]	107	1			T1	1		T3	4		T197	1
auto[1476395008:1610612735]	115	1			T1	1		T3	1		T16	1
auto[1610612736:1744830463]	90	1			T1	1		T49	1		T132	1
auto[1744830464:1879048191]	95	1			T126	1		T200	1		T20	1
auto[1879048192:2013265919]	115	1			T1	4		T3	1		T38	1
auto[2013265920:2147483647]	121	1			T1	2		T2	1		T3	1
auto[2147483648:2281701375]	117	1			T1	1		T3	1		T104	1
auto[2281701376:2415919103]	112	1			T1	2		T3	2		T17	2
auto[2415919104:2550136831]	112	1			T1	2		T17	1		T126	1
auto[2550136832:2684354559]	109	1			T1	2		T3	1		T104	1
auto[2684354560:2818572287]	101	1			T1	1		T3	1		T48	1
auto[2818572288:2952790015]	87	1			T1	2		T3	1		T38	1
auto[2952790016:3087007743]	119	1			T2	1		T3	1		T16	1
auto[3087007744:3221225471]	120	1			T1	3		T3	2		T126	1
auto[3221225472:3355443199]	109	1			T1	1		T2	1		T3	2
auto[3355443200:3489660927]	87	1			T1	2		T39	1		T196	1
auto[3489660928:3623878655]	114	1			T1	2		T2	1		T3	2
auto[3623878656:3758096383]	114	1			T1	2		T3	1		T124	2
auto[3758096384:3892314111]	110	1			T1	4		T3	5		T104	1
auto[3892314112:4026531839]	115	1			T1	1		T3	3		T48	1
auto[4026531840:4160749567]	92	1			T1	1		T3	1		T17	1
auto[4160749568:4294967295]	115	1			T1	3		T3	1		T17	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T1	2		T38	1		T47	1
auto[0:134217727]	auto[1]	53	1			T1	1		T48	1		T55	1
auto[134217728:268435455]	auto[0]	46	1			T1	2		T4	1		T400	1
auto[134217728:268435455]	auto[1]	47	1			T1	1		T3	1		T104	1
auto[268435456:402653183]	auto[0]	51	1			T1	1		T82	1		T185	1
auto[268435456:402653183]	auto[1]	56	1			T1	1		T3	1		T46	1
auto[402653184:536870911]	auto[0]	59	1			T3	1		T20	1		T50	1
auto[402653184:536870911]	auto[1]	61	1			T3	2		T208	1		T195	1
auto[536870912:671088639]	auto[0]	54	1			T1	1		T3	1		T31	1
auto[536870912:671088639]	auto[1]	50	1			T3	2		T16	1		T47	1
auto[671088640:805306367]	auto[0]	43	1			T1	1		T104	1		T47	1
auto[671088640:805306367]	auto[1]	51	1			T1	1		T2	1		T113	1
auto[805306368:939524095]	auto[0]	54	1			T3	1		T17	1		T4	1
auto[805306368:939524095]	auto[1]	54	1			T16	1		T126	1		T49	1
auto[939524096:1073741823]	auto[0]	53	1			T1	1		T123	1		T31	1
auto[939524096:1073741823]	auto[1]	57	1			T1	2		T123	1		T46	1
auto[1073741824:1207959551]	auto[0]	53	1			T3	1		T47	1		T199	1
auto[1073741824:1207959551]	auto[1]	55	1			T3	2		T208	1		T195	1
auto[1207959552:1342177279]	auto[0]	52	1			T1	2		T3	1		T49	1
auto[1207959552:1342177279]	auto[1]	61	1			T1	1		T195	1		T192	1
auto[1342177280:1476395007]	auto[0]	54	1			T3	1		T197	1		T4	2
auto[1342177280:1476395007]	auto[1]	53	1			T1	1		T3	3		T193	1
auto[1476395008:1610612735]	auto[0]	55	1			T1	1		T38	1		T49	1
auto[1476395008:1610612735]	auto[1]	60	1			T3	1		T16	1		T133	1
auto[1610612736:1744830463]	auto[0]	45	1			T1	1		T52	4		T134	1
auto[1610612736:1744830463]	auto[1]	45	1			T49	1		T132	1		T52	1
auto[1744830464:1879048191]	auto[0]	40	1			T200	1		T20	1		T62	1
auto[1744830464:1879048191]	auto[1]	55	1			T126	1		T4	1		T52	1
auto[1879048192:2013265919]	auto[0]	59	1			T1	2		T38	1		T193	1
auto[1879048192:2013265919]	auto[1]	56	1			T1	2		T3	1		T202	1
auto[2013265920:2147483647]	auto[0]	61	1			T1	2		T2	1		T195	1
auto[2013265920:2147483647]	auto[1]	60	1			T3	1		T21	1		T371	1
auto[2147483648:2281701375]	auto[0]	58	1			T104	1		T208	2		T49	1
auto[2147483648:2281701375]	auto[1]	59	1			T1	1		T3	1		T130	1
auto[2281701376:2415919103]	auto[0]	48	1			T1	1		T3	1		T199	1
auto[2281701376:2415919103]	auto[1]	64	1			T1	1		T3	1		T17	2
auto[2415919104:2550136831]	auto[0]	57	1			T1	2		T17	1		T46	1
auto[2415919104:2550136831]	auto[1]	55	1			T126	1		T199	1		T131	1
auto[2550136832:2684354559]	auto[0]	49	1			T1	1		T39	1		T192	1
auto[2550136832:2684354559]	auto[1]	60	1			T1	1		T3	1		T104	1
auto[2684354560:2818572287]	auto[0]	46	1			T197	1		T52	1		T399	1
auto[2684354560:2818572287]	auto[1]	55	1			T1	1		T3	1		T48	1
auto[2818572288:2952790015]	auto[0]	47	1			T38	1		T199	1		T4	1
auto[2818572288:2952790015]	auto[1]	40	1			T1	2		T3	1		T202	1
auto[2952790016:3087007743]	auto[0]	53	1			T2	1		T4	1		T52	2
auto[2952790016:3087007743]	auto[1]	66	1			T3	1		T16	1		T17	1
auto[3087007744:3221225471]	auto[0]	55	1			T39	1		T50	1		T51	1
auto[3087007744:3221225471]	auto[1]	65	1			T1	3		T3	2		T126	1
auto[3221225472:3355443199]	auto[0]	53	1			T2	1		T3	1		T17	1
auto[3221225472:3355443199]	auto[1]	56	1			T1	1		T3	1		T16	1
auto[3355443200:3489660927]	auto[0]	47	1			T1	1		T55	1		T50	1
auto[3355443200:3489660927]	auto[1]	40	1			T1	1		T39	1		T196	1
auto[3489660928:3623878655]	auto[0]	58	1			T1	2		T46	1		T192	1
auto[3489660928:3623878655]	auto[1]	56	1			T2	1		T3	2		T124	1
auto[3623878656:3758096383]	auto[0]	53	1			T1	1		T124	1		T199	1
auto[3623878656:3758096383]	auto[1]	61	1			T1	1		T3	1		T124	1
auto[3758096384:3892314111]	auto[0]	52	1			T1	2		T3	1		T202	1
auto[3758096384:3892314111]	auto[1]	58	1			T1	2		T3	4		T104	1
auto[3892314112:4026531839]	auto[0]	59	1			T3	1		T143	1		T68	2
auto[3892314112:4026531839]	auto[1]	56	1			T1	1		T3	2		T48	1
auto[4026531840:4160749567]	auto[0]	41	1			T1	1		T3	1		T17	1
auto[4026531840:4160749567]	auto[1]	51	1			T4	1		T82	1		T231	1
auto[4160749568:4294967295]	auto[0]	52	1			T1	2		T3	1		T123	1
auto[4160749568:4294967295]	auto[1]	63	1			T1	1		T17	1		T200	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1675

1

T1

26

T2

3

T3

19

auto[1]

1758

1

T1

29

T2

2

T3

25

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	125	1			T1	1		T3	2		T200	1
auto[134217728:268435455]	89	1			T1	1		T3	1		T17	1
auto[268435456:402653183]	109	1			T1	2		T3	3		T31	1
auto[402653184:536870911]	110	1			T3	1		T197	1		T192	2
auto[536870912:671088639]	111	1			T1	2		T3	1		T16	2
auto[671088640:805306367]	102	1			T1	4		T3	1		T199	1
auto[805306368:939524095]	112	1			T1	1		T3	1		T16	1
auto[939524096:1073741823]	98	1			T1	2		T3	1		T195	1
auto[1073741824:1207959551]	105	1			T1	3		T124	1		T126	2
auto[1207959552:1342177279]	106	1			T1	2		T3	2		T16	1
auto[1342177280:1476395007]	109	1			T1	2		T17	1		T104	1
auto[1476395008:1610612735]	113	1			T1	4		T2	1		T3	2
auto[1610612736:1744830463]	118	1			T3	1		T208	1		T202	1
auto[1744830464:1879048191]	93	1			T1	1		T3	1		T104	1
auto[1879048192:2013265919]	99	1			T1	1		T3	5		T104	1
auto[2013265920:2147483647]	101	1			T1	1		T2	1		T3	1
auto[2147483648:2281701375]	110	1			T1	1		T3	1		T68	1
auto[2281701376:2415919103]	108	1			T3	2		T123	1		T113	1
auto[2415919104:2550136831]	109	1			T1	2		T3	1		T126	1
auto[2550136832:2684354559]	113	1			T1	1		T3	3		T16	1
auto[2684354560:2818572287]	108	1			T1	2		T3	3		T39	1
auto[2818572288:2952790015]	113	1			T1	3		T3	1		T124	1
auto[2952790016:3087007743]	118	1			T1	3		T3	1		T17	1
auto[3087007744:3221225471]	100	1			T1	2		T3	4		T208	1
auto[3221225472:3355443199]	112	1			T1	2		T104	2		T192	1
auto[3355443200:3489660927]	101	1			T3	1		T17	2		T208	1
auto[3489660928:3623878655]	103	1			T1	2		T126	1		T38	1
auto[3623878656:3758096383]	93	1			T1	2		T123	1		T49	1
auto[3758096384:3892314111]	91	1			T1	2		T3	1		T47	1
auto[3892314112:4026531839]	104	1			T1	5		T2	2		T195	1
auto[4026531840:4160749567]	124	1			T2	1		T3	1		T200	1
auto[4160749568:4294967295]	126	1			T1	1		T3	2		T17	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T1	1		T131	1		T21	1
auto[0:134217727]	auto[1]	67	1			T3	2		T200	1		T49	1
auto[134217728:268435455]	auto[0]	43	1			T1	1		T3	1		T208	1
auto[134217728:268435455]	auto[1]	46	1			T17	1		T195	2		T144	2
auto[268435456:402653183]	auto[0]	49	1			T1	1		T3	3		T31	1
auto[268435456:402653183]	auto[1]	60	1			T1	1		T199	1		T193	1
auto[402653184:536870911]	auto[0]	60	1			T3	1		T197	1		T192	1
auto[402653184:536870911]	auto[1]	50	1			T192	1		T143	1		T4	1
auto[536870912:671088639]	auto[0]	53	1			T1	1		T47	3		T143	1
auto[536870912:671088639]	auto[1]	58	1			T1	1		T3	1		T16	2
auto[671088640:805306367]	auto[0]	50	1			T1	1		T199	1		T49	1
auto[671088640:805306367]	auto[1]	52	1			T1	3		T3	1		T62	1
auto[805306368:939524095]	auto[0]	58	1			T1	1		T3	1		T17	1
auto[805306368:939524095]	auto[1]	54	1			T16	1		T48	1		T208	1
auto[939524096:1073741823]	auto[0]	41	1			T1	1		T3	1		T4	1
auto[939524096:1073741823]	auto[1]	57	1			T1	1		T195	1		T202	1
auto[1073741824:1207959551]	auto[0]	43	1			T68	1		T51	1		T52	2
auto[1073741824:1207959551]	auto[1]	62	1			T1	3		T124	1		T126	2
auto[1207959552:1342177279]	auto[0]	45	1			T193	1		T255	1		T52	1
auto[1207959552:1342177279]	auto[1]	61	1			T1	2		T3	2		T16	1
auto[1342177280:1476395007]	auto[0]	50	1			T104	1		T50	2		T4	1
auto[1342177280:1476395007]	auto[1]	59	1			T1	2		T17	1		T126	1
auto[1476395008:1610612735]	auto[0]	55	1			T1	1		T2	1		T46	1
auto[1476395008:1610612735]	auto[1]	58	1			T1	3		T3	2		T46	1
auto[1610612736:1744830463]	auto[0]	61	1			T208	1		T192	1		T96	1
auto[1610612736:1744830463]	auto[1]	57	1			T3	1		T202	1		T55	1
auto[1744830464:1879048191]	auto[0]	53	1			T1	1		T3	1		T104	1
auto[1744830464:1879048191]	auto[1]	40	1			T55	1		T68	1		T4	1
auto[1879048192:2013265919]	auto[0]	46	1			T1	1		T3	2		T124	1
auto[1879048192:2013265919]	auto[1]	53	1			T3	3		T104	1		T47	2
auto[2013265920:2147483647]	auto[0]	50	1			T2	1		T193	1		T20	1
auto[2013265920:2147483647]	auto[1]	51	1			T1	1		T3	1		T56	1
auto[2147483648:2281701375]	auto[0]	53	1			T206	1		T4	1		T255	1
auto[2147483648:2281701375]	auto[1]	57	1			T1	1		T3	1		T68	1
auto[2281701376:2415919103]	auto[0]	49	1			T3	1		T68	1		T4	1
auto[2281701376:2415919103]	auto[1]	59	1			T3	1		T123	1		T113	1
auto[2415919104:2550136831]	auto[0]	53	1			T1	1		T3	1		T192	1
auto[2415919104:2550136831]	auto[1]	56	1			T1	1		T126	1		T68	1
auto[2550136832:2684354559]	auto[0]	61	1			T1	1		T3	2		T17	1
auto[2550136832:2684354559]	auto[1]	52	1			T3	1		T16	1		T124	1
auto[2684354560:2818572287]	auto[0]	51	1			T3	1		T39	1		T143	1
auto[2684354560:2818572287]	auto[1]	57	1			T1	2		T3	2		T46	1
auto[2818572288:2952790015]	auto[0]	47	1			T1	2		T3	1		T131	1
auto[2818572288:2952790015]	auto[1]	66	1			T1	1		T124	1		T48	1
auto[2952790016:3087007743]	auto[0]	63	1			T1	3		T17	1		T4	1
auto[2952790016:3087007743]	auto[1]	55	1			T3	1		T4	1		T133	1
auto[3087007744:3221225471]	auto[0]	38	1			T1	1		T3	2		T208	1
auto[3087007744:3221225471]	auto[1]	62	1			T1	1		T3	2		T47	1
auto[3221225472:3355443199]	auto[0]	58	1			T1	1		T199	1		T68	1
auto[3221225472:3355443199]	auto[1]	54	1			T1	1		T104	2		T192	1
auto[3355443200:3489660927]	auto[0]	47	1			T17	2		T208	1		T96	1
auto[3355443200:3489660927]	auto[1]	54	1			T3	1		T96	1		T50	1
auto[3489660928:3623878655]	auto[0]	55	1			T1	2		T38	1		T39	1
auto[3489660928:3623878655]	auto[1]	48	1			T126	1		T49	1		T4	2
auto[3623878656:3758096383]	auto[0]	48	1			T1	2		T123	1		T68	1
auto[3623878656:3758096383]	auto[1]	45	1			T49	1		T52	3		T264	1
auto[3758096384:3892314111]	auto[0]	43	1			T1	1		T185	1		T5	2
auto[3758096384:3892314111]	auto[1]	48	1			T1	1		T3	1		T47	1
auto[3892314112:4026531839]	auto[0]	54	1			T1	2		T2	1		T249	1
auto[3892314112:4026531839]	auto[1]	50	1			T1	3		T2	1		T195	1
auto[4026531840:4160749567]	auto[0]	66	1			T3	1		T200	1		T52	1
auto[4026531840:4160749567]	auto[1]	58	1			T2	1		T143	1		T131	1
auto[4160749568:4294967295]	auto[0]	74	1			T17	1		T38	1		T39	1
auto[4160749568:4294967295]	auto[1]	52	1			T1	1		T3	2		T200	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1671

1

T1

27

T2

3

T3

11

auto[1]

1763

1

T1

28

T2

2

T3

33

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T1	1		T16	1		T208	1
auto[134217728:268435455]	105	1			T1	1		T3	2		T197	1
auto[268435456:402653183]	97	1			T1	2		T3	1		T195	1
auto[402653184:536870911]	94	1			T1	2		T3	1		T46	1
auto[536870912:671088639]	113	1			T3	1		T126	1		T47	1
auto[671088640:805306367]	122	1			T1	2		T3	4		T39	1
auto[805306368:939524095]	110	1			T1	2		T3	1		T16	1
auto[939524096:1073741823]	116	1			T1	3		T3	1		T16	1
auto[1073741824:1207959551]	102	1			T1	3		T3	3		T31	1
auto[1207959552:1342177279]	113	1			T1	4		T104	1		T195	1
auto[1342177280:1476395007]	94	1			T1	1		T2	1		T17	2
auto[1476395008:1610612735]	107	1			T1	1		T2	1		T3	1
auto[1610612736:1744830463]	97	1			T1	2		T2	1		T3	1
auto[1744830464:1879048191]	124	1			T17	1		T38	1		T113	1
auto[1879048192:2013265919]	110	1			T1	1		T3	1		T124	1
auto[2013265920:2147483647]	99	1			T1	3		T3	1		T126	1
auto[2147483648:2281701375]	118	1			T1	3		T2	1		T3	2
auto[2281701376:2415919103]	97	1			T1	1		T3	1		T17	1
auto[2415919104:2550136831]	114	1			T1	1		T3	3		T39	1
auto[2550136832:2684354559]	125	1			T2	1		T3	1		T17	1
auto[2684354560:2818572287]	102	1			T1	2		T3	2		T124	1
auto[2818572288:2952790015]	111	1			T1	4		T3	2		T124	1
auto[2952790016:3087007743]	112	1			T1	2		T3	2		T16	1
auto[3087007744:3221225471]	104	1			T1	1		T3	1		T17	1
auto[3221225472:3355443199]	115	1			T1	1		T123	1		T104	1
auto[3355443200:3489660927]	124	1			T1	4		T3	1		T123	1
auto[3489660928:3623878655]	98	1			T1	1		T3	2		T126	1
auto[3623878656:3758096383]	89	1			T1	1		T3	1		T126	1
auto[3758096384:3892314111]	106	1			T1	1		T3	3		T16	1
auto[3892314112:4026531839]	108	1			T1	2		T3	2		T49	1
auto[4026531840:4160749567]	103	1			T1	1		T3	3		T192	1
auto[4160749568:4294967295]	98	1			T1	2		T17	1		T48	1