Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4606

1

T1

76

T2

10

T3

66

auto[1]

2262

1

T1

34

T3

22

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	186	1			T1	2		T3	6		T49	2
auto[134217728:268435455]	244	1			T1	2		T3	2		T4	10
auto[268435456:402653183]	242	1			T1	6		T126	2		T31	2
auto[402653184:536870911]	212	1			T1	8		T3	4		T192	2
auto[536870912:671088639]	210	1			T1	4		T3	6		T48	2
auto[671088640:805306367]	216	1			T1	2		T3	2		T39	2
auto[805306368:939524095]	224	1			T1	2		T3	2		T17	4
auto[939524096:1073741823]	220	1			T1	8		T3	2		T104	2
auto[1073741824:1207959551]	216	1			T1	6		T123	2		T208	2
auto[1207959552:1342177279]	210	1			T1	2		T3	4		T39	2
auto[1342177280:1476395007]	182	1			T2	2		T3	6		T16	2
auto[1476395008:1610612735]	222	1			T1	2		T2	2		T3	2
auto[1610612736:1744830463]	224	1			T1	4		T104	2		T126	2
auto[1744830464:1879048191]	226	1			T1	2		T2	2		T3	4
auto[1879048192:2013265919]	192	1			T3	6		T17	2		T39	2
auto[2013265920:2147483647]	196	1			T1	2		T3	4		T143	2
auto[2147483648:2281701375]	220	1			T1	4		T3	4		T38	4
auto[2281701376:2415919103]	224	1			T1	8		T3	2		T17	2
auto[2415919104:2550136831]	226	1			T1	2		T124	2		T208	2
auto[2550136832:2684354559]	230	1			T1	4		T3	2		T195	2
auto[2684354560:2818572287]	196	1			T3	2		T200	2		T143	2
auto[2818572288:2952790015]	196	1			T1	4		T3	4		T17	2
auto[2952790016:3087007743]	230	1			T1	2		T3	6		T104	2
auto[3087007744:3221225471]	226	1			T104	2		T196	2		T46	2
auto[3221225472:3355443199]	210	1			T1	6		T197	2		T47	2
auto[3355443200:3489660927]	170	1			T1	4		T16	2		T21	2
auto[3489660928:3623878655]	202	1			T1	2		T2	2		T3	4
auto[3623878656:3758096383]	240	1			T1	6		T3	4		T17	2
auto[3758096384:3892314111]	234	1			T1	4		T124	2		T195	2
auto[3892314112:4026531839]	178	1			T3	6		T192	2		T199	2
auto[4026531840:4160749567]	246	1			T1	8		T2	2		T3	2
auto[4160749568:4294967295]	218	1			T1	4		T3	2		T16	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	144	1			T1	2		T3	4		T49	2
auto[0:134217727]	auto[1]	42	1			T3	2		T68	2		T82	2
auto[134217728:268435455]	auto[0]	160	1			T1	2		T3	2		T4	8
auto[134217728:268435455]	auto[1]	84	1			T4	2		T52	2		T236	2
auto[268435456:402653183]	auto[0]	174	1			T1	6		T31	2		T47	2
auto[268435456:402653183]	auto[1]	68	1			T126	2		T200	2		T206	2
auto[402653184:536870911]	auto[0]	126	1			T1	8		T3	4		T49	2
auto[402653184:536870911]	auto[1]	86	1			T192	2		T255	2		T5	2
auto[536870912:671088639]	auto[0]	144	1			T1	2		T3	6		T51	2
auto[536870912:671088639]	auto[1]	66	1			T1	2		T48	2		T195	2
auto[671088640:805306367]	auto[0]	136	1			T3	2		T47	4		T199	2
auto[671088640:805306367]	auto[1]	80	1			T1	2		T39	2		T68	2
auto[805306368:939524095]	auto[0]	136	1			T1	2		T17	2		T39	2
auto[805306368:939524095]	auto[1]	88	1			T3	2		T17	2		T130	2
auto[939524096:1073741823]	auto[0]	156	1			T1	4		T3	2		T104	2
auto[939524096:1073741823]	auto[1]	64	1			T1	4		T38	2		T206	2
auto[1073741824:1207959551]	auto[0]	150	1			T1	6		T123	2		T208	2
auto[1073741824:1207959551]	auto[1]	66	1			T68	2		T52	2		T5	2
auto[1207959552:1342177279]	auto[0]	136	1			T1	2		T3	4		T47	2
auto[1207959552:1342177279]	auto[1]	74	1			T39	2		T143	2		T144	2
auto[1342177280:1476395007]	auto[0]	120	1			T2	2		T3	4		T16	2
auto[1342177280:1476395007]	auto[1]	62	1			T3	2		T20	2		T58	2
auto[1476395008:1610612735]	auto[0]	150	1			T1	2		T2	2		T3	2
auto[1476395008:1610612735]	auto[1]	72	1			T16	2		T123	2		T200	2
auto[1610612736:1744830463]	auto[0]	144	1			T1	2		T104	2		T199	2
auto[1610612736:1744830463]	auto[1]	80	1			T1	2		T126	2		T46	2
auto[1744830464:1879048191]	auto[0]	134	1			T1	2		T2	2		T124	2
auto[1744830464:1879048191]	auto[1]	92	1			T3	4		T208	2		T192	2
auto[1879048192:2013265919]	auto[0]	122	1			T3	6		T17	2		T39	2
auto[1879048192:2013265919]	auto[1]	70	1			T192	2		T130	2		T68	2
auto[2013265920:2147483647]	auto[0]	138	1			T1	2		T3	2		T143	2
auto[2013265920:2147483647]	auto[1]	58	1			T3	2		T42	2		T6	2
auto[2147483648:2281701375]	auto[0]	152	1			T1	2		T3	2		T4	4
auto[2147483648:2281701375]	auto[1]	68	1			T1	2		T3	2		T38	4
auto[2281701376:2415919103]	auto[0]	164	1			T1	8		T3	2		T17	2
auto[2281701376:2415919103]	auto[1]	60	1			T126	2		T144	2		T68	2
auto[2415919104:2550136831]	auto[0]	150	1			T1	2		T124	2		T208	2
auto[2415919104:2550136831]	auto[1]	76	1			T38	2		T4	2		T105	2
auto[2550136832:2684354559]	auto[0]	162	1			T3	2		T195	2		T55	2
auto[2550136832:2684354559]	auto[1]	68	1			T1	4		T62	2		T4	2
auto[2684354560:2818572287]	auto[0]	124	1			T3	2		T143	2		T4	4
auto[2684354560:2818572287]	auto[1]	72	1			T200	2		T21	2		T5	4
auto[2818572288:2952790015]	auto[0]	132	1			T1	2		T3	2		T17	2
auto[2818572288:2952790015]	auto[1]	64	1			T1	2		T3	2		T52	4
auto[2952790016:3087007743]	auto[0]	162	1			T1	2		T3	4		T104	2
auto[2952790016:3087007743]	auto[1]	68	1			T3	2		T206	2		T4	2
auto[3087007744:3221225471]	auto[0]	170	1			T104	2		T196	2		T46	2
auto[3087007744:3221225471]	auto[1]	56	1			T55	2		T4	2		T52	6
auto[3221225472:3355443199]	auto[0]	138	1			T1	4		T197	2		T47	2
auto[3221225472:3355443199]	auto[1]	72	1			T1	2		T144	2		T206	2
auto[3355443200:3489660927]	auto[0]	104	1			T1	4		T16	2		T4	2
auto[3355443200:3489660927]	auto[1]	66	1			T21	2		T52	2		T5	2
auto[3489660928:3623878655]	auto[0]	126	1			T1	2		T2	2		T3	4
auto[3489660928:3623878655]	auto[1]	76	1			T96	2		T62	2		T105	2
auto[3623878656:3758096383]	auto[0]	150	1			T3	2		T17	2		T195	2
auto[3623878656:3758096383]	auto[1]	90	1			T1	6		T3	2		T126	2
auto[3758096384:3892314111]	auto[0]	154	1			T1	2		T124	2		T195	2
auto[3758096384:3892314111]	auto[1]	80	1			T1	2		T68	2		T52	2
auto[3892314112:4026531839]	auto[0]	116	1			T3	4		T193	2		T50	2
auto[3892314112:4026531839]	auto[1]	62	1			T3	2		T192	2		T199	2
auto[4026531840:4160749567]	auto[0]	174	1			T1	2		T2	2		T3	2
auto[4026531840:4160749567]	auto[1]	72	1			T1	6		T17	2		T126	2
auto[4160749568:4294967295]	auto[0]	158	1			T1	4		T3	2		T16	4
auto[4160749568:4294967295]	auto[1]	60	1			T51	2		T185	2		T52	4