Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2987

1

T1

41

T2

5

T3

42

auto[1]

281

1

T104

2

T113

10

T143

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	118	1			T1	3		T2	1		T3	3
auto[134217728:268435455]	104	1			T1	3		T3	2		T104	1
auto[268435456:402653183]	110	1			T1	2		T3	4		T113	1
auto[402653184:536870911]	95	1			T1	2		T2	1		T126	1
auto[536870912:671088639]	90	1			T1	1		T3	1		T17	1
auto[671088640:805306367]	101	1			T1	2		T3	1		T38	1
auto[805306368:939524095]	106	1			T1	2		T3	2		T16	1
auto[939524096:1073741823]	116	1			T1	1		T3	3		T124	1
auto[1073741824:1207959551]	92	1			T3	4		T104	1		T39	1
auto[1207959552:1342177279]	116	1			T1	1		T2	1		T3	1
auto[1342177280:1476395007]	96	1			T17	1		T192	1		T199	1
auto[1476395008:1610612735]	100	1			T1	1		T3	2		T17	1
auto[1610612736:1744830463]	94	1			T1	2		T208	1		T192	1
auto[1744830464:1879048191]	110	1			T1	2		T3	2		T197	1
auto[1879048192:2013265919]	112	1			T3	1		T16	1		T38	1
auto[2013265920:2147483647]	88	1			T1	1		T3	1		T16	1
auto[2147483648:2281701375]	115	1			T17	1		T104	1		T208	1
auto[2281701376:2415919103]	100	1			T1	1		T16	1		T104	1
auto[2415919104:2550136831]	108	1			T1	2		T3	1		T143	1
auto[2550136832:2684354559]	83	1			T2	1		T3	2		T38	1
auto[2684354560:2818572287]	103	1			T3	2		T208	1		T46	1
auto[2818572288:2952790015]	97	1			T1	1		T3	2		T104	1
auto[2952790016:3087007743]	106	1			T1	2		T3	1		T113	1
auto[3087007744:3221225471]	91	1			T1	4		T200	1		T47	1
auto[3221225472:3355443199]	104	1			T1	1		T3	1		T132	1
auto[3355443200:3489660927]	105	1			T1	2		T3	1		T124	1
auto[3489660928:3623878655]	112	1			T2	1		T3	1		T17	1
auto[3623878656:3758096383]	96	1			T1	1		T3	3		T126	1
auto[3758096384:3892314111]	99	1			T1	1		T17	1		T48	1
auto[3892314112:4026531839]	104	1			T56	1		T46	1		T195	1
auto[4026531840:4160749567]	116	1			T1	2		T39	1		T195	1
auto[4160749568:4294967295]	81	1			T1	1		T3	1		T16	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	114	1			T1	3		T2	1		T3	3
auto[0:134217727]	auto[1]	4	1			T250	1		T232	1		T403	1
auto[134217728:268435455]	auto[0]	95	1			T1	3		T3	2		T104	1
auto[134217728:268435455]	auto[1]	9	1			T144	1		T133	1		T397	1
auto[268435456:402653183]	auto[0]	99	1			T1	2		T3	4		T130	1
auto[268435456:402653183]	auto[1]	11	1			T113	1		T131	1		T250	1
auto[402653184:536870911]	auto[0]	90	1			T1	2		T2	1		T126	1
auto[402653184:536870911]	auto[1]	5	1			T239	1		T395	1		T392	1
auto[536870912:671088639]	auto[0]	79	1			T1	1		T3	1		T17	1
auto[536870912:671088639]	auto[1]	11	1			T104	1		T133	1		T253	1
auto[671088640:805306367]	auto[0]	93	1			T1	2		T3	1		T38	1
auto[671088640:805306367]	auto[1]	8	1			T113	1		T263	1		T379	1
auto[805306368:939524095]	auto[0]	95	1			T1	2		T3	2		T16	1
auto[805306368:939524095]	auto[1]	11	1			T130	1		T144	1		T133	1
auto[939524096:1073741823]	auto[0]	109	1			T1	1		T3	3		T124	1
auto[939524096:1073741823]	auto[1]	7	1			T254	1		T239	1		T398	1
auto[1073741824:1207959551]	auto[0]	85	1			T3	4		T104	1		T39	1
auto[1073741824:1207959551]	auto[1]	7	1			T113	1		T254	1		T239	1
auto[1207959552:1342177279]	auto[0]	104	1			T1	1		T2	1		T3	1
auto[1207959552:1342177279]	auto[1]	12	1			T131	1		T133	2		T263	1
auto[1342177280:1476395007]	auto[0]	85	1			T17	1		T192	1		T199	1
auto[1342177280:1476395007]	auto[1]	11	1			T287	1		T239	1		T396	3
auto[1476395008:1610612735]	auto[0]	93	1			T1	1		T3	2		T17	1
auto[1476395008:1610612735]	auto[1]	7	1			T132	1		T254	1		T239	1
auto[1610612736:1744830463]	auto[0]	90	1			T1	2		T208	1		T192	1
auto[1610612736:1744830463]	auto[1]	4	1			T379	1		T232	1		T395	1
auto[1744830464:1879048191]	auto[0]	103	1			T1	2		T3	2		T197	1
auto[1744830464:1879048191]	auto[1]	7	1			T113	1		T130	1		T380	1
auto[1879048192:2013265919]	auto[0]	97	1			T3	1		T16	1		T38	1
auto[1879048192:2013265919]	auto[1]	15	1			T143	1		T133	1		T253	1
auto[2013265920:2147483647]	auto[0]	79	1			T1	1		T3	1		T16	1
auto[2013265920:2147483647]	auto[1]	9	1			T144	1		T253	1		T231	1
auto[2147483648:2281701375]	auto[0]	101	1			T17	1		T104	1		T208	1
auto[2147483648:2281701375]	auto[1]	14	1			T133	2		T253	1		T254	1
auto[2281701376:2415919103]	auto[0]	92	1			T1	1		T16	1		T104	1
auto[2281701376:2415919103]	auto[1]	8	1			T253	2		T309	2		T401	1
auto[2415919104:2550136831]	auto[0]	100	1			T1	2		T3	1		T143	1
auto[2415919104:2550136831]	auto[1]	8	1			T133	1		T253	1		T263	1
auto[2550136832:2684354559]	auto[0]	77	1			T2	1		T3	2		T38	1
auto[2550136832:2684354559]	auto[1]	6	1			T254	1		T251	1		T287	1
auto[2684354560:2818572287]	auto[0]	85	1			T3	2		T208	1		T46	1
auto[2684354560:2818572287]	auto[1]	18	1			T113	1		T133	2		T287	1
auto[2818572288:2952790015]	auto[0]	89	1			T1	1		T3	2		T124	2
auto[2818572288:2952790015]	auto[1]	8	1			T104	1		T113	1		T130	1
auto[2952790016:3087007743]	auto[0]	96	1			T1	2		T3	1		T68	1
auto[2952790016:3087007743]	auto[1]	10	1			T113	1		T253	1		T396	1
auto[3087007744:3221225471]	auto[0]	88	1			T1	4		T200	1		T47	1
auto[3087007744:3221225471]	auto[1]	3	1			T397	2		T404	1		-	-
auto[3221225472:3355443199]	auto[0]	94	1			T1	1		T3	1		T132	1
auto[3221225472:3355443199]	auto[1]	10	1			T250	1		T254	1		T289	1
auto[3355443200:3489660927]	auto[0]	101	1			T1	2		T3	1		T124	1
auto[3355443200:3489660927]	auto[1]	4	1			T133	1		T239	1		T396	1
auto[3489660928:3623878655]	auto[0]	99	1			T2	1		T3	1		T17	1
auto[3489660928:3623878655]	auto[1]	13	1			T113	1		T144	1		T254	2
auto[3623878656:3758096383]	auto[0]	86	1			T1	1		T3	3		T126	1
auto[3623878656:3758096383]	auto[1]	10	1			T134	1		T396	2		T325	1
auto[3758096384:3892314111]	auto[0]	96	1			T1	1		T17	1		T48	1
auto[3758096384:3892314111]	auto[1]	3	1			T254	1		T402	1		T394	1
auto[3892314112:4026531839]	auto[0]	95	1			T56	1		T46	1		T195	1
auto[3892314112:4026531839]	auto[1]	9	1			T113	2		T251	2		T396	1
auto[4026531840:4160749567]	auto[0]	104	1			T1	2		T39	1		T195	1
auto[4026531840:4160749567]	auto[1]	12	1			T133	1		T251	1		T287	1
auto[4160749568:4294967295]	auto[0]	74	1			T1	1		T3	1		T16	1
auto[4160749568:4294967295]	auto[1]	7	1			T143	1		T395	1		T309	1