Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2987

1

T1

41

T2

5

T3

42

auto[1]

291

1

T104

1

T113

6

T130

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T1	1		T3	1		T126	1
auto[134217728:268435455]	112	1			T1	1		T3	1		T17	1
auto[268435456:402653183]	99	1			T3	1		T48	1		T208	1
auto[402653184:536870911]	107	1			T1	1		T2	2		T3	3
auto[536870912:671088639]	110	1			T1	2		T2	1		T3	1
auto[671088640:805306367]	91	1			T1	1		T3	1		T124	1
auto[805306368:939524095]	92	1			T1	2		T3	2		T49	1
auto[939524096:1073741823]	115	1			T2	1		T3	1		T38	1
auto[1073741824:1207959551]	102	1			T1	1		T38	1		T199	1
auto[1207959552:1342177279]	124	1			T1	2		T3	3		T16	1
auto[1342177280:1476395007]	98	1			T1	1		T17	1		T192	1
auto[1476395008:1610612735]	93	1			T1	1		T3	5		T123	1
auto[1610612736:1744830463]	99	1			T1	2		T130	1		T131	1
auto[1744830464:1879048191]	98	1			T3	1		T17	2		T104	1
auto[1879048192:2013265919]	86	1			T1	1		T208	1		T39	1
auto[2013265920:2147483647]	91	1			T1	1		T3	2		T31	1
auto[2147483648:2281701375]	106	1			T1	2		T3	2		T38	1
auto[2281701376:2415919103]	104	1			T1	1		T208	1		T96	1
auto[2415919104:2550136831]	115	1			T113	1		T62	1		T68	1
auto[2550136832:2684354559]	107	1			T2	1		T3	1		T16	1
auto[2684354560:2818572287]	98	1			T1	2		T123	1		T124	1
auto[2818572288:2952790015]	120	1			T1	2		T3	3		T126	1
auto[2952790016:3087007743]	98	1			T1	2		T3	2		T104	1
auto[3087007744:3221225471]	95	1			T1	1		T3	3		T16	1
auto[3221225472:3355443199]	117	1			T1	4		T3	3		T126	1
auto[3355443200:3489660927]	82	1			T1	1		T17	1		T48	1
auto[3489660928:3623878655]	101	1			T1	1		T16	1		T208	1
auto[3623878656:3758096383]	112	1			T1	2		T3	3		T17	2
auto[3758096384:3892314111]	88	1			T1	1		T17	1		T48	1
auto[3892314112:4026531839]	110	1			T1	1		T3	1		T195	1
auto[4026531840:4160749567]	100	1			T1	3		T3	1		T104	1
auto[4160749568:4294967295]	99	1			T1	1		T3	1		T16	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	94	1			T1	1		T3	1		T126	1
auto[0:134217727]	auto[1]	15	1			T250	1		T254	2		T396	1
auto[134217728:268435455]	auto[0]	106	1			T1	1		T3	1		T17	1
auto[134217728:268435455]	auto[1]	6	1			T133	1		T254	1		T325	1
auto[268435456:402653183]	auto[0]	91	1			T3	1		T48	1		T208	1
auto[268435456:402653183]	auto[1]	8	1			T133	1		T251	1		T396	2
auto[402653184:536870911]	auto[0]	95	1			T1	1		T2	2		T3	3
auto[402653184:536870911]	auto[1]	12	1			T144	1		T133	2		T253	1
auto[536870912:671088639]	auto[0]	96	1			T1	2		T2	1		T3	1
auto[536870912:671088639]	auto[1]	14	1			T144	1		T396	1		T397	3
auto[671088640:805306367]	auto[0]	83	1			T1	1		T3	1		T124	1
auto[671088640:805306367]	auto[1]	8	1			T113	1		T130	1		T309	1
auto[805306368:939524095]	auto[0]	88	1			T1	2		T3	2		T49	1
auto[805306368:939524095]	auto[1]	4	1			T396	2		T232	1		T297	1
auto[939524096:1073741823]	auto[0]	101	1			T2	1		T3	1		T38	1
auto[939524096:1073741823]	auto[1]	14	1			T113	1		T144	1		T239	1
auto[1073741824:1207959551]	auto[0]	97	1			T1	1		T38	1		T199	1
auto[1073741824:1207959551]	auto[1]	5	1			T132	1		T357	1		T232	1
auto[1207959552:1342177279]	auto[0]	118	1			T1	2		T3	3		T16	1
auto[1207959552:1342177279]	auto[1]	6	1			T113	1		T239	1		T397	1
auto[1342177280:1476395007]	auto[0]	88	1			T1	1		T17	1		T192	1
auto[1342177280:1476395007]	auto[1]	10	1			T131	1		T250	1		T251	1
auto[1476395008:1610612735]	auto[0]	89	1			T1	1		T3	5		T123	1
auto[1476395008:1610612735]	auto[1]	4	1			T250	1		T380	1		T397	1
auto[1610612736:1744830463]	auto[0]	90	1			T1	2		T130	1		T131	1
auto[1610612736:1744830463]	auto[1]	9	1			T231	1		T254	1		T344	1
auto[1744830464:1879048191]	auto[0]	88	1			T3	1		T17	2		T192	1
auto[1744830464:1879048191]	auto[1]	10	1			T104	1		T263	1		T254	2
auto[1879048192:2013265919]	auto[0]	83	1			T1	1		T208	1		T39	1
auto[1879048192:2013265919]	auto[1]	3	1			T232	1		T233	1		T404	1
auto[2013265920:2147483647]	auto[0]	82	1			T1	1		T3	2		T31	1
auto[2013265920:2147483647]	auto[1]	9	1			T113	1		T253	2		T251	1
auto[2147483648:2281701375]	auto[0]	98	1			T1	2		T3	2		T38	1
auto[2147483648:2281701375]	auto[1]	8	1			T130	1		T133	1		T253	1
auto[2281701376:2415919103]	auto[0]	96	1			T1	1		T208	1		T96	1
auto[2281701376:2415919103]	auto[1]	8	1			T133	1		T396	1		T313	1
auto[2415919104:2550136831]	auto[0]	107	1			T62	1		T68	1		T50	1
auto[2415919104:2550136831]	auto[1]	8	1			T113	1		T133	1		T134	1
auto[2550136832:2684354559]	auto[0]	98	1			T2	1		T3	1		T16	1
auto[2550136832:2684354559]	auto[1]	9	1			T144	1		T231	1		T251	1
auto[2684354560:2818572287]	auto[0]	90	1			T1	2		T123	1		T124	1
auto[2684354560:2818572287]	auto[1]	8	1			T289	1		T397	1		T325	1
auto[2818572288:2952790015]	auto[0]	105	1			T1	2		T3	3		T126	1
auto[2818572288:2952790015]	auto[1]	15	1			T133	1		T253	1		T379	1
auto[2952790016:3087007743]	auto[0]	88	1			T1	2		T3	2		T104	1
auto[2952790016:3087007743]	auto[1]	10	1			T133	2		T254	1		T232	1
auto[3087007744:3221225471]	auto[0]	88	1			T1	1		T3	3		T16	1
auto[3087007744:3221225471]	auto[1]	7	1			T133	2		T287	1		T396	1
auto[3221225472:3355443199]	auto[0]	108	1			T1	4		T3	3		T126	1
auto[3221225472:3355443199]	auto[1]	9	1			T144	1		T133	1		T250	1
auto[3355443200:3489660927]	auto[0]	78	1			T1	1		T17	1		T48	1
auto[3355443200:3489660927]	auto[1]	4	1			T250	1		T254	1		T289	1
auto[3489660928:3623878655]	auto[0]	91	1			T1	1		T16	1		T208	1
auto[3489660928:3623878655]	auto[1]	10	1			T133	1		T253	1		T289	1
auto[3623878656:3758096383]	auto[0]	97	1			T1	2		T3	3		T17	2
auto[3623878656:3758096383]	auto[1]	15	1			T113	1		T253	1		T231	1
auto[3758096384:3892314111]	auto[0]	78	1			T1	1		T17	1		T48	1
auto[3758096384:3892314111]	auto[1]	10	1			T253	1		T250	1		T254	1
auto[3892314112:4026531839]	auto[0]	94	1			T1	1		T3	1		T195	1
auto[3892314112:4026531839]	auto[1]	16	1			T130	1		T144	1		T231	1
auto[4026531840:4160749567]	auto[0]	90	1			T1	3		T3	1		T104	1
auto[4026531840:4160749567]	auto[1]	10	1			T130	1		T144	1		T263	1
auto[4160749568:4294967295]	auto[0]	92	1			T1	1		T3	1		T16	1
auto[4160749568:4294967295]	auto[1]	7	1			T263	1		T354	1		T395	2