Unified Coverage Report :: Group Instance : sealing_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1648

1

T1

30

T2

3

T3

16

auto[1]

1786

1

T1

25

T2

2

T3

28

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	116	1			T3	1		T104	1		T124	1
auto[134217728:268435455]	110	1			T1	2		T3	2		T17	1
auto[268435456:402653183]	106	1			T3	1		T104	1		T62	1
auto[402653184:536870911]	107	1			T1	3		T3	1		T47	1
auto[536870912:671088639]	106	1			T1	1		T3	1		T124	1
auto[671088640:805306367]	122	1			T1	3		T2	1		T3	1
auto[805306368:939524095]	108	1			T1	1		T3	1		T126	1
auto[939524096:1073741823]	101	1			T1	1		T3	1		T104	1
auto[1073741824:1207959551]	107	1			T1	3		T16	1		T197	1
auto[1207959552:1342177279]	102	1			T1	1		T2	1		T38	1
auto[1342177280:1476395007]	95	1			T1	2		T2	1		T3	1
auto[1476395008:1610612735]	96	1			T1	2		T2	1		T3	1
auto[1610612736:1744830463]	86	1			T1	2		T3	1		T202	1
auto[1744830464:1879048191]	102	1			T1	1		T3	2		T123	1
auto[1879048192:2013265919]	119	1			T1	1		T31	1		T4	1
auto[2013265920:2147483647]	101	1			T3	2		T38	1		T47	1
auto[2147483648:2281701375]	127	1			T1	1		T3	1		T16	1
auto[2281701376:2415919103]	89	1			T1	3		T3	4		T17	1
auto[2415919104:2550136831]	108	1			T1	5		T3	1		T17	1
auto[2550136832:2684354559]	110	1			T1	1		T3	3		T199	1
auto[2684354560:2818572287]	106	1			T1	1		T3	2		T199	1
auto[2818572288:2952790015]	105	1			T1	1		T2	1		T3	1
auto[2952790016:3087007743]	117	1			T1	4		T3	2		T17	1
auto[3087007744:3221225471]	118	1			T1	2		T202	1		T47	1
auto[3221225472:3355443199]	116	1			T1	1		T3	2		T126	1
auto[3355443200:3489660927]	115	1			T1	4		T3	1		T16	1
auto[3489660928:3623878655]	128	1			T1	4		T3	4		T16	1
auto[3623878656:3758096383]	105	1			T1	2		T3	2		T46	1
auto[3758096384:3892314111]	80	1			T17	1		T49	2		T144	1
auto[3892314112:4026531839]	113	1			T1	1		T3	1		T123	1
auto[4026531840:4160749567]	107	1			T1	1		T3	4		T17	1
auto[4160749568:4294967295]	106	1			T1	1		T16	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T104	1		T39	1		T47	1
auto[0:134217727]	auto[1]	58	1			T3	1		T124	1		T113	1
auto[134217728:268435455]	auto[0]	53	1			T1	1		T17	1		T52	1
auto[134217728:268435455]	auto[1]	57	1			T1	1		T3	2		T208	1
auto[268435456:402653183]	auto[0]	42	1			T3	1		T62	1		T51	1
auto[268435456:402653183]	auto[1]	64	1			T104	1		T82	1		T255	1
auto[402653184:536870911]	auto[0]	49	1			T1	2		T193	1		T50	1
auto[402653184:536870911]	auto[1]	58	1			T1	1		T3	1		T47	1
auto[536870912:671088639]	auto[0]	52	1			T1	1		T3	1		T68	1
auto[536870912:671088639]	auto[1]	54	1			T124	1		T195	2		T47	1
auto[671088640:805306367]	auto[0]	59	1			T1	3		T2	1		T3	1
auto[671088640:805306367]	auto[1]	63	1			T17	1		T126	2		T208	1
auto[805306368:939524095]	auto[0]	52	1			T208	1		T39	1		T46	1
auto[805306368:939524095]	auto[1]	56	1			T1	1		T3	1		T126	1
auto[939524096:1073741823]	auto[0]	41	1			T104	1		T49	1		T4	1
auto[939524096:1073741823]	auto[1]	60	1			T1	1		T3	1		T56	1
auto[1073741824:1207959551]	auto[0]	52	1			T1	1		T197	1		T96	1
auto[1073741824:1207959551]	auto[1]	55	1			T1	2		T16	1		T62	1
auto[1207959552:1342177279]	auto[0]	44	1			T4	1		T51	1		T52	1
auto[1207959552:1342177279]	auto[1]	58	1			T1	1		T2	1		T38	1
auto[1342177280:1476395007]	auto[0]	44	1			T3	1		T192	1		T131	1
auto[1342177280:1476395007]	auto[1]	51	1			T1	2		T2	1		T46	1
auto[1476395008:1610612735]	auto[0]	47	1			T1	2		T2	1		T3	1
auto[1476395008:1610612735]	auto[1]	49	1			T124	1		T130	1		T68	1
auto[1610612736:1744830463]	auto[0]	37	1			T1	1		T206	1		T4	1
auto[1610612736:1744830463]	auto[1]	49	1			T1	1		T3	1		T202	1
auto[1744830464:1879048191]	auto[0]	59	1			T3	1		T123	1		T208	1
auto[1744830464:1879048191]	auto[1]	43	1			T1	1		T3	1		T46	1
auto[1879048192:2013265919]	auto[0]	64	1			T1	1		T31	1		T4	1
auto[1879048192:2013265919]	auto[1]	55	1			T255	1		T400	1		T30	1
auto[2013265920:2147483647]	auto[0]	48	1			T3	1		T38	1		T47	1
auto[2013265920:2147483647]	auto[1]	53	1			T3	1		T52	3		T5	2
auto[2147483648:2281701375]	auto[0]	57	1			T1	1		T17	1		T39	1
auto[2147483648:2281701375]	auto[1]	70	1			T3	1		T16	1		T123	1
auto[2281701376:2415919103]	auto[0]	51	1			T1	2		T3	1		T202	1
auto[2281701376:2415919103]	auto[1]	38	1			T1	1		T3	3		T17	1
auto[2415919104:2550136831]	auto[0]	55	1			T1	3		T17	1		T143	1
auto[2415919104:2550136831]	auto[1]	53	1			T1	2		T3	1		T132	1
auto[2550136832:2684354559]	auto[0]	60	1			T3	1		T199	1		T50	1
auto[2550136832:2684354559]	auto[1]	50	1			T1	1		T3	2		T62	2
auto[2684354560:2818572287]	auto[0]	48	1			T3	1		T199	1		T143	1
auto[2684354560:2818572287]	auto[1]	58	1			T1	1		T3	1		T130	1
auto[2818572288:2952790015]	auto[0]	52	1			T1	1		T2	1		T3	1
auto[2818572288:2952790015]	auto[1]	53	1			T200	1		T192	1		T130	1
auto[2952790016:3087007743]	auto[0]	52	1			T1	3		T3	1		T17	1
auto[2952790016:3087007743]	auto[1]	65	1			T1	1		T3	1		T104	1
auto[3087007744:3221225471]	auto[0]	64	1			T1	1		T47	1		T55	1
auto[3087007744:3221225471]	auto[1]	54	1			T1	1		T202	1		T236	1
auto[3221225472:3355443199]	auto[0]	56	1			T49	1		T68	1		T399	1
auto[3221225472:3355443199]	auto[1]	60	1			T1	1		T3	2		T126	1
auto[3355443200:3489660927]	auto[0]	60	1			T1	1		T3	1		T4	1
auto[3355443200:3489660927]	auto[1]	55	1			T1	3		T16	1		T48	1
auto[3489660928:3623878655]	auto[0]	69	1			T1	3		T3	2		T124	1
auto[3489660928:3623878655]	auto[1]	59	1			T1	1		T3	2		T16	1
auto[3623878656:3758096383]	auto[0]	54	1			T1	1		T3	1		T192	1
auto[3623878656:3758096383]	auto[1]	51	1			T1	1		T3	1		T46	1
auto[3758096384:3892314111]	auto[0]	27	1			T4	1		T52	1		T42	1
auto[3758096384:3892314111]	auto[1]	53	1			T17	1		T49	2		T144	1
auto[3892314112:4026531839]	auto[0]	56	1			T193	1		T20	1		T96	1
auto[3892314112:4026531839]	auto[1]	57	1			T1	1		T3	1		T123	1
auto[4026531840:4160749567]	auto[0]	42	1			T1	1		T199	1		T55	1
auto[4026531840:4160749567]	auto[1]	65	1			T3	4		T17	1		T48	1
auto[4160749568:4294967295]	auto[0]	44	1			T1	1		T249	1		T51	1
auto[4160749568:4294967295]	auto[1]	62	1			T16	1		T48	1		T192	1