Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6895

1

T1

111

T2

10

T3

101

auto[1]

297

1

T104

1

T113

14

T143

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2890	1			T1	45		T2	5		T3	37
auto[134217728:268435455]	167	1			T1	4		T2	1		T3	1
auto[268435456:402653183]	147	1			T1	4		T16	2		T123	1
auto[402653184:536870911]	180	1			T1	2		T2	1		T3	5
auto[536870912:671088639]	147	1			T1	1		T3	5		T126	1
auto[671088640:805306367]	122	1			T1	1		T17	1		T48	1
auto[805306368:939524095]	147	1			T1	2		T3	3		T17	1
auto[939524096:1073741823]	142	1			T1	2		T3	1		T16	1
auto[1073741824:1207959551]	133	1			T1	1		T3	1		T16	1
auto[1207959552:1342177279]	132	1			T1	1		T3	5		T16	1
auto[1342177280:1476395007]	125	1			T1	3		T200	1		T49	1
auto[1476395008:1610612735]	136	1			T1	2		T2	1		T3	3
auto[1610612736:1744830463]	150	1			T1	2		T3	4		T16	1
auto[1744830464:1879048191]	137	1			T1	2		T3	2		T17	1
auto[1879048192:2013265919]	132	1			T1	3		T3	1		T123	1
auto[2013265920:2147483647]	137	1			T1	2		T3	3		T17	1
auto[2147483648:2281701375]	132	1			T1	3		T3	3		T104	1
auto[2281701376:2415919103]	135	1			T1	5		T17	1		T192	1
auto[2415919104:2550136831]	133	1			T1	1		T3	2		T17	1
auto[2550136832:2684354559]	132	1			T1	1		T3	3		T38	2
auto[2684354560:2818572287]	131	1			T1	2		T3	3		T126	1
auto[2818572288:2952790015]	133	1			T3	2		T16	1		T200	1
auto[2952790016:3087007743]	127	1			T1	2		T16	1		T17	1
auto[3087007744:3221225471]	138	1			T3	2		T197	2		T192	1
auto[3221225472:3355443199]	125	1			T1	1		T3	2		T113	1
auto[3355443200:3489660927]	153	1			T1	2		T3	3		T17	2
auto[3489660928:3623878655]	141	1			T1	4		T2	1		T3	2
auto[3623878656:3758096383]	130	1			T1	3		T2	1		T3	3
auto[3758096384:3892314111]	127	1			T1	4		T3	1		T104	1
auto[3892314112:4026531839]	142	1			T1	2		T3	2		T16	3
auto[4026531840:4160749567]	147	1			T1	3		T3	1		T17	2
auto[4160749568:4294967295]	142	1			T1	1		T3	1		T16	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2876	1			T1	45		T2	5		T3	37
auto[0:134217727]	auto[1]	14	1			T144	1		T253	1		T239	4
auto[134217728:268435455]	auto[0]	163	1			T1	4		T2	1		T3	1
auto[134217728:268435455]	auto[1]	4	1			T397	1		T365	1		T401	1
auto[268435456:402653183]	auto[0]	139	1			T1	4		T16	2		T123	1
auto[268435456:402653183]	auto[1]	8	1			T113	1		T133	1		T253	1
auto[402653184:536870911]	auto[0]	173	1			T1	2		T2	1		T3	5
auto[402653184:536870911]	auto[1]	7	1			T253	1		T239	1		T398	1
auto[536870912:671088639]	auto[0]	136	1			T1	1		T3	5		T126	1
auto[536870912:671088639]	auto[1]	11	1			T113	1		T132	1		T133	1
auto[671088640:805306367]	auto[0]	114	1			T1	1		T17	1		T48	1
auto[671088640:805306367]	auto[1]	8	1			T250	1		T254	1		T392	1
auto[805306368:939524095]	auto[0]	138	1			T1	2		T3	3		T17	1
auto[805306368:939524095]	auto[1]	9	1			T250	2		T254	1		T239	1
auto[939524096:1073741823]	auto[0]	130	1			T1	2		T3	1		T16	1
auto[939524096:1073741823]	auto[1]	12	1			T113	1		T232	1		T397	1
auto[1073741824:1207959551]	auto[0]	122	1			T1	1		T3	1		T16	1
auto[1073741824:1207959551]	auto[1]	11	1			T250	1		T254	1		T287	1
auto[1207959552:1342177279]	auto[0]	125	1			T1	1		T3	5		T16	1
auto[1207959552:1342177279]	auto[1]	7	1			T113	1		T253	1		T263	1
auto[1342177280:1476395007]	auto[0]	118	1			T1	3		T200	1		T49	1
auto[1342177280:1476395007]	auto[1]	7	1			T251	1		T397	2		T395	1
auto[1476395008:1610612735]	auto[0]	123	1			T1	2		T2	1		T3	3
auto[1476395008:1610612735]	auto[1]	13	1			T113	2		T144	1		T289	1
auto[1610612736:1744830463]	auto[0]	147	1			T1	2		T3	4		T16	1
auto[1610612736:1744830463]	auto[1]	3	1			T113	1		T263	1		T254	1
auto[1744830464:1879048191]	auto[0]	124	1			T1	2		T3	2		T17	1
auto[1744830464:1879048191]	auto[1]	13	1			T113	1		T253	2		T250	1
auto[1879048192:2013265919]	auto[0]	123	1			T1	3		T3	1		T123	1
auto[1879048192:2013265919]	auto[1]	9	1			T133	1		T396	1		T289	1
auto[2013265920:2147483647]	auto[0]	125	1			T1	2		T3	3		T17	1
auto[2013265920:2147483647]	auto[1]	12	1			T113	1		T144	2		T131	1
auto[2147483648:2281701375]	auto[0]	122	1			T1	3		T3	3		T104	1
auto[2147483648:2281701375]	auto[1]	10	1			T231	2		T250	1		T251	1
auto[2281701376:2415919103]	auto[0]	127	1			T1	5		T17	1		T192	1
auto[2281701376:2415919103]	auto[1]	8	1			T143	2		T133	1		T239	1
auto[2415919104:2550136831]	auto[0]	122	1			T1	1		T3	2		T17	1
auto[2415919104:2550136831]	auto[1]	11	1			T113	1		T396	1		T357	1
auto[2550136832:2684354559]	auto[0]	124	1			T1	1		T3	3		T38	2
auto[2550136832:2684354559]	auto[1]	8	1			T113	1		T231	1		T254	1
auto[2684354560:2818572287]	auto[0]	120	1			T1	2		T3	3		T126	1
auto[2684354560:2818572287]	auto[1]	11	1			T253	1		T251	2		T396	1
auto[2818572288:2952790015]	auto[0]	121	1			T3	2		T16	1		T200	1
auto[2818572288:2952790015]	auto[1]	12	1			T130	1		T144	1		T133	1
auto[2952790016:3087007743]	auto[0]	119	1			T1	2		T16	1		T17	1
auto[2952790016:3087007743]	auto[1]	8	1			T253	1		T231	1		T263	1
auto[3087007744:3221225471]	auto[0]	128	1			T3	2		T197	2		T192	1
auto[3087007744:3221225471]	auto[1]	10	1			T232	1		T397	2		T325	1
auto[3221225472:3355443199]	auto[0]	118	1			T1	1		T3	2		T47	1
auto[3221225472:3355443199]	auto[1]	7	1			T113	1		T239	1		T354	1
auto[3355443200:3489660927]	auto[0]	143	1			T1	2		T3	3		T17	2
auto[3355443200:3489660927]	auto[1]	10	1			T396	1		T344	1		T379	1
auto[3489660928:3623878655]	auto[0]	133	1			T1	4		T2	1		T3	2
auto[3489660928:3623878655]	auto[1]	8	1			T113	1		T231	1		T254	1
auto[3623878656:3758096383]	auto[0]	118	1			T1	3		T2	1		T3	3
auto[3623878656:3758096383]	auto[1]	12	1			T113	1		T134	1		T251	1
auto[3758096384:3892314111]	auto[0]	121	1			T1	4		T3	1		T124	1
auto[3758096384:3892314111]	auto[1]	6	1			T104	1		T287	1		T397	1
auto[3892314112:4026531839]	auto[0]	131	1			T1	2		T3	2		T16	3
auto[3892314112:4026531839]	auto[1]	11	1			T133	2		T253	1		T254	1
auto[4026531840:4160749567]	auto[0]	137	1			T1	3		T3	1		T17	2
auto[4026531840:4160749567]	auto[1]	10	1			T231	1		T396	1		T357	1
auto[4160749568:4294967295]	auto[0]	135	1			T1	1		T3	1		T16	1
auto[4160749568:4294967295]	auto[1]	7	1			T289	1		T395	1		T392	1