Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.04 97.91 98.47 100.00 99.02 98.41 91.19


Total test records in report: 1085
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1003 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2215190695 Jun 05 04:29:05 PM PDT 24 Jun 05 04:29:07 PM PDT 24 32968790 ps
T1004 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2232524986 Jun 05 04:28:27 PM PDT 24 Jun 05 04:28:28 PM PDT 24 12200188 ps
T1005 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.880338901 Jun 05 04:28:10 PM PDT 24 Jun 05 04:28:11 PM PDT 24 16123272 ps
T1006 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3564154714 Jun 05 04:28:23 PM PDT 24 Jun 05 04:28:25 PM PDT 24 86362412 ps
T1007 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2881757885 Jun 05 04:28:46 PM PDT 24 Jun 05 04:29:02 PM PDT 24 816735848 ps
T1008 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.337594392 Jun 05 04:28:47 PM PDT 24 Jun 05 04:28:49 PM PDT 24 18522267 ps
T1009 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.648614169 Jun 05 04:28:53 PM PDT 24 Jun 05 04:28:55 PM PDT 24 340408513 ps
T1010 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3128653443 Jun 05 04:28:06 PM PDT 24 Jun 05 04:28:08 PM PDT 24 19250204 ps
T1011 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.221889469 Jun 05 04:28:38 PM PDT 24 Jun 05 04:28:40 PM PDT 24 186595285 ps
T1012 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1032592456 Jun 05 04:28:22 PM PDT 24 Jun 05 04:28:25 PM PDT 24 49954715 ps
T1013 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2819926500 Jun 05 04:28:51 PM PDT 24 Jun 05 04:28:54 PM PDT 24 215388873 ps
T1014 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1413718019 Jun 05 04:28:26 PM PDT 24 Jun 05 04:28:28 PM PDT 24 27063836 ps
T1015 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.903844020 Jun 05 04:28:00 PM PDT 24 Jun 05 04:28:02 PM PDT 24 51185788 ps
T1016 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3371996357 Jun 05 04:28:24 PM PDT 24 Jun 05 04:28:32 PM PDT 24 168325027 ps
T1017 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.451445426 Jun 05 04:28:14 PM PDT 24 Jun 05 04:28:16 PM PDT 24 97128777 ps
T1018 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3956230499 Jun 05 04:29:07 PM PDT 24 Jun 05 04:29:09 PM PDT 24 13824525 ps
T1019 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3441702774 Jun 05 04:28:22 PM PDT 24 Jun 05 04:28:24 PM PDT 24 179606041 ps
T1020 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1674597996 Jun 05 04:28:55 PM PDT 24 Jun 05 04:29:01 PM PDT 24 117685167 ps
T1021 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2229801878 Jun 05 04:28:35 PM PDT 24 Jun 05 04:28:38 PM PDT 24 70177596 ps
T173 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3519923688 Jun 05 04:28:23 PM PDT 24 Jun 05 04:28:27 PM PDT 24 72205660 ps
T169 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1270206199 Jun 05 04:28:17 PM PDT 24 Jun 05 04:28:26 PM PDT 24 482841703 ps
T1022 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3387516926 Jun 05 04:29:07 PM PDT 24 Jun 05 04:29:09 PM PDT 24 46034020 ps
T1023 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3235952663 Jun 05 04:28:55 PM PDT 24 Jun 05 04:28:56 PM PDT 24 100167563 ps
T1024 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3636200130 Jun 05 04:28:47 PM PDT 24 Jun 05 04:28:49 PM PDT 24 15667058 ps
T1025 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2314641758 Jun 05 04:28:46 PM PDT 24 Jun 05 04:28:48 PM PDT 24 52166699 ps
T1026 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.371993461 Jun 05 04:28:00 PM PDT 24 Jun 05 04:28:03 PM PDT 24 40883252 ps
T1027 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3791719415 Jun 05 04:29:07 PM PDT 24 Jun 05 04:29:09 PM PDT 24 34293098 ps
T1028 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.301261956 Jun 05 04:28:14 PM PDT 24 Jun 05 04:28:18 PM PDT 24 111062464 ps
T1029 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1820853272 Jun 05 04:28:47 PM PDT 24 Jun 05 04:28:49 PM PDT 24 37011666 ps
T1030 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3682422877 Jun 05 04:29:05 PM PDT 24 Jun 05 04:29:06 PM PDT 24 19225208 ps
T1031 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1649664440 Jun 05 04:28:16 PM PDT 24 Jun 05 04:28:18 PM PDT 24 224010914 ps
T1032 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2533427642 Jun 05 04:29:07 PM PDT 24 Jun 05 04:29:09 PM PDT 24 7719253 ps
T1033 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3080425623 Jun 05 04:28:30 PM PDT 24 Jun 05 04:28:31 PM PDT 24 14370769 ps
T1034 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3721357216 Jun 05 04:28:06 PM PDT 24 Jun 05 04:28:09 PM PDT 24 38220310 ps
T1035 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1908315857 Jun 05 04:28:44 PM PDT 24 Jun 05 04:28:48 PM PDT 24 281536957 ps
T1036 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.370204883 Jun 05 04:28:53 PM PDT 24 Jun 05 04:28:56 PM PDT 24 54024892 ps
T1037 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.148749541 Jun 05 04:28:47 PM PDT 24 Jun 05 04:28:50 PM PDT 24 144496106 ps
T1038 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2898957563 Jun 05 04:29:05 PM PDT 24 Jun 05 04:29:07 PM PDT 24 9495614 ps
T1039 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2714612737 Jun 05 04:29:07 PM PDT 24 Jun 05 04:29:09 PM PDT 24 52695218 ps
T1040 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.113147296 Jun 05 04:29:06 PM PDT 24 Jun 05 04:29:07 PM PDT 24 9253461 ps
T1041 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1225758121 Jun 05 04:28:54 PM PDT 24 Jun 05 04:28:56 PM PDT 24 83987761 ps
T1042 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.207465307 Jun 05 04:28:35 PM PDT 24 Jun 05 04:28:39 PM PDT 24 44941897 ps
T1043 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2838940623 Jun 05 04:28:56 PM PDT 24 Jun 05 04:29:01 PM PDT 24 367711037 ps
T1044 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.350855189 Jun 05 04:28:14 PM PDT 24 Jun 05 04:28:22 PM PDT 24 880207744 ps
T1045 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2789825514 Jun 05 04:28:48 PM PDT 24 Jun 05 04:28:51 PM PDT 24 23811132 ps
T1046 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1761293079 Jun 05 04:29:07 PM PDT 24 Jun 05 04:29:09 PM PDT 24 13384182 ps
T1047 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1641217013 Jun 05 04:28:27 PM PDT 24 Jun 05 04:28:33 PM PDT 24 375566336 ps
T1048 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1517194107 Jun 05 04:28:46 PM PDT 24 Jun 05 04:28:51 PM PDT 24 236018992 ps
T1049 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2190450827 Jun 05 04:28:26 PM PDT 24 Jun 05 04:28:27 PM PDT 24 43356115 ps
T1050 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3999023895 Jun 05 04:28:29 PM PDT 24 Jun 05 04:28:34 PM PDT 24 156230937 ps
T1051 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3613463159 Jun 05 04:28:27 PM PDT 24 Jun 05 04:28:28 PM PDT 24 21809227 ps
T1052 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4002670108 Jun 05 04:29:07 PM PDT 24 Jun 05 04:29:09 PM PDT 24 37200167 ps
T1053 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.123521190 Jun 05 04:28:53 PM PDT 24 Jun 05 04:28:55 PM PDT 24 187766158 ps
T1054 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2698742999 Jun 05 04:28:55 PM PDT 24 Jun 05 04:28:58 PM PDT 24 543692899 ps
T1055 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1055385090 Jun 05 04:27:59 PM PDT 24 Jun 05 04:28:03 PM PDT 24 785006993 ps
T1056 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2952394868 Jun 05 04:28:02 PM PDT 24 Jun 05 04:28:03 PM PDT 24 13694485 ps
T1057 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.521472714 Jun 05 04:28:45 PM PDT 24 Jun 05 04:28:47 PM PDT 24 50191135 ps
T1058 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1077391901 Jun 05 04:28:01 PM PDT 24 Jun 05 04:28:11 PM PDT 24 311172084 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1294415647 Jun 05 04:28:17 PM PDT 24 Jun 05 04:28:18 PM PDT 24 35153480 ps
T1060 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3642026200 Jun 05 04:28:35 PM PDT 24 Jun 05 04:28:36 PM PDT 24 29014083 ps
T1061 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1865708670 Jun 05 04:28:33 PM PDT 24 Jun 05 04:28:38 PM PDT 24 598834822 ps
T1062 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2497438817 Jun 05 04:28:14 PM PDT 24 Jun 05 04:28:22 PM PDT 24 205337866 ps
T1063 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1308286979 Jun 05 04:28:54 PM PDT 24 Jun 05 04:28:57 PM PDT 24 40026615 ps
T1064 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.246478878 Jun 05 04:28:33 PM PDT 24 Jun 05 04:28:39 PM PDT 24 771428790 ps
T1065 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1275877647 Jun 05 04:28:55 PM PDT 24 Jun 05 04:29:00 PM PDT 24 97940992 ps
T1066 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.370661898 Jun 05 04:28:46 PM PDT 24 Jun 05 04:28:50 PM PDT 24 468047133 ps
T1067 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1592972571 Jun 05 04:29:05 PM PDT 24 Jun 05 04:29:06 PM PDT 24 9732324 ps
T1068 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.235841097 Jun 05 04:28:56 PM PDT 24 Jun 05 04:28:58 PM PDT 24 228276661 ps
T1069 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2222840231 Jun 05 04:28:57 PM PDT 24 Jun 05 04:29:09 PM PDT 24 1242109847 ps
T1070 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3644726912 Jun 05 04:28:01 PM PDT 24 Jun 05 04:28:03 PM PDT 24 68293335 ps
T1071 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.94874279 Jun 05 04:29:05 PM PDT 24 Jun 05 04:29:07 PM PDT 24 34396376 ps
T1072 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3427094369 Jun 05 04:28:11 PM PDT 24 Jun 05 04:28:13 PM PDT 24 154850259 ps
T1073 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2431968700 Jun 05 04:28:28 PM PDT 24 Jun 05 04:28:32 PM PDT 24 302120652 ps
T1074 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2096176194 Jun 05 04:29:08 PM PDT 24 Jun 05 04:29:10 PM PDT 24 12531827 ps
T1075 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.726249000 Jun 05 04:28:52 PM PDT 24 Jun 05 04:29:03 PM PDT 24 483661057 ps
T1076 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2043446156 Jun 05 04:28:05 PM PDT 24 Jun 05 04:28:13 PM PDT 24 137511246 ps
T1077 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4198078694 Jun 05 04:28:30 PM PDT 24 Jun 05 04:28:32 PM PDT 24 120331550 ps
T1078 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.49399985 Jun 05 04:29:07 PM PDT 24 Jun 05 04:29:09 PM PDT 24 14179128 ps
T1079 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4115465259 Jun 05 04:28:31 PM PDT 24 Jun 05 04:28:34 PM PDT 24 24503915 ps
T1080 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3343990510 Jun 05 04:28:56 PM PDT 24 Jun 05 04:29:07 PM PDT 24 1965224141 ps
T1081 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1980039425 Jun 05 04:28:52 PM PDT 24 Jun 05 04:28:57 PM PDT 24 99137740 ps
T1082 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3305862866 Jun 05 04:28:56 PM PDT 24 Jun 05 04:28:58 PM PDT 24 14388678 ps
T1083 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3545461201 Jun 05 04:28:08 PM PDT 24 Jun 05 04:28:09 PM PDT 24 17637300 ps
T1084 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2164343936 Jun 05 04:28:22 PM PDT 24 Jun 05 04:28:24 PM PDT 24 52873394 ps
T1085 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4018701878 Jun 05 04:29:06 PM PDT 24 Jun 05 04:29:07 PM PDT 24 197885575 ps

Test location /workspace/coverage/default/0.keymgr_stress_all.2394825199
Short name T1
Test name
Test status
Simulation time 4406071787 ps
CPU time 41.22 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:09:12 PM PDT 24
Peak memory 222828 kb
Host smart-d873a2b4-e30a-431b-bece-84ce367f5e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394825199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2394825199
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3897212184
Short name T52
Test name
Test status
Simulation time 13044588764 ps
CPU time 238.77 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:14:50 PM PDT 24
Peak memory 216240 kb
Host smart-3cd2eac4-dade-4ad5-b80a-54385b698ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897212184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3897212184
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2472718805
Short name T10
Test name
Test status
Simulation time 466259152 ps
CPU time 10.76 seconds
Started Jun 05 04:08:48 PM PDT 24
Finished Jun 05 04:08:59 PM PDT 24
Peak memory 229176 kb
Host smart-3f8f11a9-72ca-4bbb-8331-9dba2c46e608
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472718805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2472718805
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1326885778
Short name T120
Test name
Test status
Simulation time 1223362400 ps
CPU time 12.28 seconds
Started Jun 05 04:11:00 PM PDT 24
Finished Jun 05 04:11:14 PM PDT 24
Peak memory 222572 kb
Host smart-10e3666c-1136-43a9-b9f8-0996f83f2882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326885778 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1326885778
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2557073476
Short name T5
Test name
Test status
Simulation time 8223779999 ps
CPU time 49.08 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:12:16 PM PDT 24
Peak memory 221952 kb
Host smart-f45e4917-1073-498b-9db9-864daa6e265f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557073476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2557073476
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2988855715
Short name T133
Test name
Test status
Simulation time 2498340194 ps
CPU time 32.75 seconds
Started Jun 05 04:10:02 PM PDT 24
Finished Jun 05 04:10:36 PM PDT 24
Peak memory 214392 kb
Host smart-69b7d3dd-976d-4ddc-b496-71037b1d6963
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988855715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2988855715
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3047849400
Short name T24
Test name
Test status
Simulation time 249354606 ps
CPU time 5.29 seconds
Started Jun 05 04:10:11 PM PDT 24
Finished Jun 05 04:10:18 PM PDT 24
Peak memory 222732 kb
Host smart-da5822c3-1eee-42ff-bb48-1ddb2a492bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047849400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3047849400
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4276809501
Short name T3
Test name
Test status
Simulation time 5816160821 ps
CPU time 63.64 seconds
Started Jun 05 04:09:30 PM PDT 24
Finished Jun 05 04:10:35 PM PDT 24
Peak memory 222616 kb
Host smart-67d2d582-f661-414e-ac94-969d9f31c4cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276809501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4276809501
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1129996276
Short name T8
Test name
Test status
Simulation time 4720457424 ps
CPU time 35.56 seconds
Started Jun 05 04:09:01 PM PDT 24
Finished Jun 05 04:09:38 PM PDT 24
Peak memory 210028 kb
Host smart-bbf88760-fc1e-431b-ae36-8fbbcd6d8877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129996276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1129996276
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1705575184
Short name T395
Test name
Test status
Simulation time 1452625186 ps
CPU time 82.7 seconds
Started Jun 05 04:11:15 PM PDT 24
Finished Jun 05 04:12:39 PM PDT 24
Peak memory 215416 kb
Host smart-bd49520e-ba4b-4de8-bff1-a0661d78364a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705575184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1705575184
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2769886650
Short name T106
Test name
Test status
Simulation time 1633625027 ps
CPU time 9.13 seconds
Started Jun 05 04:28:22 PM PDT 24
Finished Jun 05 04:28:31 PM PDT 24
Peak memory 214140 kb
Host smart-529905b7-08ce-4184-8a6c-1edaa458a3bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769886650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2769886650
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.39230710
Short name T154
Test name
Test status
Simulation time 531594233 ps
CPU time 4.97 seconds
Started Jun 05 04:27:58 PM PDT 24
Finished Jun 05 04:28:04 PM PDT 24
Peak memory 205936 kb
Host smart-5fee3a2c-3140-4124-85e8-7ca736c8278a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39230710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.39230710
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.4189644725
Short name T23
Test name
Test status
Simulation time 249440916 ps
CPU time 4.07 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:32 PM PDT 24
Peak memory 215124 kb
Host smart-bcee122d-4553-402e-97f2-0b5c0f224e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189644725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.4189644725
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.230221960
Short name T39
Test name
Test status
Simulation time 499249247 ps
CPU time 2.81 seconds
Started Jun 05 04:10:34 PM PDT 24
Finished Jun 05 04:10:38 PM PDT 24
Peak memory 221620 kb
Host smart-e5adb021-5c04-4fa1-9379-124be06b6647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230221960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.230221960
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.4135834209
Short name T17
Test name
Test status
Simulation time 901927896 ps
CPU time 18.2 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:11:00 PM PDT 24
Peak memory 222632 kb
Host smart-53843593-3653-4fe4-8ce4-ab804c118450
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135834209 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.4135834209
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3356717572
Short name T396
Test name
Test status
Simulation time 5159039299 ps
CPU time 71.76 seconds
Started Jun 05 04:09:47 PM PDT 24
Finished Jun 05 04:11:00 PM PDT 24
Peak memory 215188 kb
Host smart-411a42ae-bad2-48d1-b6b6-633e217f7aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356717572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3356717572
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.835312570
Short name T6
Test name
Test status
Simulation time 12383901141 ps
CPU time 122.15 seconds
Started Jun 05 04:10:12 PM PDT 24
Finished Jun 05 04:12:15 PM PDT 24
Peak memory 221720 kb
Host smart-f2409a3e-4364-4041-902c-17e3041501be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835312570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.835312570
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2017528597
Short name T254
Test name
Test status
Simulation time 5708252218 ps
CPU time 15.89 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:16 PM PDT 24
Peak memory 214360 kb
Host smart-dce89731-a6ef-4baf-afec-02cb373e3662
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017528597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2017528597
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.36664564
Short name T940
Test name
Test status
Simulation time 534298512 ps
CPU time 4.46 seconds
Started Jun 05 04:28:46 PM PDT 24
Finished Jun 05 04:28:51 PM PDT 24
Peak memory 214272 kb
Host smart-bdd6b528-237a-4856-bb81-13b2613c66fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36664564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow
_reg_errors.36664564
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3735930325
Short name T394
Test name
Test status
Simulation time 14451741125 ps
CPU time 54.89 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:10:23 PM PDT 24
Peak memory 214892 kb
Host smart-86b2d77c-c485-4144-9e07-6ac630ea4529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735930325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3735930325
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1920717051
Short name T164
Test name
Test status
Simulation time 440885853 ps
CPU time 21.13 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:20 PM PDT 24
Peak memory 220748 kb
Host smart-ce8149a5-ad54-4d83-822c-40d3b7c373f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920717051 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1920717051
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2368092404
Short name T38
Test name
Test status
Simulation time 233425811 ps
CPU time 4.85 seconds
Started Jun 05 04:09:19 PM PDT 24
Finished Jun 05 04:09:24 PM PDT 24
Peak memory 210136 kb
Host smart-589ed226-8176-4f59-b964-f5a7aea399e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368092404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2368092404
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1475345484
Short name T31
Test name
Test status
Simulation time 41165364 ps
CPU time 2.47 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:10:35 PM PDT 24
Peak memory 214304 kb
Host smart-278345dd-7384-4e89-8500-3388b50ba268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475345484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1475345484
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3460769378
Short name T113
Test name
Test status
Simulation time 748894474 ps
CPU time 9.73 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:14 PM PDT 24
Peak memory 214316 kb
Host smart-84c325ad-563b-4ade-8308-0260e026ace6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460769378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3460769378
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1438239015
Short name T148
Test name
Test status
Simulation time 51612333 ps
CPU time 3.84 seconds
Started Jun 05 04:09:58 PM PDT 24
Finished Jun 05 04:10:03 PM PDT 24
Peak memory 218540 kb
Host smart-b7025e02-05b3-41a0-8591-6eea7cc1193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438239015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1438239015
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.4196923038
Short name T50
Test name
Test status
Simulation time 373883283 ps
CPU time 3.06 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:32 PM PDT 24
Peak memory 214280 kb
Host smart-f8679f88-374e-44b2-97c1-4c9c26e3e693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196923038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.4196923038
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3474869479
Short name T329
Test name
Test status
Simulation time 2896736775 ps
CPU time 40.32 seconds
Started Jun 05 04:09:45 PM PDT 24
Finished Jun 05 04:10:27 PM PDT 24
Peak memory 215184 kb
Host smart-2c252dd7-defc-4268-abf9-8910e36d24b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474869479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3474869479
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1740004119
Short name T253
Test name
Test status
Simulation time 425208957 ps
CPU time 5.81 seconds
Started Jun 05 04:11:28 PM PDT 24
Finished Jun 05 04:11:35 PM PDT 24
Peak memory 214332 kb
Host smart-428c5e9e-76fa-4594-bb0e-7b7059df08d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740004119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1740004119
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2629722541
Short name T374
Test name
Test status
Simulation time 147835854 ps
CPU time 1.96 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 209928 kb
Host smart-73f6ccff-f09a-4e7f-9657-15383510b7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629722541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2629722541
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.56156958
Short name T72
Test name
Test status
Simulation time 8303899549 ps
CPU time 83.81 seconds
Started Jun 05 04:09:57 PM PDT 24
Finished Jun 05 04:11:21 PM PDT 24
Peak memory 216216 kb
Host smart-d39697af-4cf5-42ea-9bb0-f165d63854e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56156958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.56156958
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3014843011
Short name T93
Test name
Test status
Simulation time 15377904 ps
CPU time 0.74 seconds
Started Jun 05 04:11:06 PM PDT 24
Finished Jun 05 04:11:08 PM PDT 24
Peak memory 205932 kb
Host smart-ae9380f5-f12c-4e7c-b9f3-6c0ccdb6795a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014843011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3014843011
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3908385188
Short name T4
Test name
Test status
Simulation time 4225998586 ps
CPU time 122.6 seconds
Started Jun 05 04:10:21 PM PDT 24
Finished Jun 05 04:12:24 PM PDT 24
Peak memory 222556 kb
Host smart-e7612c5c-6e79-4788-a421-8b01c2076506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908385188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3908385188
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3126423809
Short name T74
Test name
Test status
Simulation time 4800166487 ps
CPU time 40.85 seconds
Started Jun 05 04:11:17 PM PDT 24
Finished Jun 05 04:11:59 PM PDT 24
Peak memory 215900 kb
Host smart-d9985d68-6988-4451-af9b-31cf379773aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126423809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3126423809
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1002089871
Short name T30
Test name
Test status
Simulation time 478445548 ps
CPU time 3.88 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:21 PM PDT 24
Peak memory 210616 kb
Host smart-666038ce-27ca-467f-8016-45b58e986a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002089871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1002089871
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.909237189
Short name T144
Test name
Test status
Simulation time 140355172 ps
CPU time 7.92 seconds
Started Jun 05 04:11:17 PM PDT 24
Finished Jun 05 04:11:26 PM PDT 24
Peak memory 215428 kb
Host smart-d2603829-68a2-4496-93a0-35225d19187d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909237189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.909237189
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1953257306
Short name T67
Test name
Test status
Simulation time 847950586 ps
CPU time 33.25 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:12:11 PM PDT 24
Peak memory 216228 kb
Host smart-a2ab4382-8f25-4226-b6a1-709277e0565a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953257306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1953257306
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4016631838
Short name T171
Test name
Test status
Simulation time 5191686455 ps
CPU time 13.06 seconds
Started Jun 05 04:28:53 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 213844 kb
Host smart-92042962-1fba-40d7-a69c-63dd7b1a04e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016631838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4016631838
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1568943817
Short name T397
Test name
Test status
Simulation time 6546401315 ps
CPU time 58.72 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:10:26 PM PDT 24
Peak memory 215496 kb
Host smart-9337ab94-dfdb-4f54-b3d7-e2d7c6468e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568943817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1568943817
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1270206199
Short name T169
Test name
Test status
Simulation time 482841703 ps
CPU time 9.17 seconds
Started Jun 05 04:28:17 PM PDT 24
Finished Jun 05 04:28:26 PM PDT 24
Peak memory 213968 kb
Host smart-5f6d7dce-882b-4b8d-a59c-802b9c86b26c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270206199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1270206199
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1552018548
Short name T88
Test name
Test status
Simulation time 579225597 ps
CPU time 4.82 seconds
Started Jun 05 04:10:42 PM PDT 24
Finished Jun 05 04:10:48 PM PDT 24
Peak memory 214268 kb
Host smart-ed06576e-5b0b-4ae6-8a05-0b43e47a20f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552018548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1552018548
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1621793561
Short name T350
Test name
Test status
Simulation time 110757753 ps
CPU time 4.62 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 222364 kb
Host smart-e8d73853-fceb-495b-8234-4b82b732ead2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621793561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1621793561
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2334908469
Short name T279
Test name
Test status
Simulation time 197464078 ps
CPU time 2.75 seconds
Started Jun 05 04:10:06 PM PDT 24
Finished Jun 05 04:10:10 PM PDT 24
Peak memory 214336 kb
Host smart-97a2f863-1a9e-44b1-b91a-f5fe52c6c538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334908469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2334908469
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2725434113
Short name T250
Test name
Test status
Simulation time 1056524064 ps
CPU time 10.05 seconds
Started Jun 05 04:08:40 PM PDT 24
Finished Jun 05 04:08:50 PM PDT 24
Peak memory 214332 kb
Host smart-ba95310d-27ef-4046-b626-c916f484d537
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2725434113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2725434113
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.4282843561
Short name T332
Test name
Test status
Simulation time 63291808 ps
CPU time 2.54 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:20 PM PDT 24
Peak memory 220184 kb
Host smart-e2daa899-a04d-4051-b383-b35498f924f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282843561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4282843561
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2995491048
Short name T160
Test name
Test status
Simulation time 382114382 ps
CPU time 3.7 seconds
Started Jun 05 04:28:30 PM PDT 24
Finished Jun 05 04:28:34 PM PDT 24
Peak memory 213972 kb
Host smart-faa6be1a-0673-4b35-8512-f2e75794d596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995491048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2995491048
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3112622223
Short name T146
Test name
Test status
Simulation time 310905687 ps
CPU time 3.22 seconds
Started Jun 05 04:08:33 PM PDT 24
Finished Jun 05 04:08:37 PM PDT 24
Peak memory 217156 kb
Host smart-8793e7bb-bbd3-4bba-99e5-910bcbfdbb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112622223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3112622223
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1819501741
Short name T150
Test name
Test status
Simulation time 136169889 ps
CPU time 4.53 seconds
Started Jun 05 04:09:26 PM PDT 24
Finished Jun 05 04:09:32 PM PDT 24
Peak memory 217792 kb
Host smart-92c1f6a5-3d6c-4356-aa66-c60ca1cf74a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819501741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1819501741
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.879640557
Short name T49
Test name
Test status
Simulation time 161023377 ps
CPU time 2.87 seconds
Started Jun 05 04:09:57 PM PDT 24
Finished Jun 05 04:10:00 PM PDT 24
Peak memory 214328 kb
Host smart-2f25fc6d-294a-4dba-bb2d-e1431df2a10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879640557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.879640557
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3167612245
Short name T226
Test name
Test status
Simulation time 1098210816 ps
CPU time 39.83 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 222572 kb
Host smart-49111f30-0c34-4993-999f-25cf7ccb02b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167612245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3167612245
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3593169263
Short name T68
Test name
Test status
Simulation time 7703081605 ps
CPU time 20.34 seconds
Started Jun 05 04:10:33 PM PDT 24
Finished Jun 05 04:10:54 PM PDT 24
Peak memory 222620 kb
Host smart-a9c0d464-85f5-463a-8814-30a11f577918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593169263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3593169263
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2653717682
Short name T232
Test name
Test status
Simulation time 259630781 ps
CPU time 12.76 seconds
Started Jun 05 04:10:57 PM PDT 24
Finished Jun 05 04:11:10 PM PDT 24
Peak memory 214320 kb
Host smart-68e2ecb8-eab3-4465-87f4-bbe46b87f7c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653717682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2653717682
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3728127057
Short name T166
Test name
Test status
Simulation time 114050065 ps
CPU time 2.42 seconds
Started Jun 05 04:10:13 PM PDT 24
Finished Jun 05 04:10:16 PM PDT 24
Peak memory 209960 kb
Host smart-7a81dcc6-efd0-4d53-b33d-9ed7f6f38adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728127057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3728127057
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.117464914
Short name T45
Test name
Test status
Simulation time 2099559568 ps
CPU time 12.08 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:43 PM PDT 24
Peak memory 234460 kb
Host smart-38e8679d-2658-4153-9575-277cec8367f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117464914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.117464914
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2856648971
Short name T65
Test name
Test status
Simulation time 192346550 ps
CPU time 2.52 seconds
Started Jun 05 04:11:07 PM PDT 24
Finished Jun 05 04:11:11 PM PDT 24
Peak memory 222632 kb
Host smart-3ae18e37-b203-43ab-a965-7c1a72261279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856648971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2856648971
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1519209059
Short name T221
Test name
Test status
Simulation time 6873388982 ps
CPU time 37.62 seconds
Started Jun 05 04:09:42 PM PDT 24
Finished Jun 05 04:10:21 PM PDT 24
Peak memory 216528 kb
Host smart-63e9381a-d663-4754-b62f-f8dcd2ccd966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519209059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1519209059
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4165301233
Short name T401
Test name
Test status
Simulation time 793855126 ps
CPU time 9.59 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:08:41 PM PDT 24
Peak memory 214440 kb
Host smart-ae74e185-d06c-4a10-aa71-d6523f8619f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165301233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4165301233
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1113837629
Short name T210
Test name
Test status
Simulation time 546678346 ps
CPU time 26.62 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:11:19 PM PDT 24
Peak memory 215604 kb
Host smart-20c6a80a-25f5-444c-a7b9-b597565c3f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113837629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1113837629
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2775815096
Short name T262
Test name
Test status
Simulation time 182227153 ps
CPU time 4.8 seconds
Started Jun 05 04:11:38 PM PDT 24
Finished Jun 05 04:11:44 PM PDT 24
Peak memory 222572 kb
Host smart-ec034dc9-a13a-4bfb-9894-cc722769dd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775815096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2775815096
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3964185084
Short name T264
Test name
Test status
Simulation time 119472913 ps
CPU time 4.02 seconds
Started Jun 05 04:08:55 PM PDT 24
Finished Jun 05 04:08:59 PM PDT 24
Peak memory 214368 kb
Host smart-2c9b8a77-9250-4fb0-8a11-66d2ab8faf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964185084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3964185084
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2826522424
Short name T149
Test name
Test status
Simulation time 415826121 ps
CPU time 4.11 seconds
Started Jun 05 04:09:26 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 218008 kb
Host smart-8152d6b0-e7f9-455e-83fb-40bf600dc40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826522424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2826522424
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1136368361
Short name T147
Test name
Test status
Simulation time 135283982 ps
CPU time 4.62 seconds
Started Jun 05 04:09:55 PM PDT 24
Finished Jun 05 04:10:01 PM PDT 24
Peak memory 222636 kb
Host smart-5aee0c2e-6a2b-431e-8d17-5cdb15f633c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136368361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1136368361
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2974069587
Short name T145
Test name
Test status
Simulation time 105318271 ps
CPU time 3.19 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 222612 kb
Host smart-050a767d-172d-4761-a394-4495c492ccb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974069587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2974069587
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2957632048
Short name T230
Test name
Test status
Simulation time 99438034 ps
CPU time 3.92 seconds
Started Jun 05 04:09:43 PM PDT 24
Finished Jun 05 04:09:48 PM PDT 24
Peak memory 208444 kb
Host smart-debae045-f3fa-4979-9233-aad7243dd0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957632048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2957632048
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1748547811
Short name T406
Test name
Test status
Simulation time 60729008 ps
CPU time 4.25 seconds
Started Jun 05 04:09:47 PM PDT 24
Finished Jun 05 04:09:52 PM PDT 24
Peak memory 215132 kb
Host smart-5822214f-1992-4b1a-9ef5-f7002e96abf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748547811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1748547811
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.478104380
Short name T243
Test name
Test status
Simulation time 83615557 ps
CPU time 3.68 seconds
Started Jun 05 04:09:45 PM PDT 24
Finished Jun 05 04:09:50 PM PDT 24
Peak memory 218344 kb
Host smart-0739af17-a67a-41ae-a9cb-398ec7b9d628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478104380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.478104380
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.104676162
Short name T801
Test name
Test status
Simulation time 53406368 ps
CPU time 2.52 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:07 PM PDT 24
Peak memory 210120 kb
Host smart-541cd544-0922-45c5-8f2b-8aca79fad0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104676162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.104676162
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2640572593
Short name T77
Test name
Test status
Simulation time 6714467097 ps
CPU time 66.61 seconds
Started Jun 05 04:10:11 PM PDT 24
Finished Jun 05 04:11:19 PM PDT 24
Peak memory 215428 kb
Host smart-b0037dd4-6de8-4909-9d0b-a2e84035960e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640572593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2640572593
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3265900587
Short name T361
Test name
Test status
Simulation time 569991448 ps
CPU time 5.68 seconds
Started Jun 05 04:10:29 PM PDT 24
Finished Jun 05 04:10:35 PM PDT 24
Peak memory 214256 kb
Host smart-e2256eae-5513-4750-a784-845be5c4cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265900587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3265900587
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3677976782
Short name T233
Test name
Test status
Simulation time 3270117128 ps
CPU time 39.31 seconds
Started Jun 05 04:11:29 PM PDT 24
Finished Jun 05 04:12:09 PM PDT 24
Peak memory 214640 kb
Host smart-11e600ff-c187-4579-b573-88914edce887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677976782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3677976782
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.251578791
Short name T26
Test name
Test status
Simulation time 183867668 ps
CPU time 4.9 seconds
Started Jun 05 04:09:05 PM PDT 24
Finished Jun 05 04:09:11 PM PDT 24
Peak memory 219172 kb
Host smart-f3cdade6-5ae6-4274-9f17-a43d273a1a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251578791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.251578791
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2813750489
Short name T309
Test name
Test status
Simulation time 4950238807 ps
CPU time 29.82 seconds
Started Jun 05 04:09:15 PM PDT 24
Finished Jun 05 04:09:45 PM PDT 24
Peak memory 222540 kb
Host smart-96b0c286-35ff-488b-bc39-d8781accf22d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813750489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2813750489
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3830519836
Short name T172
Test name
Test status
Simulation time 1223881403 ps
CPU time 8.39 seconds
Started Jun 05 04:28:06 PM PDT 24
Finished Jun 05 04:28:15 PM PDT 24
Peak memory 213956 kb
Host smart-fa50b7e3-a91d-46e6-85a2-7e1696b60eb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830519836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3830519836
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3596081148
Short name T162
Test name
Test status
Simulation time 194906029 ps
CPU time 5.14 seconds
Started Jun 05 04:28:38 PM PDT 24
Finished Jun 05 04:28:44 PM PDT 24
Peak memory 213856 kb
Host smart-0e9daacb-8c72-4e0f-b06e-06f3e57e28a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596081148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3596081148
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3697845546
Short name T165
Test name
Test status
Simulation time 227596235 ps
CPU time 3.05 seconds
Started Jun 05 04:28:46 PM PDT 24
Finished Jun 05 04:28:50 PM PDT 24
Peak memory 213868 kb
Host smart-a70e5193-2c58-408e-b632-4b484ee60290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697845546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3697845546
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1895641778
Short name T446
Test name
Test status
Simulation time 1784997056 ps
CPU time 34.14 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:09:04 PM PDT 24
Peak memory 208508 kb
Host smart-ae7a0730-ac20-4e05-958e-216082821153
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895641778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1895641778
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1424252032
Short name T387
Test name
Test status
Simulation time 121755887 ps
CPU time 2.36 seconds
Started Jun 05 04:08:32 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 207204 kb
Host smart-b29f250f-b5c0-4f87-a0d0-7d88d810a9fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424252032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1424252032
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3207394451
Short name T223
Test name
Test status
Simulation time 1976309456 ps
CPU time 30 seconds
Started Jun 05 04:09:29 PM PDT 24
Finished Jun 05 04:10:00 PM PDT 24
Peak memory 220800 kb
Host smart-f6035a37-cfb4-4dc1-873c-215405fc93d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207394451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3207394451
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3964079
Short name T316
Test name
Test status
Simulation time 228058058 ps
CPU time 2.95 seconds
Started Jun 05 04:09:29 PM PDT 24
Finished Jun 05 04:09:33 PM PDT 24
Peak memory 214264 kb
Host smart-9c290e68-012b-428f-9537-084f3dd42fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3964079
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1622071275
Short name T672
Test name
Test status
Simulation time 52133076 ps
CPU time 1.72 seconds
Started Jun 05 04:09:36 PM PDT 24
Finished Jun 05 04:09:39 PM PDT 24
Peak memory 210056 kb
Host smart-044d89d5-25d2-4b62-81bd-3699e582ec70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622071275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1622071275
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3622026149
Short name T865
Test name
Test status
Simulation time 103484872 ps
CPU time 3.33 seconds
Started Jun 05 04:09:36 PM PDT 24
Finished Jun 05 04:09:40 PM PDT 24
Peak memory 214260 kb
Host smart-5e299beb-4077-4d69-a355-942a9a62d9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622026149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3622026149
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2812453061
Short name T271
Test name
Test status
Simulation time 154823093 ps
CPU time 5.35 seconds
Started Jun 05 04:09:48 PM PDT 24
Finished Jun 05 04:09:54 PM PDT 24
Peak memory 214400 kb
Host smart-112cfbcb-a832-4e06-8cb0-2d14cbbf8092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812453061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2812453061
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3259382289
Short name T211
Test name
Test status
Simulation time 430788411 ps
CPU time 4.21 seconds
Started Jun 05 04:09:44 PM PDT 24
Finished Jun 05 04:09:49 PM PDT 24
Peak memory 206396 kb
Host smart-d8a4ca43-16b3-4dda-8efe-ae343a743cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259382289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3259382289
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.580158953
Short name T323
Test name
Test status
Simulation time 2797569546 ps
CPU time 24.68 seconds
Started Jun 05 04:09:53 PM PDT 24
Finished Jun 05 04:10:18 PM PDT 24
Peak memory 215408 kb
Host smart-0297b5b3-5511-40cf-b87d-4fe773090216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580158953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.580158953
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2971555058
Short name T225
Test name
Test status
Simulation time 354202772 ps
CPU time 4.01 seconds
Started Jun 05 04:08:35 PM PDT 24
Finished Jun 05 04:08:39 PM PDT 24
Peak memory 209536 kb
Host smart-64fd17ee-4a52-4aff-b3f7-f1ed85a860bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971555058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2971555058
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.118883634
Short name T355
Test name
Test status
Simulation time 67603857 ps
CPU time 2.45 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 210560 kb
Host smart-8a8e969c-a489-4eb1-9264-896144424708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118883634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.118883634
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.944978333
Short name T301
Test name
Test status
Simulation time 78985243 ps
CPU time 2.98 seconds
Started Jun 05 04:10:04 PM PDT 24
Finished Jun 05 04:10:08 PM PDT 24
Peak memory 214328 kb
Host smart-4cb495fd-6a36-4301-b1f3-31806ed2e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944978333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.944978333
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.706970450
Short name T80
Test name
Test status
Simulation time 324819063 ps
CPU time 3.52 seconds
Started Jun 05 04:10:05 PM PDT 24
Finished Jun 05 04:10:10 PM PDT 24
Peak memory 214848 kb
Host smart-d32212ab-87b9-406f-870d-1abe7964b07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706970450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.706970450
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.4037370208
Short name T297
Test name
Test status
Simulation time 435943806 ps
CPU time 7.11 seconds
Started Jun 05 04:10:11 PM PDT 24
Finished Jun 05 04:10:19 PM PDT 24
Peak memory 215232 kb
Host smart-2e08cb67-41b3-425b-b957-9d8815a611c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037370208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.4037370208
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3329172462
Short name T58
Test name
Test status
Simulation time 2099772912 ps
CPU time 22.85 seconds
Started Jun 05 04:10:12 PM PDT 24
Finished Jun 05 04:10:36 PM PDT 24
Peak memory 216732 kb
Host smart-d05cc497-2987-4e21-8696-1680c732cb73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329172462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3329172462
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.622522895
Short name T366
Test name
Test status
Simulation time 44419849 ps
CPU time 2.79 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:52 PM PDT 24
Peak memory 214236 kb
Host smart-13358e10-19e9-49cf-8a39-712b82d0ae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622522895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.622522895
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.656016942
Short name T152
Test name
Test status
Simulation time 210768784 ps
CPU time 3.03 seconds
Started Jun 05 04:10:48 PM PDT 24
Finished Jun 05 04:10:51 PM PDT 24
Peak memory 218036 kb
Host smart-6adfff78-c60e-4efb-a1cb-27073ac219e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656016942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.656016942
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1264210544
Short name T151
Test name
Test status
Simulation time 653886860 ps
CPU time 3.12 seconds
Started Jun 05 04:11:28 PM PDT 24
Finished Jun 05 04:11:32 PM PDT 24
Peak memory 216780 kb
Host smart-471ad1b5-e0fa-42d5-a1f7-ddc19c0992da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264210544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1264210544
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3757044834
Short name T978
Test name
Test status
Simulation time 467182668 ps
CPU time 11.29 seconds
Started Jun 05 04:28:04 PM PDT 24
Finished Jun 05 04:28:15 PM PDT 24
Peak memory 205652 kb
Host smart-a1d83546-58f6-4244-b072-751282fde3b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757044834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
757044834
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1707623436
Short name T925
Test name
Test status
Simulation time 151259893 ps
CPU time 7.68 seconds
Started Jun 05 04:28:03 PM PDT 24
Finished Jun 05 04:28:11 PM PDT 24
Peak memory 205688 kb
Host smart-3a8a6872-8512-4ee6-93dd-7492e0da9b77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707623436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
707623436
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3644726912
Short name T1070
Test name
Test status
Simulation time 68293335 ps
CPU time 1.14 seconds
Started Jun 05 04:28:01 PM PDT 24
Finished Jun 05 04:28:03 PM PDT 24
Peak memory 205700 kb
Host smart-8a3959bc-8cf5-4b3f-b97b-6eaffc938399
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644726912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
644726912
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.903844020
Short name T1015
Test name
Test status
Simulation time 51185788 ps
CPU time 1.8 seconds
Started Jun 05 04:28:00 PM PDT 24
Finished Jun 05 04:28:02 PM PDT 24
Peak memory 205684 kb
Host smart-5ad18f85-3f3e-444a-94fb-cd8e601df49d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903844020 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.903844020
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2952394868
Short name T1056
Test name
Test status
Simulation time 13694485 ps
CPU time 1.25 seconds
Started Jun 05 04:28:02 PM PDT 24
Finished Jun 05 04:28:03 PM PDT 24
Peak memory 205728 kb
Host smart-60b89736-24d5-483f-b5a0-8933c7a9da12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952394868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2952394868
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3168860188
Short name T935
Test name
Test status
Simulation time 12155469 ps
CPU time 0.71 seconds
Started Jun 05 04:27:58 PM PDT 24
Finished Jun 05 04:28:00 PM PDT 24
Peak memory 205388 kb
Host smart-4647abe1-0269-4fc6-8184-d057706efc14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168860188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3168860188
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.371993461
Short name T1026
Test name
Test status
Simulation time 40883252 ps
CPU time 2.47 seconds
Started Jun 05 04:28:00 PM PDT 24
Finished Jun 05 04:28:03 PM PDT 24
Peak memory 205684 kb
Host smart-cc1ad356-7e13-459d-856b-15a9e370d6e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371993461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.371993461
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.723729721
Short name T111
Test name
Test status
Simulation time 98008051 ps
CPU time 2.06 seconds
Started Jun 05 04:28:03 PM PDT 24
Finished Jun 05 04:28:05 PM PDT 24
Peak memory 214148 kb
Host smart-7d8f089e-55d4-4ffc-80f5-e6cfe712f00c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723729721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.723729721
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1207562865
Short name T115
Test name
Test status
Simulation time 85695661 ps
CPU time 3.78 seconds
Started Jun 05 04:27:59 PM PDT 24
Finished Jun 05 04:28:03 PM PDT 24
Peak memory 214320 kb
Host smart-3f79ee8d-49b0-48e3-b333-f145ef30658b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207562865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1207562865
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.122327316
Short name T971
Test name
Test status
Simulation time 56967612 ps
CPU time 3.39 seconds
Started Jun 05 04:27:59 PM PDT 24
Finished Jun 05 04:28:03 PM PDT 24
Peak memory 213940 kb
Host smart-5a29565d-b923-4136-8760-47a1c8afea3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122327316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.122327316
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.610126480
Short name T993
Test name
Test status
Simulation time 707701550 ps
CPU time 4.84 seconds
Started Jun 05 04:28:08 PM PDT 24
Finished Jun 05 04:28:13 PM PDT 24
Peak memory 205768 kb
Host smart-90c896f5-5b56-416f-acfe-5c26c5791be3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610126480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.610126480
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2043446156
Short name T1076
Test name
Test status
Simulation time 137511246 ps
CPU time 7.79 seconds
Started Jun 05 04:28:05 PM PDT 24
Finished Jun 05 04:28:13 PM PDT 24
Peak memory 205732 kb
Host smart-43febbcb-ef6c-41e8-ae30-8b198fca45ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043446156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
043446156
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3325315529
Short name T931
Test name
Test status
Simulation time 47108672 ps
CPU time 0.97 seconds
Started Jun 05 04:28:09 PM PDT 24
Finished Jun 05 04:28:11 PM PDT 24
Peak memory 205720 kb
Host smart-434080b8-9d95-4651-b3df-e5a77372b7d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325315529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
325315529
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3721357216
Short name T1034
Test name
Test status
Simulation time 38220310 ps
CPU time 2.7 seconds
Started Jun 05 04:28:06 PM PDT 24
Finished Jun 05 04:28:09 PM PDT 24
Peak memory 213948 kb
Host smart-6c77c0fe-54ae-490e-a495-014e03d229fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721357216 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3721357216
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3381688016
Short name T947
Test name
Test status
Simulation time 57075042 ps
CPU time 1.19 seconds
Started Jun 05 04:28:07 PM PDT 24
Finished Jun 05 04:28:09 PM PDT 24
Peak memory 205468 kb
Host smart-65038fc7-b486-4ee5-926e-06aed9ba0d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381688016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3381688016
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.880338901
Short name T1005
Test name
Test status
Simulation time 16123272 ps
CPU time 0.74 seconds
Started Jun 05 04:28:10 PM PDT 24
Finished Jun 05 04:28:11 PM PDT 24
Peak memory 205396 kb
Host smart-8c6e346c-3209-4503-a3f1-aa06d55b0ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880338901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.880338901
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3626863016
Short name T138
Test name
Test status
Simulation time 464574227 ps
CPU time 2.74 seconds
Started Jun 05 04:28:06 PM PDT 24
Finished Jun 05 04:28:09 PM PDT 24
Peak memory 205792 kb
Host smart-85359e75-daa8-4c31-b9c9-2c739c051327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626863016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3626863016
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1055385090
Short name T1055
Test name
Test status
Simulation time 785006993 ps
CPU time 3.28 seconds
Started Jun 05 04:27:59 PM PDT 24
Finished Jun 05 04:28:03 PM PDT 24
Peak memory 214500 kb
Host smart-da1e6a8c-2590-41cf-8a5c-20b22a6e93a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055385090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1055385090
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1077391901
Short name T1058
Test name
Test status
Simulation time 311172084 ps
CPU time 9.11 seconds
Started Jun 05 04:28:01 PM PDT 24
Finished Jun 05 04:28:11 PM PDT 24
Peak memory 214216 kb
Host smart-e755c32c-4c96-4b3c-973f-fd052709c2d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077391901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1077391901
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4102106287
Short name T945
Test name
Test status
Simulation time 607389656 ps
CPU time 3.36 seconds
Started Jun 05 04:28:01 PM PDT 24
Finished Jun 05 04:28:05 PM PDT 24
Peak memory 216392 kb
Host smart-404977ba-bb36-48a9-ab2c-165cee155d1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102106287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4102106287
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1322543872
Short name T939
Test name
Test status
Simulation time 44115641 ps
CPU time 1.55 seconds
Started Jun 05 04:28:36 PM PDT 24
Finished Jun 05 04:28:38 PM PDT 24
Peak memory 213936 kb
Host smart-0744bf54-8501-4bad-90ea-9ce554ef29cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322543872 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1322543872
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.221889469
Short name T1011
Test name
Test status
Simulation time 186595285 ps
CPU time 1.17 seconds
Started Jun 05 04:28:38 PM PDT 24
Finished Jun 05 04:28:40 PM PDT 24
Peak memory 205588 kb
Host smart-ca4b875e-f458-47cb-be21-3b87edc22369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221889469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.221889469
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3689203538
Short name T966
Test name
Test status
Simulation time 14593457 ps
CPU time 0.78 seconds
Started Jun 05 04:28:36 PM PDT 24
Finished Jun 05 04:28:37 PM PDT 24
Peak memory 205384 kb
Host smart-05c1c38c-acc4-4a0a-95ad-9eda1b3df9b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689203538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3689203538
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4255170117
Short name T141
Test name
Test status
Simulation time 207328592 ps
CPU time 2.45 seconds
Started Jun 05 04:28:37 PM PDT 24
Finished Jun 05 04:28:40 PM PDT 24
Peak memory 205560 kb
Host smart-b1fac3d5-5bc4-4ef3-8e92-1d1749d1726f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255170117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.4255170117
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1865708670
Short name T1061
Test name
Test status
Simulation time 598834822 ps
CPU time 4.61 seconds
Started Jun 05 04:28:33 PM PDT 24
Finished Jun 05 04:28:38 PM PDT 24
Peak memory 214300 kb
Host smart-7b0c0bbb-56ea-4e1d-ba1c-1ae095249c4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865708670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1865708670
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3999023895
Short name T1050
Test name
Test status
Simulation time 156230937 ps
CPU time 4.39 seconds
Started Jun 05 04:28:29 PM PDT 24
Finished Jun 05 04:28:34 PM PDT 24
Peak memory 220100 kb
Host smart-1a9448ac-4f72-4f95-a653-59bfe41bc535
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999023895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3999023895
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.619500264
Short name T937
Test name
Test status
Simulation time 216863990 ps
CPU time 2.42 seconds
Started Jun 05 04:28:36 PM PDT 24
Finished Jun 05 04:28:38 PM PDT 24
Peak memory 213936 kb
Host smart-7bcdb34e-898f-4ffd-9653-ba6c8d125c0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619500264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.619500264
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2160658358
Short name T927
Test name
Test status
Simulation time 21723649 ps
CPU time 1.61 seconds
Started Jun 05 04:28:47 PM PDT 24
Finished Jun 05 04:28:49 PM PDT 24
Peak memory 214012 kb
Host smart-42318c02-4e03-48f1-b114-631af5310418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160658358 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2160658358
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1820853272
Short name T1029
Test name
Test status
Simulation time 37011666 ps
CPU time 0.98 seconds
Started Jun 05 04:28:47 PM PDT 24
Finished Jun 05 04:28:49 PM PDT 24
Peak memory 205628 kb
Host smart-48de5e5e-13e3-48ad-9cc5-2a229a04e866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820853272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1820853272
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3703143583
Short name T997
Test name
Test status
Simulation time 10536968 ps
CPU time 0.81 seconds
Started Jun 05 04:28:38 PM PDT 24
Finished Jun 05 04:28:40 PM PDT 24
Peak memory 205324 kb
Host smart-ddda9088-e9c0-4a03-836e-9d366ad1ac6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703143583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3703143583
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.521472714
Short name T1057
Test name
Test status
Simulation time 50191135 ps
CPU time 1.62 seconds
Started Jun 05 04:28:45 PM PDT 24
Finished Jun 05 04:28:47 PM PDT 24
Peak memory 205632 kb
Host smart-e5dc90dd-6cf4-4e9c-8f44-722c81538e6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521472714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.521472714
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1434400031
Short name T970
Test name
Test status
Simulation time 72915089 ps
CPU time 1.82 seconds
Started Jun 05 04:28:37 PM PDT 24
Finished Jun 05 04:28:39 PM PDT 24
Peak memory 214232 kb
Host smart-ed380f47-29ff-4246-9daa-ce973baf78ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434400031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1434400031
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.644215186
Short name T108
Test name
Test status
Simulation time 2726640078 ps
CPU time 5.65 seconds
Started Jun 05 04:28:38 PM PDT 24
Finished Jun 05 04:28:44 PM PDT 24
Peak memory 222576 kb
Host smart-77629f1a-b599-41bb-80aa-f4e4a504b0dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644215186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.644215186
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1193065078
Short name T979
Test name
Test status
Simulation time 395836108 ps
CPU time 2.64 seconds
Started Jun 05 04:28:36 PM PDT 24
Finished Jun 05 04:28:39 PM PDT 24
Peak memory 217040 kb
Host smart-3cf11e3b-a85b-4931-89e1-ef86bcc458bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193065078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1193065078
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.4090854453
Short name T159
Test name
Test status
Simulation time 177122900 ps
CPU time 3.78 seconds
Started Jun 05 04:28:38 PM PDT 24
Finished Jun 05 04:28:42 PM PDT 24
Peak memory 213828 kb
Host smart-0aa04eea-a40b-489b-983b-edd0a6e976ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090854453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.4090854453
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.4287520811
Short name T991
Test name
Test status
Simulation time 85305152 ps
CPU time 1.54 seconds
Started Jun 05 04:28:46 PM PDT 24
Finished Jun 05 04:28:49 PM PDT 24
Peak memory 214188 kb
Host smart-587efdc1-ae7d-4873-9d74-a56298fa072f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287520811 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.4287520811
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4069521460
Short name T136
Test name
Test status
Simulation time 89156774 ps
CPU time 1.58 seconds
Started Jun 05 04:28:44 PM PDT 24
Finished Jun 05 04:28:46 PM PDT 24
Peak memory 205776 kb
Host smart-97b124eb-d7bb-424b-99a8-82f8a31a4128
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069521460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4069521460
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1888527672
Short name T923
Test name
Test status
Simulation time 19001864 ps
CPU time 0.73 seconds
Started Jun 05 04:28:47 PM PDT 24
Finished Jun 05 04:28:48 PM PDT 24
Peak memory 205372 kb
Host smart-70ee6a2d-c9aa-46b8-8705-2a880c566306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888527672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1888527672
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1517194107
Short name T1048
Test name
Test status
Simulation time 236018992 ps
CPU time 3.45 seconds
Started Jun 05 04:28:46 PM PDT 24
Finished Jun 05 04:28:51 PM PDT 24
Peak memory 205936 kb
Host smart-fec87884-b47a-4688-b3f0-610fbdd76ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517194107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1517194107
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1908315857
Short name T1035
Test name
Test status
Simulation time 281536957 ps
CPU time 3.75 seconds
Started Jun 05 04:28:44 PM PDT 24
Finished Jun 05 04:28:48 PM PDT 24
Peak memory 214268 kb
Host smart-3b520d13-cdd5-42b7-95b0-c101f1028955
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908315857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1908315857
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.553379096
Short name T986
Test name
Test status
Simulation time 45913542 ps
CPU time 1.67 seconds
Started Jun 05 04:28:47 PM PDT 24
Finished Jun 05 04:28:49 PM PDT 24
Peak memory 216088 kb
Host smart-70639280-d1af-4438-b5ce-0b2d34e8c684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553379096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.553379096
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.808226562
Short name T969
Test name
Test status
Simulation time 30064590 ps
CPU time 1.06 seconds
Started Jun 05 04:28:45 PM PDT 24
Finished Jun 05 04:28:46 PM PDT 24
Peak memory 205768 kb
Host smart-e7d12eeb-9244-42b7-9101-62bb8a9f2f36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808226562 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.808226562
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.337594392
Short name T1008
Test name
Test status
Simulation time 18522267 ps
CPU time 1.32 seconds
Started Jun 05 04:28:47 PM PDT 24
Finished Jun 05 04:28:49 PM PDT 24
Peak memory 205728 kb
Host smart-26d5dc00-199c-40a8-b95a-3915b1273f50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337594392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.337594392
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2314641758
Short name T1025
Test name
Test status
Simulation time 52166699 ps
CPU time 0.75 seconds
Started Jun 05 04:28:46 PM PDT 24
Finished Jun 05 04:28:48 PM PDT 24
Peak memory 205348 kb
Host smart-c5ba3132-0820-469b-8712-e4514c4b4016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314641758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2314641758
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2789825514
Short name T1045
Test name
Test status
Simulation time 23811132 ps
CPU time 1.65 seconds
Started Jun 05 04:28:48 PM PDT 24
Finished Jun 05 04:28:51 PM PDT 24
Peak memory 205716 kb
Host smart-a647cce8-b809-4a1d-9016-c16cac50b31e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789825514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2789825514
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2233720651
Short name T951
Test name
Test status
Simulation time 78258278 ps
CPU time 1.42 seconds
Started Jun 05 04:28:47 PM PDT 24
Finished Jun 05 04:28:49 PM PDT 24
Peak memory 206016 kb
Host smart-9c3568b5-9857-4134-b6c7-0bf5fe266896
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233720651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2233720651
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2881757885
Short name T1007
Test name
Test status
Simulation time 816735848 ps
CPU time 15.9 seconds
Started Jun 05 04:28:46 PM PDT 24
Finished Jun 05 04:29:02 PM PDT 24
Peak memory 220884 kb
Host smart-9a8df06b-bf64-405e-9a53-e58d8a11316e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881757885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2881757885
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.370661898
Short name T1066
Test name
Test status
Simulation time 468047133 ps
CPU time 3.46 seconds
Started Jun 05 04:28:46 PM PDT 24
Finished Jun 05 04:28:50 PM PDT 24
Peak memory 213896 kb
Host smart-dab276c0-0667-4cad-9dfd-fd7a554c7096
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370661898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.370661898
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.428685370
Short name T974
Test name
Test status
Simulation time 442491247 ps
CPU time 4.08 seconds
Started Jun 05 04:28:45 PM PDT 24
Finished Jun 05 04:28:50 PM PDT 24
Peak memory 213896 kb
Host smart-23aff319-6c98-497a-9ee4-95415d9d52b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428685370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.428685370
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3338430831
Short name T953
Test name
Test status
Simulation time 148754742 ps
CPU time 2.54 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:58 PM PDT 24
Peak memory 218952 kb
Host smart-a1420d4a-0e62-4e5f-b7aa-a3042219869b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338430831 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3338430831
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2391355482
Short name T995
Test name
Test status
Simulation time 21152041 ps
CPU time 0.98 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:56 PM PDT 24
Peak memory 205524 kb
Host smart-4ee0d243-def5-4274-a0a3-62d0c859bca2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391355482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2391355482
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3636200130
Short name T1024
Test name
Test status
Simulation time 15667058 ps
CPU time 0.8 seconds
Started Jun 05 04:28:47 PM PDT 24
Finished Jun 05 04:28:49 PM PDT 24
Peak memory 205308 kb
Host smart-b08a41ed-6be0-4d4d-b994-cb0f840a29e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636200130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3636200130
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1156232342
Short name T989
Test name
Test status
Simulation time 47230581 ps
CPU time 1.54 seconds
Started Jun 05 04:28:52 PM PDT 24
Finished Jun 05 04:28:54 PM PDT 24
Peak memory 205652 kb
Host smart-6e7a2d82-8d71-4015-b75a-d0979a57de6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156232342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1156232342
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.148749541
Short name T1037
Test name
Test status
Simulation time 144496106 ps
CPU time 2.58 seconds
Started Jun 05 04:28:47 PM PDT 24
Finished Jun 05 04:28:50 PM PDT 24
Peak memory 214120 kb
Host smart-a78b054e-b6db-4c49-a18f-1d449859e2a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148749541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.148749541
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3908639881
Short name T984
Test name
Test status
Simulation time 541981893 ps
CPU time 6.6 seconds
Started Jun 05 04:28:49 PM PDT 24
Finished Jun 05 04:28:56 PM PDT 24
Peak memory 214508 kb
Host smart-d1bfead6-df34-44b4-b38d-f415220c61f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908639881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3908639881
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3030368967
Short name T980
Test name
Test status
Simulation time 57015461 ps
CPU time 2 seconds
Started Jun 05 04:28:48 PM PDT 24
Finished Jun 05 04:28:50 PM PDT 24
Peak memory 213956 kb
Host smart-a7f0e9b4-7fea-4d23-965e-1c105083f2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030368967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3030368967
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2058350629
Short name T373
Test name
Test status
Simulation time 191424983 ps
CPU time 3.08 seconds
Started Jun 05 04:28:49 PM PDT 24
Finished Jun 05 04:28:53 PM PDT 24
Peak memory 214000 kb
Host smart-d9313dbb-fed9-48e2-a571-2b2f1f50086d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058350629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2058350629
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.990235760
Short name T964
Test name
Test status
Simulation time 120053529 ps
CPU time 1.22 seconds
Started Jun 05 04:28:56 PM PDT 24
Finished Jun 05 04:28:58 PM PDT 24
Peak memory 205820 kb
Host smart-e56a517b-e50a-472c-a62e-10254297bd1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990235760 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.990235760
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.449769908
Short name T943
Test name
Test status
Simulation time 66424263 ps
CPU time 0.91 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:56 PM PDT 24
Peak memory 205524 kb
Host smart-dce05105-0a03-4ea2-be67-7d4a3e27b637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449769908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.449769908
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.123521190
Short name T1053
Test name
Test status
Simulation time 187766158 ps
CPU time 0.8 seconds
Started Jun 05 04:28:53 PM PDT 24
Finished Jun 05 04:28:55 PM PDT 24
Peak memory 205320 kb
Host smart-73fce166-9b7c-4408-85f1-4e6837385867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123521190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.123521190
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.4007783352
Short name T973
Test name
Test status
Simulation time 135285361 ps
CPU time 1.43 seconds
Started Jun 05 04:28:56 PM PDT 24
Finished Jun 05 04:28:58 PM PDT 24
Peak memory 213900 kb
Host smart-7f88b6e5-1883-41ed-9aca-b96e9866408a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007783352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.4007783352
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3685982215
Short name T116
Test name
Test status
Simulation time 47560515 ps
CPU time 1.48 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:56 PM PDT 24
Peak memory 214128 kb
Host smart-2dfcd211-be43-43be-ad3f-e436214952ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685982215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3685982215
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2838940623
Short name T1043
Test name
Test status
Simulation time 367711037 ps
CPU time 4.72 seconds
Started Jun 05 04:28:56 PM PDT 24
Finished Jun 05 04:29:01 PM PDT 24
Peak memory 214324 kb
Host smart-73b25fd7-85d8-4bb1-8cc2-7c6b8ae26d0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838940623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2838940623
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1335788431
Short name T918
Test name
Test status
Simulation time 55276560 ps
CPU time 3.5 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:58 PM PDT 24
Peak memory 222100 kb
Host smart-b99cb094-956c-4cca-a981-351610e6d8e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335788431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1335788431
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.370204883
Short name T1036
Test name
Test status
Simulation time 54024892 ps
CPU time 2.39 seconds
Started Jun 05 04:28:53 PM PDT 24
Finished Jun 05 04:28:56 PM PDT 24
Peak memory 213968 kb
Host smart-a2836460-befd-4f01-a7cf-4e6a101d5d10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370204883 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.370204883
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.235841097
Short name T1068
Test name
Test status
Simulation time 228276661 ps
CPU time 1.47 seconds
Started Jun 05 04:28:56 PM PDT 24
Finished Jun 05 04:28:58 PM PDT 24
Peak memory 205724 kb
Host smart-4da6a002-b0ad-4aff-bc29-553d76b3ecb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235841097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.235841097
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3235952663
Short name T1023
Test name
Test status
Simulation time 100167563 ps
CPU time 0.8 seconds
Started Jun 05 04:28:55 PM PDT 24
Finished Jun 05 04:28:56 PM PDT 24
Peak memory 205388 kb
Host smart-2984c2c3-dc30-44a4-88ba-36b29eedd08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235952663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3235952663
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3510519713
Short name T982
Test name
Test status
Simulation time 30810667 ps
CPU time 1.94 seconds
Started Jun 05 04:28:53 PM PDT 24
Finished Jun 05 04:28:56 PM PDT 24
Peak memory 205780 kb
Host smart-2ca7d5f2-fa52-4ea1-bbd2-6fbe406c71f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510519713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3510519713
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3606678328
Short name T985
Test name
Test status
Simulation time 426064999 ps
CPU time 1.94 seconds
Started Jun 05 04:28:55 PM PDT 24
Finished Jun 05 04:28:57 PM PDT 24
Peak memory 214328 kb
Host smart-8122bbe9-95fb-49d7-b97c-32f5b129bc2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606678328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3606678328
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1674597996
Short name T1020
Test name
Test status
Simulation time 117685167 ps
CPU time 5.61 seconds
Started Jun 05 04:28:55 PM PDT 24
Finished Jun 05 04:29:01 PM PDT 24
Peak memory 220184 kb
Host smart-25fbbd12-3a3c-4e33-bf1f-04492b876603
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674597996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1674597996
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2819926500
Short name T1013
Test name
Test status
Simulation time 215388873 ps
CPU time 2.79 seconds
Started Jun 05 04:28:51 PM PDT 24
Finished Jun 05 04:28:54 PM PDT 24
Peak memory 213792 kb
Host smart-11dc16e3-6558-4a8b-8e87-9dd75b4cf5c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819926500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2819926500
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.402701548
Short name T158
Test name
Test status
Simulation time 210016554 ps
CPU time 9.08 seconds
Started Jun 05 04:28:57 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 205652 kb
Host smart-bafb0b08-cae9-4141-b962-1c69fba7c1c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402701548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.402701548
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.164207522
Short name T924
Test name
Test status
Simulation time 25094906 ps
CPU time 1.16 seconds
Started Jun 05 04:28:53 PM PDT 24
Finished Jun 05 04:28:54 PM PDT 24
Peak memory 205700 kb
Host smart-d8a2ad0a-8c8f-463c-a9c8-644d91007001
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164207522 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.164207522
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1020454162
Short name T139
Test name
Test status
Simulation time 112855591 ps
CPU time 1.37 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:56 PM PDT 24
Peak memory 205728 kb
Host smart-3e3e50a7-014e-419c-a2c8-3db9fa08b71b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020454162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1020454162
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3305862866
Short name T1082
Test name
Test status
Simulation time 14388678 ps
CPU time 0.77 seconds
Started Jun 05 04:28:56 PM PDT 24
Finished Jun 05 04:28:58 PM PDT 24
Peak memory 205348 kb
Host smart-c06b35ac-c614-4875-9a57-2a5c978c8288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305862866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3305862866
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2561866034
Short name T135
Test name
Test status
Simulation time 477997933 ps
CPU time 4.05 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:59 PM PDT 24
Peak memory 205688 kb
Host smart-17b32aa6-d894-4454-8ba2-0367e10e3225
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561866034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2561866034
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2608962732
Short name T976
Test name
Test status
Simulation time 312144515 ps
CPU time 3.56 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:58 PM PDT 24
Peak memory 214244 kb
Host smart-7995cd1b-5a76-4c85-83d0-f08457c7770d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608962732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2608962732
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.819162248
Short name T987
Test name
Test status
Simulation time 1032677492 ps
CPU time 7.01 seconds
Started Jun 05 04:28:55 PM PDT 24
Finished Jun 05 04:29:03 PM PDT 24
Peak memory 214272 kb
Host smart-8ebbe103-6e41-4cb1-b413-170b7581e794
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819162248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.819162248
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3104843752
Short name T920
Test name
Test status
Simulation time 500092870 ps
CPU time 3.16 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:58 PM PDT 24
Peak memory 213896 kb
Host smart-d8d5ac8a-e4b7-446c-9dfb-b5a317e5ff71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104843752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3104843752
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2212644205
Short name T167
Test name
Test status
Simulation time 354785557 ps
CPU time 8.17 seconds
Started Jun 05 04:28:55 PM PDT 24
Finished Jun 05 04:29:04 PM PDT 24
Peak memory 206060 kb
Host smart-8762ad05-bfbb-4157-bcd4-cf4838ea0389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212644205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2212644205
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1308286979
Short name T1063
Test name
Test status
Simulation time 40026615 ps
CPU time 1.31 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:57 PM PDT 24
Peak memory 205656 kb
Host smart-f918f9aa-7745-41a6-937d-910a867ed492
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308286979 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1308286979
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.648614169
Short name T1009
Test name
Test status
Simulation time 340408513 ps
CPU time 1.22 seconds
Started Jun 05 04:28:53 PM PDT 24
Finished Jun 05 04:28:55 PM PDT 24
Peak memory 205764 kb
Host smart-a2f97ce7-ca31-48b1-8085-8dac154619c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648614169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.648614169
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.468709620
Short name T948
Test name
Test status
Simulation time 68969423 ps
CPU time 0.73 seconds
Started Jun 05 04:28:53 PM PDT 24
Finished Jun 05 04:28:55 PM PDT 24
Peak memory 205356 kb
Host smart-136ff420-47d8-441b-bb1f-ebab7d845d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468709620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.468709620
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1225758121
Short name T1041
Test name
Test status
Simulation time 83987761 ps
CPU time 1.65 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:56 PM PDT 24
Peak memory 205712 kb
Host smart-02902500-0740-4ce9-bfb6-f2008935e178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225758121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1225758121
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1093814054
Short name T983
Test name
Test status
Simulation time 1104655668 ps
CPU time 3.6 seconds
Started Jun 05 04:28:53 PM PDT 24
Finished Jun 05 04:28:57 PM PDT 24
Peak memory 214172 kb
Host smart-f5d82b63-0342-444a-b948-c028e8563a56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093814054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1093814054
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3343990510
Short name T1080
Test name
Test status
Simulation time 1965224141 ps
CPU time 10.92 seconds
Started Jun 05 04:28:56 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 214188 kb
Host smart-08fd0a1f-b5ea-4f86-8aec-12e80d8d86eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343990510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3343990510
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1980039425
Short name T1081
Test name
Test status
Simulation time 99137740 ps
CPU time 3.84 seconds
Started Jun 05 04:28:52 PM PDT 24
Finished Jun 05 04:28:57 PM PDT 24
Peak memory 216584 kb
Host smart-f30583b4-9f0e-4330-9c5c-916e20219113
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980039425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1980039425
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2463997331
Short name T153
Test name
Test status
Simulation time 118361149 ps
CPU time 3.65 seconds
Started Jun 05 04:28:54 PM PDT 24
Finished Jun 05 04:28:59 PM PDT 24
Peak memory 213940 kb
Host smart-cf6d253a-b251-4bc7-be02-4db001a388ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463997331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2463997331
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2177170476
Short name T946
Test name
Test status
Simulation time 163123981 ps
CPU time 1.59 seconds
Started Jun 05 04:29:05 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 213928 kb
Host smart-bb76f838-cda6-4396-b6a2-6d55799553a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177170476 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2177170476
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3387516926
Short name T1022
Test name
Test status
Simulation time 46034020 ps
CPU time 1.23 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205764 kb
Host smart-c10c3127-cf9f-4c67-80c0-3086f4a81841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387516926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3387516926
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1847464058
Short name T988
Test name
Test status
Simulation time 12010444 ps
CPU time 0.72 seconds
Started Jun 05 04:29:05 PM PDT 24
Finished Jun 05 04:29:06 PM PDT 24
Peak memory 205300 kb
Host smart-f8fcdd32-9ed2-4e8a-8b20-da103468f8a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847464058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1847464058
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3566364008
Short name T990
Test name
Test status
Simulation time 39547342 ps
CPU time 1.45 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205652 kb
Host smart-8cec9616-b9c2-4aa5-b950-5a41b796f9a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566364008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3566364008
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1275877647
Short name T1065
Test name
Test status
Simulation time 97940992 ps
CPU time 3.6 seconds
Started Jun 05 04:28:55 PM PDT 24
Finished Jun 05 04:29:00 PM PDT 24
Peak memory 214268 kb
Host smart-5d69ec5e-412a-4962-8f4c-85bd92bf81ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275877647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1275877647
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.726249000
Short name T1075
Test name
Test status
Simulation time 483661057 ps
CPU time 10.1 seconds
Started Jun 05 04:28:52 PM PDT 24
Finished Jun 05 04:29:03 PM PDT 24
Peak memory 214192 kb
Host smart-ac956390-fee6-4616-8508-2b082eca09ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726249000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.726249000
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2698742999
Short name T1054
Test name
Test status
Simulation time 543692899 ps
CPU time 1.79 seconds
Started Jun 05 04:28:55 PM PDT 24
Finished Jun 05 04:28:58 PM PDT 24
Peak memory 213896 kb
Host smart-b284825b-f949-404b-8ad4-fed30b7978d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698742999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2698742999
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2222840231
Short name T1069
Test name
Test status
Simulation time 1242109847 ps
CPU time 11.37 seconds
Started Jun 05 04:28:57 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 213900 kb
Host smart-41430d92-0e5a-478c-92b7-705482b34741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222840231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2222840231
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1668320414
Short name T140
Test name
Test status
Simulation time 68793768 ps
CPU time 4.32 seconds
Started Jun 05 04:28:11 PM PDT 24
Finished Jun 05 04:28:16 PM PDT 24
Peak memory 205804 kb
Host smart-a263fe3e-abac-4a47-b5c4-fde5e45ca994
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668320414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
668320414
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3450644368
Short name T944
Test name
Test status
Simulation time 863420636 ps
CPU time 14.58 seconds
Started Jun 05 04:28:11 PM PDT 24
Finished Jun 05 04:28:26 PM PDT 24
Peak memory 205692 kb
Host smart-bbdcfc2f-ede4-4da3-8ecf-3b3b23317c69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450644368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
450644368
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4155804891
Short name T926
Test name
Test status
Simulation time 47177945 ps
CPU time 1.08 seconds
Started Jun 05 04:28:06 PM PDT 24
Finished Jun 05 04:28:08 PM PDT 24
Peak memory 205696 kb
Host smart-bfd57929-f50d-4698-9617-3ff7e7cf207c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155804891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.4
155804891
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4167379438
Short name T378
Test name
Test status
Simulation time 58497604 ps
CPU time 1.38 seconds
Started Jun 05 04:28:06 PM PDT 24
Finished Jun 05 04:28:08 PM PDT 24
Peak memory 205788 kb
Host smart-451614f4-b292-47b4-89b1-74a1128daead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167379438 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4167379438
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.898188382
Short name T959
Test name
Test status
Simulation time 132866427 ps
CPU time 1.07 seconds
Started Jun 05 04:28:06 PM PDT 24
Finished Jun 05 04:28:07 PM PDT 24
Peak memory 205704 kb
Host smart-9aa81338-a58d-4c4a-bdab-06796199bbed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898188382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.898188382
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3545461201
Short name T1083
Test name
Test status
Simulation time 17637300 ps
CPU time 0.83 seconds
Started Jun 05 04:28:08 PM PDT 24
Finished Jun 05 04:28:09 PM PDT 24
Peak memory 205392 kb
Host smart-0f41998c-91a9-4d66-bede-99062ab54e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545461201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3545461201
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3128653443
Short name T1010
Test name
Test status
Simulation time 19250204 ps
CPU time 1.45 seconds
Started Jun 05 04:28:06 PM PDT 24
Finished Jun 05 04:28:08 PM PDT 24
Peak memory 205652 kb
Host smart-a2b49881-e97b-46bd-8512-b4b85e6bd536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128653443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3128653443
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3891392522
Short name T992
Test name
Test status
Simulation time 177553498 ps
CPU time 1.76 seconds
Started Jun 05 04:28:05 PM PDT 24
Finished Jun 05 04:28:07 PM PDT 24
Peak memory 214264 kb
Host smart-ad803010-348c-49f6-95c3-7e811c8dc885
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891392522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3891392522
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3705242340
Short name T107
Test name
Test status
Simulation time 534437418 ps
CPU time 6.43 seconds
Started Jun 05 04:28:06 PM PDT 24
Finished Jun 05 04:28:13 PM PDT 24
Peak memory 214268 kb
Host smart-89d19a3b-cf37-4203-bc40-0b296229172b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705242340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3705242340
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2551062533
Short name T928
Test name
Test status
Simulation time 70337216 ps
CPU time 1.62 seconds
Started Jun 05 04:28:05 PM PDT 24
Finished Jun 05 04:28:07 PM PDT 24
Peak memory 213964 kb
Host smart-e06669e3-e4e1-4b6f-b374-07b883d1c1ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551062533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2551062533
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1060537043
Short name T170
Test name
Test status
Simulation time 149795269 ps
CPU time 3.08 seconds
Started Jun 05 04:28:05 PM PDT 24
Finished Jun 05 04:28:08 PM PDT 24
Peak memory 205808 kb
Host smart-e22be16e-6456-43f9-a5ab-c1784db67749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060537043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1060537043
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2242913301
Short name T975
Test name
Test status
Simulation time 12305796 ps
CPU time 0.76 seconds
Started Jun 05 04:29:05 PM PDT 24
Finished Jun 05 04:29:06 PM PDT 24
Peak memory 205304 kb
Host smart-68b8f67d-ab16-4c45-8b7e-2539c22f2dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242913301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2242913301
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2533427642
Short name T1032
Test name
Test status
Simulation time 7719253 ps
CPU time 0.72 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205308 kb
Host smart-af81053e-1c72-4fd8-b15e-e4319bf4b0b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533427642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2533427642
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2215190695
Short name T1003
Test name
Test status
Simulation time 32968790 ps
CPU time 0.73 seconds
Started Jun 05 04:29:05 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 205308 kb
Host smart-e8245e55-35e5-4558-9be9-dbfa24ac76ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215190695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2215190695
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3914681032
Short name T934
Test name
Test status
Simulation time 29180322 ps
CPU time 0.75 seconds
Started Jun 05 04:29:05 PM PDT 24
Finished Jun 05 04:29:06 PM PDT 24
Peak memory 205188 kb
Host smart-25552a82-f200-4e8f-91d1-ac2d32ef98e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914681032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3914681032
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1858085665
Short name T932
Test name
Test status
Simulation time 9635251 ps
CPU time 0.71 seconds
Started Jun 05 04:29:05 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 205312 kb
Host smart-6f9165c4-5760-4fe4-bee2-9e71e7b038ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858085665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1858085665
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4018701878
Short name T1085
Test name
Test status
Simulation time 197885575 ps
CPU time 0.83 seconds
Started Jun 05 04:29:06 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 205312 kb
Host smart-80e4736e-af78-4e21-812d-c35f55b2cf24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018701878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4018701878
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1526291451
Short name T961
Test name
Test status
Simulation time 34198411 ps
CPU time 0.78 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205304 kb
Host smart-7a45b98d-cafa-482f-b835-1819966db88b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526291451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1526291451
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.113147296
Short name T1040
Test name
Test status
Simulation time 9253461 ps
CPU time 0.78 seconds
Started Jun 05 04:29:06 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 205392 kb
Host smart-3146d908-d6a0-4707-97a8-200ec687404b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113147296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.113147296
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3557749778
Short name T929
Test name
Test status
Simulation time 33468203 ps
CPU time 0.7 seconds
Started Jun 05 04:29:06 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 205308 kb
Host smart-d1bdfbb6-c0ed-4e01-9dfd-48c974e038df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557749778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3557749778
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1397918555
Short name T956
Test name
Test status
Simulation time 75430836 ps
CPU time 0.8 seconds
Started Jun 05 04:29:09 PM PDT 24
Finished Jun 05 04:29:11 PM PDT 24
Peak memory 205324 kb
Host smart-adbc61a8-65d7-4637-8a6b-cf0b85b40f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397918555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1397918555
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3176325521
Short name T142
Test name
Test status
Simulation time 73529331 ps
CPU time 4.71 seconds
Started Jun 05 04:28:14 PM PDT 24
Finished Jun 05 04:28:20 PM PDT 24
Peak memory 205612 kb
Host smart-607c0590-54f8-4449-9a0d-0f34daf62309
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176325521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
176325521
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3967981564
Short name T938
Test name
Test status
Simulation time 1460346123 ps
CPU time 16.15 seconds
Started Jun 05 04:28:14 PM PDT 24
Finished Jun 05 04:28:31 PM PDT 24
Peak memory 205564 kb
Host smart-3912b0f8-a550-4d03-aea6-4b3439892b81
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967981564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
967981564
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1294415647
Short name T1059
Test name
Test status
Simulation time 35153480 ps
CPU time 0.88 seconds
Started Jun 05 04:28:17 PM PDT 24
Finished Jun 05 04:28:18 PM PDT 24
Peak memory 205444 kb
Host smart-d8ba618e-163b-4eac-9419-73f4650df299
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294415647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
294415647
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.451445426
Short name T1017
Test name
Test status
Simulation time 97128777 ps
CPU time 1.25 seconds
Started Jun 05 04:28:14 PM PDT 24
Finished Jun 05 04:28:16 PM PDT 24
Peak memory 205932 kb
Host smart-d0251b9c-379a-4b7e-b800-5908c5897e21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451445426 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.451445426
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1055680034
Short name T1001
Test name
Test status
Simulation time 56614195 ps
CPU time 1.12 seconds
Started Jun 05 04:28:17 PM PDT 24
Finished Jun 05 04:28:19 PM PDT 24
Peak memory 205772 kb
Host smart-05fde820-3831-48b3-8e4d-b0b612951eba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055680034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1055680034
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1007178835
Short name T967
Test name
Test status
Simulation time 23982611 ps
CPU time 0.86 seconds
Started Jun 05 04:28:18 PM PDT 24
Finished Jun 05 04:28:19 PM PDT 24
Peak memory 205244 kb
Host smart-1c4775ff-6929-40b9-8e4d-fc71af30d6b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007178835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1007178835
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3279419576
Short name T1002
Test name
Test status
Simulation time 53743028 ps
CPU time 2.06 seconds
Started Jun 05 04:28:14 PM PDT 24
Finished Jun 05 04:28:17 PM PDT 24
Peak memory 205560 kb
Host smart-4c95d5cf-58cb-41ea-8f09-60138589e892
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279419576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3279419576
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3950947132
Short name T112
Test name
Test status
Simulation time 139111395 ps
CPU time 2.61 seconds
Started Jun 05 04:28:08 PM PDT 24
Finished Jun 05 04:28:11 PM PDT 24
Peak memory 214268 kb
Host smart-9768c5a6-d0da-4770-a83c-ebae301b4a67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950947132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3950947132
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2497438817
Short name T1062
Test name
Test status
Simulation time 205337866 ps
CPU time 7.81 seconds
Started Jun 05 04:28:14 PM PDT 24
Finished Jun 05 04:28:22 PM PDT 24
Peak memory 214400 kb
Host smart-762cd78b-7227-42fd-99df-d5780e76ed32
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497438817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2497438817
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.301261956
Short name T1028
Test name
Test status
Simulation time 111062464 ps
CPU time 2.7 seconds
Started Jun 05 04:28:14 PM PDT 24
Finished Jun 05 04:28:18 PM PDT 24
Peak memory 213832 kb
Host smart-60e9fda0-92da-4ae5-a8df-5aef4f8b5146
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301261956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.301261956
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.133513116
Short name T933
Test name
Test status
Simulation time 186895523 ps
CPU time 3.12 seconds
Started Jun 05 04:28:14 PM PDT 24
Finished Jun 05 04:28:18 PM PDT 24
Peak memory 213860 kb
Host smart-d678fcda-988e-4043-90bc-e842dce94f29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133513116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
133513116
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3917594304
Short name T998
Test name
Test status
Simulation time 22665063 ps
CPU time 0.78 seconds
Started Jun 05 04:29:09 PM PDT 24
Finished Jun 05 04:29:10 PM PDT 24
Peak memory 205360 kb
Host smart-d86656b9-778f-4cdc-be36-711261ff4cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917594304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3917594304
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3791719415
Short name T1027
Test name
Test status
Simulation time 34293098 ps
CPU time 0.83 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205384 kb
Host smart-b54a57a8-d811-4e8d-b8a5-2e576ea48e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791719415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3791719415
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2898957563
Short name T1038
Test name
Test status
Simulation time 9495614 ps
CPU time 0.73 seconds
Started Jun 05 04:29:05 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 205388 kb
Host smart-58e53830-e567-4a4e-a245-e0bbb1c10802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898957563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2898957563
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3235811791
Short name T954
Test name
Test status
Simulation time 12784501 ps
CPU time 0.78 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205284 kb
Host smart-d42ba61e-b83c-45c2-9828-28382e281458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235811791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3235811791
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4002670108
Short name T1052
Test name
Test status
Simulation time 37200167 ps
CPU time 0.88 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205380 kb
Host smart-647957ba-4f46-4879-a122-24b8a2f20a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002670108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.4002670108
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1497846453
Short name T968
Test name
Test status
Simulation time 10467098 ps
CPU time 0.72 seconds
Started Jun 05 04:29:03 PM PDT 24
Finished Jun 05 04:29:05 PM PDT 24
Peak memory 205252 kb
Host smart-88ec4381-432f-4151-b5bd-e5209a96b013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497846453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1497846453
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.983229088
Short name T996
Test name
Test status
Simulation time 7900794 ps
CPU time 0.72 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:08 PM PDT 24
Peak memory 205392 kb
Host smart-278dccb4-e5c7-4ff8-aaaf-110dc92f8532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983229088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.983229088
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2096176194
Short name T1074
Test name
Test status
Simulation time 12531827 ps
CPU time 0.73 seconds
Started Jun 05 04:29:08 PM PDT 24
Finished Jun 05 04:29:10 PM PDT 24
Peak memory 205400 kb
Host smart-c45e3c5a-4900-4bc2-8b8b-6cf57ad9ad06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096176194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2096176194
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1517824452
Short name T917
Test name
Test status
Simulation time 114068076 ps
CPU time 0.76 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205324 kb
Host smart-9d9954cb-8bfc-4106-84ab-8d98785ee473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517824452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1517824452
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1647359445
Short name T919
Test name
Test status
Simulation time 11947406 ps
CPU time 0.78 seconds
Started Jun 05 04:29:06 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 205300 kb
Host smart-07c10e3d-caf3-4ec6-8852-6d776955f684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647359445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1647359445
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2448287166
Short name T962
Test name
Test status
Simulation time 665687739 ps
CPU time 14.51 seconds
Started Jun 05 04:28:15 PM PDT 24
Finished Jun 05 04:28:30 PM PDT 24
Peak memory 205756 kb
Host smart-bf6046d3-88d6-4b69-b40b-01882dc3665c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448287166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
448287166
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2482208061
Short name T155
Test name
Test status
Simulation time 2623772264 ps
CPU time 31.89 seconds
Started Jun 05 04:28:14 PM PDT 24
Finished Jun 05 04:28:47 PM PDT 24
Peak memory 205772 kb
Host smart-df18427a-e7ce-4d12-b23e-9faa1b5062f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482208061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
482208061
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3427094369
Short name T1072
Test name
Test status
Simulation time 154850259 ps
CPU time 1 seconds
Started Jun 05 04:28:11 PM PDT 24
Finished Jun 05 04:28:13 PM PDT 24
Peak memory 205516 kb
Host smart-bef881c4-be7b-4579-aa33-eeeaad6b09fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427094369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
427094369
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3564154714
Short name T1006
Test name
Test status
Simulation time 86362412 ps
CPU time 1.04 seconds
Started Jun 05 04:28:23 PM PDT 24
Finished Jun 05 04:28:25 PM PDT 24
Peak memory 205580 kb
Host smart-de8d296c-2820-4f69-b12d-38d81a206cbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564154714 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3564154714
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.415112158
Short name T137
Test name
Test status
Simulation time 47727874 ps
CPU time 1.31 seconds
Started Jun 05 04:28:12 PM PDT 24
Finished Jun 05 04:28:14 PM PDT 24
Peak memory 205636 kb
Host smart-28b12211-4951-43c8-a53f-b2a53e3a75e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415112158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.415112158
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1663581049
Short name T999
Test name
Test status
Simulation time 10920554 ps
CPU time 0.79 seconds
Started Jun 05 04:28:15 PM PDT 24
Finished Jun 05 04:28:17 PM PDT 24
Peak memory 205268 kb
Host smart-cb57b1a1-1249-4919-83e0-41d892a994ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663581049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1663581049
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1032592456
Short name T1012
Test name
Test status
Simulation time 49954715 ps
CPU time 2.22 seconds
Started Jun 05 04:28:22 PM PDT 24
Finished Jun 05 04:28:25 PM PDT 24
Peak memory 205684 kb
Host smart-8bce25ab-d7d3-425b-9694-f19117eae856
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032592456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1032592456
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1649664440
Short name T1031
Test name
Test status
Simulation time 224010914 ps
CPU time 1.45 seconds
Started Jun 05 04:28:16 PM PDT 24
Finished Jun 05 04:28:18 PM PDT 24
Peak memory 214288 kb
Host smart-45761497-6e1c-4626-b52b-a5fad08d9498
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649664440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1649664440
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.350855189
Short name T1044
Test name
Test status
Simulation time 880207744 ps
CPU time 7.9 seconds
Started Jun 05 04:28:14 PM PDT 24
Finished Jun 05 04:28:22 PM PDT 24
Peak memory 214048 kb
Host smart-e29a4176-0a63-4735-9608-d269db9ee4a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350855189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.350855189
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3242500589
Short name T942
Test name
Test status
Simulation time 81711010 ps
CPU time 1.43 seconds
Started Jun 05 04:28:15 PM PDT 24
Finished Jun 05 04:28:17 PM PDT 24
Peak memory 213844 kb
Host smart-8a85f775-d0e4-4e70-884f-8d2c643788ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242500589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3242500589
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3956230499
Short name T1018
Test name
Test status
Simulation time 13824525 ps
CPU time 0.75 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205384 kb
Host smart-40def08c-0b8b-4991-b5a8-d7084235127e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956230499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3956230499
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.94874279
Short name T1071
Test name
Test status
Simulation time 34396376 ps
CPU time 0.81 seconds
Started Jun 05 04:29:05 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 205316 kb
Host smart-6d239d06-a844-465f-8c5f-0f55dd750b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94874279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.94874279
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1592972571
Short name T1067
Test name
Test status
Simulation time 9732324 ps
CPU time 0.72 seconds
Started Jun 05 04:29:05 PM PDT 24
Finished Jun 05 04:29:06 PM PDT 24
Peak memory 205312 kb
Host smart-3b629845-d4ab-48aa-80a2-34fe7c1b2079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592972571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1592972571
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2220128493
Short name T1000
Test name
Test status
Simulation time 54795049 ps
CPU time 0.72 seconds
Started Jun 05 04:29:08 PM PDT 24
Finished Jun 05 04:29:10 PM PDT 24
Peak memory 205304 kb
Host smart-256caefe-56bb-4e7a-8867-4e00b7c3a73c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220128493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2220128493
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.49399985
Short name T1078
Test name
Test status
Simulation time 14179128 ps
CPU time 0.73 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205392 kb
Host smart-5d00575b-ef2b-4d44-beb6-9953140a6126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49399985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.49399985
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2714612737
Short name T1039
Test name
Test status
Simulation time 52695218 ps
CPU time 0.73 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205368 kb
Host smart-d301556d-b633-4c91-afee-f50c470661b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714612737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2714612737
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1562682480
Short name T922
Test name
Test status
Simulation time 37357855 ps
CPU time 0.82 seconds
Started Jun 05 04:29:04 PM PDT 24
Finished Jun 05 04:29:06 PM PDT 24
Peak memory 205400 kb
Host smart-c7a63387-57a0-453b-8e11-f501699c0c46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562682480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1562682480
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1761293079
Short name T1046
Test name
Test status
Simulation time 13384182 ps
CPU time 0.9 seconds
Started Jun 05 04:29:07 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 205388 kb
Host smart-1ed9934b-e40b-41c6-800c-87e3d9787b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761293079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1761293079
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3682422877
Short name T1030
Test name
Test status
Simulation time 19225208 ps
CPU time 0.69 seconds
Started Jun 05 04:29:05 PM PDT 24
Finished Jun 05 04:29:06 PM PDT 24
Peak memory 205384 kb
Host smart-0b6841f4-7e4e-4869-aeef-640eec37ea8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682422877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3682422877
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2659767707
Short name T957
Test name
Test status
Simulation time 68476050 ps
CPU time 0.74 seconds
Started Jun 05 04:29:06 PM PDT 24
Finished Jun 05 04:29:07 PM PDT 24
Peak memory 205328 kb
Host smart-07010906-3897-4560-92d0-e5ca5b0fd90c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659767707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2659767707
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2164343936
Short name T1084
Test name
Test status
Simulation time 52873394 ps
CPU time 1.14 seconds
Started Jun 05 04:28:22 PM PDT 24
Finished Jun 05 04:28:24 PM PDT 24
Peak memory 205760 kb
Host smart-019c7b2f-db34-4421-bc89-e260ea5edd9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164343936 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2164343936
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3613463159
Short name T1051
Test name
Test status
Simulation time 21809227 ps
CPU time 1.21 seconds
Started Jun 05 04:28:27 PM PDT 24
Finished Jun 05 04:28:28 PM PDT 24
Peak memory 205692 kb
Host smart-4b81cb51-a620-4be1-8f4a-911ddefee4d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613463159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3613463159
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2387982777
Short name T994
Test name
Test status
Simulation time 15153580 ps
CPU time 0.84 seconds
Started Jun 05 04:28:22 PM PDT 24
Finished Jun 05 04:28:23 PM PDT 24
Peak memory 205384 kb
Host smart-72cb9b58-1b14-4121-af62-4b6c5d34cdb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387982777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2387982777
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.395929645
Short name T952
Test name
Test status
Simulation time 113446742 ps
CPU time 4.52 seconds
Started Jun 05 04:28:23 PM PDT 24
Finished Jun 05 04:28:28 PM PDT 24
Peak memory 205696 kb
Host smart-72e9e5c9-d148-4649-8579-f7c7b6ae3157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395929645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.395929645
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1625021138
Short name T110
Test name
Test status
Simulation time 103829392 ps
CPU time 2.79 seconds
Started Jun 05 04:28:23 PM PDT 24
Finished Jun 05 04:28:26 PM PDT 24
Peak memory 214164 kb
Host smart-3e628ee8-4192-47f9-a57b-cb58cff599ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625021138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1625021138
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3371996357
Short name T1016
Test name
Test status
Simulation time 168325027 ps
CPU time 7.3 seconds
Started Jun 05 04:28:24 PM PDT 24
Finished Jun 05 04:28:32 PM PDT 24
Peak memory 214220 kb
Host smart-07af7e6c-35ed-4552-bb9c-6033eef03afc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371996357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3371996357
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3253607917
Short name T977
Test name
Test status
Simulation time 56470314 ps
CPU time 3.83 seconds
Started Jun 05 04:28:21 PM PDT 24
Finished Jun 05 04:28:25 PM PDT 24
Peak memory 213924 kb
Host smart-2143763a-596c-46f8-81c3-fe3688c69b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253607917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3253607917
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2960705904
Short name T377
Test name
Test status
Simulation time 71363298 ps
CPU time 3.07 seconds
Started Jun 05 04:28:24 PM PDT 24
Finished Jun 05 04:28:28 PM PDT 24
Peak memory 213896 kb
Host smart-58edf9cc-e348-4d39-8daa-02a2542f41df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960705904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2960705904
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3905246470
Short name T958
Test name
Test status
Simulation time 57566954 ps
CPU time 1.5 seconds
Started Jun 05 04:28:23 PM PDT 24
Finished Jun 05 04:28:26 PM PDT 24
Peak memory 216272 kb
Host smart-791853f4-9c25-4275-a21e-a1dbf5e8229e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905246470 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3905246470
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2190450827
Short name T1049
Test name
Test status
Simulation time 43356115 ps
CPU time 1.08 seconds
Started Jun 05 04:28:26 PM PDT 24
Finished Jun 05 04:28:27 PM PDT 24
Peak memory 205728 kb
Host smart-4b299383-7bb5-4f19-9f53-73dbefcc4a1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190450827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2190450827
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2232524986
Short name T1004
Test name
Test status
Simulation time 12200188 ps
CPU time 0.73 seconds
Started Jun 05 04:28:27 PM PDT 24
Finished Jun 05 04:28:28 PM PDT 24
Peak memory 205240 kb
Host smart-e63def0c-c137-4e83-9522-d1fe7908348d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232524986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2232524986
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3441702774
Short name T1019
Test name
Test status
Simulation time 179606041 ps
CPU time 1.52 seconds
Started Jun 05 04:28:22 PM PDT 24
Finished Jun 05 04:28:24 PM PDT 24
Peak memory 205616 kb
Host smart-5783e4e4-2c7d-43bf-bcc7-ef3ff9c09922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441702774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3441702774
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.659626393
Short name T965
Test name
Test status
Simulation time 228034505 ps
CPU time 6.29 seconds
Started Jun 05 04:28:26 PM PDT 24
Finished Jun 05 04:28:33 PM PDT 24
Peak memory 214220 kb
Host smart-c27c7e4d-f11a-4e0a-8406-d2467509cd04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659626393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.659626393
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.668423770
Short name T981
Test name
Test status
Simulation time 459124883 ps
CPU time 15.37 seconds
Started Jun 05 04:28:24 PM PDT 24
Finished Jun 05 04:28:40 PM PDT 24
Peak memory 220312 kb
Host smart-419e1ee4-1443-4f5a-8427-14b4940b0b16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668423770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.668423770
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3855847726
Short name T936
Test name
Test status
Simulation time 55405599 ps
CPU time 1.65 seconds
Started Jun 05 04:28:23 PM PDT 24
Finished Jun 05 04:28:25 PM PDT 24
Peak memory 205776 kb
Host smart-a043953b-5b93-49cc-96b4-5cfca8a7844a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855847726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3855847726
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3519923688
Short name T173
Test name
Test status
Simulation time 72205660 ps
CPU time 3.11 seconds
Started Jun 05 04:28:23 PM PDT 24
Finished Jun 05 04:28:27 PM PDT 24
Peak memory 205824 kb
Host smart-5a1bac4d-599f-46bd-93c5-53faaefeb5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519923688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3519923688
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3710999933
Short name T960
Test name
Test status
Simulation time 28700488 ps
CPU time 1.74 seconds
Started Jun 05 04:28:28 PM PDT 24
Finished Jun 05 04:28:30 PM PDT 24
Peak memory 214016 kb
Host smart-17bdbc45-e68b-4d56-bfb3-99a0bf5fe645
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710999933 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3710999933
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1726001110
Short name T941
Test name
Test status
Simulation time 59587754 ps
CPU time 0.93 seconds
Started Jun 05 04:28:32 PM PDT 24
Finished Jun 05 04:28:33 PM PDT 24
Peak memory 205516 kb
Host smart-97aa6725-0a3f-4a88-ac30-874d03bd662e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726001110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1726001110
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3080425623
Short name T1033
Test name
Test status
Simulation time 14370769 ps
CPU time 0.89 seconds
Started Jun 05 04:28:30 PM PDT 24
Finished Jun 05 04:28:31 PM PDT 24
Peak memory 205492 kb
Host smart-1df4d548-cbc3-489f-90c6-61e0819c5f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080425623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3080425623
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2219761559
Short name T972
Test name
Test status
Simulation time 413929203 ps
CPU time 2.92 seconds
Started Jun 05 04:28:33 PM PDT 24
Finished Jun 05 04:28:37 PM PDT 24
Peak memory 205768 kb
Host smart-2622cd06-a701-422b-a6e8-843863a23b57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219761559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2219761559
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1911365315
Short name T117
Test name
Test status
Simulation time 276267492 ps
CPU time 2.71 seconds
Started Jun 05 04:28:21 PM PDT 24
Finished Jun 05 04:28:24 PM PDT 24
Peak memory 222324 kb
Host smart-a16123fe-30ae-4072-b63c-87b21a011d6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911365315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1911365315
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.143824501
Short name T950
Test name
Test status
Simulation time 23152684 ps
CPU time 1.56 seconds
Started Jun 05 04:28:21 PM PDT 24
Finished Jun 05 04:28:24 PM PDT 24
Peak memory 205616 kb
Host smart-38cdd9e7-cbde-4dd6-aaff-c3a65a77e136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143824501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.143824501
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1967417937
Short name T176
Test name
Test status
Simulation time 199088502 ps
CPU time 3.16 seconds
Started Jun 05 04:28:28 PM PDT 24
Finished Jun 05 04:28:32 PM PDT 24
Peak memory 214716 kb
Host smart-0859b6b1-cd0a-4cb0-a7c6-4a09a4f40b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967417937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1967417937
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3740806907
Short name T930
Test name
Test status
Simulation time 33424855 ps
CPU time 2.13 seconds
Started Jun 05 04:28:32 PM PDT 24
Finished Jun 05 04:28:35 PM PDT 24
Peak memory 214032 kb
Host smart-c807c6c1-ad62-4d67-9da5-9d3826cd847b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740806907 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3740806907
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1413718019
Short name T1014
Test name
Test status
Simulation time 27063836 ps
CPU time 1.52 seconds
Started Jun 05 04:28:26 PM PDT 24
Finished Jun 05 04:28:28 PM PDT 24
Peak memory 205616 kb
Host smart-2b107210-0222-419b-aedb-098f53a7ce9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413718019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1413718019
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3642026200
Short name T1060
Test name
Test status
Simulation time 29014083 ps
CPU time 0.79 seconds
Started Jun 05 04:28:35 PM PDT 24
Finished Jun 05 04:28:36 PM PDT 24
Peak memory 205348 kb
Host smart-00c8673e-69e9-454a-bb62-ba016914f194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642026200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3642026200
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1476944021
Short name T963
Test name
Test status
Simulation time 119011769 ps
CPU time 3.24 seconds
Started Jun 05 04:28:35 PM PDT 24
Finished Jun 05 04:28:39 PM PDT 24
Peak memory 205724 kb
Host smart-18eed46e-3fc2-487a-987f-b3344dc39d2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476944021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1476944021
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2431968700
Short name T1073
Test name
Test status
Simulation time 302120652 ps
CPU time 2.91 seconds
Started Jun 05 04:28:28 PM PDT 24
Finished Jun 05 04:28:32 PM PDT 24
Peak memory 214304 kb
Host smart-adc0e300-56bc-4bb9-b7e4-9e507f60249b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431968700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2431968700
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.246478878
Short name T1064
Test name
Test status
Simulation time 771428790 ps
CPU time 5.61 seconds
Started Jun 05 04:28:33 PM PDT 24
Finished Jun 05 04:28:39 PM PDT 24
Peak memory 214280 kb
Host smart-268d6e0c-6e2a-49bd-baf6-63a9c1f884ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246478878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.246478878
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.207465307
Short name T1042
Test name
Test status
Simulation time 44941897 ps
CPU time 3.42 seconds
Started Jun 05 04:28:35 PM PDT 24
Finished Jun 05 04:28:39 PM PDT 24
Peak memory 213952 kb
Host smart-51412d77-fdd1-46a2-96eb-62d5bc46dd66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207465307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.207465307
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2229801878
Short name T1021
Test name
Test status
Simulation time 70177596 ps
CPU time 2.53 seconds
Started Jun 05 04:28:35 PM PDT 24
Finished Jun 05 04:28:38 PM PDT 24
Peak memory 213804 kb
Host smart-1dcc2164-87e3-47d2-a586-558da9a6d0dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229801878 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2229801878
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4198078694
Short name T1077
Test name
Test status
Simulation time 120331550 ps
CPU time 1.05 seconds
Started Jun 05 04:28:30 PM PDT 24
Finished Jun 05 04:28:32 PM PDT 24
Peak memory 205456 kb
Host smart-7ec5c1a2-9d75-48ba-94e5-c1df32b0ffe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198078694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4198078694
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1498091841
Short name T949
Test name
Test status
Simulation time 20969992 ps
CPU time 0.69 seconds
Started Jun 05 04:28:41 PM PDT 24
Finished Jun 05 04:28:42 PM PDT 24
Peak memory 205324 kb
Host smart-c38bb19e-7a28-4396-bed4-b45208ede825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498091841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1498091841
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4115465259
Short name T1079
Test name
Test status
Simulation time 24503915 ps
CPU time 1.74 seconds
Started Jun 05 04:28:31 PM PDT 24
Finished Jun 05 04:28:34 PM PDT 24
Peak memory 205708 kb
Host smart-b4aa1193-fcc0-4b5b-86c9-3dc1134c36d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115465259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4115465259
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4231898067
Short name T114
Test name
Test status
Simulation time 200985337 ps
CPU time 3.48 seconds
Started Jun 05 04:28:31 PM PDT 24
Finished Jun 05 04:28:35 PM PDT 24
Peak memory 214160 kb
Host smart-5b1e439b-19f2-4750-b1bc-abdecc29baf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231898067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4231898067
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2524591754
Short name T955
Test name
Test status
Simulation time 295721662 ps
CPU time 4.92 seconds
Started Jun 05 04:28:31 PM PDT 24
Finished Jun 05 04:28:37 PM PDT 24
Peak memory 220316 kb
Host smart-b1fbb42d-4abe-4059-b79e-8f19a686b331
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524591754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2524591754
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3028995
Short name T921
Test name
Test status
Simulation time 501951023 ps
CPU time 2.34 seconds
Started Jun 05 04:28:31 PM PDT 24
Finished Jun 05 04:28:34 PM PDT 24
Peak memory 213924 kb
Host smart-112cb9d6-396b-47ee-9fc9-611da6367386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3028995
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1641217013
Short name T1047
Test name
Test status
Simulation time 375566336 ps
CPU time 4.98 seconds
Started Jun 05 04:28:27 PM PDT 24
Finished Jun 05 04:28:33 PM PDT 24
Peak memory 214164 kb
Host smart-8af36d02-aa0b-45c2-bd16-9d4106f70afc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641217013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1641217013
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3856727920
Short name T413
Test name
Test status
Simulation time 35985279 ps
CPU time 0.76 seconds
Started Jun 05 04:08:29 PM PDT 24
Finished Jun 05 04:08:31 PM PDT 24
Peak memory 205908 kb
Host smart-26c73744-2c4b-4fa6-bdc0-e48ceb76cad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856727920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3856727920
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.377565637
Short name T380
Test name
Test status
Simulation time 113962606 ps
CPU time 2.85 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 214340 kb
Host smart-345235ff-290b-42b9-96ed-463af239412a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377565637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.377565637
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1619888616
Short name T21
Test name
Test status
Simulation time 227620610 ps
CPU time 2.93 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 221684 kb
Host smart-4b516f26-d295-433c-96d0-371682f4804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619888616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1619888616
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.88653665
Short name T671
Test name
Test status
Simulation time 79051962 ps
CPU time 1.68 seconds
Started Jun 05 04:08:32 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 207508 kb
Host smart-0ade6d2e-ee9a-4674-a30c-33e1e225dd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88653665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.88653665
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1904465344
Short name T553
Test name
Test status
Simulation time 277218579 ps
CPU time 7.93 seconds
Started Jun 05 04:08:29 PM PDT 24
Finished Jun 05 04:08:38 PM PDT 24
Peak memory 222188 kb
Host smart-d1d64e7d-e831-4293-8210-311c8b44e06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904465344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1904465344
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3672347031
Short name T491
Test name
Test status
Simulation time 569115009 ps
CPU time 5.71 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:08:38 PM PDT 24
Peak memory 214676 kb
Host smart-abc91ec2-9607-4829-9dc6-dfb0892c3490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672347031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3672347031
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.582046774
Short name T288
Test name
Test status
Simulation time 301943339 ps
CPU time 4.26 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 222440 kb
Host smart-a6001242-1840-493e-a112-6570b4d50bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582046774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.582046774
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2799535637
Short name T356
Test name
Test status
Simulation time 384896993 ps
CPU time 5.41 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:08:37 PM PDT 24
Peak memory 218316 kb
Host smart-199329ff-ae09-45bd-8af9-791357143d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799535637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2799535637
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3287942763
Short name T628
Test name
Test status
Simulation time 1013490105 ps
CPU time 3.4 seconds
Started Jun 05 04:08:21 PM PDT 24
Finished Jun 05 04:08:25 PM PDT 24
Peak memory 208680 kb
Host smart-96c12741-73e4-4ac5-8699-d0fa239e0c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287942763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3287942763
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2549330185
Short name T818
Test name
Test status
Simulation time 490803532 ps
CPU time 6.05 seconds
Started Jun 05 04:08:22 PM PDT 24
Finished Jun 05 04:08:29 PM PDT 24
Peak memory 208476 kb
Host smart-2ebfe72b-e284-4e6d-807a-9cdec0ef3bcb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549330185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2549330185
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3729612484
Short name T574
Test name
Test status
Simulation time 180468516 ps
CPU time 3.24 seconds
Started Jun 05 04:08:22 PM PDT 24
Finished Jun 05 04:08:26 PM PDT 24
Peak memory 206956 kb
Host smart-5c733099-5a13-4067-81bf-e045f9947f34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729612484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3729612484
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1838941861
Short name T438
Test name
Test status
Simulation time 203762649 ps
CPU time 3.01 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 218392 kb
Host smart-0d107127-3b50-4528-b89b-7ace27c7ce6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838941861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1838941861
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3978996431
Short name T660
Test name
Test status
Simulation time 2635924994 ps
CPU time 4.82 seconds
Started Jun 05 04:08:21 PM PDT 24
Finished Jun 05 04:08:26 PM PDT 24
Peak memory 208440 kb
Host smart-c9419272-e484-49bd-a0fb-c231b0aa7811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978996431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3978996431
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.102866966
Short name T78
Test name
Test status
Simulation time 614614956 ps
CPU time 17.7 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:49 PM PDT 24
Peak memory 222608 kb
Host smart-4a9614ce-62c0-40e1-a648-ac0bcac7f0fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102866966 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.102866966
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.4282992569
Short name T701
Test name
Test status
Simulation time 594489086 ps
CPU time 8.65 seconds
Started Jun 05 04:08:29 PM PDT 24
Finished Jun 05 04:08:38 PM PDT 24
Peak memory 210108 kb
Host smart-be31b8de-4ec3-44a6-a3f4-a67eddcc3b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282992569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.4282992569
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3597218684
Short name T189
Test name
Test status
Simulation time 503613414 ps
CPU time 2.65 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 209996 kb
Host smart-aa0755bf-7238-4f6a-9f62-51ffae89f751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597218684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3597218684
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2427086962
Short name T843
Test name
Test status
Simulation time 9688282 ps
CPU time 0.82 seconds
Started Jun 05 04:08:33 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 205940 kb
Host smart-763b1bd1-a60d-4154-948a-457ae8a807dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427086962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2427086962
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3437958458
Short name T104
Test name
Test status
Simulation time 200336428 ps
CPU time 3.3 seconds
Started Jun 05 04:08:29 PM PDT 24
Finished Jun 05 04:08:33 PM PDT 24
Peak memory 215648 kb
Host smart-6aa62d8b-ab5c-4747-acb5-bf20e22aea05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437958458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3437958458
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1333361266
Short name T56
Test name
Test status
Simulation time 615284328 ps
CPU time 3.51 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 208084 kb
Host smart-4c3bed7c-a507-4df8-81a7-217476b2ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333361266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1333361266
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.377472263
Short name T84
Test name
Test status
Simulation time 113197209 ps
CPU time 2.36 seconds
Started Jun 05 04:08:36 PM PDT 24
Finished Jun 05 04:08:39 PM PDT 24
Peak memory 214300 kb
Host smart-10682acb-8989-405c-b3ff-fb3aacc3c484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377472263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.377472263
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1408808498
Short name T698
Test name
Test status
Simulation time 155415831 ps
CPU time 2.43 seconds
Started Jun 05 04:08:32 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 208808 kb
Host smart-9f0865d8-cd8e-4026-99f1-a43400190fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408808498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1408808498
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1264723541
Short name T656
Test name
Test status
Simulation time 1465191801 ps
CPU time 29.17 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:09:01 PM PDT 24
Peak memory 217808 kb
Host smart-88896f10-b83d-4728-b532-9e125169ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264723541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1264723541
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2049944101
Short name T11
Test name
Test status
Simulation time 3407603224 ps
CPU time 5.85 seconds
Started Jun 05 04:08:33 PM PDT 24
Finished Jun 05 04:08:39 PM PDT 24
Peak memory 237328 kb
Host smart-84c95221-fc28-4db4-b085-f2aba85614f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049944101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2049944101
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2933863658
Short name T275
Test name
Test status
Simulation time 148254138 ps
CPU time 3.36 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 208116 kb
Host smart-4b8893bd-7df7-4ef0-98a2-443eb62a2ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933863658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2933863658
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3511265761
Short name T186
Test name
Test status
Simulation time 404123116 ps
CPU time 5.05 seconds
Started Jun 05 04:08:32 PM PDT 24
Finished Jun 05 04:08:38 PM PDT 24
Peak memory 208888 kb
Host smart-3255c05a-b0d2-46ce-99e9-1ef14fdbc6ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511265761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3511265761
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1749654
Short name T739
Test name
Test status
Simulation time 638034370 ps
CPU time 7.38 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:38 PM PDT 24
Peak memory 208208 kb
Host smart-e9eb2a6e-17d7-468e-86cf-67d396a05493
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1749654
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2507050591
Short name T345
Test name
Test status
Simulation time 198346537 ps
CPU time 2.59 seconds
Started Jun 05 04:08:32 PM PDT 24
Finished Jun 05 04:08:36 PM PDT 24
Peak memory 207364 kb
Host smart-ad8de242-e7e7-45db-8856-34f68f90865f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507050591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2507050591
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2515255783
Short name T523
Test name
Test status
Simulation time 662445507 ps
CPU time 4.25 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:08:36 PM PDT 24
Peak memory 207980 kb
Host smart-bbf40846-3a7d-4c03-8a85-c1895778d576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515255783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2515255783
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1881824533
Short name T746
Test name
Test status
Simulation time 1763672684 ps
CPU time 34.64 seconds
Started Jun 05 04:08:29 PM PDT 24
Finished Jun 05 04:09:04 PM PDT 24
Peak memory 222484 kb
Host smart-eff63a88-b287-4e37-8184-1a878cda1d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881824533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1881824533
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2040559263
Short name T109
Test name
Test status
Simulation time 505294642 ps
CPU time 18.04 seconds
Started Jun 05 04:08:33 PM PDT 24
Finished Jun 05 04:08:51 PM PDT 24
Peak memory 222720 kb
Host smart-587ca361-5643-4436-93e2-d9beb791e173
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040559263 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2040559263
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1976361544
Short name T476
Test name
Test status
Simulation time 640472086 ps
CPU time 6.13 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:36 PM PDT 24
Peak memory 214304 kb
Host smart-91608e13-eb95-4db2-9e29-46b8a381891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976361544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1976361544
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.283192036
Short name T168
Test name
Test status
Simulation time 2240630320 ps
CPU time 4.07 seconds
Started Jun 05 04:08:29 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 210432 kb
Host smart-cbbe1c3e-09f0-45d7-9499-ded663a1d981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283192036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.283192036
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2563676573
Short name T467
Test name
Test status
Simulation time 64491466 ps
CPU time 0.77 seconds
Started Jun 05 04:09:29 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 205920 kb
Host smart-16116b4d-4e04-4f09-b1f9-553c12059650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563676573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2563676573
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3708395212
Short name T404
Test name
Test status
Simulation time 213734909 ps
CPU time 3.96 seconds
Started Jun 05 04:09:17 PM PDT 24
Finished Jun 05 04:09:22 PM PDT 24
Peak memory 215224 kb
Host smart-f5045fce-86b0-4f5a-8b71-c24eeac9b7b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708395212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3708395212
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3055406877
Short name T851
Test name
Test status
Simulation time 115787511 ps
CPU time 3.83 seconds
Started Jun 05 04:09:17 PM PDT 24
Finished Jun 05 04:09:22 PM PDT 24
Peak memory 218220 kb
Host smart-6e99b111-2561-4a8d-bdd1-317af1e95872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055406877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3055406877
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.526854220
Short name T804
Test name
Test status
Simulation time 12064401025 ps
CPU time 41.87 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:59 PM PDT 24
Peak memory 222680 kb
Host smart-f7458fb7-36b2-469b-bcc4-c69db4b03e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526854220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.526854220
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1260286077
Short name T706
Test name
Test status
Simulation time 100024600 ps
CPU time 4.12 seconds
Started Jun 05 04:09:25 PM PDT 24
Finished Jun 05 04:09:30 PM PDT 24
Peak memory 214240 kb
Host smart-ac316cba-4931-44a8-b8df-7cadcd5e9e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260286077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1260286077
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3025808741
Short name T426
Test name
Test status
Simulation time 247082295 ps
CPU time 3.7 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:20 PM PDT 24
Peak memory 222516 kb
Host smart-75658e1e-9854-4a72-9e08-653583f679c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025808741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3025808741
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2761929204
Short name T705
Test name
Test status
Simulation time 291693830 ps
CPU time 6.36 seconds
Started Jun 05 04:09:17 PM PDT 24
Finished Jun 05 04:09:25 PM PDT 24
Peak memory 219268 kb
Host smart-3c7f5862-7beb-460d-ae44-ab704a7fbafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761929204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2761929204
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.4009943450
Short name T184
Test name
Test status
Simulation time 1122348791 ps
CPU time 4.99 seconds
Started Jun 05 04:09:15 PM PDT 24
Finished Jun 05 04:09:21 PM PDT 24
Peak memory 208688 kb
Host smart-0303ad8f-0269-4bed-ba1e-3687ad2d1ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009943450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.4009943450
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3259768584
Short name T15
Test name
Test status
Simulation time 1750836859 ps
CPU time 22.67 seconds
Started Jun 05 04:09:17 PM PDT 24
Finished Jun 05 04:09:41 PM PDT 24
Peak memory 209152 kb
Host smart-05c8dfc4-dd75-4906-9a3c-7136e0795ba0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259768584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3259768584
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2427160667
Short name T897
Test name
Test status
Simulation time 12378508315 ps
CPU time 47.31 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:10:04 PM PDT 24
Peak memory 208340 kb
Host smart-bb72be15-6f83-4554-88ed-29068abba644
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427160667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2427160667
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.545305431
Short name T712
Test name
Test status
Simulation time 557547435 ps
CPU time 3.55 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:21 PM PDT 24
Peak memory 208864 kb
Host smart-39728d99-84be-4579-abc8-e3a462277dd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545305431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.545305431
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1345766829
Short name T300
Test name
Test status
Simulation time 34463530 ps
CPU time 2.51 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:30 PM PDT 24
Peak memory 210236 kb
Host smart-d9e592f8-55d5-4f8b-9df9-d13464850d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345766829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1345766829
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2833377618
Short name T507
Test name
Test status
Simulation time 126045999 ps
CPU time 2.24 seconds
Started Jun 05 04:09:17 PM PDT 24
Finished Jun 05 04:09:20 PM PDT 24
Peak memory 206716 kb
Host smart-99a451ee-9cbc-477d-8e6d-a048aff85799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833377618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2833377618
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1959958523
Short name T634
Test name
Test status
Simulation time 221852937 ps
CPU time 3.82 seconds
Started Jun 05 04:09:26 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 207932 kb
Host smart-cef92cb0-5bee-45d1-b062-9cfd4403c51a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959958523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1959958523
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1512511702
Short name T163
Test name
Test status
Simulation time 289003731 ps
CPU time 5.25 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:35 PM PDT 24
Peak memory 220244 kb
Host smart-b4227962-7630-4128-a8e6-28307dda0922
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512511702 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1512511702
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2612098664
Short name T722
Test name
Test status
Simulation time 193149881 ps
CPU time 4.71 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:22 PM PDT 24
Peak memory 209176 kb
Host smart-6a47938e-09cd-4fc9-80cb-f182ebf420a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612098664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2612098664
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2290402877
Short name T659
Test name
Test status
Simulation time 242118752 ps
CPU time 4.01 seconds
Started Jun 05 04:09:26 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 210408 kb
Host smart-4e72992f-9310-48dd-b6ef-a3048b9180ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290402877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2290402877
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2574596603
Short name T490
Test name
Test status
Simulation time 17620341 ps
CPU time 0.79 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:29 PM PDT 24
Peak memory 205908 kb
Host smart-799ce7d7-b4fc-4976-b903-730ce6eb94dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574596603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2574596603
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1712983043
Short name T760
Test name
Test status
Simulation time 53795973 ps
CPU time 1.68 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 209596 kb
Host smart-1af0cff6-2d51-4504-a839-4034c1873176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712983043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1712983043
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1591798629
Short name T281
Test name
Test status
Simulation time 1150377493 ps
CPU time 3.94 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:32 PM PDT 24
Peak memory 214300 kb
Host smart-8c9585cf-b5ba-445c-9316-a7a594a392ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591798629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1591798629
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1140361784
Short name T213
Test name
Test status
Simulation time 272516341 ps
CPU time 2.94 seconds
Started Jun 05 04:09:29 PM PDT 24
Finished Jun 05 04:09:33 PM PDT 24
Peak memory 209032 kb
Host smart-4d544697-686c-420b-9f02-a98d33e8ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140361784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1140361784
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3638914172
Short name T327
Test name
Test status
Simulation time 632253305 ps
CPU time 4.82 seconds
Started Jun 05 04:09:26 PM PDT 24
Finished Jun 05 04:09:32 PM PDT 24
Peak memory 214408 kb
Host smart-3b365799-f852-4746-929d-31f2c2819577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638914172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3638914172
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.4107527829
Short name T864
Test name
Test status
Simulation time 118634208 ps
CPU time 2.46 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 206820 kb
Host smart-e18eb9a7-c32a-48e4-8e3c-0527f083fe64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107527829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.4107527829
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.737212917
Short name T531
Test name
Test status
Simulation time 57444169 ps
CPU time 3.05 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 206800 kb
Host smart-ebf90b83-3c0b-4b33-beb6-d93917274455
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737212917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.737212917
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.873533076
Short name T749
Test name
Test status
Simulation time 1420352981 ps
CPU time 40.88 seconds
Started Jun 05 04:09:25 PM PDT 24
Finished Jun 05 04:10:07 PM PDT 24
Peak memory 209220 kb
Host smart-d8c3e043-b44e-442a-ade3-1362d526b006
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873533076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.873533076
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2158412697
Short name T240
Test name
Test status
Simulation time 411833825 ps
CPU time 13.9 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:42 PM PDT 24
Peak memory 207908 kb
Host smart-dbb1ddc4-1bd1-49c7-acbf-36a8932f8034
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158412697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2158412697
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1792193873
Short name T689
Test name
Test status
Simulation time 1484049013 ps
CPU time 8.62 seconds
Started Jun 05 04:09:31 PM PDT 24
Finished Jun 05 04:09:41 PM PDT 24
Peak memory 207644 kb
Host smart-c2ddaf52-782f-45cc-bb9b-59c4fb9fc436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792193873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1792193873
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1465955553
Short name T100
Test name
Test status
Simulation time 103750440 ps
CPU time 3.85 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:33 PM PDT 24
Peak memory 208504 kb
Host smart-3eec0ee6-c721-4fb9-89c2-ae3a0d9aca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465955553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1465955553
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2344960389
Short name T668
Test name
Test status
Simulation time 882130457 ps
CPU time 9.68 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:39 PM PDT 24
Peak memory 222500 kb
Host smart-d89ab0fa-493c-4872-b1c3-15666adeabb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344960389 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2344960389
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.70237280
Short name T870
Test name
Test status
Simulation time 104770605 ps
CPU time 5.22 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:35 PM PDT 24
Peak memory 214336 kb
Host smart-e67c849c-32e2-4022-abe5-7a38b9b7863c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70237280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.70237280
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.4134762148
Short name T64
Test name
Test status
Simulation time 41351030 ps
CPU time 2.66 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 210384 kb
Host smart-67d91109-d7c4-44ac-9c1c-ddf1e79caf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134762148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4134762148
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.319427175
Short name T419
Test name
Test status
Simulation time 46717855 ps
CPU time 0.85 seconds
Started Jun 05 04:09:30 PM PDT 24
Finished Jun 05 04:09:32 PM PDT 24
Peak memory 205952 kb
Host smart-0a64db94-141a-487f-9174-8d0b078f5b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319427175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.319427175
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3576806052
Short name T33
Test name
Test status
Simulation time 302635290 ps
CPU time 3.51 seconds
Started Jun 05 04:09:26 PM PDT 24
Finished Jun 05 04:09:30 PM PDT 24
Peak memory 209324 kb
Host smart-8f37e7f4-b161-45b0-8dc1-3bc44908608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576806052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3576806052
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1968394949
Short name T519
Test name
Test status
Simulation time 136211223 ps
CPU time 3.73 seconds
Started Jun 05 04:09:29 PM PDT 24
Finished Jun 05 04:09:34 PM PDT 24
Peak memory 222428 kb
Host smart-6986456d-cfea-4e76-a3de-5b942be4c591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968394949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1968394949
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1338070513
Short name T55
Test name
Test status
Simulation time 175168498 ps
CPU time 2.28 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 219856 kb
Host smart-31a1cce6-92e4-46b2-b869-517dfed97408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338070513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1338070513
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1551221842
Short name T304
Test name
Test status
Simulation time 31371814 ps
CPU time 2.35 seconds
Started Jun 05 04:09:30 PM PDT 24
Finished Jun 05 04:09:33 PM PDT 24
Peak memory 207732 kb
Host smart-a771ee3d-8417-4938-bb57-ce1d3fc84354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551221842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1551221842
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1408174705
Short name T710
Test name
Test status
Simulation time 7227789987 ps
CPU time 18.77 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:47 PM PDT 24
Peak memory 208128 kb
Host smart-3c12f2ab-2ea1-445a-ac37-a7d534957934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408174705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1408174705
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1183664961
Short name T910
Test name
Test status
Simulation time 816062290 ps
CPU time 20.75 seconds
Started Jun 05 04:09:31 PM PDT 24
Finished Jun 05 04:09:53 PM PDT 24
Peak memory 208088 kb
Host smart-891100d7-d6c2-4d88-9d42-7ea14317f726
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183664961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1183664961
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3561970082
Short name T205
Test name
Test status
Simulation time 120744298 ps
CPU time 1.88 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:29 PM PDT 24
Peak memory 207404 kb
Host smart-faccd61f-c603-4279-98db-8e6cbbafa2a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561970082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3561970082
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.643557915
Short name T585
Test name
Test status
Simulation time 32249937 ps
CPU time 2.31 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:30 PM PDT 24
Peak memory 206920 kb
Host smart-4d4c5250-c7dc-467c-87e1-de7ee9621a31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643557915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.643557915
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3201235091
Short name T546
Test name
Test status
Simulation time 108306807 ps
CPU time 1.89 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 207784 kb
Host smart-01105e49-0a25-4d68-997d-071e3586720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201235091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3201235091
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3822911293
Short name T802
Test name
Test status
Simulation time 34971560 ps
CPU time 2.4 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 208444 kb
Host smart-729c3252-eaec-40e9-bae8-907b769b31ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822911293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3822911293
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1012771607
Short name T648
Test name
Test status
Simulation time 672070343 ps
CPU time 18.56 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:48 PM PDT 24
Peak memory 208316 kb
Host smart-913bbf8e-2779-4142-815d-19fc229de4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012771607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1012771607
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1212895082
Short name T487
Test name
Test status
Simulation time 80502834 ps
CPU time 2.01 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:30 PM PDT 24
Peak memory 209704 kb
Host smart-b8cfc76b-565b-4baa-8868-d5ad0161111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212895082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1212895082
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.411185344
Short name T774
Test name
Test status
Simulation time 11675926 ps
CPU time 0.86 seconds
Started Jun 05 04:09:41 PM PDT 24
Finished Jun 05 04:09:43 PM PDT 24
Peak memory 205940 kb
Host smart-2c286088-aeda-48ac-804a-f2ac461b091f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411185344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.411185344
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.619730839
Short name T231
Test name
Test status
Simulation time 58463762 ps
CPU time 4.04 seconds
Started Jun 05 04:09:30 PM PDT 24
Finished Jun 05 04:09:35 PM PDT 24
Peak memory 214416 kb
Host smart-d1595d0a-5c0f-4364-9da8-a1a8ae80a789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619730839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.619730839
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.725852300
Short name T40
Test name
Test status
Simulation time 319185468 ps
CPU time 4.66 seconds
Started Jun 05 04:09:35 PM PDT 24
Finished Jun 05 04:09:41 PM PDT 24
Peak memory 218312 kb
Host smart-20f3f6a3-e4ab-42d4-919a-a64e06459fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725852300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.725852300
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3931823572
Short name T807
Test name
Test status
Simulation time 84549344 ps
CPU time 2.4 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 209176 kb
Host smart-f7d3432a-9155-4fd6-b11f-52ef288bc819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931823572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3931823572
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1967380942
Short name T642
Test name
Test status
Simulation time 207868163 ps
CPU time 3.08 seconds
Started Jun 05 04:09:36 PM PDT 24
Finished Jun 05 04:09:39 PM PDT 24
Peak memory 214304 kb
Host smart-4b551998-498f-4ff4-bc13-164068b6acb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967380942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1967380942
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3273465827
Short name T745
Test name
Test status
Simulation time 138533943 ps
CPU time 2.71 seconds
Started Jun 05 04:09:40 PM PDT 24
Finished Jun 05 04:09:44 PM PDT 24
Peak memory 214176 kb
Host smart-cc11b67f-d173-4b86-8edd-bb35a50b1922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273465827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3273465827
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1731243014
Short name T489
Test name
Test status
Simulation time 60928249 ps
CPU time 2.3 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:31 PM PDT 24
Peak memory 220592 kb
Host smart-98762854-aceb-446c-b1b2-d113a5ebb54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731243014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1731243014
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3433175666
Short name T363
Test name
Test status
Simulation time 87193972 ps
CPU time 3.98 seconds
Started Jun 05 04:09:28 PM PDT 24
Finished Jun 05 04:09:34 PM PDT 24
Peak memory 208052 kb
Host smart-e2fabed4-d53f-43b0-b56d-8db40bbc1893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433175666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3433175666
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3607408166
Short name T247
Test name
Test status
Simulation time 952822025 ps
CPU time 6.2 seconds
Started Jun 05 04:09:29 PM PDT 24
Finished Jun 05 04:09:36 PM PDT 24
Peak memory 208604 kb
Host smart-b202461f-00ec-4e00-9f45-b0be7e310f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607408166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3607408166
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2956017649
Short name T790
Test name
Test status
Simulation time 112715920 ps
CPU time 2.23 seconds
Started Jun 05 04:09:30 PM PDT 24
Finished Jun 05 04:09:33 PM PDT 24
Peak memory 206828 kb
Host smart-76cd3f6d-72c4-46e4-b0b5-c42f2ff94057
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956017649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2956017649
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1046914643
Short name T204
Test name
Test status
Simulation time 119901106 ps
CPU time 3.25 seconds
Started Jun 05 04:09:30 PM PDT 24
Finished Jun 05 04:09:34 PM PDT 24
Peak memory 206956 kb
Host smart-4a8f0e2b-497f-4ab6-a6e9-d3eab89f566f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046914643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1046914643
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.166942348
Short name T675
Test name
Test status
Simulation time 891662830 ps
CPU time 7.11 seconds
Started Jun 05 04:09:29 PM PDT 24
Finished Jun 05 04:09:37 PM PDT 24
Peak memory 208108 kb
Host smart-353cfd46-1660-4941-9953-90611b7c5929
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166942348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.166942348
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.4019087628
Short name T768
Test name
Test status
Simulation time 262260747 ps
CPU time 2.87 seconds
Started Jun 05 04:09:38 PM PDT 24
Finished Jun 05 04:09:43 PM PDT 24
Peak memory 215712 kb
Host smart-0ead2ffe-5970-4c3c-81b7-4de0cd97ca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019087628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.4019087628
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3523162340
Short name T420
Test name
Test status
Simulation time 2628055284 ps
CPU time 22.73 seconds
Started Jun 05 04:09:27 PM PDT 24
Finished Jun 05 04:09:50 PM PDT 24
Peak memory 208868 kb
Host smart-356439e3-f25d-4708-914d-d52f74f78afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523162340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3523162340
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1846273536
Short name T849
Test name
Test status
Simulation time 2880863987 ps
CPU time 41.64 seconds
Started Jun 05 04:09:37 PM PDT 24
Finished Jun 05 04:10:20 PM PDT 24
Peak memory 222516 kb
Host smart-a6bb4e2b-688c-4d9c-b040-bd38c8554cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846273536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1846273536
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1953443796
Short name T901
Test name
Test status
Simulation time 4583560951 ps
CPU time 20.23 seconds
Started Jun 05 04:09:37 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 222740 kb
Host smart-51d34977-89ac-421a-83ab-b5e0e83a813f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953443796 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1953443796
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3832605667
Short name T863
Test name
Test status
Simulation time 223547853 ps
CPU time 5.1 seconds
Started Jun 05 04:09:34 PM PDT 24
Finished Jun 05 04:09:40 PM PDT 24
Peak memory 210560 kb
Host smart-35f983f1-9948-4998-8094-95aad31228ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832605667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3832605667
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2021297069
Short name T415
Test name
Test status
Simulation time 9918876 ps
CPU time 0.75 seconds
Started Jun 05 04:09:39 PM PDT 24
Finished Jun 05 04:09:41 PM PDT 24
Peak memory 205860 kb
Host smart-b06b04f2-5755-47d3-80c4-27ae41db6b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021297069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2021297069
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1534168630
Short name T392
Test name
Test status
Simulation time 273004066 ps
CPU time 4.62 seconds
Started Jun 05 04:09:35 PM PDT 24
Finished Jun 05 04:09:40 PM PDT 24
Peak memory 215400 kb
Host smart-339fdd3b-dd93-440c-bb12-d6175f0959ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534168630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1534168630
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1106563485
Short name T330
Test name
Test status
Simulation time 51029143 ps
CPU time 2.58 seconds
Started Jun 05 04:09:38 PM PDT 24
Finished Jun 05 04:09:41 PM PDT 24
Peak memory 209236 kb
Host smart-852f14d8-072a-42c5-9689-eb98168a7b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106563485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1106563485
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4015757159
Short name T331
Test name
Test status
Simulation time 73090243 ps
CPU time 1.58 seconds
Started Jun 05 04:09:42 PM PDT 24
Finished Jun 05 04:09:45 PM PDT 24
Peak memory 214212 kb
Host smart-3b9d83bf-cf5c-4bc1-8ec2-206fd6dcfbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015757159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4015757159
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3395877092
Short name T219
Test name
Test status
Simulation time 78435614 ps
CPU time 3.68 seconds
Started Jun 05 04:09:37 PM PDT 24
Finished Jun 05 04:09:41 PM PDT 24
Peak memory 218712 kb
Host smart-83f8de89-0754-4f8d-8610-6339f395fb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395877092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3395877092
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2222509645
Short name T912
Test name
Test status
Simulation time 161676030 ps
CPU time 6.55 seconds
Started Jun 05 04:09:44 PM PDT 24
Finished Jun 05 04:09:52 PM PDT 24
Peak memory 207508 kb
Host smart-ca2c8193-aa71-41c3-9b34-9b09f9676440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222509645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2222509645
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.773291016
Short name T664
Test name
Test status
Simulation time 337330067 ps
CPU time 5.47 seconds
Started Jun 05 04:09:38 PM PDT 24
Finished Jun 05 04:09:46 PM PDT 24
Peak memory 208396 kb
Host smart-c5265315-31a0-417c-a594-677c78e6627d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773291016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.773291016
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3491577632
Short name T417
Test name
Test status
Simulation time 62754358 ps
CPU time 2.35 seconds
Started Jun 05 04:09:41 PM PDT 24
Finished Jun 05 04:09:45 PM PDT 24
Peak memory 206984 kb
Host smart-e82ce194-f883-45a7-a377-2a757429963f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491577632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3491577632
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1104956821
Short name T474
Test name
Test status
Simulation time 1976725296 ps
CPU time 23.09 seconds
Started Jun 05 04:09:38 PM PDT 24
Finished Jun 05 04:10:03 PM PDT 24
Peak memory 208224 kb
Host smart-cc885eae-3de9-42fd-9812-47fd42bac430
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104956821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1104956821
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2233970047
Short name T748
Test name
Test status
Simulation time 2460429439 ps
CPU time 25.51 seconds
Started Jun 05 04:09:37 PM PDT 24
Finished Jun 05 04:10:03 PM PDT 24
Peak memory 208384 kb
Host smart-93f4005c-fecb-4deb-be4c-9aa0ed2de59e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233970047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2233970047
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.38768104
Short name T385
Test name
Test status
Simulation time 185170933 ps
CPU time 2.37 seconds
Started Jun 05 04:09:38 PM PDT 24
Finished Jun 05 04:09:42 PM PDT 24
Peak memory 216116 kb
Host smart-b0823987-4aaa-4e2c-8f5c-ab0de3725de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38768104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.38768104
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.339606362
Short name T713
Test name
Test status
Simulation time 502417769 ps
CPU time 2.89 seconds
Started Jun 05 04:09:41 PM PDT 24
Finished Jun 05 04:09:45 PM PDT 24
Peak memory 206736 kb
Host smart-783b5215-5f55-4e47-8758-f43aa14f249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339606362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.339606362
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3951629256
Short name T857
Test name
Test status
Simulation time 2065257447 ps
CPU time 18.59 seconds
Started Jun 05 04:09:44 PM PDT 24
Finished Jun 05 04:10:04 PM PDT 24
Peak memory 221020 kb
Host smart-19ebfbbc-063a-40dc-8335-efacfc96f980
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951629256 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3951629256
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.617727964
Short name T842
Test name
Test status
Simulation time 354298666 ps
CPU time 4.32 seconds
Started Jun 05 04:09:35 PM PDT 24
Finished Jun 05 04:09:40 PM PDT 24
Peak memory 207976 kb
Host smart-1b41b4ba-542a-4909-88cf-8e6cab404b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617727964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.617727964
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.4228218473
Short name T684
Test name
Test status
Simulation time 646349051 ps
CPU time 6.85 seconds
Started Jun 05 04:09:36 PM PDT 24
Finished Jun 05 04:09:44 PM PDT 24
Peak memory 210100 kb
Host smart-df4de524-4c97-43a8-9f49-033e36e543e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228218473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4228218473
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.42359857
Short name T539
Test name
Test status
Simulation time 19937580 ps
CPU time 0.81 seconds
Started Jun 05 04:09:38 PM PDT 24
Finished Jun 05 04:09:41 PM PDT 24
Peak memory 205940 kb
Host smart-437d9422-279c-4f63-a82f-47f2210139b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42359857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.42359857
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3021282617
Short name T334
Test name
Test status
Simulation time 69901597 ps
CPU time 4.18 seconds
Started Jun 05 04:09:44 PM PDT 24
Finished Jun 05 04:09:49 PM PDT 24
Peak memory 222488 kb
Host smart-20888648-5acd-430e-a897-8a7ecffbd561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021282617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3021282617
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1259356184
Short name T433
Test name
Test status
Simulation time 666115142 ps
CPU time 2.61 seconds
Started Jun 05 04:09:37 PM PDT 24
Finished Jun 05 04:09:40 PM PDT 24
Peak memory 220112 kb
Host smart-6fec9bf7-614f-4575-b445-1ee52dc845e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259356184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1259356184
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.799836158
Short name T726
Test name
Test status
Simulation time 32840742 ps
CPU time 1.63 seconds
Started Jun 05 04:09:36 PM PDT 24
Finished Jun 05 04:09:39 PM PDT 24
Peak memory 208216 kb
Host smart-c786615a-3de6-437b-99e1-9d146ebfc68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799836158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.799836158
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.4054154764
Short name T368
Test name
Test status
Simulation time 120975187 ps
CPU time 2.24 seconds
Started Jun 05 04:09:37 PM PDT 24
Finished Jun 05 04:09:40 PM PDT 24
Peak memory 214852 kb
Host smart-0cfa73ba-9d17-4020-a8fb-a4ccb2cdbf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054154764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.4054154764
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1783354753
Short name T217
Test name
Test status
Simulation time 413948845 ps
CPU time 3.66 seconds
Started Jun 05 04:09:41 PM PDT 24
Finished Jun 05 04:09:46 PM PDT 24
Peak memory 220040 kb
Host smart-a6e40fa8-c1c3-4a96-b779-66e6c7751dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783354753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1783354753
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1882588290
Short name T515
Test name
Test status
Simulation time 914549905 ps
CPU time 10.02 seconds
Started Jun 05 04:09:37 PM PDT 24
Finished Jun 05 04:09:48 PM PDT 24
Peak memory 214340 kb
Host smart-4c140a63-3f35-40aa-9520-6328dbb291ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882588290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1882588290
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.235437864
Short name T765
Test name
Test status
Simulation time 84511474 ps
CPU time 3.64 seconds
Started Jun 05 04:09:38 PM PDT 24
Finished Jun 05 04:09:43 PM PDT 24
Peak memory 208684 kb
Host smart-f06de218-1320-4f3d-bdf4-c86325f364df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235437864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.235437864
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3205535157
Short name T79
Test name
Test status
Simulation time 5907098468 ps
CPU time 19.44 seconds
Started Jun 05 04:09:37 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 209012 kb
Host smart-25744226-915d-43cd-9255-804e161bec3d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205535157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3205535157
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2331859265
Short name T796
Test name
Test status
Simulation time 2747524206 ps
CPU time 15.46 seconds
Started Jun 05 04:09:37 PM PDT 24
Finished Jun 05 04:09:54 PM PDT 24
Peak memory 208060 kb
Host smart-4cead90a-adbb-488c-9e63-87aaa00dcb4b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331859265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2331859265
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2553685695
Short name T827
Test name
Test status
Simulation time 142940267 ps
CPU time 2.77 seconds
Started Jun 05 04:09:36 PM PDT 24
Finished Jun 05 04:09:40 PM PDT 24
Peak memory 208756 kb
Host smart-c868b054-9e83-4a4d-90a1-b1baef387d90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553685695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2553685695
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3125143712
Short name T651
Test name
Test status
Simulation time 298603975 ps
CPU time 3.25 seconds
Started Jun 05 04:09:39 PM PDT 24
Finished Jun 05 04:09:44 PM PDT 24
Peak memory 209136 kb
Host smart-1dc830df-5410-403b-bce4-a4fc4008907f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125143712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3125143712
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3388480699
Short name T854
Test name
Test status
Simulation time 66705525 ps
CPU time 2.83 seconds
Started Jun 05 04:09:40 PM PDT 24
Finished Jun 05 04:09:45 PM PDT 24
Peak memory 207856 kb
Host smart-e089c504-cfd2-4466-932a-861df18f385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388480699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3388480699
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1742798123
Short name T755
Test name
Test status
Simulation time 448442614 ps
CPU time 8.82 seconds
Started Jun 05 04:09:37 PM PDT 24
Finished Jun 05 04:09:47 PM PDT 24
Peak memory 208084 kb
Host smart-2cbe7e3b-d1ca-4b0b-b8ba-ee5381559428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742798123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1742798123
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3592006883
Short name T118
Test name
Test status
Simulation time 123069106 ps
CPU time 2.6 seconds
Started Jun 05 04:09:36 PM PDT 24
Finished Jun 05 04:09:40 PM PDT 24
Peak memory 210044 kb
Host smart-babbf58c-62ee-4058-a714-3bbc44e6547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592006883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3592006883
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4195048405
Short name T423
Test name
Test status
Simulation time 26496160 ps
CPU time 0.8 seconds
Started Jun 05 04:09:44 PM PDT 24
Finished Jun 05 04:09:46 PM PDT 24
Peak memory 205928 kb
Host smart-1245eb1b-7a97-4785-a1cd-14b3cba9bbab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195048405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4195048405
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2723017264
Short name T63
Test name
Test status
Simulation time 777479805 ps
CPU time 15.44 seconds
Started Jun 05 04:09:47 PM PDT 24
Finished Jun 05 04:10:04 PM PDT 24
Peak memory 221464 kb
Host smart-710183a3-63c0-4e44-a98a-87960347cba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723017264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2723017264
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1627859839
Short name T788
Test name
Test status
Simulation time 411047163 ps
CPU time 4.99 seconds
Started Jun 05 04:09:46 PM PDT 24
Finished Jun 05 04:09:52 PM PDT 24
Peak memory 207900 kb
Host smart-8ba84c3c-8124-4643-80c3-936196ed92a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627859839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1627859839
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2159881956
Short name T25
Test name
Test status
Simulation time 198871651 ps
CPU time 4.6 seconds
Started Jun 05 04:09:47 PM PDT 24
Finished Jun 05 04:09:53 PM PDT 24
Peak memory 222052 kb
Host smart-e9f7a33c-3ddd-4989-b9e2-aec26438ce98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159881956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2159881956
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.4078064001
Short name T320
Test name
Test status
Simulation time 102370235 ps
CPU time 2.24 seconds
Started Jun 05 04:09:45 PM PDT 24
Finished Jun 05 04:09:49 PM PDT 24
Peak memory 214236 kb
Host smart-2f548861-2b80-4a74-a137-3e2d45b31040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078064001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.4078064001
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_random.1822786571
Short name T735
Test name
Test status
Simulation time 699758128 ps
CPU time 4.87 seconds
Started Jun 05 04:09:45 PM PDT 24
Finished Jun 05 04:09:51 PM PDT 24
Peak memory 208548 kb
Host smart-5b189910-c236-49ac-a9a0-89208348ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822786571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1822786571
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2852855388
Short name T359
Test name
Test status
Simulation time 2617319878 ps
CPU time 19.51 seconds
Started Jun 05 04:09:42 PM PDT 24
Finished Jun 05 04:10:03 PM PDT 24
Peak memory 208732 kb
Host smart-0efc3783-d02a-41cb-8fd0-3beb6c918c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852855388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2852855388
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2302897722
Short name T758
Test name
Test status
Simulation time 178591208 ps
CPU time 2.83 seconds
Started Jun 05 04:09:42 PM PDT 24
Finished Jun 05 04:09:46 PM PDT 24
Peak memory 206840 kb
Host smart-6fa7a2cf-3e88-4257-96d6-3e082d055945
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302897722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2302897722
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3977368276
Short name T828
Test name
Test status
Simulation time 85307358 ps
CPU time 1.9 seconds
Started Jun 05 04:09:36 PM PDT 24
Finished Jun 05 04:09:39 PM PDT 24
Peak memory 208656 kb
Host smart-4018356e-6371-40d4-bc32-fb01b798a20c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977368276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3977368276
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4148436943
Short name T846
Test name
Test status
Simulation time 332246125 ps
CPU time 2.84 seconds
Started Jun 05 04:09:40 PM PDT 24
Finished Jun 05 04:09:44 PM PDT 24
Peak memory 208956 kb
Host smart-65a18ee6-486e-43b4-b2cb-8f28bf68561b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148436943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4148436943
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2136565382
Short name T711
Test name
Test status
Simulation time 97716132 ps
CPU time 1.98 seconds
Started Jun 05 04:09:46 PM PDT 24
Finished Jun 05 04:09:49 PM PDT 24
Peak memory 218304 kb
Host smart-184a29aa-c5aa-4cbd-b798-0081d2f094c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136565382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2136565382
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2320157962
Short name T719
Test name
Test status
Simulation time 52351741 ps
CPU time 2.53 seconds
Started Jun 05 04:09:44 PM PDT 24
Finished Jun 05 04:09:48 PM PDT 24
Peak memory 206792 kb
Host smart-04c0d6c4-db77-4bdb-a9b7-519bf466e2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320157962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2320157962
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.4193765775
Short name T267
Test name
Test status
Simulation time 17932126360 ps
CPU time 127.38 seconds
Started Jun 05 04:09:47 PM PDT 24
Finished Jun 05 04:11:56 PM PDT 24
Peak memory 220788 kb
Host smart-143e2146-7f12-483d-a5cf-ba4eb8d5b308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193765775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.4193765775
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3742055506
Short name T632
Test name
Test status
Simulation time 448269610 ps
CPU time 9.81 seconds
Started Jun 05 04:09:46 PM PDT 24
Finished Jun 05 04:09:56 PM PDT 24
Peak memory 219868 kb
Host smart-50dfbbd8-a1f4-4239-938e-0d63aa99f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742055506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3742055506
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2338401351
Short name T718
Test name
Test status
Simulation time 60721922 ps
CPU time 1.62 seconds
Started Jun 05 04:09:47 PM PDT 24
Finished Jun 05 04:09:50 PM PDT 24
Peak memory 209928 kb
Host smart-062842eb-e383-4eef-8f2d-3e88ccb73791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338401351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2338401351
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1724388259
Short name T605
Test name
Test status
Simulation time 34219310 ps
CPU time 0.72 seconds
Started Jun 05 04:09:48 PM PDT 24
Finished Jun 05 04:09:49 PM PDT 24
Peak memory 205860 kb
Host smart-9b7b4072-5f9c-4b45-ad3d-2bf5a83aacd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724388259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1724388259
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1856076185
Short name T773
Test name
Test status
Simulation time 463708167 ps
CPU time 7.43 seconds
Started Jun 05 04:09:46 PM PDT 24
Finished Jun 05 04:09:54 PM PDT 24
Peak memory 208984 kb
Host smart-ec573b35-a6d2-403b-8f2f-2b7665feb88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856076185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1856076185
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.281969329
Short name T260
Test name
Test status
Simulation time 164954545 ps
CPU time 1.97 seconds
Started Jun 05 04:09:44 PM PDT 24
Finished Jun 05 04:09:47 PM PDT 24
Peak memory 214284 kb
Host smart-32b34792-24a2-4ccc-b25a-f55bc86b1b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281969329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.281969329
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3084120045
Short name T258
Test name
Test status
Simulation time 30271203 ps
CPU time 2.08 seconds
Started Jun 05 04:09:46 PM PDT 24
Finished Jun 05 04:09:49 PM PDT 24
Peak memory 214160 kb
Host smart-c41f0db2-d874-46fb-aeb3-c659b2022a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084120045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3084120045
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2447670003
Short name T209
Test name
Test status
Simulation time 706233234 ps
CPU time 3.81 seconds
Started Jun 05 04:09:49 PM PDT 24
Finished Jun 05 04:09:54 PM PDT 24
Peak memory 215824 kb
Host smart-0eddace0-cba6-4eba-bccf-ecc51c87ded7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447670003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2447670003
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.197270916
Short name T654
Test name
Test status
Simulation time 3444531426 ps
CPU time 65.19 seconds
Started Jun 05 04:09:47 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 208192 kb
Host smart-4bce2fc2-0107-43db-8a16-a3a1f9b7db5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197270916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.197270916
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3617820611
Short name T775
Test name
Test status
Simulation time 22790831 ps
CPU time 1.84 seconds
Started Jun 05 04:09:48 PM PDT 24
Finished Jun 05 04:09:51 PM PDT 24
Peak memory 206828 kb
Host smart-360692b5-3596-4f4e-89cf-e512254f87c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617820611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3617820611
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1220839491
Short name T907
Test name
Test status
Simulation time 871636759 ps
CPU time 6.11 seconds
Started Jun 05 04:09:46 PM PDT 24
Finished Jun 05 04:09:53 PM PDT 24
Peak memory 208780 kb
Host smart-32da0620-333b-40bd-85a6-c95586da5661
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220839491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1220839491
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3654248310
Short name T14
Test name
Test status
Simulation time 70204032 ps
CPU time 3.59 seconds
Started Jun 05 04:09:45 PM PDT 24
Finished Jun 05 04:09:50 PM PDT 24
Peak memory 208772 kb
Host smart-69ada8c3-2e81-4091-8414-5f700c4483a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654248310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3654248310
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.4287798837
Short name T183
Test name
Test status
Simulation time 2611989754 ps
CPU time 27.33 seconds
Started Jun 05 04:09:45 PM PDT 24
Finished Jun 05 04:10:14 PM PDT 24
Peak memory 208864 kb
Host smart-225aa20b-444d-4b04-b9d0-701f15f8f84c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287798837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.4287798837
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3979026649
Short name T191
Test name
Test status
Simulation time 205841115 ps
CPU time 4.5 seconds
Started Jun 05 04:09:45 PM PDT 24
Finished Jun 05 04:09:51 PM PDT 24
Peak memory 206800 kb
Host smart-97ab87b0-17a4-40d1-a1e8-f642598ec7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979026649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3979026649
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.4142304320
Short name T340
Test name
Test status
Simulation time 96392105269 ps
CPU time 235.55 seconds
Started Jun 05 04:09:45 PM PDT 24
Finished Jun 05 04:13:42 PM PDT 24
Peak memory 217708 kb
Host smart-3084d311-6835-4f21-88c8-c451133d0c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142304320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.4142304320
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3540121924
Short name T734
Test name
Test status
Simulation time 750208447 ps
CPU time 3.83 seconds
Started Jun 05 04:09:45 PM PDT 24
Finished Jun 05 04:09:50 PM PDT 24
Peak memory 208152 kb
Host smart-abc3ddda-7c26-4928-b4c9-2b9046dd42c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540121924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3540121924
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2790754924
Short name T699
Test name
Test status
Simulation time 87046652 ps
CPU time 2.3 seconds
Started Jun 05 04:09:48 PM PDT 24
Finished Jun 05 04:09:51 PM PDT 24
Peak memory 210600 kb
Host smart-b9c69673-3255-4aac-adea-bb36a3698003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790754924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2790754924
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.321201955
Short name T450
Test name
Test status
Simulation time 22293311 ps
CPU time 0.91 seconds
Started Jun 05 04:09:53 PM PDT 24
Finished Jun 05 04:09:55 PM PDT 24
Peak memory 205952 kb
Host smart-a241d4da-27aa-4b59-8923-73671ccf3a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321201955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.321201955
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.759428292
Short name T287
Test name
Test status
Simulation time 166799180 ps
CPU time 4.24 seconds
Started Jun 05 04:09:46 PM PDT 24
Finished Jun 05 04:09:52 PM PDT 24
Peak memory 222404 kb
Host smart-37206d37-f275-4a4b-bb57-8d93582f29e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759428292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.759428292
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.4162727654
Short name T806
Test name
Test status
Simulation time 135651445 ps
CPU time 3.94 seconds
Started Jun 05 04:09:57 PM PDT 24
Finished Jun 05 04:10:02 PM PDT 24
Peak memory 214252 kb
Host smart-d2c82f52-05f1-4c58-b7b8-801d4d80f47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162727654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4162727654
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.66691790
Short name T791
Test name
Test status
Simulation time 715269184 ps
CPU time 18.2 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:10:13 PM PDT 24
Peak memory 209992 kb
Host smart-1bb5cc26-309d-47f8-ac43-35356f4c649e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66691790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.66691790
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1927918260
Short name T317
Test name
Test status
Simulation time 36253954 ps
CPU time 2.32 seconds
Started Jun 05 04:09:53 PM PDT 24
Finished Jun 05 04:09:56 PM PDT 24
Peak memory 221336 kb
Host smart-1af775cc-b312-44ce-b8e7-71c3252ed8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927918260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1927918260
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1889836528
Short name T779
Test name
Test status
Simulation time 362549486 ps
CPU time 3.24 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 206008 kb
Host smart-9b2aaf8f-8423-4fe8-b1e7-001b56c8d5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889836528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1889836528
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4047191954
Short name T850
Test name
Test status
Simulation time 97110318 ps
CPU time 4.6 seconds
Started Jun 05 04:09:57 PM PDT 24
Finished Jun 05 04:10:02 PM PDT 24
Peak memory 209436 kb
Host smart-15dae70b-c73b-4fe4-ab24-11f72359bfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047191954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4047191954
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2791650983
Short name T208
Test name
Test status
Simulation time 434298978 ps
CPU time 8.46 seconds
Started Jun 05 04:09:46 PM PDT 24
Finished Jun 05 04:09:55 PM PDT 24
Peak memory 208040 kb
Host smart-8884be0a-9247-4b14-9b3b-3be25adadd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791650983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2791650983
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3518187416
Short name T792
Test name
Test status
Simulation time 183128454 ps
CPU time 2.25 seconds
Started Jun 05 04:09:46 PM PDT 24
Finished Jun 05 04:09:49 PM PDT 24
Peak memory 206932 kb
Host smart-8efe4737-c68a-457c-a496-0849d05df48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518187416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3518187416
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2401292335
Short name T763
Test name
Test status
Simulation time 797940763 ps
CPU time 2.6 seconds
Started Jun 05 04:09:48 PM PDT 24
Finished Jun 05 04:09:51 PM PDT 24
Peak memory 207684 kb
Host smart-1bca9045-77f4-4533-b218-1e982e33b2de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401292335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2401292335
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1148956209
Short name T747
Test name
Test status
Simulation time 112957695 ps
CPU time 3.12 seconds
Started Jun 05 04:09:47 PM PDT 24
Finished Jun 05 04:09:52 PM PDT 24
Peak memory 206996 kb
Host smart-28441601-288d-4d04-83e2-c6b8a3067934
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148956209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1148956209
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3812629334
Short name T203
Test name
Test status
Simulation time 32487602 ps
CPU time 2.3 seconds
Started Jun 05 04:09:46 PM PDT 24
Finished Jun 05 04:09:49 PM PDT 24
Peak memory 207392 kb
Host smart-a662969b-cbb9-47d1-a2a0-8497fdbf168a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812629334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3812629334
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2466640861
Short name T841
Test name
Test status
Simulation time 145075378 ps
CPU time 1.96 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:09:56 PM PDT 24
Peak memory 209556 kb
Host smart-43206d30-fde7-459d-be39-ae41a202fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466640861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2466640861
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3097900527
Short name T778
Test name
Test status
Simulation time 259835903 ps
CPU time 3.09 seconds
Started Jun 05 04:09:47 PM PDT 24
Finished Jun 05 04:09:52 PM PDT 24
Peak memory 208228 kb
Host smart-d4719b3b-e682-4860-bbc0-510ac12fa962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097900527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3097900527
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3149915694
Short name T75
Test name
Test status
Simulation time 239438968 ps
CPU time 9.46 seconds
Started Jun 05 04:09:57 PM PDT 24
Finished Jun 05 04:10:07 PM PDT 24
Peak memory 221976 kb
Host smart-06bfacd9-29a3-4976-95a0-d42b95a13229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149915694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3149915694
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2708183248
Short name T122
Test name
Test status
Simulation time 1585245234 ps
CPU time 13.72 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:10:09 PM PDT 24
Peak memory 219496 kb
Host smart-94ed83e5-96ab-4162-8dfa-0b2a1c622d61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708183248 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2708183248
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1112165112
Short name T537
Test name
Test status
Simulation time 188229606 ps
CPU time 3.37 seconds
Started Jun 05 04:09:58 PM PDT 24
Finished Jun 05 04:10:02 PM PDT 24
Peak memory 214548 kb
Host smart-afa96b13-e73d-4249-94f4-3f70f6f9054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112165112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1112165112
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3105750017
Short name T481
Test name
Test status
Simulation time 190360358 ps
CPU time 5.83 seconds
Started Jun 05 04:09:58 PM PDT 24
Finished Jun 05 04:10:05 PM PDT 24
Peak memory 211176 kb
Host smart-24f992a2-2ef4-4aa6-aa6a-ee28cf04a5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105750017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3105750017
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3450040057
Short name T424
Test name
Test status
Simulation time 13847297 ps
CPU time 0.82 seconds
Started Jun 05 04:09:53 PM PDT 24
Finished Jun 05 04:09:54 PM PDT 24
Peak memory 205952 kb
Host smart-892dab9e-33c5-4014-828e-4df2a67d3330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450040057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3450040057
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.587551396
Short name T881
Test name
Test status
Simulation time 437096459 ps
CPU time 6.04 seconds
Started Jun 05 04:09:55 PM PDT 24
Finished Jun 05 04:10:02 PM PDT 24
Peak memory 215424 kb
Host smart-549ee9f6-a2a0-46a8-8730-e649c94cb154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587551396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.587551396
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3101870016
Short name T400
Test name
Test status
Simulation time 334689533 ps
CPU time 2.06 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:09:57 PM PDT 24
Peak memory 208252 kb
Host smart-e1c7efb0-c6e3-4bfc-ad89-92f6b4113e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101870016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3101870016
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1232846016
Short name T676
Test name
Test status
Simulation time 151898624 ps
CPU time 5.74 seconds
Started Jun 05 04:09:59 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 218384 kb
Host smart-f3fdde02-8c95-4f92-a893-530704c34ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232846016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1232846016
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1723328787
Short name T709
Test name
Test status
Simulation time 59305788 ps
CPU time 2 seconds
Started Jun 05 04:09:55 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 214192 kb
Host smart-30d11992-f8fb-44ca-adff-8f08a0794578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723328787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1723328787
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1702400533
Short name T448
Test name
Test status
Simulation time 102525207 ps
CPU time 2.35 seconds
Started Jun 05 04:09:56 PM PDT 24
Finished Jun 05 04:09:59 PM PDT 24
Peak memory 206584 kb
Host smart-a429c9fa-ea47-47a3-aec9-db9338e5acef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702400533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1702400533
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.4003198480
Short name T237
Test name
Test status
Simulation time 110903894 ps
CPU time 5.38 seconds
Started Jun 05 04:09:53 PM PDT 24
Finished Jun 05 04:10:00 PM PDT 24
Peak memory 209004 kb
Host smart-654eca4f-2991-471b-999f-c5854de717d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003198480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4003198480
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.914270927
Short name T852
Test name
Test status
Simulation time 245244874 ps
CPU time 3.14 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 208080 kb
Host smart-ab75a256-0d53-4b6d-ab68-546f8ecd8436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914270927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.914270927
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.4070554090
Short name T540
Test name
Test status
Simulation time 379211493 ps
CPU time 3.06 seconds
Started Jun 05 04:09:55 PM PDT 24
Finished Jun 05 04:09:59 PM PDT 24
Peak memory 206824 kb
Host smart-08c36aed-dd59-44bb-94b8-d116aefce13b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070554090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4070554090
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2679887727
Short name T542
Test name
Test status
Simulation time 795872879 ps
CPU time 3.14 seconds
Started Jun 05 04:09:53 PM PDT 24
Finished Jun 05 04:09:57 PM PDT 24
Peak memory 208580 kb
Host smart-9eda7cde-2f00-49d1-be30-eeb53877a123
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679887727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2679887727
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1451268916
Short name T625
Test name
Test status
Simulation time 251344443 ps
CPU time 2.97 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 207052 kb
Host smart-71040137-a056-437a-a395-e92210a2f6bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451268916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1451268916
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2889624322
Short name T641
Test name
Test status
Simulation time 577805219 ps
CPU time 7.87 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:10:02 PM PDT 24
Peak memory 214320 kb
Host smart-e8beb50a-9a83-461c-ab6d-cb3c0dec51a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889624322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2889624322
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3887006051
Short name T805
Test name
Test status
Simulation time 672701789 ps
CPU time 4.21 seconds
Started Jun 05 04:09:57 PM PDT 24
Finished Jun 05 04:10:02 PM PDT 24
Peak memory 206992 kb
Host smart-3659c41e-8922-4e75-b938-4e06045f4fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887006051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3887006051
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3812303077
Short name T255
Test name
Test status
Simulation time 54471538 ps
CPU time 3.25 seconds
Started Jun 05 04:09:55 PM PDT 24
Finished Jun 05 04:09:59 PM PDT 24
Peak memory 214332 kb
Host smart-1821cb6d-dc5d-4365-a4d3-9bbbd640aba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812303077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3812303077
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2452279239
Short name T57
Test name
Test status
Simulation time 46214364 ps
CPU time 2 seconds
Started Jun 05 04:09:55 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 210180 kb
Host smart-5662bd0e-754f-4d34-8282-6cf14e775d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452279239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2452279239
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.371913522
Short name T708
Test name
Test status
Simulation time 43937315 ps
CPU time 0.83 seconds
Started Jun 05 04:08:44 PM PDT 24
Finished Jun 05 04:08:45 PM PDT 24
Peak memory 205908 kb
Host smart-3fc52af8-9426-44af-ab76-f00608d6d03a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371913522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.371913522
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.236662969
Short name T669
Test name
Test status
Simulation time 119068634 ps
CPU time 3.66 seconds
Started Jun 05 04:08:43 PM PDT 24
Finished Jun 05 04:08:47 PM PDT 24
Peak memory 208780 kb
Host smart-4ea4de7b-cb0a-4756-a2e5-128e9db7ecb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236662969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.236662969
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1284004737
Short name T797
Test name
Test status
Simulation time 202849606 ps
CPU time 3.33 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 210304 kb
Host smart-db9590e9-d44d-44c5-b8ee-e2698f6d150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284004737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1284004737
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1681909301
Short name T261
Test name
Test status
Simulation time 63028789 ps
CPU time 2.27 seconds
Started Jun 05 04:08:41 PM PDT 24
Finished Jun 05 04:08:44 PM PDT 24
Peak memory 214308 kb
Host smart-1a77aa0f-c0f4-42a2-86aa-77483b7c4afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681909301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1681909301
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.4249435235
Short name T315
Test name
Test status
Simulation time 220900599 ps
CPU time 3.59 seconds
Started Jun 05 04:08:39 PM PDT 24
Finished Jun 05 04:08:43 PM PDT 24
Peak memory 220044 kb
Host smart-f4d6f05e-34e1-4555-b0eb-6f47f56bd078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249435235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.4249435235
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.3274142408
Short name T496
Test name
Test status
Simulation time 818834600 ps
CPU time 5.49 seconds
Started Jun 05 04:08:36 PM PDT 24
Finished Jun 05 04:08:42 PM PDT 24
Peak memory 209896 kb
Host smart-163b1b71-4de4-445d-b22d-a0100a2d6f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274142408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3274142408
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.962395072
Short name T12
Test name
Test status
Simulation time 442797429 ps
CPU time 11.95 seconds
Started Jun 05 04:08:47 PM PDT 24
Finished Jun 05 04:09:00 PM PDT 24
Peak memory 237340 kb
Host smart-4e6d46f3-c72f-4587-af77-23fb676dec19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962395072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.962395072
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.844304409
Short name T535
Test name
Test status
Simulation time 270544869 ps
CPU time 4.12 seconds
Started Jun 05 04:08:36 PM PDT 24
Finished Jun 05 04:08:40 PM PDT 24
Peak memory 208372 kb
Host smart-60569c57-d064-4ae0-9aba-7c0c48ee8c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844304409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.844304409
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3901323540
Short name T372
Test name
Test status
Simulation time 78058781 ps
CPU time 3.3 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:08:35 PM PDT 24
Peak memory 206880 kb
Host smart-a5667ec4-73c8-449e-83f4-089585cbb9fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901323540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3901323540
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3684051824
Short name T346
Test name
Test status
Simulation time 745309807 ps
CPU time 4.03 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 206956 kb
Host smart-3d1c0c9c-abd7-47bf-9256-9d6ee8ee7918
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684051824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3684051824
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2798901285
Short name T347
Test name
Test status
Simulation time 20698330 ps
CPU time 1.76 seconds
Started Jun 05 04:08:31 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 206840 kb
Host smart-232c814d-b029-4677-9528-c7ac5437b6b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798901285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2798901285
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2207194866
Short name T364
Test name
Test status
Simulation time 271265426 ps
CPU time 4.05 seconds
Started Jun 05 04:08:40 PM PDT 24
Finished Jun 05 04:08:45 PM PDT 24
Peak memory 214320 kb
Host smart-38bd51de-fb95-4c1a-b910-8b136137305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207194866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2207194866
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.190535190
Short name T412
Test name
Test status
Simulation time 420038049 ps
CPU time 4.92 seconds
Started Jun 05 04:08:30 PM PDT 24
Finished Jun 05 04:08:36 PM PDT 24
Peak memory 207772 kb
Host smart-3c843992-4d1e-4c46-885d-68fb69b5704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190535190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.190535190
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1940465675
Short name T678
Test name
Test status
Simulation time 1788865437 ps
CPU time 39.25 seconds
Started Jun 05 04:08:40 PM PDT 24
Finished Jun 05 04:09:20 PM PDT 24
Peak memory 216092 kb
Host smart-1c0e1cfd-5656-49fe-82a9-88dcb0961421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940465675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1940465675
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2739276648
Short name T119
Test name
Test status
Simulation time 177565644 ps
CPU time 7.98 seconds
Started Jun 05 04:08:41 PM PDT 24
Finished Jun 05 04:08:49 PM PDT 24
Peak memory 222620 kb
Host smart-4ee41f7f-4847-4305-9ff0-01ccf786be82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739276648 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2739276648
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3312871861
Short name T185
Test name
Test status
Simulation time 346057885 ps
CPU time 3.74 seconds
Started Jun 05 04:08:29 PM PDT 24
Finished Jun 05 04:08:34 PM PDT 24
Peak memory 209384 kb
Host smart-5275a700-ae90-4bec-be2b-0a98a3cc5d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312871861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3312871861
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3714788726
Short name T482
Test name
Test status
Simulation time 39065072 ps
CPU time 1.64 seconds
Started Jun 05 04:08:40 PM PDT 24
Finished Jun 05 04:08:43 PM PDT 24
Peak memory 209716 kb
Host smart-9251caef-a864-450d-bb0f-adf95d4305c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714788726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3714788726
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.4020843935
Short name T440
Test name
Test status
Simulation time 20382363 ps
CPU time 0.98 seconds
Started Jun 05 04:09:59 PM PDT 24
Finished Jun 05 04:10:01 PM PDT 24
Peak memory 206048 kb
Host smart-f42e1ca6-59f0-4944-a9cf-56a616bcce5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020843935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4020843935
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1277591837
Short name T679
Test name
Test status
Simulation time 370603336 ps
CPU time 5.2 seconds
Started Jun 05 04:09:58 PM PDT 24
Finished Jun 05 04:10:05 PM PDT 24
Peak memory 215744 kb
Host smart-1e84e00e-5e04-4ee4-a991-bc996192fb24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1277591837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1277591837
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2433825448
Short name T571
Test name
Test status
Simulation time 760163420 ps
CPU time 19.58 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:10:15 PM PDT 24
Peak memory 208164 kb
Host smart-664f4ceb-014f-4192-b917-c37a6a076be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433825448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2433825448
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2030401322
Short name T462
Test name
Test status
Simulation time 51564452 ps
CPU time 2.2 seconds
Started Jun 05 04:09:55 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 209132 kb
Host smart-985029cc-e31c-420e-b2d7-14a61e8a48d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030401322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2030401322
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3839117453
Short name T784
Test name
Test status
Simulation time 51510602 ps
CPU time 1.76 seconds
Started Jun 05 04:09:55 PM PDT 24
Finished Jun 05 04:09:57 PM PDT 24
Peak memory 216480 kb
Host smart-c2f1a5da-3796-46f3-b2ee-229f30617cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839117453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3839117453
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.4276050019
Short name T453
Test name
Test status
Simulation time 241414634 ps
CPU time 5.27 seconds
Started Jun 05 04:09:56 PM PDT 24
Finished Jun 05 04:10:02 PM PDT 24
Peak memory 208852 kb
Host smart-9057e497-b144-4453-9678-9596d65d4ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276050019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.4276050019
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.4071387732
Short name T248
Test name
Test status
Simulation time 127591128 ps
CPU time 3.24 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 208676 kb
Host smart-e756681e-513d-45f8-a0c4-9b777667df7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071387732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.4071387732
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1037695137
Short name T622
Test name
Test status
Simulation time 87732792 ps
CPU time 3.87 seconds
Started Jun 05 04:09:53 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 208828 kb
Host smart-16245425-f84b-42f0-b708-1c2c931041b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037695137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1037695137
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2120019240
Short name T621
Test name
Test status
Simulation time 149143977 ps
CPU time 2.53 seconds
Started Jun 05 04:09:53 PM PDT 24
Finished Jun 05 04:09:56 PM PDT 24
Peak memory 206932 kb
Host smart-25caa0bd-fab6-4025-ac8b-2c1605f31c39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120019240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2120019240
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1529002043
Short name T530
Test name
Test status
Simulation time 1416840486 ps
CPU time 41.1 seconds
Started Jun 05 04:09:57 PM PDT 24
Finished Jun 05 04:10:39 PM PDT 24
Peak memory 208528 kb
Host smart-31a42077-094d-45d2-9fb9-710babbe3f90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529002043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1529002043
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3464478811
Short name T525
Test name
Test status
Simulation time 59713452 ps
CPU time 2.73 seconds
Started Jun 05 04:09:55 PM PDT 24
Finished Jun 05 04:09:59 PM PDT 24
Peak memory 214304 kb
Host smart-2fb81ce1-abd7-4fcd-8965-23d50286c746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464478811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3464478811
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3482299632
Short name T456
Test name
Test status
Simulation time 184383576 ps
CPU time 2.45 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:09:58 PM PDT 24
Peak memory 206712 kb
Host smart-ee17155f-7f2a-45bc-851a-1ef13a5e06d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482299632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3482299632
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.968433948
Short name T759
Test name
Test status
Simulation time 403557257 ps
CPU time 7.54 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:10:03 PM PDT 24
Peak memory 219900 kb
Host smart-df2989c4-af38-4e8f-90e4-e1b675132d67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968433948 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.968433948
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1446347911
Short name T235
Test name
Test status
Simulation time 594245720 ps
CPU time 7.1 seconds
Started Jun 05 04:09:54 PM PDT 24
Finished Jun 05 04:10:02 PM PDT 24
Peak memory 210240 kb
Host smart-5d41a480-1297-4a4c-896f-dd30ccc3e153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446347911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1446347911
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3319956201
Short name T161
Test name
Test status
Simulation time 29825167 ps
CPU time 1.82 seconds
Started Jun 05 04:09:57 PM PDT 24
Finished Jun 05 04:10:00 PM PDT 24
Peak memory 209884 kb
Host smart-60e39a96-0178-46c0-ac44-204dbb4897ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319956201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3319956201
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1025062882
Short name T418
Test name
Test status
Simulation time 40535062 ps
CPU time 0.73 seconds
Started Jun 05 04:10:04 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 205868 kb
Host smart-23cfb4c3-7e19-4cf0-90dd-bf8dcf87cc9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025062882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1025062882
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3712191313
Short name T860
Test name
Test status
Simulation time 259686740 ps
CPU time 2.14 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 217284 kb
Host smart-a9e8fbc6-09f2-463b-92cc-61b6e1a84973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712191313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3712191313
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2144031538
Short name T341
Test name
Test status
Simulation time 197014206 ps
CPU time 2.69 seconds
Started Jun 05 04:10:04 PM PDT 24
Finished Jun 05 04:10:07 PM PDT 24
Peak memory 209816 kb
Host smart-2a8b72a0-2a3d-45fb-be9d-8f19be6f2ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144031538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2144031538
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1490221806
Short name T589
Test name
Test status
Simulation time 136119374 ps
CPU time 3.31 seconds
Started Jun 05 04:10:09 PM PDT 24
Finished Jun 05 04:10:13 PM PDT 24
Peak memory 214468 kb
Host smart-530effe5-d00d-47eb-9b20-4a67ce8125e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490221806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1490221806
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.8131643
Short name T905
Test name
Test status
Simulation time 104475443 ps
CPU time 5.07 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:09 PM PDT 24
Peak memory 210172 kb
Host smart-f972d5c6-4b5c-4613-883f-eec0cd1d672d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8131643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.8131643
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2225211934
Short name T195
Test name
Test status
Simulation time 177551464 ps
CPU time 3.25 seconds
Started Jun 05 04:10:02 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 214300 kb
Host smart-abeb9ac0-80eb-4b72-90d9-36fc7c71c8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225211934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2225211934
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.112458926
Short name T738
Test name
Test status
Simulation time 488854756 ps
CPU time 4.76 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:09 PM PDT 24
Peak memory 208524 kb
Host smart-1b24ba2d-faef-419f-a4e7-5f242e39e034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112458926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.112458926
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3526158718
Short name T696
Test name
Test status
Simulation time 44075721 ps
CPU time 1.92 seconds
Started Jun 05 04:10:06 PM PDT 24
Finished Jun 05 04:10:09 PM PDT 24
Peak memory 208688 kb
Host smart-e3e4e3c5-0deb-435f-9c8f-02f1443e4401
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526158718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3526158718
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1286355608
Short name T825
Test name
Test status
Simulation time 1312623626 ps
CPU time 47.18 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:51 PM PDT 24
Peak memory 208436 kb
Host smart-c4fc670f-7dcd-4406-bfbb-9ffe71fe5f15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286355608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1286355608
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1919283461
Short name T890
Test name
Test status
Simulation time 95371192 ps
CPU time 2.77 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:07 PM PDT 24
Peak memory 207088 kb
Host smart-a728bf84-5bc4-4200-91f9-36abcf57451c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919283461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1919283461
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.260920114
Short name T541
Test name
Test status
Simulation time 37662485 ps
CPU time 1.99 seconds
Started Jun 05 04:10:02 PM PDT 24
Finished Jun 05 04:10:05 PM PDT 24
Peak memory 214332 kb
Host smart-bc5b2163-8004-49ec-ab89-9ce75ce02fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260920114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.260920114
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.59532119
Short name T657
Test name
Test status
Simulation time 63045991 ps
CPU time 2.42 seconds
Started Jun 05 04:09:58 PM PDT 24
Finished Jun 05 04:10:02 PM PDT 24
Peak memory 206044 kb
Host smart-7c525d99-7bc2-4342-8209-36081ef4e869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59532119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.59532119
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1777225555
Short name T495
Test name
Test status
Simulation time 155585314 ps
CPU time 5.38 seconds
Started Jun 05 04:10:04 PM PDT 24
Finished Jun 05 04:10:10 PM PDT 24
Peak memory 216004 kb
Host smart-bdd6ba6e-ae7d-43b1-9cab-54cd0053b5bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777225555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1777225555
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.434353759
Short name T629
Test name
Test status
Simulation time 324307261 ps
CPU time 10.28 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:14 PM PDT 24
Peak memory 222544 kb
Host smart-fbd10ce7-da72-4cd3-8304-0f48872675f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434353759 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.434353759
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.576882695
Short name T608
Test name
Test status
Simulation time 286869309 ps
CPU time 5.8 seconds
Started Jun 05 04:10:05 PM PDT 24
Finished Jun 05 04:10:11 PM PDT 24
Peak memory 207228 kb
Host smart-0b3b8d2a-164f-40a9-bce0-2b05f6d07561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576882695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.576882695
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.446231406
Short name T787
Test name
Test status
Simulation time 366577766 ps
CPU time 2.62 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:07 PM PDT 24
Peak memory 210516 kb
Host smart-68f78d2e-7197-4206-9276-9fd9315ca7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446231406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.446231406
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3600656002
Short name T103
Test name
Test status
Simulation time 15761054 ps
CPU time 0.95 seconds
Started Jun 05 04:10:04 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 206100 kb
Host smart-1cc8c5c1-9e84-4555-a08a-edd027afd8c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600656002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3600656002
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1085306001
Short name T402
Test name
Test status
Simulation time 100850564 ps
CPU time 3.66 seconds
Started Jun 05 04:10:06 PM PDT 24
Finished Jun 05 04:10:11 PM PDT 24
Peak memory 214356 kb
Host smart-e5a07ec7-6c26-4b66-9553-0135e8b939e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085306001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1085306001
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3835132854
Short name T42
Test name
Test status
Simulation time 148979922 ps
CPU time 6.55 seconds
Started Jun 05 04:10:09 PM PDT 24
Finished Jun 05 04:10:16 PM PDT 24
Peak memory 214260 kb
Host smart-8edc80a1-5b66-408c-ba70-6e32678a3d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835132854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3835132854
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2404801945
Short name T473
Test name
Test status
Simulation time 369872251 ps
CPU time 2.94 seconds
Started Jun 05 04:10:06 PM PDT 24
Finished Jun 05 04:10:10 PM PDT 24
Peak memory 214340 kb
Host smart-a8d91f2e-416c-49c6-a47c-0dd28aee6d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404801945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2404801945
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.979470778
Short name T736
Test name
Test status
Simulation time 181916929 ps
CPU time 4.78 seconds
Started Jun 05 04:10:02 PM PDT 24
Finished Jun 05 04:10:07 PM PDT 24
Peak memory 208824 kb
Host smart-cbddf3ac-c132-4498-ba45-14a1444f4184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979470778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.979470778
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3979222602
Short name T278
Test name
Test status
Simulation time 496943941 ps
CPU time 12.42 seconds
Started Jun 05 04:10:01 PM PDT 24
Finished Jun 05 04:10:14 PM PDT 24
Peak memory 208660 kb
Host smart-af259601-69e9-47a4-a2ea-8e5d503d16c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979222602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3979222602
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2066834070
Short name T503
Test name
Test status
Simulation time 51101985 ps
CPU time 2.9 seconds
Started Jun 05 04:10:05 PM PDT 24
Finished Jun 05 04:10:09 PM PDT 24
Peak memory 207344 kb
Host smart-159e2352-b04b-4382-827e-9d5b25ac2691
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066834070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2066834070
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1577308790
Short name T673
Test name
Test status
Simulation time 227341124 ps
CPU time 6.16 seconds
Started Jun 05 04:10:06 PM PDT 24
Finished Jun 05 04:10:13 PM PDT 24
Peak memory 208004 kb
Host smart-1ea3074a-16cc-46af-b8c4-74f00a814fb6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577308790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1577308790
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3539746827
Short name T665
Test name
Test status
Simulation time 114096558 ps
CPU time 2.91 seconds
Started Jun 05 04:10:04 PM PDT 24
Finished Jun 05 04:10:08 PM PDT 24
Peak memory 206928 kb
Host smart-cf9d4030-c59a-4274-b68e-757384e780a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539746827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3539746827
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3151507091
Short name T658
Test name
Test status
Simulation time 80721856 ps
CPU time 2.2 seconds
Started Jun 05 04:10:02 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 215220 kb
Host smart-d0cb032b-bb81-4a42-9dd5-b93743376712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151507091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3151507091
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2002193264
Short name T422
Test name
Test status
Simulation time 355287728 ps
CPU time 6.45 seconds
Started Jun 05 04:10:03 PM PDT 24
Finished Jun 05 04:10:11 PM PDT 24
Peak memory 208536 kb
Host smart-2492aa14-c412-44e8-adbc-869a2a3f5498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002193264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2002193264
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1748707346
Short name T578
Test name
Test status
Simulation time 789041338 ps
CPU time 6.35 seconds
Started Jun 05 04:10:04 PM PDT 24
Finished Jun 05 04:10:11 PM PDT 24
Peak memory 209092 kb
Host smart-e73d571f-f7c6-4bf1-b7ee-4b90a52d7627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748707346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1748707346
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2493263634
Short name T121
Test name
Test status
Simulation time 1086465469 ps
CPU time 9.39 seconds
Started Jun 05 04:10:04 PM PDT 24
Finished Jun 05 04:10:14 PM PDT 24
Peak memory 222716 kb
Host smart-cd3035aa-633a-425b-ab6a-ae76e1d81d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493263634 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2493263634
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2606584083
Short name T441
Test name
Test status
Simulation time 2038784449 ps
CPU time 35.5 seconds
Started Jun 05 04:10:10 PM PDT 24
Finished Jun 05 04:10:46 PM PDT 24
Peak memory 209432 kb
Host smart-fdc79538-2921-413d-8c26-75dca8f965fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606584083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2606584083
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.984246281
Short name T898
Test name
Test status
Simulation time 43561640 ps
CPU time 0.79 seconds
Started Jun 05 04:10:10 PM PDT 24
Finished Jun 05 04:10:11 PM PDT 24
Peak memory 205956 kb
Host smart-ca08ea44-8f07-4041-9cec-7bf1eb508966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984246281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.984246281
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3356118424
Short name T215
Test name
Test status
Simulation time 345170123 ps
CPU time 3.17 seconds
Started Jun 05 04:10:14 PM PDT 24
Finished Jun 05 04:10:18 PM PDT 24
Peak memory 221452 kb
Host smart-b8ee9632-b3c4-4b9e-838c-7afb75578dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356118424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3356118424
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2134085533
Short name T800
Test name
Test status
Simulation time 242643082 ps
CPU time 3.06 seconds
Started Jun 05 04:10:06 PM PDT 24
Finished Jun 05 04:10:10 PM PDT 24
Peak memory 210224 kb
Host smart-b22e423c-6e35-4cde-b153-e1062035ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134085533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2134085533
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4124761112
Short name T333
Test name
Test status
Simulation time 64989012 ps
CPU time 2.55 seconds
Started Jun 05 04:10:04 PM PDT 24
Finished Jun 05 04:10:08 PM PDT 24
Peak memory 214408 kb
Host smart-e0fc7b73-537a-4126-891f-d8e947bc5933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124761112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4124761112
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2437346285
Short name T82
Test name
Test status
Simulation time 37588659 ps
CPU time 2.95 seconds
Started Jun 05 04:10:05 PM PDT 24
Finished Jun 05 04:10:09 PM PDT 24
Peak memory 220568 kb
Host smart-a42adb72-3434-402b-b347-15b0797a1206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437346285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2437346285
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2287058660
Short name T783
Test name
Test status
Simulation time 94893212 ps
CPU time 4.14 seconds
Started Jun 05 04:10:11 PM PDT 24
Finished Jun 05 04:10:16 PM PDT 24
Peak memory 220484 kb
Host smart-5436bf3f-cb80-4488-be85-0d00d959816f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287058660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2287058660
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2390455207
Short name T575
Test name
Test status
Simulation time 90928834 ps
CPU time 4.69 seconds
Started Jun 05 04:10:04 PM PDT 24
Finished Jun 05 04:10:10 PM PDT 24
Peak memory 209364 kb
Host smart-7289f6ef-7c24-4105-b76f-a0384ddd649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390455207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2390455207
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3391194175
Short name T290
Test name
Test status
Simulation time 49418449 ps
CPU time 2.74 seconds
Started Jun 05 04:10:02 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 206792 kb
Host smart-e63f743a-f6b1-4e0d-ae83-2480d4dabf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391194175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3391194175
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.4061775564
Short name T604
Test name
Test status
Simulation time 50965435 ps
CPU time 2.84 seconds
Started Jun 05 04:10:02 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 207904 kb
Host smart-6e8d52d6-f9ee-4588-b15f-8909fb408526
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061775564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.4061775564
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4187299495
Short name T472
Test name
Test status
Simulation time 49052648 ps
CPU time 2.88 seconds
Started Jun 05 04:10:02 PM PDT 24
Finished Jun 05 04:10:06 PM PDT 24
Peak memory 206956 kb
Host smart-d5d75cc4-4711-488d-840c-0ecf11f93275
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187299495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4187299495
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.4131133939
Short name T861
Test name
Test status
Simulation time 21119198 ps
CPU time 1.94 seconds
Started Jun 05 04:10:05 PM PDT 24
Finished Jun 05 04:10:08 PM PDT 24
Peak memory 206940 kb
Host smart-af7b6fb7-dfda-481c-b175-ce5d1bb14f35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131133939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4131133939
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2298020986
Short name T202
Test name
Test status
Simulation time 437145232 ps
CPU time 3.74 seconds
Started Jun 05 04:10:13 PM PDT 24
Finished Jun 05 04:10:17 PM PDT 24
Peak memory 209324 kb
Host smart-72568901-5d4b-46eb-b19d-ddcb4ee54634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298020986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2298020986
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2986539643
Short name T445
Test name
Test status
Simulation time 168795421 ps
CPU time 5.35 seconds
Started Jun 05 04:10:01 PM PDT 24
Finished Jun 05 04:10:07 PM PDT 24
Peak memory 207936 kb
Host smart-b06105af-a2ec-4055-a808-82178f7be807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986539643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2986539643
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2936417344
Short name T126
Test name
Test status
Simulation time 135963773 ps
CPU time 3.79 seconds
Started Jun 05 04:10:11 PM PDT 24
Finished Jun 05 04:10:15 PM PDT 24
Peak memory 209192 kb
Host smart-5ab19c34-e309-4f68-87fa-edce0f217bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936417344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2936417344
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3724421984
Short name T174
Test name
Test status
Simulation time 99829881 ps
CPU time 3.5 seconds
Started Jun 05 04:10:11 PM PDT 24
Finished Jun 05 04:10:16 PM PDT 24
Peak memory 210288 kb
Host smart-92a6a14c-5d45-464e-a42e-bc9a32de2b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724421984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3724421984
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1684563546
Short name T434
Test name
Test status
Simulation time 61776224 ps
CPU time 0.94 seconds
Started Jun 05 04:10:13 PM PDT 24
Finished Jun 05 04:10:15 PM PDT 24
Peak memory 206016 kb
Host smart-6a8c0629-31f5-4e80-9cc3-05b314cb5f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684563546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1684563546
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2892323248
Short name T29
Test name
Test status
Simulation time 284884927 ps
CPU time 1.96 seconds
Started Jun 05 04:10:14 PM PDT 24
Finished Jun 05 04:10:17 PM PDT 24
Peak memory 221200 kb
Host smart-0a25fd0c-c007-46c7-972a-79628eb304d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892323248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2892323248
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.943376185
Short name T609
Test name
Test status
Simulation time 62674521 ps
CPU time 1.48 seconds
Started Jun 05 04:10:18 PM PDT 24
Finished Jun 05 04:10:21 PM PDT 24
Peak memory 206880 kb
Host smart-409b58c4-0bb2-49d3-9810-06b1274cc3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943376185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.943376185
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.4047260621
Short name T731
Test name
Test status
Simulation time 121343948 ps
CPU time 1.94 seconds
Started Jun 05 04:10:11 PM PDT 24
Finished Jun 05 04:10:14 PM PDT 24
Peak memory 214360 kb
Host smart-b2eb9ec9-2745-48a0-a76e-d436774bb06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047260621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.4047260621
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3987064579
Short name T294
Test name
Test status
Simulation time 76707402 ps
CPU time 2.12 seconds
Started Jun 05 04:10:13 PM PDT 24
Finished Jun 05 04:10:16 PM PDT 24
Peak memory 214272 kb
Host smart-22fa3b24-b223-4530-858f-3ff68517e82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987064579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3987064579
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.244814861
Short name T742
Test name
Test status
Simulation time 342665656 ps
CPU time 3.5 seconds
Started Jun 05 04:10:13 PM PDT 24
Finished Jun 05 04:10:18 PM PDT 24
Peak memory 214400 kb
Host smart-102a7cde-dca2-4481-b48a-ecd0cce78911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244814861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.244814861
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.852073400
Short name T302
Test name
Test status
Simulation time 278944787 ps
CPU time 4.9 seconds
Started Jun 05 04:10:13 PM PDT 24
Finished Jun 05 04:10:19 PM PDT 24
Peak memory 222392 kb
Host smart-eaa605b4-46bf-4b42-9413-bdbe357c5ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852073400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.852073400
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3012595931
Short name T502
Test name
Test status
Simulation time 423456837 ps
CPU time 2.73 seconds
Started Jun 05 04:10:19 PM PDT 24
Finished Jun 05 04:10:22 PM PDT 24
Peak memory 207024 kb
Host smart-e2f26083-14ea-4ca5-9dec-a5bdf4422457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012595931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3012595931
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2744690445
Short name T468
Test name
Test status
Simulation time 717111643 ps
CPU time 5.66 seconds
Started Jun 05 04:10:10 PM PDT 24
Finished Jun 05 04:10:17 PM PDT 24
Peak memory 208632 kb
Host smart-893ce207-550d-43b5-83d3-5da5a1381fcd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744690445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2744690445
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.403977781
Short name T856
Test name
Test status
Simulation time 101653847 ps
CPU time 3.06 seconds
Started Jun 05 04:10:11 PM PDT 24
Finished Jun 05 04:10:15 PM PDT 24
Peak memory 207024 kb
Host smart-c28406b3-f055-4951-b784-8f80402d71c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403977781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.403977781
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.949546984
Short name T786
Test name
Test status
Simulation time 423949893 ps
CPU time 5.37 seconds
Started Jun 05 04:10:08 PM PDT 24
Finished Jun 05 04:10:14 PM PDT 24
Peak memory 208128 kb
Host smart-af55c565-a06c-474c-8b39-6a2304817520
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949546984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.949546984
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.707332717
Short name T886
Test name
Test status
Simulation time 211105412 ps
CPU time 2.54 seconds
Started Jun 05 04:10:12 PM PDT 24
Finished Jun 05 04:10:15 PM PDT 24
Peak memory 209916 kb
Host smart-291db199-8158-420b-9482-bfbee413a15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707332717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.707332717
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.800247191
Short name T425
Test name
Test status
Simulation time 221251016 ps
CPU time 2.21 seconds
Started Jun 05 04:10:12 PM PDT 24
Finished Jun 05 04:10:15 PM PDT 24
Peak memory 206720 kb
Host smart-aa07e47c-b5f9-45a4-9aca-933f19ffde61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800247191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.800247191
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.824281780
Short name T550
Test name
Test status
Simulation time 179062087 ps
CPU time 4.5 seconds
Started Jun 05 04:10:12 PM PDT 24
Finished Jun 05 04:10:17 PM PDT 24
Peak memory 209256 kb
Host smart-9e8404f6-a94e-40e4-82e7-c750bcd849f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824281780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.824281780
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.738030106
Short name T375
Test name
Test status
Simulation time 352906898 ps
CPU time 3.3 seconds
Started Jun 05 04:10:14 PM PDT 24
Finished Jun 05 04:10:18 PM PDT 24
Peak memory 209908 kb
Host smart-2b76a5cc-bf4b-4cb5-8764-0641d4d6bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738030106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.738030106
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.971616238
Short name T680
Test name
Test status
Simulation time 12233030 ps
CPU time 0.94 seconds
Started Jun 05 04:10:12 PM PDT 24
Finished Jun 05 04:10:14 PM PDT 24
Peak memory 205924 kb
Host smart-a785ca4a-00d0-4b62-a1bd-b4314ad37ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971616238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.971616238
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3125124327
Short name T289
Test name
Test status
Simulation time 2213470754 ps
CPU time 61.29 seconds
Started Jun 05 04:10:10 PM PDT 24
Finished Jun 05 04:11:12 PM PDT 24
Peak memory 215700 kb
Host smart-f5ba3b79-2372-4bc1-905b-67d9fee19246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125124327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3125124327
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.540866358
Short name T916
Test name
Test status
Simulation time 125221024 ps
CPU time 5.27 seconds
Started Jun 05 04:10:12 PM PDT 24
Finished Jun 05 04:10:18 PM PDT 24
Peak memory 209684 kb
Host smart-2ef25b0a-810a-40db-93b5-1f2697e725aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540866358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.540866358
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3969231679
Short name T321
Test name
Test status
Simulation time 70470969 ps
CPU time 1.73 seconds
Started Jun 05 04:10:10 PM PDT 24
Finished Jun 05 04:10:12 PM PDT 24
Peak memory 214248 kb
Host smart-883fccd6-f089-4288-98b8-d7cc866acd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969231679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3969231679
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2044585982
Short name T597
Test name
Test status
Simulation time 573791274 ps
CPU time 6.64 seconds
Started Jun 05 04:10:11 PM PDT 24
Finished Jun 05 04:10:19 PM PDT 24
Peak memory 222344 kb
Host smart-dcbb32e4-7aa2-4a51-bfdc-5a5f0e5170f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044585982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2044585982
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1753092562
Short name T339
Test name
Test status
Simulation time 80056485 ps
CPU time 3.93 seconds
Started Jun 05 04:10:18 PM PDT 24
Finished Jun 05 04:10:23 PM PDT 24
Peak memory 209752 kb
Host smart-230ed531-795b-4e14-97fe-3f9df53a6b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753092562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1753092562
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1931168341
Short name T194
Test name
Test status
Simulation time 263629047 ps
CPU time 3.24 seconds
Started Jun 05 04:10:11 PM PDT 24
Finished Jun 05 04:10:15 PM PDT 24
Peak memory 208500 kb
Host smart-1f11ce75-4405-4200-bfa1-69bd77adef69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931168341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1931168341
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2147210589
Short name T613
Test name
Test status
Simulation time 89475365 ps
CPU time 3.25 seconds
Started Jun 05 04:10:14 PM PDT 24
Finished Jun 05 04:10:18 PM PDT 24
Peak memory 208744 kb
Host smart-97e76d12-95a9-4507-868b-67153c38ed4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147210589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2147210589
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2441870136
Short name T469
Test name
Test status
Simulation time 19828363 ps
CPU time 1.78 seconds
Started Jun 05 04:10:14 PM PDT 24
Finished Jun 05 04:10:16 PM PDT 24
Peak memory 207080 kb
Host smart-c32cd600-81a7-4c39-a3fe-76d1510a2eda
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441870136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2441870136
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3306015205
Short name T328
Test name
Test status
Simulation time 257558706 ps
CPU time 3.17 seconds
Started Jun 05 04:10:10 PM PDT 24
Finished Jun 05 04:10:14 PM PDT 24
Peak memory 206968 kb
Host smart-43687645-10f4-408c-8d74-17b647eb0f24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306015205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3306015205
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3365316777
Short name T557
Test name
Test status
Simulation time 365933686 ps
CPU time 1.92 seconds
Started Jun 05 04:10:09 PM PDT 24
Finished Jun 05 04:10:12 PM PDT 24
Peak memory 215736 kb
Host smart-45abceb0-eee8-435e-ae78-ad7e12ab65d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365316777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3365316777
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3237211908
Short name T182
Test name
Test status
Simulation time 22667231 ps
CPU time 1.82 seconds
Started Jun 05 04:10:12 PM PDT 24
Finished Jun 05 04:10:15 PM PDT 24
Peak memory 208332 kb
Host smart-7ea1ea5f-12f3-43c3-96b0-e330f9a6f44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237211908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3237211908
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3255215026
Short name T594
Test name
Test status
Simulation time 1448349606 ps
CPU time 6.02 seconds
Started Jun 05 04:10:10 PM PDT 24
Finished Jun 05 04:10:17 PM PDT 24
Peak memory 218404 kb
Host smart-95ed61d8-7d55-470c-93e9-9938f882409c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255215026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3255215026
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1660361479
Short name T500
Test name
Test status
Simulation time 47316279 ps
CPU time 0.85 seconds
Started Jun 05 04:10:19 PM PDT 24
Finished Jun 05 04:10:21 PM PDT 24
Peak memory 205936 kb
Host smart-4f706310-45b5-430f-9e24-3650cd41a094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660361479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1660361479
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1098960351
Short name T398
Test name
Test status
Simulation time 29285279 ps
CPU time 2.43 seconds
Started Jun 05 04:10:19 PM PDT 24
Finished Jun 05 04:10:23 PM PDT 24
Peak memory 214332 kb
Host smart-b444ac11-4ed8-4800-86ee-5c3e7789f687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098960351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1098960351
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2133632473
Short name T770
Test name
Test status
Simulation time 185430346 ps
CPU time 3.16 seconds
Started Jun 05 04:10:22 PM PDT 24
Finished Jun 05 04:10:26 PM PDT 24
Peak memory 217740 kb
Host smart-5b5af527-a60d-4386-bf2c-44820657fd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133632473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2133632473
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3678560980
Short name T612
Test name
Test status
Simulation time 273566482 ps
CPU time 3.45 seconds
Started Jun 05 04:10:21 PM PDT 24
Finished Jun 05 04:10:25 PM PDT 24
Peak memory 207760 kb
Host smart-e9561cbf-3597-439b-8ac9-6cdb295c4ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678560980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3678560980
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1490211190
Short name T319
Test name
Test status
Simulation time 131382569 ps
CPU time 1.74 seconds
Started Jun 05 04:10:21 PM PDT 24
Finished Jun 05 04:10:24 PM PDT 24
Peak memory 214380 kb
Host smart-8be5bf62-c8ee-4037-8ce6-db717d319a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490211190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1490211190
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3344522215
Short name T577
Test name
Test status
Simulation time 108988258 ps
CPU time 3.65 seconds
Started Jun 05 04:10:24 PM PDT 24
Finished Jun 05 04:10:28 PM PDT 24
Peak memory 214276 kb
Host smart-2ceb99b0-fa81-49fe-96e6-3b08d55bf35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344522215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3344522215
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.851548402
Short name T224
Test name
Test status
Simulation time 3382161170 ps
CPU time 8.47 seconds
Started Jun 05 04:10:20 PM PDT 24
Finished Jun 05 04:10:29 PM PDT 24
Peak memory 210768 kb
Host smart-17da49d5-7a12-46fd-8c98-7a923946b30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851548402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.851548402
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1558384245
Short name T292
Test name
Test status
Simulation time 5024325036 ps
CPU time 56.67 seconds
Started Jun 05 04:10:20 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 214412 kb
Host smart-59c5451b-7897-430a-b302-5bd21b28e893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558384245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1558384245
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1918023388
Short name T695
Test name
Test status
Simulation time 1949073321 ps
CPU time 13.47 seconds
Started Jun 05 04:10:14 PM PDT 24
Finished Jun 05 04:10:28 PM PDT 24
Peak memory 208020 kb
Host smart-2d35177c-6dae-4865-9697-4e6aefd21335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918023388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1918023388
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.822394391
Short name T815
Test name
Test status
Simulation time 1366365444 ps
CPU time 12.03 seconds
Started Jun 05 04:10:20 PM PDT 24
Finished Jun 05 04:10:33 PM PDT 24
Peak memory 208308 kb
Host smart-ad8fa91c-8db9-40b9-8b7c-e56ca4603652
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822394391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.822394391
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.76045792
Short name T563
Test name
Test status
Simulation time 240394576 ps
CPU time 2.7 seconds
Started Jun 05 04:10:22 PM PDT 24
Finished Jun 05 04:10:26 PM PDT 24
Peak memory 206860 kb
Host smart-a6e9942f-0987-418e-9392-4b3558480488
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76045792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.76045792
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.948785991
Short name T466
Test name
Test status
Simulation time 111193808 ps
CPU time 3.79 seconds
Started Jun 05 04:10:19 PM PDT 24
Finished Jun 05 04:10:24 PM PDT 24
Peak memory 209072 kb
Host smart-fa66b453-568d-4624-b46f-1f64dfa20686
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948785991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.948785991
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1572186857
Short name T269
Test name
Test status
Simulation time 2142986507 ps
CPU time 16.22 seconds
Started Jun 05 04:10:22 PM PDT 24
Finished Jun 05 04:10:39 PM PDT 24
Peak memory 214336 kb
Host smart-f5d57217-ac7d-46b2-b54d-740dea2879e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572186857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1572186857
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1169072320
Short name T125
Test name
Test status
Simulation time 19444921 ps
CPU time 1.64 seconds
Started Jun 05 04:10:19 PM PDT 24
Finished Jun 05 04:10:21 PM PDT 24
Peak memory 207016 kb
Host smart-e0010601-cf36-4c96-a1b7-6d4037d95414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169072320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1169072320
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2073273662
Short name T761
Test name
Test status
Simulation time 840862233 ps
CPU time 22.31 seconds
Started Jun 05 04:10:19 PM PDT 24
Finished Jun 05 04:10:42 PM PDT 24
Peak memory 220516 kb
Host smart-3fba521f-c66c-486d-bca5-abe491c5d71b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073273662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2073273662
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3935938009
Short name T343
Test name
Test status
Simulation time 149207506 ps
CPU time 6.44 seconds
Started Jun 05 04:10:18 PM PDT 24
Finished Jun 05 04:10:25 PM PDT 24
Peak memory 214328 kb
Host smart-fa14b377-0a64-4bc7-b037-ea29ee1034f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935938009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3935938009
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.954233165
Short name T777
Test name
Test status
Simulation time 162031700 ps
CPU time 3.09 seconds
Started Jun 05 04:10:19 PM PDT 24
Finished Jun 05 04:10:23 PM PDT 24
Peak memory 210332 kb
Host smart-f1a79193-a1d6-4b11-b686-891d09830e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954233165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.954233165
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.619142781
Short name T677
Test name
Test status
Simulation time 26606318 ps
CPU time 0.79 seconds
Started Jun 05 04:10:21 PM PDT 24
Finished Jun 05 04:10:23 PM PDT 24
Peak memory 205848 kb
Host smart-681b9af5-e982-4288-a0ac-dcf883eac6a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619142781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.619142781
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3562921726
Short name T130
Test name
Test status
Simulation time 372329645 ps
CPU time 3.93 seconds
Started Jun 05 04:10:19 PM PDT 24
Finished Jun 05 04:10:24 PM PDT 24
Peak memory 214280 kb
Host smart-cc587724-7fe8-4d9c-a000-a5df5170e82a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562921726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3562921726
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1013263423
Short name T623
Test name
Test status
Simulation time 96807693 ps
CPU time 2.84 seconds
Started Jun 05 04:10:23 PM PDT 24
Finished Jun 05 04:10:26 PM PDT 24
Peak memory 214288 kb
Host smart-f2fc64f4-6bf4-42ca-ba86-60c47810f65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013263423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1013263423
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.282331274
Short name T98
Test name
Test status
Simulation time 1495272243 ps
CPU time 3.38 seconds
Started Jun 05 04:10:20 PM PDT 24
Finished Jun 05 04:10:25 PM PDT 24
Peak memory 207556 kb
Host smart-cfaf2feb-54f3-487f-a553-a10527127004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282331274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.282331274
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1619406988
Short name T352
Test name
Test status
Simulation time 167402923 ps
CPU time 2.06 seconds
Started Jun 05 04:10:24 PM PDT 24
Finished Jun 05 04:10:27 PM PDT 24
Peak memory 214328 kb
Host smart-bc8dddff-fc09-4495-a5e5-1a2678c192b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619406988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1619406988
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.711922794
Short name T265
Test name
Test status
Simulation time 242960517 ps
CPU time 5.73 seconds
Started Jun 05 04:10:23 PM PDT 24
Finished Jun 05 04:10:29 PM PDT 24
Peak memory 222456 kb
Host smart-db8ff49b-cce4-4844-b9c2-8532251d5f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711922794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.711922794
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1217812834
Short name T834
Test name
Test status
Simulation time 157624111 ps
CPU time 3.07 seconds
Started Jun 05 04:10:20 PM PDT 24
Finished Jun 05 04:10:24 PM PDT 24
Peak memory 220476 kb
Host smart-a1d12912-5a7f-489c-b283-93f7ca70e913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217812834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1217812834
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1995886328
Short name T335
Test name
Test status
Simulation time 445848229 ps
CPU time 5.23 seconds
Started Jun 05 04:10:20 PM PDT 24
Finished Jun 05 04:10:26 PM PDT 24
Peak memory 209148 kb
Host smart-eeb15c5f-9ab5-46aa-8a89-d59e3ab1045e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995886328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1995886328
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.882080846
Short name T737
Test name
Test status
Simulation time 57208165 ps
CPU time 2.86 seconds
Started Jun 05 04:10:24 PM PDT 24
Finished Jun 05 04:10:27 PM PDT 24
Peak memory 208232 kb
Host smart-446080c8-9720-4ecd-811f-5c366237a859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882080846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.882080846
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1441825842
Short name T809
Test name
Test status
Simulation time 24874714 ps
CPU time 1.98 seconds
Started Jun 05 04:10:22 PM PDT 24
Finished Jun 05 04:10:25 PM PDT 24
Peak memory 208596 kb
Host smart-13a2d580-f050-410f-aaa0-20faa57d08f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441825842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1441825842
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1260256418
Short name T465
Test name
Test status
Simulation time 69830423 ps
CPU time 1.8 seconds
Started Jun 05 04:10:20 PM PDT 24
Finished Jun 05 04:10:23 PM PDT 24
Peak memory 206804 kb
Host smart-ce10a402-f96e-4251-9a5e-bfc5e998a793
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260256418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1260256418
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3184039504
Short name T619
Test name
Test status
Simulation time 98332782 ps
CPU time 3.93 seconds
Started Jun 05 04:10:21 PM PDT 24
Finished Jun 05 04:10:26 PM PDT 24
Peak memory 214332 kb
Host smart-09c3e9d0-7bc7-4707-94ca-ed6047fd6528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184039504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3184039504
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1174037357
Short name T198
Test name
Test status
Simulation time 215112797 ps
CPU time 2.44 seconds
Started Jun 05 04:10:19 PM PDT 24
Finished Jun 05 04:10:23 PM PDT 24
Peak memory 206808 kb
Host smart-a71ed1a6-b3c6-46d1-b5c1-7587fe37e534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174037357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1174037357
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1480721569
Short name T596
Test name
Test status
Simulation time 611123547 ps
CPU time 4.94 seconds
Started Jun 05 04:10:18 PM PDT 24
Finished Jun 05 04:10:24 PM PDT 24
Peak memory 207856 kb
Host smart-85416c0b-0c42-4a87-b22d-f3a3f3533755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480721569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1480721569
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.710714450
Short name T376
Test name
Test status
Simulation time 30217765 ps
CPU time 2.09 seconds
Started Jun 05 04:10:20 PM PDT 24
Finished Jun 05 04:10:23 PM PDT 24
Peak memory 210152 kb
Host smart-b8db5892-430c-441f-a524-641d682e8135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710714450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.710714450
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3336776399
Short name T715
Test name
Test status
Simulation time 11652552 ps
CPU time 0.77 seconds
Started Jun 05 04:10:28 PM PDT 24
Finished Jun 05 04:10:29 PM PDT 24
Peak memory 205940 kb
Host smart-622402c7-8d30-45e9-95d4-8aecf7872123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336776399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3336776399
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1657683536
Short name T263
Test name
Test status
Simulation time 175332879 ps
CPU time 9.48 seconds
Started Jun 05 04:10:35 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 214476 kb
Host smart-baf37e08-6e71-4675-a5c1-49f7a2c608dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1657683536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1657683536
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2314607535
Short name T348
Test name
Test status
Simulation time 36730694 ps
CPU time 1.73 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:34 PM PDT 24
Peak memory 218516 kb
Host smart-9c85d5b5-2211-4464-986a-5330b2110538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314607535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2314607535
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3081469129
Short name T229
Test name
Test status
Simulation time 183719481 ps
CPU time 5.28 seconds
Started Jun 05 04:10:34 PM PDT 24
Finished Jun 05 04:10:40 PM PDT 24
Peak memory 220704 kb
Host smart-56f16a00-f466-4966-b1ba-5bc5865590ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081469129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3081469129
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3061543957
Short name T296
Test name
Test status
Simulation time 139577389 ps
CPU time 3.55 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:35 PM PDT 24
Peak memory 221504 kb
Host smart-6debc18f-6d5f-44fd-b4f7-bb3a7992cc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061543957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3061543957
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.367314172
Short name T646
Test name
Test status
Simulation time 81651592 ps
CPU time 3.94 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:36 PM PDT 24
Peak memory 208432 kb
Host smart-61cbb25f-f015-4128-a84b-cf1eb1a31243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367314172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.367314172
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2611199196
Short name T429
Test name
Test status
Simulation time 475817580 ps
CPU time 5.97 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:38 PM PDT 24
Peak memory 209988 kb
Host smart-985af9f9-8eb8-452f-812d-cff09b299384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611199196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2611199196
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.4149076049
Short name T234
Test name
Test status
Simulation time 49562785 ps
CPU time 2.62 seconds
Started Jun 05 04:10:19 PM PDT 24
Finished Jun 05 04:10:23 PM PDT 24
Peak memory 208364 kb
Host smart-0cc3a92a-9281-46c2-b032-46d7627072e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149076049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.4149076049
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2096371948
Short name T471
Test name
Test status
Simulation time 8419546375 ps
CPU time 16.85 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:49 PM PDT 24
Peak memory 209060 kb
Host smart-787831d5-b655-4a45-95de-0919c9627a95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096371948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2096371948
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1848412796
Short name T532
Test name
Test status
Simulation time 141820546 ps
CPU time 4.58 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:36 PM PDT 24
Peak memory 208560 kb
Host smart-98b3416d-f320-41df-b72a-d5e179477922
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848412796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1848412796
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3563973518
Short name T889
Test name
Test status
Simulation time 336078602 ps
CPU time 3.96 seconds
Started Jun 05 04:10:29 PM PDT 24
Finished Jun 05 04:10:33 PM PDT 24
Peak memory 208864 kb
Host smart-0ad0a9c8-10d9-48b7-9f81-ae4070fa1b64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563973518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3563973518
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4156159589
Short name T508
Test name
Test status
Simulation time 80320595 ps
CPU time 3.85 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:34 PM PDT 24
Peak memory 210268 kb
Host smart-2f296253-270e-4c4e-9a2b-9ffd741a2ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156159589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4156159589
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1023791572
Short name T826
Test name
Test status
Simulation time 76614967 ps
CPU time 1.64 seconds
Started Jun 05 04:10:21 PM PDT 24
Finished Jun 05 04:10:24 PM PDT 24
Peak memory 206712 kb
Host smart-9ecdfaae-be04-4a72-abe7-4ada5e394695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023791572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1023791572
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3648696389
Short name T157
Test name
Test status
Simulation time 1949127732 ps
CPU time 18.32 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:50 PM PDT 24
Peak memory 222864 kb
Host smart-d430a19a-5267-41c4-957a-ca69dcce9163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648696389 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3648696389
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1714740029
Short name T824
Test name
Test status
Simulation time 1764974602 ps
CPU time 5.89 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:38 PM PDT 24
Peak memory 207784 kb
Host smart-9b9bab60-440f-4c5e-873f-181578031a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714740029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1714740029
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2602245127
Short name T740
Test name
Test status
Simulation time 1482690437 ps
CPU time 14.3 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:46 PM PDT 24
Peak memory 210496 kb
Host smart-f166b819-5f12-4f64-a034-e8114494c8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602245127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2602245127
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.4215420108
Short name T421
Test name
Test status
Simulation time 15250359 ps
CPU time 0.8 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:33 PM PDT 24
Peak memory 205940 kb
Host smart-b862a57d-ee9f-4913-a184-638dd11d83d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215420108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.4215420108
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1217307911
Short name T633
Test name
Test status
Simulation time 122759262 ps
CPU time 2.7 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:35 PM PDT 24
Peak memory 214320 kb
Host smart-b461f806-90c2-4e75-be7a-5f64f77ddbe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217307911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1217307911
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2335777962
Short name T32
Test name
Test status
Simulation time 125483057 ps
CPU time 4.13 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:35 PM PDT 24
Peak memory 219924 kb
Host smart-98a64fa6-bb8e-4bee-a381-f4f1080efd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335777962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2335777962
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3713318782
Short name T635
Test name
Test status
Simulation time 340801376 ps
CPU time 11.57 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 208268 kb
Host smart-213d28f8-e7ed-41a2-a36f-baf7748bb621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713318782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3713318782
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2112202614
Short name T87
Test name
Test status
Simulation time 165367271 ps
CPU time 4.22 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:34 PM PDT 24
Peak memory 209408 kb
Host smart-dd3aa3d6-1e5b-4844-866d-8d4bf4aa5793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112202614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2112202614
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1716314157
Short name T480
Test name
Test status
Simulation time 308967534 ps
CPU time 2.75 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:10:35 PM PDT 24
Peak memory 216624 kb
Host smart-8e49ce50-06d3-4756-abed-d4616a05f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716314157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1716314157
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_random.222982328
Short name T871
Test name
Test status
Simulation time 1319167186 ps
CPU time 24.47 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:10:57 PM PDT 24
Peak memory 209168 kb
Host smart-b75f5021-1487-496b-9a77-c6beff2f1df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222982328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.222982328
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3712954753
Short name T447
Test name
Test status
Simulation time 615812061 ps
CPU time 4.1 seconds
Started Jun 05 04:10:33 PM PDT 24
Finished Jun 05 04:10:38 PM PDT 24
Peak memory 208336 kb
Host smart-bfad9df2-a276-447f-980b-534fc520e58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712954753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3712954753
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1236689048
Short name T312
Test name
Test status
Simulation time 61200695 ps
CPU time 2.34 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:34 PM PDT 24
Peak memory 207004 kb
Host smart-529ab3aa-8f5b-48f8-9a3f-0ff42b5a3601
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236689048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1236689048
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3602267662
Short name T238
Test name
Test status
Simulation time 786274207 ps
CPU time 3.07 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:35 PM PDT 24
Peak memory 206996 kb
Host smart-209261b3-500d-465d-8af4-d8a3980243bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602267662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3602267662
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1269271106
Short name T615
Test name
Test status
Simulation time 2591119052 ps
CPU time 28.26 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:11:02 PM PDT 24
Peak memory 208956 kb
Host smart-cddd834a-337a-4944-b669-d8573bade684
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269271106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1269271106
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2978568632
Short name T866
Test name
Test status
Simulation time 839835234 ps
CPU time 7.71 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:10:41 PM PDT 24
Peak memory 208640 kb
Host smart-56d8297d-e412-4fb7-b32f-c735cdc167a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978568632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2978568632
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.249984814
Short name T527
Test name
Test status
Simulation time 23194500 ps
CPU time 1.83 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:10:35 PM PDT 24
Peak memory 207116 kb
Host smart-97a2461e-8bf0-4859-acf1-5d3c3b389ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249984814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.249984814
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1665372781
Short name T595
Test name
Test status
Simulation time 128259528 ps
CPU time 2.66 seconds
Started Jun 05 04:10:34 PM PDT 24
Finished Jun 05 04:10:37 PM PDT 24
Peak memory 208996 kb
Host smart-3f5f44d7-1986-4e69-817d-7166cafc9c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665372781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1665372781
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.912425348
Short name T552
Test name
Test status
Simulation time 75215945 ps
CPU time 3.03 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:34 PM PDT 24
Peak memory 209840 kb
Host smart-f71ab2e4-3420-4936-ad1b-833943d06f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912425348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.912425348
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1872308358
Short name T830
Test name
Test status
Simulation time 11623443 ps
CPU time 0.78 seconds
Started Jun 05 04:08:43 PM PDT 24
Finished Jun 05 04:08:44 PM PDT 24
Peak memory 205948 kb
Host smart-bdb035ab-2095-4d76-aee0-81fe18f6ff03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872308358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1872308358
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1080360050
Short name T22
Test name
Test status
Simulation time 117883613 ps
CPU time 5.04 seconds
Started Jun 05 04:08:40 PM PDT 24
Finished Jun 05 04:08:45 PM PDT 24
Peak memory 222528 kb
Host smart-775edeaf-2795-40e1-9129-41c47b5feac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080360050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1080360050
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1059868357
Short name T245
Test name
Test status
Simulation time 40632411 ps
CPU time 2.44 seconds
Started Jun 05 04:08:42 PM PDT 24
Finished Jun 05 04:08:45 PM PDT 24
Peak memory 214352 kb
Host smart-19813866-3448-4a04-9ba2-022e0259569d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059868357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1059868357
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.405575514
Short name T832
Test name
Test status
Simulation time 274625315 ps
CPU time 4.75 seconds
Started Jun 05 04:08:41 PM PDT 24
Finished Jun 05 04:08:46 PM PDT 24
Peak memory 208740 kb
Host smart-e5c08162-0d49-4361-8b2c-236af61a6d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405575514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.405575514
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1984627953
Short name T206
Test name
Test status
Simulation time 1513496924 ps
CPU time 4.2 seconds
Started Jun 05 04:08:41 PM PDT 24
Finished Jun 05 04:08:46 PM PDT 24
Peak memory 214360 kb
Host smart-c0484220-ba9a-4526-978a-feb106bab7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984627953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1984627953
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1055647548
Short name T794
Test name
Test status
Simulation time 113360297 ps
CPU time 2.26 seconds
Started Jun 05 04:08:40 PM PDT 24
Finished Jun 05 04:08:43 PM PDT 24
Peak memory 219276 kb
Host smart-92ae4e26-c7b1-46f0-a964-adc96f513cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055647548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1055647548
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.353877618
Short name T484
Test name
Test status
Simulation time 1006102647 ps
CPU time 22.51 seconds
Started Jun 05 04:08:47 PM PDT 24
Finished Jun 05 04:09:10 PM PDT 24
Peak memory 209272 kb
Host smart-f2553a6c-0557-4a4b-bc94-b25f2b5dd0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353877618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.353877618
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3582539457
Short name T44
Test name
Test status
Simulation time 2859339100 ps
CPU time 16.89 seconds
Started Jun 05 04:08:41 PM PDT 24
Finished Jun 05 04:08:59 PM PDT 24
Peak memory 231756 kb
Host smart-71e1f560-f875-427b-a6a2-1b5907f262b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582539457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3582539457
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2525023561
Short name T512
Test name
Test status
Simulation time 103624199 ps
CPU time 2.86 seconds
Started Jun 05 04:08:41 PM PDT 24
Finished Jun 05 04:08:44 PM PDT 24
Peak memory 206920 kb
Host smart-d180bcd4-3d91-462e-9fd5-7e4b440e7e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525023561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2525023561
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1825070713
Short name T741
Test name
Test status
Simulation time 20726763055 ps
CPU time 45.15 seconds
Started Jun 05 04:08:40 PM PDT 24
Finished Jun 05 04:09:26 PM PDT 24
Peak memory 208464 kb
Host smart-42810941-2525-4e77-bca0-f7c449dad089
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825070713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1825070713
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3533637168
Short name T703
Test name
Test status
Simulation time 471364227 ps
CPU time 11.57 seconds
Started Jun 05 04:08:45 PM PDT 24
Finished Jun 05 04:08:58 PM PDT 24
Peak memory 208072 kb
Host smart-f3ff978a-aaf9-48d7-9576-a1a459882c4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533637168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3533637168
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.567741025
Short name T207
Test name
Test status
Simulation time 894180042 ps
CPU time 4.79 seconds
Started Jun 05 04:08:48 PM PDT 24
Finished Jun 05 04:08:53 PM PDT 24
Peak memory 206820 kb
Host smart-b61ae7a7-4ceb-4d86-aded-76a1845e9a7b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567741025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.567741025
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1169137788
Short name T638
Test name
Test status
Simulation time 501293378 ps
CPU time 3.16 seconds
Started Jun 05 04:08:41 PM PDT 24
Finished Jun 05 04:08:45 PM PDT 24
Peak memory 218228 kb
Host smart-a65dea84-3b90-4352-9611-d11b0bf92407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169137788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1169137788
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1426650359
Short name T878
Test name
Test status
Simulation time 105129601 ps
CPU time 2.86 seconds
Started Jun 05 04:08:40 PM PDT 24
Finished Jun 05 04:08:43 PM PDT 24
Peak memory 208444 kb
Host smart-6a9e4cd9-08c7-4d36-bb38-a3d4af6aab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426650359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1426650359
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1011324092
Short name T188
Test name
Test status
Simulation time 644942823 ps
CPU time 23.48 seconds
Started Jun 05 04:08:41 PM PDT 24
Finished Jun 05 04:09:05 PM PDT 24
Peak memory 222412 kb
Host smart-3bd38f40-7c90-493d-8f10-18b25a33a9b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011324092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1011324092
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1554601883
Short name T274
Test name
Test status
Simulation time 1724329311 ps
CPU time 52.35 seconds
Started Jun 05 04:08:40 PM PDT 24
Finished Jun 05 04:09:33 PM PDT 24
Peak memory 214296 kb
Host smart-23e1c6e1-5897-4c73-a5ad-255054504271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554601883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1554601883
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1514263214
Short name T586
Test name
Test status
Simulation time 125623087 ps
CPU time 2.31 seconds
Started Jun 05 04:08:48 PM PDT 24
Finished Jun 05 04:08:51 PM PDT 24
Peak memory 210572 kb
Host smart-becf955a-14ae-4313-90e2-3130e6a8f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514263214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1514263214
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2572473189
Short name T616
Test name
Test status
Simulation time 14361237 ps
CPU time 0.8 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:10:33 PM PDT 24
Peak memory 205960 kb
Host smart-c72a5e77-77e3-43ec-9456-dbd11eeb2f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572473189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2572473189
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1011072354
Short name T403
Test name
Test status
Simulation time 109428404 ps
CPU time 5.95 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:37 PM PDT 24
Peak memory 215112 kb
Host smart-ff6e77af-feb6-4dd5-b407-2a20f1762a6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011072354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1011072354
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4206894288
Short name T35
Test name
Test status
Simulation time 458310899 ps
CPU time 3.49 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:10:36 PM PDT 24
Peak memory 219184 kb
Host smart-22e67c2a-16be-44a3-aee7-e85fe902f256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206894288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4206894288
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.71903023
Short name T268
Test name
Test status
Simulation time 665510919 ps
CPU time 3.21 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:34 PM PDT 24
Peak memory 218188 kb
Host smart-180bdbc2-07ba-454b-964f-9ea58a47edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71903023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.71903023
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2321130201
Short name T299
Test name
Test status
Simulation time 84289792 ps
CPU time 3.69 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:35 PM PDT 24
Peak memory 215384 kb
Host smart-5412e7f0-8c51-4ff1-aae6-4fed5ce17c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321130201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2321130201
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2136202369
Short name T636
Test name
Test status
Simulation time 128003353 ps
CPU time 3.56 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:34 PM PDT 24
Peak memory 220308 kb
Host smart-2991d117-de40-4232-ae37-09dea87f46ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136202369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2136202369
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2935624519
Short name T307
Test name
Test status
Simulation time 933519740 ps
CPU time 23.53 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:56 PM PDT 24
Peak memory 209732 kb
Host smart-6d822c6c-8336-441c-b6a9-3b596bf4a813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935624519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2935624519
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1978702271
Short name T298
Test name
Test status
Simulation time 129706902 ps
CPU time 2.5 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:33 PM PDT 24
Peak memory 208432 kb
Host smart-16110da4-1f60-49de-a7e4-94469c543491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978702271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1978702271
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1968926444
Short name T587
Test name
Test status
Simulation time 107364147 ps
CPU time 3.52 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:10:37 PM PDT 24
Peak memory 208652 kb
Host smart-9fcccfcb-0c0c-4260-b41c-3af249504423
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968926444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1968926444
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1040605598
Short name T384
Test name
Test status
Simulation time 61406382 ps
CPU time 2.24 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:34 PM PDT 24
Peak memory 206784 kb
Host smart-fba1b76a-72bb-4de7-aa6f-c1313788ac97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040605598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1040605598
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2746594780
Short name T853
Test name
Test status
Simulation time 108864803 ps
CPU time 3.65 seconds
Started Jun 05 04:10:34 PM PDT 24
Finished Jun 05 04:10:38 PM PDT 24
Peak memory 208308 kb
Host smart-66c5feff-bc7b-4781-9dc3-f30d319a4bd4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746594780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2746594780
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.52277707
Short name T536
Test name
Test status
Simulation time 313364511 ps
CPU time 3.7 seconds
Started Jun 05 04:10:33 PM PDT 24
Finished Jun 05 04:10:38 PM PDT 24
Peak memory 214260 kb
Host smart-299d5bd5-119b-4fac-a6cd-8a9b12a8617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52277707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.52277707
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1915965518
Short name T567
Test name
Test status
Simulation time 172112252 ps
CPU time 4.23 seconds
Started Jun 05 04:10:30 PM PDT 24
Finished Jun 05 04:10:36 PM PDT 24
Peak memory 208540 kb
Host smart-794d14fe-c566-4449-a7b7-8aa2c919be6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915965518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1915965518
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.804875092
Short name T54
Test name
Test status
Simulation time 1023505131 ps
CPU time 21.93 seconds
Started Jun 05 04:10:32 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 222060 kb
Host smart-d3b76507-a8fb-410f-9f03-99611aedd6d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804875092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.804875092
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1281283588
Short name T47
Test name
Test status
Simulation time 1069252243 ps
CPU time 6.88 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:39 PM PDT 24
Peak memory 222632 kb
Host smart-1a9adad6-4f6c-4c4c-ac24-edded020f2fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281283588 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1281283588
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2498737922
Short name T606
Test name
Test status
Simulation time 132627190 ps
CPU time 4.83 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:37 PM PDT 24
Peak memory 209708 kb
Host smart-858162a0-cd75-44d8-9280-712da88b5517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498737922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2498737922
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.500711873
Short name T479
Test name
Test status
Simulation time 208706446 ps
CPU time 1.96 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:34 PM PDT 24
Peak memory 214396 kb
Host smart-8b9a828f-ff90-4d99-8cee-ef28b6622388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500711873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.500711873
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1062371330
Short name T442
Test name
Test status
Simulation time 17677965 ps
CPU time 0.82 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:52 PM PDT 24
Peak memory 205864 kb
Host smart-5e350f98-27c9-43d8-beef-2eae8f2cd9c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062371330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1062371330
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2656013767
Short name T354
Test name
Test status
Simulation time 53382229 ps
CPU time 3.86 seconds
Started Jun 05 04:10:39 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 215652 kb
Host smart-985e6fba-6594-4a48-8799-b50374664746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656013767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2656013767
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2432147301
Short name T516
Test name
Test status
Simulation time 163582398 ps
CPU time 1.83 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:10:44 PM PDT 24
Peak memory 221584 kb
Host smart-dc30c7f6-775a-4e2f-a9f2-2d914b98a18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432147301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2432147301
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1721316218
Short name T70
Test name
Test status
Simulation time 297332783 ps
CPU time 3.04 seconds
Started Jun 05 04:10:39 PM PDT 24
Finished Jun 05 04:10:44 PM PDT 24
Peak memory 207928 kb
Host smart-f824aaf2-e77c-4427-8ead-060d33d74d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721316218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1721316218
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3853205834
Short name T702
Test name
Test status
Simulation time 433329693 ps
CPU time 3.16 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 214176 kb
Host smart-37cdcb68-626c-46c2-94ed-8f6e614c0a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853205834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3853205834
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1132840666
Short name T915
Test name
Test status
Simulation time 79972286 ps
CPU time 3.6 seconds
Started Jun 05 04:10:39 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 209292 kb
Host smart-2a7c85b4-8d3f-468d-9b7a-1dc559b4b796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132840666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1132840666
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4023369254
Short name T124
Test name
Test status
Simulation time 1362665686 ps
CPU time 4.96 seconds
Started Jun 05 04:10:53 PM PDT 24
Finished Jun 05 04:10:59 PM PDT 24
Peak memory 208384 kb
Host smart-5ea32252-e83e-4b27-a60f-4870fcb924dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023369254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4023369254
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1839022687
Short name T524
Test name
Test status
Simulation time 178146322 ps
CPU time 3.36 seconds
Started Jun 05 04:10:35 PM PDT 24
Finished Jun 05 04:10:39 PM PDT 24
Peak memory 208400 kb
Host smart-f4c7c1a2-6a1a-441d-9afd-81850afe6144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839022687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1839022687
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3613720721
Short name T653
Test name
Test status
Simulation time 688360845 ps
CPU time 4.65 seconds
Started Jun 05 04:10:35 PM PDT 24
Finished Jun 05 04:10:40 PM PDT 24
Peak memory 208368 kb
Host smart-178a3d1b-9507-44c7-a66f-ddc993a0e1ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613720721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3613720721
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2510814369
Short name T286
Test name
Test status
Simulation time 469633820 ps
CPU time 7.32 seconds
Started Jun 05 04:10:35 PM PDT 24
Finished Jun 05 04:10:43 PM PDT 24
Peak memory 208564 kb
Host smart-e7c40f0d-14ca-40e3-8095-6c69998f9c94
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510814369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2510814369
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3288035511
Short name T617
Test name
Test status
Simulation time 331613296 ps
CPU time 4.17 seconds
Started Jun 05 04:10:31 PM PDT 24
Finished Jun 05 04:10:36 PM PDT 24
Peak memory 208928 kb
Host smart-0b26e629-b671-460c-b88b-7824694913bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288035511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3288035511
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.296465382
Short name T310
Test name
Test status
Simulation time 125234015 ps
CPU time 4.79 seconds
Started Jun 05 04:10:39 PM PDT 24
Finished Jun 05 04:10:46 PM PDT 24
Peak memory 208984 kb
Host smart-6328ccef-f2ba-45b5-8261-ed105872444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296465382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.296465382
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.4219675623
Short name T414
Test name
Test status
Simulation time 332472748 ps
CPU time 3.84 seconds
Started Jun 05 04:10:33 PM PDT 24
Finished Jun 05 04:10:38 PM PDT 24
Peak memory 206904 kb
Host smart-b6c5ee51-e3a4-4d8c-98d6-f8c25ef80907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219675623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.4219675623
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.401093128
Short name T181
Test name
Test status
Simulation time 2682977551 ps
CPU time 23.77 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:11:15 PM PDT 24
Peak memory 222688 kb
Host smart-0ce9f182-4f9f-4e72-a5a0-2b5273bf4ab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401093128 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.401093128
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1479735991
Short name T580
Test name
Test status
Simulation time 262432145 ps
CPU time 7.16 seconds
Started Jun 05 04:10:39 PM PDT 24
Finished Jun 05 04:10:48 PM PDT 24
Peak memory 208584 kb
Host smart-ce3e9991-0043-4be9-a8de-7bb2d33a603f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479735991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1479735991
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.438717953
Short name T41
Test name
Test status
Simulation time 37984473 ps
CPU time 2.09 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 210032 kb
Host smart-a026cf04-6079-4562-b2f2-e6d6cae248c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438717953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.438717953
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.94690274
Short name T882
Test name
Test status
Simulation time 21640833 ps
CPU time 0.78 seconds
Started Jun 05 04:10:43 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 205864 kb
Host smart-ce975960-21e3-44e7-8cb9-f649d3088b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94690274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.94690274
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1312782874
Short name T132
Test name
Test status
Simulation time 36892156 ps
CPU time 2.82 seconds
Started Jun 05 04:10:44 PM PDT 24
Finished Jun 05 04:10:48 PM PDT 24
Peak memory 214240 kb
Host smart-1169a849-fc84-4f37-aa77-a0a1c4ab4801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312782874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1312782874
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2413126636
Short name T470
Test name
Test status
Simulation time 125615990 ps
CPU time 2.27 seconds
Started Jun 05 04:10:39 PM PDT 24
Finished Jun 05 04:10:43 PM PDT 24
Peak memory 221376 kb
Host smart-66e36223-b908-4435-80f5-69b2f12986de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413126636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2413126636
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2109743760
Short name T909
Test name
Test status
Simulation time 168616838 ps
CPU time 2.83 seconds
Started Jun 05 04:10:41 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 209796 kb
Host smart-9d7a5030-c2ee-4176-9439-9ad63b377867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109743760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2109743760
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3551576777
Short name T893
Test name
Test status
Simulation time 31938005 ps
CPU time 2.3 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:10:44 PM PDT 24
Peak memory 214336 kb
Host smart-c7bf582e-7df7-4d0f-bc91-534c48f66ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551576777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3551576777
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1737754989
Short name T295
Test name
Test status
Simulation time 151844474 ps
CPU time 4.95 seconds
Started Jun 05 04:10:53 PM PDT 24
Finished Jun 05 04:10:59 PM PDT 24
Peak memory 221576 kb
Host smart-1f92ca68-1ff5-49e6-87e5-3cfcda43dc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737754989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1737754989
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.85777252
Short name T526
Test name
Test status
Simulation time 295999066 ps
CPU time 3.12 seconds
Started Jun 05 04:10:53 PM PDT 24
Finished Jun 05 04:10:57 PM PDT 24
Peak memory 220212 kb
Host smart-3fd80078-ddbb-4d00-bb14-c3a1ad0b67d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85777252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.85777252
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4043425267
Short name T867
Test name
Test status
Simulation time 120706418 ps
CPU time 4.82 seconds
Started Jun 05 04:10:38 PM PDT 24
Finished Jun 05 04:10:44 PM PDT 24
Peak memory 209260 kb
Host smart-2fd5a1b0-1778-4634-b719-37a2e707b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043425267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4043425267
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1896901237
Short name T360
Test name
Test status
Simulation time 314636817 ps
CPU time 2.74 seconds
Started Jun 05 04:10:42 PM PDT 24
Finished Jun 05 04:10:46 PM PDT 24
Peak memory 206776 kb
Host smart-571511fe-549c-4ac9-b2f2-7534ff80ac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896901237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1896901237
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2106916559
Short name T560
Test name
Test status
Simulation time 125892141 ps
CPU time 4.49 seconds
Started Jun 05 04:10:38 PM PDT 24
Finished Jun 05 04:10:44 PM PDT 24
Peak memory 206976 kb
Host smart-80a3dd2c-a8c8-4e6f-b22c-7813092b231b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106916559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2106916559
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.4117018575
Short name T452
Test name
Test status
Simulation time 111453155 ps
CPU time 4.11 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:10:46 PM PDT 24
Peak memory 206820 kb
Host smart-d05599c9-64ae-4220-b70f-0d53cb9835c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117018575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.4117018575
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2884468021
Short name T391
Test name
Test status
Simulation time 1195864948 ps
CPU time 36.85 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 208452 kb
Host smart-fbc9adaa-de93-4c03-b532-d075f94dcc1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884468021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2884468021
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3059015253
Short name T833
Test name
Test status
Simulation time 371041469 ps
CPU time 3.16 seconds
Started Jun 05 04:10:41 PM PDT 24
Finished Jun 05 04:10:46 PM PDT 24
Peak memory 214304 kb
Host smart-f36ab4b2-a38f-4e81-9390-5e686d3075b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059015253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3059015253
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.75247418
Short name T18
Test name
Test status
Simulation time 122234105 ps
CPU time 3.07 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 208416 kb
Host smart-e6e33ab0-fd06-4a87-8616-31ab214484a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75247418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.75247418
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3510862220
Short name T793
Test name
Test status
Simulation time 3536132007 ps
CPU time 14.4 seconds
Started Jun 05 04:10:43 PM PDT 24
Finished Jun 05 04:10:59 PM PDT 24
Peak memory 216416 kb
Host smart-aee228e8-5ccd-4970-b0c3-d45574c99ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510862220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3510862220
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.442670794
Short name T817
Test name
Test status
Simulation time 517520852 ps
CPU time 4.74 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:10:46 PM PDT 24
Peak memory 207676 kb
Host smart-5505f7a1-1ac5-430a-aa84-cefa7661fafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442670794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.442670794
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2930881250
Short name T620
Test name
Test status
Simulation time 81178725 ps
CPU time 2.89 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 210888 kb
Host smart-b6b85258-113d-44f0-a3a4-e1eb1a2b5019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930881250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2930881250
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3004262363
Short name T410
Test name
Test status
Simulation time 45527261 ps
CPU time 0.69 seconds
Started Jun 05 04:10:37 PM PDT 24
Finished Jun 05 04:10:38 PM PDT 24
Peak memory 205928 kb
Host smart-fde14386-fa29-4ebc-a170-cb3da9af4cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004262363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3004262363
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1220019639
Short name T239
Test name
Test status
Simulation time 313534591 ps
CPU time 9.06 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:10:50 PM PDT 24
Peak memory 215368 kb
Host smart-b1c7123a-61e2-492d-be9b-4c0e8d46acff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220019639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1220019639
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1402434181
Short name T9
Test name
Test status
Simulation time 430593527 ps
CPU time 4.81 seconds
Started Jun 05 04:10:52 PM PDT 24
Finished Jun 05 04:10:58 PM PDT 24
Peak memory 210696 kb
Host smart-d78999ba-5639-4154-ad2c-83ee05f29e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402434181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1402434181
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1522313792
Short name T428
Test name
Test status
Simulation time 233775647 ps
CPU time 1.71 seconds
Started Jun 05 04:10:43 PM PDT 24
Finished Jun 05 04:10:46 PM PDT 24
Peak memory 214052 kb
Host smart-d6a7b8a6-bde3-4c97-b447-bccce91a6941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522313792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1522313792
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.619739265
Short name T90
Test name
Test status
Simulation time 902514145 ps
CPU time 6.7 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:57 PM PDT 24
Peak memory 209624 kb
Host smart-9c4e4b18-d614-469f-bbb4-c52c72c34f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619739265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.619739265
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1973556465
Short name T692
Test name
Test status
Simulation time 39745308 ps
CPU time 2.23 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:10:44 PM PDT 24
Peak memory 214264 kb
Host smart-e73cf2ff-a269-461f-8114-ec1d47ada0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973556465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1973556465
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4115667632
Short name T771
Test name
Test status
Simulation time 146564161 ps
CPU time 4.55 seconds
Started Jun 05 04:10:39 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 209244 kb
Host smart-801e7d1f-b86d-4a46-ac71-e2166cdfee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115667632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4115667632
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2589595165
Short name T478
Test name
Test status
Simulation time 992818054 ps
CPU time 25.14 seconds
Started Jun 05 04:10:43 PM PDT 24
Finished Jun 05 04:11:10 PM PDT 24
Peak memory 208216 kb
Host smart-97af85df-7fc9-4a11-adc5-79f290f0d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589595165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2589595165
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1798593188
Short name T283
Test name
Test status
Simulation time 188338596 ps
CPU time 4.49 seconds
Started Jun 05 04:10:36 PM PDT 24
Finished Jun 05 04:10:42 PM PDT 24
Peak memory 209060 kb
Host smart-7c821bc4-5a9b-4807-8e09-18902f0cffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798593188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1798593188
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1268429702
Short name T522
Test name
Test status
Simulation time 740664763 ps
CPU time 5.14 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:10:47 PM PDT 24
Peak memory 208592 kb
Host smart-59cb64e8-a8d3-4274-bac2-761519d46c0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268429702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1268429702
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1380024403
Short name T558
Test name
Test status
Simulation time 116792066 ps
CPU time 3.14 seconds
Started Jun 05 04:10:42 PM PDT 24
Finished Jun 05 04:10:46 PM PDT 24
Peak memory 208392 kb
Host smart-bcfce59c-1d06-4eaf-8d84-155143afc7a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380024403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1380024403
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2384604242
Short name T691
Test name
Test status
Simulation time 504417931 ps
CPU time 4.52 seconds
Started Jun 05 04:10:41 PM PDT 24
Finished Jun 05 04:10:47 PM PDT 24
Peak memory 208532 kb
Host smart-b835ed57-14a5-43a0-915e-cec54adb3fbe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384604242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2384604242
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.859025965
Short name T505
Test name
Test status
Simulation time 46577805 ps
CPU time 2.91 seconds
Started Jun 05 04:10:39 PM PDT 24
Finished Jun 05 04:10:44 PM PDT 24
Peak memory 218408 kb
Host smart-9b0dc3f5-7c0b-4049-b6cc-8d57f3dbe319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859025965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.859025965
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2309179404
Short name T884
Test name
Test status
Simulation time 518422331 ps
CPU time 3.51 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 207536 kb
Host smart-e89143e4-4c1a-4a85-9115-85c115e96fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309179404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2309179404
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2902043301
Short name T591
Test name
Test status
Simulation time 2003644194 ps
CPU time 49.32 seconds
Started Jun 05 04:10:40 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 216244 kb
Host smart-97ffd029-b760-433a-90b3-f4358b60cf2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902043301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2902043301
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3377614420
Short name T371
Test name
Test status
Simulation time 447983160 ps
CPU time 11.8 seconds
Started Jun 05 04:10:53 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 208116 kb
Host smart-d622e42b-d370-40fe-a7da-7408e591faf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377614420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3377614420
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.82889502
Short name T838
Test name
Test status
Simulation time 87127055 ps
CPU time 0.88 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:51 PM PDT 24
Peak memory 205948 kb
Host smart-af972147-b887-45b9-bdf3-d4037145a386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82889502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.82889502
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1599275819
Short name T655
Test name
Test status
Simulation time 585344723 ps
CPU time 1.64 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:10:54 PM PDT 24
Peak memory 216340 kb
Host smart-6b421144-da4e-4146-b594-a850c62e8e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599275819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1599275819
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3330378921
Short name T869
Test name
Test status
Simulation time 516750427 ps
CPU time 3.16 seconds
Started Jun 05 04:10:48 PM PDT 24
Finished Jun 05 04:10:52 PM PDT 24
Peak memory 207412 kb
Host smart-22a9ea56-a0ae-4e20-9907-269ec6f7ab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330378921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3330378921
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.72615992
Short name T693
Test name
Test status
Simulation time 241072703 ps
CPU time 8.28 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:11:00 PM PDT 24
Peak memory 214504 kb
Host smart-01ff910b-9075-4071-bb13-3b5a903a7b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72615992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.72615992
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2902938152
Short name T485
Test name
Test status
Simulation time 112859203 ps
CPU time 3.59 seconds
Started Jun 05 04:10:47 PM PDT 24
Finished Jun 05 04:10:51 PM PDT 24
Peak memory 220204 kb
Host smart-284dd0b4-96bf-4d91-b408-cd799d45159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902938152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2902938152
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2482248904
Short name T721
Test name
Test status
Simulation time 231222306 ps
CPU time 3.01 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 215956 kb
Host smart-1814650e-aabe-4117-80d6-08b333b813bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482248904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2482248904
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.4043658929
Short name T576
Test name
Test status
Simulation time 3582211379 ps
CPU time 24.97 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:11:16 PM PDT 24
Peak memory 208968 kb
Host smart-206c15a0-4037-4d51-b5a9-127c1a130cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043658929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.4043658929
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2222948342
Short name T190
Test name
Test status
Simulation time 1361459404 ps
CPU time 43.37 seconds
Started Jun 05 04:10:53 PM PDT 24
Finished Jun 05 04:11:37 PM PDT 24
Peak memory 209116 kb
Host smart-d3fcb259-7caa-4db0-99cb-13b1d6a1de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222948342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2222948342
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2133291112
Short name T358
Test name
Test status
Simulation time 65097379 ps
CPU time 2.92 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 208556 kb
Host smart-29d9147f-5d03-4c8c-9ef0-d2bc0b3a7bf8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133291112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2133291112
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.15864632
Short name T461
Test name
Test status
Simulation time 85316706 ps
CPU time 1.89 seconds
Started Jun 05 04:10:42 PM PDT 24
Finished Jun 05 04:10:45 PM PDT 24
Peak memory 207600 kb
Host smart-09bb22a2-f964-44b5-892c-dd3e29e0a6c4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15864632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.15864632
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1231167273
Short name T650
Test name
Test status
Simulation time 755113243 ps
CPU time 25.24 seconds
Started Jun 05 04:10:53 PM PDT 24
Finished Jun 05 04:11:19 PM PDT 24
Peak memory 209076 kb
Host smart-99f242c2-17d2-4e90-86f5-a018c163c8c6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231167273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1231167273
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2164898164
Short name T624
Test name
Test status
Simulation time 263573050 ps
CPU time 3.43 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:54 PM PDT 24
Peak memory 214352 kb
Host smart-95ab15f6-eefd-4cbc-9d71-18ddec9f016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164898164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2164898164
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3312113886
Short name T463
Test name
Test status
Simulation time 248746846 ps
CPU time 2.94 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:54 PM PDT 24
Peak memory 208652 kb
Host smart-974df367-30d9-4bf2-a0ed-5e09c72d05e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312113886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3312113886
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3870710280
Short name T813
Test name
Test status
Simulation time 729716957 ps
CPU time 6.31 seconds
Started Jun 05 04:10:48 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 214340 kb
Host smart-faacd062-fb3a-4a79-8a84-53128d053cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870710280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3870710280
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1409590470
Short name T19
Test name
Test status
Simulation time 141986858 ps
CPU time 1.91 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:52 PM PDT 24
Peak memory 210016 kb
Host smart-3df2b228-444a-465f-9d32-8c58f78f6979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409590470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1409590470
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4080639033
Short name T94
Test name
Test status
Simulation time 12043053 ps
CPU time 0.9 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 205960 kb
Host smart-3357d26b-1cb9-42fe-bf1b-be28470e587e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080639033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4080639033
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.734479174
Short name T407
Test name
Test status
Simulation time 18338550444 ps
CPU time 52.91 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:11:43 PM PDT 24
Peak memory 222540 kb
Host smart-9620d38c-b062-40c1-a786-742a6bbdfb4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734479174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.734479174
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.899776649
Short name T906
Test name
Test status
Simulation time 24990277 ps
CPU time 1.56 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:52 PM PDT 24
Peak memory 208860 kb
Host smart-f9da6bca-6ca3-4191-8e29-0c2745d81743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899776649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.899776649
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2006187232
Short name T661
Test name
Test status
Simulation time 51316077 ps
CPU time 2.9 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 214316 kb
Host smart-95f40c91-f9e0-4864-ab29-4c746954225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006187232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2006187232
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1218754326
Short name T241
Test name
Test status
Simulation time 224001676 ps
CPU time 2.25 seconds
Started Jun 05 04:10:48 PM PDT 24
Finished Jun 05 04:10:51 PM PDT 24
Peak memory 214288 kb
Host smart-a7e9e4ec-3998-44f6-8dee-e52cee2021e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218754326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1218754326
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2873661661
Short name T501
Test name
Test status
Simulation time 302681965 ps
CPU time 2.7 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:52 PM PDT 24
Peak memory 209704 kb
Host smart-b1399e6d-52fc-4b9e-9f25-f62e3032335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873661661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2873661661
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2037105626
Short name T311
Test name
Test status
Simulation time 1133302686 ps
CPU time 16.9 seconds
Started Jun 05 04:10:48 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 209284 kb
Host smart-e1858ac4-2818-4ab5-ba26-171c6be6a2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037105626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2037105626
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1632157138
Short name T582
Test name
Test status
Simulation time 467971738 ps
CPU time 3.45 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 208460 kb
Host smart-d5040e1e-3a27-4ca4-af1d-7768218c816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632157138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1632157138
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.684298867
Short name T855
Test name
Test status
Simulation time 128662256 ps
CPU time 2.51 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 206932 kb
Host smart-360e506d-5a9d-4692-99d4-6ca8b9611688
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684298867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.684298867
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1095377535
Short name T436
Test name
Test status
Simulation time 34128996 ps
CPU time 2.28 seconds
Started Jun 05 04:10:52 PM PDT 24
Finished Jun 05 04:10:56 PM PDT 24
Peak memory 208540 kb
Host smart-a30f7f9c-d864-48ed-8e4c-3aef792d927a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095377535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1095377535
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1433723958
Short name T547
Test name
Test status
Simulation time 110883495 ps
CPU time 2.65 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:10:54 PM PDT 24
Peak memory 208868 kb
Host smart-07432028-bd62-4ffe-aecc-1bd584010057
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433723958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1433723958
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2807796802
Short name T199
Test name
Test status
Simulation time 360608383 ps
CPU time 4.53 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:54 PM PDT 24
Peak memory 210072 kb
Host smart-bab4d1b1-de28-4270-828d-2267df8c720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807796802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2807796802
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3673314545
Short name T780
Test name
Test status
Simulation time 106313629 ps
CPU time 1.74 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 207420 kb
Host smart-c09fea05-c63e-4056-ac74-eb2eee934ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673314545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3673314545
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1404086361
Short name T276
Test name
Test status
Simulation time 257595990 ps
CPU time 8.19 seconds
Started Jun 05 04:10:49 PM PDT 24
Finished Jun 05 04:10:58 PM PDT 24
Peak memory 215480 kb
Host smart-9a8d6645-0d6c-4c6b-bf4d-f81a65165b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404086361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1404086361
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.560129421
Short name T326
Test name
Test status
Simulation time 559770666 ps
CPU time 3.96 seconds
Started Jun 05 04:10:52 PM PDT 24
Finished Jun 05 04:10:57 PM PDT 24
Peak memory 207716 kb
Host smart-19f45ea2-8e8b-4d59-9cc3-719db1d581ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560129421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.560129421
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3527150060
Short name T868
Test name
Test status
Simulation time 528966569 ps
CPU time 2.66 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:10:54 PM PDT 24
Peak memory 209796 kb
Host smart-d0e01a17-b3aa-45f8-92b3-24c3e8161dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527150060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3527150060
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1339091593
Short name T725
Test name
Test status
Simulation time 20426337 ps
CPU time 0.97 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:52 PM PDT 24
Peak memory 206120 kb
Host smart-e6988b17-e7b6-4f0a-84c1-49106d0c7e6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339091593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1339091593
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.389939783
Short name T357
Test name
Test status
Simulation time 219713608 ps
CPU time 4.14 seconds
Started Jun 05 04:10:48 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 215312 kb
Host smart-542e4487-5481-4d89-a0d9-a22ea007f3d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389939783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.389939783
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.68303022
Short name T645
Test name
Test status
Simulation time 50669724 ps
CPU time 1.95 seconds
Started Jun 05 04:10:52 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 208760 kb
Host smart-fb227950-f7cf-4d63-a0c0-bdb1a4ccb5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68303022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.68303022
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.396009608
Short name T899
Test name
Test status
Simulation time 69355267 ps
CPU time 2.04 seconds
Started Jun 05 04:10:52 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 213656 kb
Host smart-2c7f9354-67b5-4ebf-a56e-0d33ad1acf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396009608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.396009608
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3761292454
Short name T386
Test name
Test status
Simulation time 72898111 ps
CPU time 2.52 seconds
Started Jun 05 04:10:48 PM PDT 24
Finished Jun 05 04:10:51 PM PDT 24
Peak memory 214520 kb
Host smart-27f097e5-9135-456d-9ace-aa694f3f26cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761292454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3761292454
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1625207536
Short name T431
Test name
Test status
Simulation time 66183816 ps
CPU time 3.15 seconds
Started Jun 05 04:10:46 PM PDT 24
Finished Jun 05 04:10:50 PM PDT 24
Peak memory 207972 kb
Host smart-8114159c-f1b5-40bd-b9f7-cfbb9fe4d9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625207536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1625207536
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.920439807
Short name T666
Test name
Test status
Simulation time 1455630679 ps
CPU time 25.97 seconds
Started Jun 05 04:10:48 PM PDT 24
Finished Jun 05 04:11:15 PM PDT 24
Peak memory 209904 kb
Host smart-52534baa-bbf7-4e3a-875d-ba9c8dc234bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920439807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.920439807
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1917862441
Short name T682
Test name
Test status
Simulation time 185680177 ps
CPU time 2.93 seconds
Started Jun 05 04:10:48 PM PDT 24
Finished Jun 05 04:10:52 PM PDT 24
Peak memory 208568 kb
Host smart-012c90d8-bc8d-4fc0-9fe1-7536739b2162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917862441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1917862441
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1252985547
Short name T618
Test name
Test status
Simulation time 346000515 ps
CPU time 4.18 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:10:56 PM PDT 24
Peak memory 208532 kb
Host smart-c10afb44-9b5f-42cd-a6d1-277d0066b405
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252985547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1252985547
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1245402203
Short name T488
Test name
Test status
Simulation time 636774950 ps
CPU time 17.64 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:11:09 PM PDT 24
Peak memory 208268 kb
Host smart-d5398642-6244-4f6b-90db-c3c42374fa80
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245402203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1245402203
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2731329707
Short name T520
Test name
Test status
Simulation time 43941063 ps
CPU time 1.88 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 206888 kb
Host smart-152e7e26-4a23-4cf2-a37a-6e0a319ca350
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731329707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2731329707
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.590715091
Short name T284
Test name
Test status
Simulation time 190620065 ps
CPU time 3.5 seconds
Started Jun 05 04:10:52 PM PDT 24
Finished Jun 05 04:10:56 PM PDT 24
Peak memory 213696 kb
Host smart-c1832f16-9901-4616-a656-260756532c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590715091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.590715091
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.4180137872
Short name T727
Test name
Test status
Simulation time 32010465 ps
CPU time 2.13 seconds
Started Jun 05 04:10:48 PM PDT 24
Finished Jun 05 04:10:51 PM PDT 24
Peak memory 208428 kb
Host smart-2020e7d4-da4a-4edc-955b-6e5571f3d16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180137872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.4180137872
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3985217678
Short name T810
Test name
Test status
Simulation time 300692620 ps
CPU time 10.31 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:11:01 PM PDT 24
Peak memory 220724 kb
Host smart-6b4fc147-7f1a-4564-8c65-9601a96bbfb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985217678 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3985217678
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.34691325
Short name T607
Test name
Test status
Simulation time 824132738 ps
CPU time 6.49 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:58 PM PDT 24
Peak memory 208624 kb
Host smart-c3bdd03a-ec5d-48df-b766-0fa15d00b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34691325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.34691325
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2181675364
Short name T443
Test name
Test status
Simulation time 145654164 ps
CPU time 2.13 seconds
Started Jun 05 04:10:47 PM PDT 24
Finished Jun 05 04:10:50 PM PDT 24
Peak memory 210080 kb
Host smart-952634f1-f225-4aff-b00b-2d8e67b715fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181675364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2181675364
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2652991981
Short name T823
Test name
Test status
Simulation time 40480156 ps
CPU time 0.73 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:01 PM PDT 24
Peak memory 205968 kb
Host smart-8aa34f4d-3ec0-4de9-a8c3-19a025ac3193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652991981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2652991981
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4212377932
Short name T131
Test name
Test status
Simulation time 180430118 ps
CPU time 3.67 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 215436 kb
Host smart-a1929826-0628-45c4-b6f2-1d65b4c8be7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212377932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4212377932
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2937113144
Short name T28
Test name
Test status
Simulation time 147782412 ps
CPU time 1.26 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:00 PM PDT 24
Peak memory 207636 kb
Host smart-9fcf30e5-b291-4818-aeb6-723c843230f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937113144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2937113144
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.809733574
Short name T579
Test name
Test status
Simulation time 302369231 ps
CPU time 2.15 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 218376 kb
Host smart-a623c6f9-1336-40b2-86ae-64b08144861c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809733574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.809733574
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2791936774
Short name T89
Test name
Test status
Simulation time 239491417 ps
CPU time 3.3 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:03 PM PDT 24
Peak memory 220280 kb
Host smart-395db727-ab5b-49da-9d64-52dd0450cbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791936774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2791936774
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.40437548
Short name T561
Test name
Test status
Simulation time 283312537 ps
CPU time 2.91 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:02 PM PDT 24
Peak memory 214188 kb
Host smart-4ea98265-db85-44f6-a313-6495e841a653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40437548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.40437548
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3021197915
Short name T572
Test name
Test status
Simulation time 135548498 ps
CPU time 2.86 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:01 PM PDT 24
Peak memory 219900 kb
Host smart-2fc2b859-55da-49a8-8f1d-74948b45d87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021197915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3021197915
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1254415733
Short name T848
Test name
Test status
Simulation time 190530759 ps
CPU time 7.12 seconds
Started Jun 05 04:10:51 PM PDT 24
Finished Jun 05 04:10:59 PM PDT 24
Peak memory 207708 kb
Host smart-cc7abea9-3773-44d4-bf60-9bf7d8077fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254415733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1254415733
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2717737305
Short name T767
Test name
Test status
Simulation time 127362515 ps
CPU time 2.95 seconds
Started Jun 05 04:10:47 PM PDT 24
Finished Jun 05 04:10:51 PM PDT 24
Peak memory 207312 kb
Host smart-0d143318-3fc6-4ad5-91b9-2ecad984d71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717737305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2717737305
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3339657953
Short name T564
Test name
Test status
Simulation time 55774144 ps
CPU time 2.89 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 208040 kb
Host smart-0892d472-aa51-45be-84ec-d24aa856c04d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339657953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3339657953
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2190772968
Short name T545
Test name
Test status
Simulation time 19238990 ps
CPU time 1.82 seconds
Started Jun 05 04:10:52 PM PDT 24
Finished Jun 05 04:10:55 PM PDT 24
Peak memory 206844 kb
Host smart-66520408-4cbb-4c76-9aa0-660197bb692c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190772968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2190772968
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2025230526
Short name T514
Test name
Test status
Simulation time 733669941 ps
CPU time 9.12 seconds
Started Jun 05 04:10:52 PM PDT 24
Finished Jun 05 04:11:02 PM PDT 24
Peak memory 207072 kb
Host smart-6de01ae1-8b2d-4c21-a36f-1a78045716b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025230526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2025230526
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3598870250
Short name T879
Test name
Test status
Simulation time 171177702 ps
CPU time 2.71 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:03 PM PDT 24
Peak memory 210280 kb
Host smart-84d3ba87-7b01-4006-8320-d04ef1a77be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598870250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3598870250
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.859054640
Short name T814
Test name
Test status
Simulation time 22560314 ps
CPU time 1.74 seconds
Started Jun 05 04:10:50 PM PDT 24
Finished Jun 05 04:10:53 PM PDT 24
Peak memory 206828 kb
Host smart-2a228444-d7e3-43f2-94c3-6af041e1087d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859054640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.859054640
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.721897004
Short name T534
Test name
Test status
Simulation time 1944149465 ps
CPU time 19.26 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 222464 kb
Host smart-affb7af3-0626-4eed-a48e-e2a4a1c496c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721897004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.721897004
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.4126263312
Short name T338
Test name
Test status
Simulation time 201376369 ps
CPU time 8.43 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:08 PM PDT 24
Peak memory 222620 kb
Host smart-d507e380-20f9-4e8b-966d-3baa9f6eba02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126263312 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.4126263312
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.939070757
Short name T900
Test name
Test status
Simulation time 444545344 ps
CPU time 4.41 seconds
Started Jun 05 04:11:03 PM PDT 24
Finished Jun 05 04:11:08 PM PDT 24
Peak memory 209972 kb
Host smart-11652fcc-0679-41ba-806d-d3c15c8ea1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939070757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.939070757
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2390273290
Short name T36
Test name
Test status
Simulation time 141751727 ps
CPU time 3.73 seconds
Started Jun 05 04:11:00 PM PDT 24
Finished Jun 05 04:11:05 PM PDT 24
Peak memory 210348 kb
Host smart-75e207e9-1311-47b3-b8f2-f63fa2e56e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390273290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2390273290
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.4159224521
Short name T911
Test name
Test status
Simulation time 35341216 ps
CPU time 0.8 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:00 PM PDT 24
Peak memory 205924 kb
Host smart-42857948-ed89-420e-bff4-8a635e65ee07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159224521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4159224521
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2410788053
Short name T7
Test name
Test status
Simulation time 38428709 ps
CPU time 1.39 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:01 PM PDT 24
Peak memory 209148 kb
Host smart-67c5f7e6-016e-4acf-960f-1b13a54592a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410788053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2410788053
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3751361514
Short name T781
Test name
Test status
Simulation time 414810159 ps
CPU time 4.81 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:05 PM PDT 24
Peak memory 218284 kb
Host smart-dafbfabf-f03b-4e88-ab44-3a59d32e0018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751361514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3751361514
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.4031301896
Short name T280
Test name
Test status
Simulation time 107523532 ps
CPU time 4.81 seconds
Started Jun 05 04:11:00 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 214344 kb
Host smart-7b274857-ecbf-442a-b8d6-e63aaf68b30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031301896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4031301896
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.396856635
Short name T370
Test name
Test status
Simulation time 167634325 ps
CPU time 2.98 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:03 PM PDT 24
Peak memory 214340 kb
Host smart-a238f7a3-7d20-4fce-91a9-b18256c2b921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396856635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.396856635
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1085596614
Short name T811
Test name
Test status
Simulation time 1050283118 ps
CPU time 2.57 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:01 PM PDT 24
Peak memory 214676 kb
Host smart-97a7ca43-674f-4f4c-8121-946168660d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085596614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1085596614
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.259676534
Short name T647
Test name
Test status
Simulation time 380104083 ps
CPU time 5.1 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:05 PM PDT 24
Peak memory 208968 kb
Host smart-52f9bd9e-14cc-4e78-9fbb-a11cac275d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259676534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.259676534
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.752538213
Short name T803
Test name
Test status
Simulation time 337615776 ps
CPU time 3.23 seconds
Started Jun 05 04:11:00 PM PDT 24
Finished Jun 05 04:11:04 PM PDT 24
Peak memory 208288 kb
Host smart-725b74aa-71d5-4046-8a44-e99051e9331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752538213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.752538213
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.259781105
Short name T342
Test name
Test status
Simulation time 121314094 ps
CPU time 4.1 seconds
Started Jun 05 04:11:01 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 207120 kb
Host smart-ef17bc50-5e8a-4561-a35b-134598660897
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259781105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.259781105
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2489336025
Short name T822
Test name
Test status
Simulation time 1044528715 ps
CPU time 5.86 seconds
Started Jun 05 04:10:57 PM PDT 24
Finished Jun 05 04:11:03 PM PDT 24
Peak memory 208716 kb
Host smart-e300779e-68f2-4843-b8fc-da881d31f1e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489336025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2489336025
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3391640000
Short name T437
Test name
Test status
Simulation time 3834723625 ps
CPU time 23.94 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:24 PM PDT 24
Peak memory 207844 kb
Host smart-bcfc117d-c700-4707-8c6e-2e4e968af22d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391640000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3391640000
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.408478783
Short name T196
Test name
Test status
Simulation time 449862226 ps
CPU time 11.61 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:11 PM PDT 24
Peak memory 208712 kb
Host smart-543686e5-01ca-4a50-911f-faebd85450dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408478783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.408478783
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.4089621343
Short name T409
Test name
Test status
Simulation time 55759313 ps
CPU time 2.63 seconds
Started Jun 05 04:10:57 PM PDT 24
Finished Jun 05 04:11:00 PM PDT 24
Peak memory 207920 kb
Host smart-880a5b76-46b8-45ee-931e-d2d445cdfeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089621343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.4089621343
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2710838052
Short name T272
Test name
Test status
Simulation time 1345164466 ps
CPU time 16.41 seconds
Started Jun 05 04:11:03 PM PDT 24
Finished Jun 05 04:11:20 PM PDT 24
Peak memory 216304 kb
Host smart-2262e18c-debe-4fb5-b3b1-7a2e731e5bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710838052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2710838052
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2150918072
Short name T820
Test name
Test status
Simulation time 2564964230 ps
CPU time 5.73 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 218116 kb
Host smart-831fe60d-322d-4884-921d-3dd321e50c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150918072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2150918072
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.295670244
Short name T493
Test name
Test status
Simulation time 72228366 ps
CPU time 2.71 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:02 PM PDT 24
Peak memory 209996 kb
Host smart-7c3eca83-9926-4464-974f-5e455833ae97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295670244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.295670244
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2340560308
Short name T707
Test name
Test status
Simulation time 371155238 ps
CPU time 0.89 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:01 PM PDT 24
Peak memory 205968 kb
Host smart-11fb9b16-7e69-4ad4-abae-ff6a280f67b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340560308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2340560308
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3300152971
Short name T757
Test name
Test status
Simulation time 909998080 ps
CPU time 7.46 seconds
Started Jun 05 04:11:01 PM PDT 24
Finished Jun 05 04:11:09 PM PDT 24
Peak memory 220048 kb
Host smart-a000fd77-a0a3-4513-9105-0064d49157c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300152971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3300152971
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.34390926
Short name T349
Test name
Test status
Simulation time 84281214 ps
CPU time 1.93 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:01 PM PDT 24
Peak memory 219532 kb
Host smart-526c8e87-9cfb-4cba-8bd8-6fafb1082c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34390926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.34390926
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2874489248
Short name T369
Test name
Test status
Simulation time 181991640 ps
CPU time 4.28 seconds
Started Jun 05 04:10:57 PM PDT 24
Finished Jun 05 04:11:02 PM PDT 24
Peak memory 214336 kb
Host smart-c29d8f99-dd62-4de9-8ab8-8d817702cf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874489248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2874489248
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3552979161
Short name T639
Test name
Test status
Simulation time 379280571 ps
CPU time 3.03 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:02 PM PDT 24
Peak memory 214260 kb
Host smart-ba25f3ed-c132-4399-ab27-b9448dc553f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552979161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3552979161
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3823474383
Short name T872
Test name
Test status
Simulation time 398080584 ps
CPU time 3.71 seconds
Started Jun 05 04:11:03 PM PDT 24
Finished Jun 05 04:11:07 PM PDT 24
Peak memory 208992 kb
Host smart-fb2e4f46-8076-45a9-883e-19218dda4a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823474383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3823474383
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2374709557
Short name T799
Test name
Test status
Simulation time 92498994 ps
CPU time 4.8 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:05 PM PDT 24
Peak memory 214240 kb
Host smart-25ff5204-4a90-42b2-a868-d09ee43ee840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374709557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2374709557
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1207915932
Short name T883
Test name
Test status
Simulation time 112469155 ps
CPU time 2.39 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:02 PM PDT 24
Peak memory 206972 kb
Host smart-2994e0f1-ffd1-4413-9c54-ac710a544ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207915932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1207915932
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1464986997
Short name T874
Test name
Test status
Simulation time 174761944 ps
CPU time 2.49 seconds
Started Jun 05 04:10:57 PM PDT 24
Finished Jun 05 04:11:00 PM PDT 24
Peak memory 208544 kb
Host smart-a2ecd21f-d113-4f31-ae14-bbbf348e6e5f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464986997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1464986997
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.869102508
Short name T733
Test name
Test status
Simulation time 536917550 ps
CPU time 6.79 seconds
Started Jun 05 04:11:01 PM PDT 24
Finished Jun 05 04:11:09 PM PDT 24
Peak memory 208844 kb
Host smart-4ec66279-1bea-494e-a6fa-fcf3904be63e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869102508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.869102508
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2656281846
Short name T528
Test name
Test status
Simulation time 573865123 ps
CPU time 8 seconds
Started Jun 05 04:11:00 PM PDT 24
Finished Jun 05 04:11:09 PM PDT 24
Peak memory 208484 kb
Host smart-1e6b7080-e6b6-45ff-968b-2a1668d182c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656281846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2656281846
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1600687676
Short name T451
Test name
Test status
Simulation time 222355871 ps
CPU time 2.49 seconds
Started Jun 05 04:11:02 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 215944 kb
Host smart-15beb6d0-a9d2-41d1-a259-367767345e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600687676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1600687676
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.561746306
Short name T483
Test name
Test status
Simulation time 43339649 ps
CPU time 2.26 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:02 PM PDT 24
Peak memory 208320 kb
Host smart-76c8d311-da20-4462-9b1d-de8a87a69721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561746306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.561746306
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.305195683
Short name T568
Test name
Test status
Simulation time 7907603767 ps
CPU time 30.88 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:32 PM PDT 24
Peak memory 222700 kb
Host smart-aa7e0f07-9195-4256-8260-c63827b49951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305195683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.305195683
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.776582661
Short name T227
Test name
Test status
Simulation time 922901157 ps
CPU time 10.22 seconds
Started Jun 05 04:11:00 PM PDT 24
Finished Jun 05 04:11:11 PM PDT 24
Peak memory 220028 kb
Host smart-e3789dd8-21ac-4355-a404-399fba538ade
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776582661 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.776582661
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1453690943
Short name T601
Test name
Test status
Simulation time 51985402 ps
CPU time 3.48 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:02 PM PDT 24
Peak memory 209672 kb
Host smart-3a568085-7e97-49fc-af93-83d66637cd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453690943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1453690943
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1552372293
Short name T588
Test name
Test status
Simulation time 41341238 ps
CPU time 2.16 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:03 PM PDT 24
Peak memory 209892 kb
Host smart-c6b1b824-6014-4e6f-8843-089b22b7f04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552372293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1552372293
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1849754176
Short name T511
Test name
Test status
Simulation time 52175364 ps
CPU time 0.8 seconds
Started Jun 05 04:08:48 PM PDT 24
Finished Jun 05 04:08:50 PM PDT 24
Peak memory 205948 kb
Host smart-cc24f39c-c4ac-4edd-8e16-1bc6f90412ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849754176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1849754176
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1132762392
Short name T405
Test name
Test status
Simulation time 67877428 ps
CPU time 4.91 seconds
Started Jun 05 04:08:49 PM PDT 24
Finished Jun 05 04:08:55 PM PDT 24
Peak memory 222508 kb
Host smart-40138d4e-3812-41c4-a52c-8341d8be856e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132762392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1132762392
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.4290414990
Short name T20
Test name
Test status
Simulation time 283585839 ps
CPU time 5.57 seconds
Started Jun 05 04:08:49 PM PDT 24
Finished Jun 05 04:08:56 PM PDT 24
Peak memory 211744 kb
Host smart-33224894-fc04-4d29-8c95-37004739e644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290414990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.4290414990
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1466218639
Short name T475
Test name
Test status
Simulation time 117026181 ps
CPU time 1.82 seconds
Started Jun 05 04:08:51 PM PDT 24
Finished Jun 05 04:08:53 PM PDT 24
Peak memory 207000 kb
Host smart-884b3e97-1c5a-4705-91da-b6b47decff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466218639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1466218639
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1837403666
Short name T85
Test name
Test status
Simulation time 129377745 ps
CPU time 3.92 seconds
Started Jun 05 04:08:58 PM PDT 24
Finished Jun 05 04:09:03 PM PDT 24
Peak memory 219020 kb
Host smart-b1175143-14ce-4ff7-b342-dfb9c357b179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837403666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1837403666
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1241216029
Short name T367
Test name
Test status
Simulation time 99504466 ps
CPU time 3.25 seconds
Started Jun 05 04:08:50 PM PDT 24
Finished Jun 05 04:08:54 PM PDT 24
Peak memory 214248 kb
Host smart-f70786f3-e845-49d7-be02-5c1943da5594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241216029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1241216029
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.355898878
Short name T322
Test name
Test status
Simulation time 112225637 ps
CPU time 2.57 seconds
Started Jun 05 04:08:47 PM PDT 24
Finished Jun 05 04:08:50 PM PDT 24
Peak memory 222596 kb
Host smart-4b3c5412-ef08-439e-994a-49650ef6fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355898878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.355898878
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2491469142
Short name T744
Test name
Test status
Simulation time 1077735882 ps
CPU time 4.07 seconds
Started Jun 05 04:08:49 PM PDT 24
Finished Jun 05 04:08:53 PM PDT 24
Peak memory 210108 kb
Host smart-23ebf509-1e04-445b-8674-d5f148f483cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491469142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2491469142
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2619134000
Short name T201
Test name
Test status
Simulation time 58913281 ps
CPU time 2.25 seconds
Started Jun 05 04:08:47 PM PDT 24
Finished Jun 05 04:08:50 PM PDT 24
Peak memory 207272 kb
Host smart-e6bb65d3-6d37-4c97-9d4b-c2a20452f81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619134000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2619134000
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.206540365
Short name T549
Test name
Test status
Simulation time 253558776 ps
CPU time 2.67 seconds
Started Jun 05 04:08:56 PM PDT 24
Finished Jun 05 04:09:00 PM PDT 24
Peak memory 206876 kb
Host smart-0712474c-5d3b-4584-9552-980ac994b6d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206540365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.206540365
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1201320225
Short name T556
Test name
Test status
Simulation time 1619256961 ps
CPU time 30.94 seconds
Started Jun 05 04:08:57 PM PDT 24
Finished Jun 05 04:09:29 PM PDT 24
Peak memory 208748 kb
Host smart-c0a97e6b-0129-423c-91e4-de40e6261ca9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201320225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1201320225
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1204483030
Short name T643
Test name
Test status
Simulation time 898972280 ps
CPU time 19.14 seconds
Started Jun 05 04:08:49 PM PDT 24
Finished Jun 05 04:09:08 PM PDT 24
Peak memory 208656 kb
Host smart-8954b62e-c3b7-4f47-a5ad-a40f802f042a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204483030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1204483030
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2768186333
Short name T598
Test name
Test status
Simulation time 3180558464 ps
CPU time 23.66 seconds
Started Jun 05 04:08:48 PM PDT 24
Finished Jun 05 04:09:12 PM PDT 24
Peak memory 209808 kb
Host smart-e315d619-755b-488d-a3a0-06e25ec1b23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768186333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2768186333
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3131139131
Short name T416
Test name
Test status
Simulation time 142606728 ps
CPU time 3.87 seconds
Started Jun 05 04:08:42 PM PDT 24
Finished Jun 05 04:08:46 PM PDT 24
Peak memory 208116 kb
Host smart-4f3e7dae-ec1f-4d5b-9ec6-6b21a39606d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131139131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3131139131
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.171457746
Short name T336
Test name
Test status
Simulation time 857370145 ps
CPU time 20 seconds
Started Jun 05 04:08:49 PM PDT 24
Finished Jun 05 04:09:10 PM PDT 24
Peak memory 214348 kb
Host smart-53cba8d0-627c-4e14-9506-01cd9907b7fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171457746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.171457746
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3021233072
Short name T282
Test name
Test status
Simulation time 56935429 ps
CPU time 3.39 seconds
Started Jun 05 04:08:50 PM PDT 24
Finished Jun 05 04:08:54 PM PDT 24
Peak memory 214392 kb
Host smart-28dcb85b-538e-4699-81e2-17da9b84d06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021233072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3021233072
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3382094713
Short name T610
Test name
Test status
Simulation time 108629062 ps
CPU time 3.29 seconds
Started Jun 05 04:08:49 PM PDT 24
Finished Jun 05 04:08:53 PM PDT 24
Peak memory 210880 kb
Host smart-e42164fe-bbcc-4a7d-9ce0-7f28f0fa8f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382094713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3382094713
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1056912638
Short name T102
Test name
Test status
Simulation time 12223225 ps
CPU time 0.78 seconds
Started Jun 05 04:11:00 PM PDT 24
Finished Jun 05 04:11:02 PM PDT 24
Peak memory 205916 kb
Host smart-5c0140a9-e86e-4f40-b1cd-8fcbec3bc39e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056912638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1056912638
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3508315783
Short name T835
Test name
Test status
Simulation time 102604615 ps
CPU time 5.1 seconds
Started Jun 05 04:11:02 PM PDT 24
Finished Jun 05 04:11:08 PM PDT 24
Peak memory 214188 kb
Host smart-bd8ac300-a6c1-458c-9241-8b54b365bafd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508315783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3508315783
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2519767186
Short name T840
Test name
Test status
Simulation time 746990235 ps
CPU time 2.45 seconds
Started Jun 05 04:11:02 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 209800 kb
Host smart-8a2ddffc-5277-4b30-82de-5473aa94efb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519767186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2519767186
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3365980528
Short name T555
Test name
Test status
Simulation time 820221971 ps
CPU time 11.26 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:12 PM PDT 24
Peak memory 208428 kb
Host smart-00240e8a-dc0c-474b-8c22-89e1229a863f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365980528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3365980528
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4134737471
Short name T700
Test name
Test status
Simulation time 334684111 ps
CPU time 3.18 seconds
Started Jun 05 04:11:02 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 214384 kb
Host smart-03f6567c-146f-4749-a58c-ad9b32b4ea1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134737471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4134737471
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2652401178
Short name T652
Test name
Test status
Simulation time 249758820 ps
CPU time 3.98 seconds
Started Jun 05 04:11:03 PM PDT 24
Finished Jun 05 04:11:07 PM PDT 24
Peak memory 214340 kb
Host smart-11b131bc-b9cd-4ea9-8e5f-f0449f429368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652401178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2652401178
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.223066041
Short name T216
Test name
Test status
Simulation time 190197237 ps
CPU time 2 seconds
Started Jun 05 04:11:03 PM PDT 24
Finished Jun 05 04:11:05 PM PDT 24
Peak memory 214348 kb
Host smart-05d73736-d1ba-4739-90f6-73fe33c1c8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223066041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.223066041
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.4282032361
Short name T492
Test name
Test status
Simulation time 1459971308 ps
CPU time 32.74 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 208492 kb
Host smart-739acc14-9e0f-4bfe-8427-b8af64b6c2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282032361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.4282032361
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1016643684
Short name T831
Test name
Test status
Simulation time 59603136 ps
CPU time 2.89 seconds
Started Jun 05 04:11:03 PM PDT 24
Finished Jun 05 04:11:06 PM PDT 24
Peak memory 208692 kb
Host smart-2707ccf0-b43e-43a2-8f77-715ac40c8036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016643684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1016643684
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3769829684
Short name T894
Test name
Test status
Simulation time 458722209 ps
CPU time 5.32 seconds
Started Jun 05 04:10:58 PM PDT 24
Finished Jun 05 04:11:05 PM PDT 24
Peak memory 206916 kb
Host smart-d0023fba-771b-43b6-b5af-fea9eff8e37a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769829684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3769829684
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2881626471
Short name T683
Test name
Test status
Simulation time 605952463 ps
CPU time 5.91 seconds
Started Jun 05 04:11:00 PM PDT 24
Finished Jun 05 04:11:07 PM PDT 24
Peak memory 208144 kb
Host smart-692a8674-a594-48d9-b0fa-b174a65aba21
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881626471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2881626471
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3649597369
Short name T285
Test name
Test status
Simulation time 213171868 ps
CPU time 5.97 seconds
Started Jun 05 04:11:00 PM PDT 24
Finished Jun 05 04:11:07 PM PDT 24
Peak memory 208440 kb
Host smart-7e2a320d-47f4-4a0c-8c22-53f503a4dd1a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649597369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3649597369
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1808334162
Short name T904
Test name
Test status
Simulation time 181494037 ps
CPU time 2.22 seconds
Started Jun 05 04:11:01 PM PDT 24
Finished Jun 05 04:11:04 PM PDT 24
Peak memory 206896 kb
Host smart-508f22f5-871a-404e-b59f-f8055c2ccf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808334162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1808334162
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3287339743
Short name T847
Test name
Test status
Simulation time 500935395 ps
CPU time 2.75 seconds
Started Jun 05 04:10:59 PM PDT 24
Finished Jun 05 04:11:03 PM PDT 24
Peak memory 206804 kb
Host smart-6a8b5bdb-ca12-4fc1-94e5-ed0253259845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287339743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3287339743
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.4148023299
Short name T772
Test name
Test status
Simulation time 164660179 ps
CPU time 5.18 seconds
Started Jun 05 04:11:03 PM PDT 24
Finished Jun 05 04:11:09 PM PDT 24
Peak memory 214332 kb
Host smart-187ad0a2-e747-4877-b5fd-b8e22262a995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148023299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.4148023299
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1928527917
Short name T510
Test name
Test status
Simulation time 8747249133 ps
CPU time 83.27 seconds
Started Jun 05 04:11:03 PM PDT 24
Finished Jun 05 04:12:27 PM PDT 24
Peak memory 209256 kb
Host smart-ecf31f85-4ff0-4806-9d09-1579b42fbb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928527917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1928527917
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3064474581
Short name T175
Test name
Test status
Simulation time 47505419 ps
CPU time 1.22 seconds
Started Jun 05 04:11:01 PM PDT 24
Finished Jun 05 04:11:03 PM PDT 24
Peak memory 209632 kb
Host smart-93754549-4f8b-4646-b2bc-774025550d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064474581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3064474581
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1662535601
Short name T439
Test name
Test status
Simulation time 30651423 ps
CPU time 0.76 seconds
Started Jun 05 04:11:06 PM PDT 24
Finished Jun 05 04:11:08 PM PDT 24
Peak memory 205948 kb
Host smart-f5841745-afe0-4a08-bd69-209583569447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662535601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1662535601
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2633867772
Short name T143
Test name
Test status
Simulation time 34601742 ps
CPU time 2.5 seconds
Started Jun 05 04:11:07 PM PDT 24
Finished Jun 05 04:11:11 PM PDT 24
Peak memory 214252 kb
Host smart-b7e612cf-1605-455a-9828-df571af7c624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633867772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2633867772
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1316753108
Short name T293
Test name
Test status
Simulation time 79589444 ps
CPU time 2.16 seconds
Started Jun 05 04:11:06 PM PDT 24
Finished Jun 05 04:11:09 PM PDT 24
Peak memory 209104 kb
Host smart-1b24004e-6524-4f07-b218-2c9a460ce391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316753108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1316753108
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.255760852
Short name T27
Test name
Test status
Simulation time 100887004 ps
CPU time 4.36 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:14 PM PDT 24
Peak memory 214328 kb
Host smart-c530ed32-c71e-46fd-ad79-1a091ac925a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255760852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.255760852
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3140030137
Short name T362
Test name
Test status
Simulation time 68555283 ps
CPU time 2.68 seconds
Started Jun 05 04:11:07 PM PDT 24
Finished Jun 05 04:11:10 PM PDT 24
Peak memory 208792 kb
Host smart-ffdccad5-49b3-4aa0-b948-5bf162c20e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140030137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3140030137
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3059573244
Short name T584
Test name
Test status
Simulation time 229332739 ps
CPU time 5.25 seconds
Started Jun 05 04:11:06 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 218268 kb
Host smart-3027905d-bf88-4d7c-9906-48a61d4f35cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059573244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3059573244
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1492641391
Short name T499
Test name
Test status
Simulation time 2160715582 ps
CPU time 5.86 seconds
Started Jun 05 04:11:01 PM PDT 24
Finished Jun 05 04:11:08 PM PDT 24
Peak memory 208348 kb
Host smart-6f456c18-e88f-4e20-bc0f-cdeaf8396489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492641391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1492641391
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.4212125828
Short name T494
Test name
Test status
Simulation time 106416223 ps
CPU time 3.17 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 208576 kb
Host smart-c4a947aa-bfa8-48f7-afef-d6cd6ebccaf4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212125828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.4212125828
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2553831080
Short name T630
Test name
Test status
Simulation time 972983477 ps
CPU time 30.23 seconds
Started Jun 05 04:11:02 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 208628 kb
Host smart-1e37d672-29f3-450c-a265-8bd1de2366bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553831080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2553831080
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1193372173
Short name T873
Test name
Test status
Simulation time 36789666 ps
CPU time 2.79 seconds
Started Jun 05 04:11:07 PM PDT 24
Finished Jun 05 04:11:11 PM PDT 24
Peak memory 208768 kb
Host smart-18c4ed53-b4d6-487d-bd04-abc9c91bd0ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193372173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1193372173
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2282955179
Short name T785
Test name
Test status
Simulation time 62853956 ps
CPU time 2.83 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:12 PM PDT 24
Peak memory 209360 kb
Host smart-8be5e7e9-8a02-43a5-a8f7-204498961d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282955179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2282955179
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.380405228
Short name T637
Test name
Test status
Simulation time 161181018 ps
CPU time 2.47 seconds
Started Jun 05 04:11:02 PM PDT 24
Finished Jun 05 04:11:05 PM PDT 24
Peak memory 208348 kb
Host smart-3e0f6755-0557-47aa-9a4f-f54953ed36a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380405228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.380405228
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3476497232
Short name T73
Test name
Test status
Simulation time 908121478 ps
CPU time 15.64 seconds
Started Jun 05 04:11:05 PM PDT 24
Finished Jun 05 04:11:22 PM PDT 24
Peak memory 215532 kb
Host smart-babc187f-c419-4ed0-aec7-4fa66a6e14a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476497232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3476497232
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3315372967
Short name T249
Test name
Test status
Simulation time 35911909 ps
CPU time 2.89 seconds
Started Jun 05 04:11:07 PM PDT 24
Finished Jun 05 04:11:11 PM PDT 24
Peak memory 210120 kb
Host smart-44422ac7-6fe1-453c-b8e5-5322210cee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315372967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3315372967
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1831714945
Short name T902
Test name
Test status
Simulation time 73106145 ps
CPU time 2.01 seconds
Started Jun 05 04:11:15 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 209908 kb
Host smart-6c10adab-de77-456e-b228-1e5dc93385b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831714945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1831714945
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1097137771
Short name T379
Test name
Test status
Simulation time 292480105 ps
CPU time 3.82 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 214332 kb
Host smart-d8c4be2f-4169-4540-8f85-4545a863d071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1097137771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1097137771
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.847311900
Short name T506
Test name
Test status
Simulation time 297074595 ps
CPU time 3.77 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 221320 kb
Host smart-27a65e02-a2ae-4e8e-af21-b80f2aaae689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847311900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.847311900
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3019541515
Short name T408
Test name
Test status
Simulation time 224820433 ps
CPU time 2.79 seconds
Started Jun 05 04:11:05 PM PDT 24
Finished Jun 05 04:11:09 PM PDT 24
Peak memory 210228 kb
Host smart-dd2cb619-2015-4c90-b913-f17ab11b9993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019541515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3019541515
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.221194348
Short name T259
Test name
Test status
Simulation time 32240543 ps
CPU time 2.42 seconds
Started Jun 05 04:11:12 PM PDT 24
Finished Jun 05 04:11:16 PM PDT 24
Peak memory 214600 kb
Host smart-6de37935-63ec-41ce-aa97-6ffaeff14899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221194348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.221194348
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1788597546
Short name T538
Test name
Test status
Simulation time 135763896 ps
CPU time 3.45 seconds
Started Jun 05 04:11:07 PM PDT 24
Finished Jun 05 04:11:11 PM PDT 24
Peak memory 220808 kb
Host smart-14ddbe4e-1f2f-43aa-bc70-59bc64d0f013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788597546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1788597546
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1511044483
Short name T214
Test name
Test status
Simulation time 140717078 ps
CPU time 3.89 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 217384 kb
Host smart-10999b05-b006-42ac-9422-1d33fcd2ff07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511044483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1511044483
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2266884003
Short name T308
Test name
Test status
Simulation time 621353145 ps
CPU time 7.12 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:16 PM PDT 24
Peak memory 207804 kb
Host smart-a63d9f4d-106a-4fe9-ae35-358e5b508977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266884003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2266884003
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.260255310
Short name T798
Test name
Test status
Simulation time 416581162 ps
CPU time 2.78 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:12 PM PDT 24
Peak memory 206792 kb
Host smart-d5d0b639-e578-4bb3-8b96-9b87b2969c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260255310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.260255310
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2050295479
Short name T663
Test name
Test status
Simulation time 38668763 ps
CPU time 2.42 seconds
Started Jun 05 04:11:09 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 207072 kb
Host smart-65111487-e87a-48e8-a6fe-7a6bf13cda90
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050295479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2050295479
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.338994819
Short name T782
Test name
Test status
Simulation time 326318542 ps
CPU time 5.28 seconds
Started Jun 05 04:11:13 PM PDT 24
Finished Jun 05 04:11:20 PM PDT 24
Peak memory 206912 kb
Host smart-e8dee913-41de-46a6-8681-3c32077e1ab7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338994819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.338994819
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2131550635
Short name T389
Test name
Test status
Simulation time 291276276 ps
CPU time 10.94 seconds
Started Jun 05 04:11:06 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 208132 kb
Host smart-74f4ab86-9b1e-4768-b907-c17f6f177b31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131550635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2131550635
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3038219317
Short name T303
Test name
Test status
Simulation time 988637879 ps
CPU time 12.27 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:21 PM PDT 24
Peak memory 214340 kb
Host smart-ab155cfc-dbd5-493e-b89c-35c770afb744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038219317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3038219317
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1657751164
Short name T390
Test name
Test status
Simulation time 76948946 ps
CPU time 2.01 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:12 PM PDT 24
Peak memory 207104 kb
Host smart-f3351b6c-dc32-4932-8054-b1755650a5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657751164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1657751164
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1953754501
Short name T908
Test name
Test status
Simulation time 4415400590 ps
CPU time 53.04 seconds
Started Jun 05 04:11:10 PM PDT 24
Finished Jun 05 04:12:04 PM PDT 24
Peak memory 216936 kb
Host smart-5449a378-c757-4c22-890e-07d848c63a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953754501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1953754501
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1281202074
Short name T457
Test name
Test status
Simulation time 461276206 ps
CPU time 7.61 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:17 PM PDT 24
Peak memory 214312 kb
Host smart-b7c5caa4-a845-4abe-a8df-d17c7478c903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281202074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1281202074
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1702270036
Short name T681
Test name
Test status
Simulation time 190615968 ps
CPU time 1.72 seconds
Started Jun 05 04:11:10 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 210656 kb
Host smart-a60b0642-e158-408c-9648-ee758c972fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702270036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1702270036
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1552260078
Short name T626
Test name
Test status
Simulation time 8728376 ps
CPU time 0.75 seconds
Started Jun 05 04:11:13 PM PDT 24
Finished Jun 05 04:11:15 PM PDT 24
Peak memory 205936 kb
Host smart-a6bd1f92-f167-4625-92dc-7eba97cb8aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552260078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1552260078
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2527625423
Short name T134
Test name
Test status
Simulation time 160533020 ps
CPU time 3.3 seconds
Started Jun 05 04:11:13 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 215340 kb
Host smart-b32c2a76-88d9-4676-b06f-ea0ec0ebf7d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2527625423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2527625423
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.4115781477
Short name T62
Test name
Test status
Simulation time 115070886 ps
CPU time 4.99 seconds
Started Jun 05 04:11:10 PM PDT 24
Finished Jun 05 04:11:16 PM PDT 24
Peak memory 218388 kb
Host smart-9b435423-edca-4871-a96c-145310703915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115781477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.4115781477
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3569032271
Short name T242
Test name
Test status
Simulation time 49785866 ps
CPU time 1.81 seconds
Started Jun 05 04:11:14 PM PDT 24
Finished Jun 05 04:11:17 PM PDT 24
Peak memory 214512 kb
Host smart-1412a674-9b00-4f28-a41e-373acc645efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569032271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3569032271
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2781756735
Short name T318
Test name
Test status
Simulation time 87230042 ps
CPU time 2.6 seconds
Started Jun 05 04:11:12 PM PDT 24
Finished Jun 05 04:11:16 PM PDT 24
Peak memory 214468 kb
Host smart-abad0931-16fe-4078-9ac9-4a1e2bf1aab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781756735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2781756735
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3266931672
Short name T687
Test name
Test status
Simulation time 467823513 ps
CPU time 3.71 seconds
Started Jun 05 04:11:05 PM PDT 24
Finished Jun 05 04:11:10 PM PDT 24
Peak memory 215576 kb
Host smart-ed123d6c-3b11-49d3-9e72-bec93334a1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266931672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3266931672
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3147847743
Short name T697
Test name
Test status
Simulation time 69230006 ps
CPU time 3.21 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:12 PM PDT 24
Peak memory 218244 kb
Host smart-2cd84f6e-0888-4176-b432-21727a532d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147847743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3147847743
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3854246366
Short name T444
Test name
Test status
Simulation time 377217030 ps
CPU time 3.27 seconds
Started Jun 05 04:11:09 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 206808 kb
Host smart-6b62f101-3032-420e-a1ad-6a41233e16df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854246366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3854246366
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1330308353
Short name T449
Test name
Test status
Simulation time 53241325 ps
CPU time 2.8 seconds
Started Jun 05 04:11:06 PM PDT 24
Finished Jun 05 04:11:10 PM PDT 24
Peak memory 207072 kb
Host smart-5ad0a158-e0f6-477a-8ef4-05c207af43b5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330308353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1330308353
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3418305886
Short name T876
Test name
Test status
Simulation time 56383481 ps
CPU time 3.01 seconds
Started Jun 05 04:11:06 PM PDT 24
Finished Jun 05 04:11:10 PM PDT 24
Peak memory 208420 kb
Host smart-8f9300b5-556f-43e3-a138-0c3d79b1f6ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418305886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3418305886
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3629082080
Short name T836
Test name
Test status
Simulation time 176507744 ps
CPU time 4.76 seconds
Started Jun 05 04:11:07 PM PDT 24
Finished Jun 05 04:11:13 PM PDT 24
Peak memory 208564 kb
Host smart-98546d2c-cf45-4fe3-970f-1bedd6b272f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629082080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3629082080
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.562549449
Short name T720
Test name
Test status
Simulation time 448183966 ps
CPU time 4.06 seconds
Started Jun 05 04:11:14 PM PDT 24
Finished Jun 05 04:11:19 PM PDT 24
Peak memory 209924 kb
Host smart-ebb40c42-3cdf-462a-b7e4-b46c6ecffc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562549449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.562549449
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.312971742
Short name T458
Test name
Test status
Simulation time 183059340 ps
CPU time 2.53 seconds
Started Jun 05 04:11:12 PM PDT 24
Finished Jun 05 04:11:16 PM PDT 24
Peak memory 207132 kb
Host smart-e19252e5-531a-4ca8-a8ee-217c049f0457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312971742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.312971742
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3336555358
Short name T222
Test name
Test status
Simulation time 3274229117 ps
CPU time 37.31 seconds
Started Jun 05 04:11:12 PM PDT 24
Finished Jun 05 04:11:51 PM PDT 24
Peak memory 215564 kb
Host smart-3f46a9f2-312a-4f3c-9958-e5cf2547af33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336555358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3336555358
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2997508734
Short name T105
Test name
Test status
Simulation time 428885876 ps
CPU time 7.91 seconds
Started Jun 05 04:11:13 PM PDT 24
Finished Jun 05 04:11:22 PM PDT 24
Peak memory 222652 kb
Host smart-60537c3f-eabf-493b-8d5d-789fd6ce5d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997508734 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2997508734
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2927101481
Short name T521
Test name
Test status
Simulation time 526427011 ps
CPU time 5.72 seconds
Started Jun 05 04:11:14 PM PDT 24
Finished Jun 05 04:11:21 PM PDT 24
Peak memory 210160 kb
Host smart-e0481ac1-6e82-49d0-86ab-7d3c7227bcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927101481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2927101481
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2691930811
Short name T769
Test name
Test status
Simulation time 149970703 ps
CPU time 2.7 seconds
Started Jun 05 04:11:08 PM PDT 24
Finished Jun 05 04:11:12 PM PDT 24
Peak memory 210260 kb
Host smart-5ae973fa-8893-490d-ada2-f1de867d25f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691930811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2691930811
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.231298146
Short name T649
Test name
Test status
Simulation time 9703443 ps
CPU time 0.88 seconds
Started Jun 05 04:11:18 PM PDT 24
Finished Jun 05 04:11:20 PM PDT 24
Peak memory 205940 kb
Host smart-33f274fb-d828-42e5-a04b-c5c57f6a2bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231298146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.231298146
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3163229975
Short name T454
Test name
Test status
Simulation time 172776729 ps
CPU time 4.42 seconds
Started Jun 05 04:11:18 PM PDT 24
Finished Jun 05 04:11:24 PM PDT 24
Peak memory 209712 kb
Host smart-60bcf53a-9da8-4038-b11b-477a0efe30e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163229975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3163229975
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3754258867
Short name T570
Test name
Test status
Simulation time 59654319 ps
CPU time 2.93 seconds
Started Jun 05 04:11:17 PM PDT 24
Finished Jun 05 04:11:21 PM PDT 24
Peak memory 207952 kb
Host smart-4f1402c8-033e-4272-bede-eed0bfe910ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754258867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3754258867
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3229126665
Short name T513
Test name
Test status
Simulation time 93058855 ps
CPU time 1.87 seconds
Started Jun 05 04:11:15 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 214356 kb
Host smart-0a427385-0128-423f-9bc2-fb838f4ae8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229126665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3229126665
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4120942235
Short name T353
Test name
Test status
Simulation time 433118822 ps
CPU time 3.78 seconds
Started Jun 05 04:11:17 PM PDT 24
Finished Jun 05 04:11:22 PM PDT 24
Peak memory 221904 kb
Host smart-c24f42fe-9bd3-4ccc-b4d1-c08d92b8dfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120942235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4120942235
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3415631435
Short name T46
Test name
Test status
Simulation time 197220843 ps
CPU time 3 seconds
Started Jun 05 04:11:16 PM PDT 24
Finished Jun 05 04:11:20 PM PDT 24
Peak memory 208588 kb
Host smart-acb52926-9b5e-4180-8bf0-becc82e6f5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415631435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3415631435
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2225458912
Short name T236
Test name
Test status
Simulation time 981815386 ps
CPU time 10.58 seconds
Started Jun 05 04:11:17 PM PDT 24
Finished Jun 05 04:11:29 PM PDT 24
Peak memory 209084 kb
Host smart-17858d78-e316-4d1b-a1bc-b7959b2b1bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225458912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2225458912
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2821557252
Short name T685
Test name
Test status
Simulation time 644385891 ps
CPU time 6.87 seconds
Started Jun 05 04:11:13 PM PDT 24
Finished Jun 05 04:11:21 PM PDT 24
Peak memory 206900 kb
Host smart-63be253b-0748-4933-a29b-06c37f337bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821557252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2821557252
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1823572759
Short name T603
Test name
Test status
Simulation time 204469004 ps
CPU time 2.84 seconds
Started Jun 05 04:11:12 PM PDT 24
Finished Jun 05 04:11:16 PM PDT 24
Peak memory 206808 kb
Host smart-531d09f8-0991-4273-8edd-4e665c747f19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823572759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1823572759
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2725314822
Short name T566
Test name
Test status
Simulation time 48246429 ps
CPU time 2.69 seconds
Started Jun 05 04:11:13 PM PDT 24
Finished Jun 05 04:11:17 PM PDT 24
Peak memory 206924 kb
Host smart-6e54ea7e-bfd6-41eb-b873-f0a2952b0bfd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725314822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2725314822
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3745194377
Short name T562
Test name
Test status
Simulation time 698314371 ps
CPU time 3.65 seconds
Started Jun 05 04:11:13 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 207936 kb
Host smart-1c90b81b-aca0-4ef5-b3c7-98b5f82ac6f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745194377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3745194377
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1843299984
Short name T723
Test name
Test status
Simulation time 43933056 ps
CPU time 1.93 seconds
Started Jun 05 04:11:16 PM PDT 24
Finished Jun 05 04:11:19 PM PDT 24
Peak memory 209436 kb
Host smart-a670bca5-5bb2-4f02-83ca-3544989813b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843299984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1843299984
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2907445451
Short name T486
Test name
Test status
Simulation time 75219167 ps
CPU time 3.01 seconds
Started Jun 05 04:11:14 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 208172 kb
Host smart-b7ca3f15-af25-4824-9b43-56239c147dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907445451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2907445451
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2407274291
Short name T177
Test name
Test status
Simulation time 2665804453 ps
CPU time 13.31 seconds
Started Jun 05 04:11:16 PM PDT 24
Finished Jun 05 04:11:30 PM PDT 24
Peak memory 222636 kb
Host smart-0f9f13f6-7072-47fc-a5ad-21a799b68fe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407274291 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.2407274291
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.432029989
Short name T875
Test name
Test status
Simulation time 761336166 ps
CPU time 5.15 seconds
Started Jun 05 04:11:16 PM PDT 24
Finished Jun 05 04:11:22 PM PDT 24
Peak memory 218276 kb
Host smart-5457161a-256b-4274-900a-426349d27d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432029989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.432029989
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.581272550
Short name T602
Test name
Test status
Simulation time 103745079 ps
CPU time 3.71 seconds
Started Jun 05 04:11:19 PM PDT 24
Finished Jun 05 04:11:23 PM PDT 24
Peak memory 210396 kb
Host smart-5b12e0ea-2259-49a8-89d3-d5ced596759e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581272550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.581272550
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3323816662
Short name T690
Test name
Test status
Simulation time 15144992 ps
CPU time 1.08 seconds
Started Jun 05 04:11:18 PM PDT 24
Finished Jun 05 04:11:20 PM PDT 24
Peak memory 206088 kb
Host smart-c6d16ce2-800f-4fea-a1d5-8ed856219a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323816662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3323816662
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3332205579
Short name T611
Test name
Test status
Simulation time 163501595 ps
CPU time 3.18 seconds
Started Jun 05 04:11:18 PM PDT 24
Finished Jun 05 04:11:22 PM PDT 24
Peak memory 217240 kb
Host smart-79f943d3-86aa-4336-ad14-3ebe756cc6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332205579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3332205579
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1977148249
Short name T518
Test name
Test status
Simulation time 255030665 ps
CPU time 2.58 seconds
Started Jun 05 04:11:16 PM PDT 24
Finished Jun 05 04:11:20 PM PDT 24
Peak memory 208388 kb
Host smart-bc1addcc-19f7-41d2-baa3-e56d02942343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977148249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1977148249
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4090275706
Short name T306
Test name
Test status
Simulation time 1268299952 ps
CPU time 33.4 seconds
Started Jun 05 04:11:15 PM PDT 24
Finished Jun 05 04:11:50 PM PDT 24
Peak memory 219072 kb
Host smart-943fab20-3cdf-49e4-b922-4d584009ad33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090275706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4090275706
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3091730995
Short name T795
Test name
Test status
Simulation time 140077712 ps
CPU time 4.07 seconds
Started Jun 05 04:11:16 PM PDT 24
Finished Jun 05 04:11:21 PM PDT 24
Peak memory 214260 kb
Host smart-2f9612e0-293e-4ba4-a697-0d2d4bb87b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091730995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3091730995
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3218161615
Short name T66
Test name
Test status
Simulation time 444765755 ps
CPU time 3.89 seconds
Started Jun 05 04:11:17 PM PDT 24
Finished Jun 05 04:11:22 PM PDT 24
Peak memory 220160 kb
Host smart-04c17ddc-3581-4656-986c-81c67d649303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218161615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3218161615
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.133613192
Short name T266
Test name
Test status
Simulation time 557197691 ps
CPU time 5.09 seconds
Started Jun 05 04:11:15 PM PDT 24
Finished Jun 05 04:11:21 PM PDT 24
Peak memory 219924 kb
Host smart-b06eef8c-f454-49be-9283-b24d79692ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133613192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.133613192
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3700323054
Short name T388
Test name
Test status
Simulation time 1539351277 ps
CPU time 11.41 seconds
Started Jun 05 04:11:16 PM PDT 24
Finished Jun 05 04:11:28 PM PDT 24
Peak memory 207948 kb
Host smart-60e724e3-b021-4329-b817-b01b8dbbdd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700323054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3700323054
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2830642493
Short name T730
Test name
Test status
Simulation time 162297920 ps
CPU time 4.77 seconds
Started Jun 05 04:11:18 PM PDT 24
Finished Jun 05 04:11:24 PM PDT 24
Peak memory 208512 kb
Host smart-ef822574-2f8f-4fa5-8dab-0460c2257d1e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830642493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2830642493
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3313356614
Short name T97
Test name
Test status
Simulation time 85474534 ps
CPU time 1.9 seconds
Started Jun 05 04:11:19 PM PDT 24
Finished Jun 05 04:11:21 PM PDT 24
Peak memory 206800 kb
Host smart-1764755a-9a98-4120-b65d-f88b10a30fcc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313356614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3313356614
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1638517878
Short name T887
Test name
Test status
Simulation time 35072903 ps
CPU time 2.58 seconds
Started Jun 05 04:11:17 PM PDT 24
Finished Jun 05 04:11:20 PM PDT 24
Peak memory 207708 kb
Host smart-a70e980a-0a80-4d94-8995-4b92dce8182d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638517878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1638517878
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.482128576
Short name T123
Test name
Test status
Simulation time 170390663 ps
CPU time 3.24 seconds
Started Jun 05 04:11:17 PM PDT 24
Finished Jun 05 04:11:21 PM PDT 24
Peak memory 208064 kb
Host smart-0f286561-9936-430d-b406-331c58c6eef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482128576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.482128576
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3102712181
Short name T427
Test name
Test status
Simulation time 43263283 ps
CPU time 2.3 seconds
Started Jun 05 04:11:16 PM PDT 24
Finished Jun 05 04:11:19 PM PDT 24
Peak memory 208188 kb
Host smart-8adb611b-00ee-493d-9ddf-93c85b65fc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102712181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3102712181
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.767874203
Short name T256
Test name
Test status
Simulation time 7430323113 ps
CPU time 237.04 seconds
Started Jun 05 04:11:17 PM PDT 24
Finished Jun 05 04:15:15 PM PDT 24
Peak memory 222460 kb
Host smart-8dcf18bb-8c44-4c6f-a3a9-5288d37d351b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767874203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.767874203
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3322957731
Short name T694
Test name
Test status
Simulation time 1114690591 ps
CPU time 17.53 seconds
Started Jun 05 04:11:18 PM PDT 24
Finished Jun 05 04:11:36 PM PDT 24
Peak memory 222624 kb
Host smart-2fc67cce-1a4a-43f7-9275-47244ec7be29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322957731 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3322957731
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.729455732
Short name T812
Test name
Test status
Simulation time 220701265 ps
CPU time 6.74 seconds
Started Jun 05 04:11:15 PM PDT 24
Finished Jun 05 04:11:23 PM PDT 24
Peak memory 208580 kb
Host smart-0d32db06-5f6a-40a1-b7c4-ce5433bd9131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729455732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.729455732
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.703305447
Short name T60
Test name
Test status
Simulation time 122812221 ps
CPU time 1.83 seconds
Started Jun 05 04:11:15 PM PDT 24
Finished Jun 05 04:11:18 PM PDT 24
Peak memory 209744 kb
Host smart-b173fcb4-89ff-49c7-ad14-ec0cebeb471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703305447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.703305447
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2127553777
Short name T762
Test name
Test status
Simulation time 47237684 ps
CPU time 0.77 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:29 PM PDT 24
Peak memory 205940 kb
Host smart-65dbc7c4-121f-4071-aef1-ad4109f4db64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127553777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2127553777
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2715419574
Short name T220
Test name
Test status
Simulation time 439438333 ps
CPU time 3.16 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:30 PM PDT 24
Peak memory 214312 kb
Host smart-16980bb0-ecc2-49e7-a9cd-4935a6e868b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715419574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2715419574
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2633318992
Short name T76
Test name
Test status
Simulation time 64692513 ps
CPU time 1.55 seconds
Started Jun 05 04:11:28 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 207736 kb
Host smart-198d2536-cda7-476b-a8a6-51d8ff61fd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633318992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2633318992
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3988570342
Short name T51
Test name
Test status
Simulation time 144447162 ps
CPU time 4.87 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 214244 kb
Host smart-863457a8-1546-465b-9a36-cf121312a4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988570342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3988570342
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3992917734
Short name T351
Test name
Test status
Simulation time 87610070 ps
CPU time 2.71 seconds
Started Jun 05 04:11:28 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 219608 kb
Host smart-a96a42fc-eea6-43c0-8ddc-b38855287977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992917734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3992917734
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3295287692
Short name T218
Test name
Test status
Simulation time 512679186 ps
CPU time 4.84 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:32 PM PDT 24
Peak memory 219672 kb
Host smart-1139db8b-6c0d-491f-a185-a584323cae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295287692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3295287692
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2619474340
Short name T544
Test name
Test status
Simulation time 243954444 ps
CPU time 9.44 seconds
Started Jun 05 04:11:25 PM PDT 24
Finished Jun 05 04:11:35 PM PDT 24
Peak memory 209504 kb
Host smart-8a8cccb2-bbcd-4b26-bdea-8723909889f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619474340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2619474340
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3449845677
Short name T631
Test name
Test status
Simulation time 281237959 ps
CPU time 5.36 seconds
Started Jun 05 04:11:28 PM PDT 24
Finished Jun 05 04:11:34 PM PDT 24
Peak memory 207956 kb
Host smart-0df160b7-dec9-4053-97c0-eb314a27a578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449845677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3449845677
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.103549616
Short name T862
Test name
Test status
Simulation time 158519170 ps
CPU time 5.84 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:34 PM PDT 24
Peak memory 207824 kb
Host smart-04d8628a-b973-4ad8-ab3f-07a60a2dbc34
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103549616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.103549616
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1237989274
Short name T509
Test name
Test status
Simulation time 52871170 ps
CPU time 3.03 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 208832 kb
Host smart-cafbb39a-cba5-4ca5-b9e2-d33f8d4ec658
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237989274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1237989274
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2330612084
Short name T662
Test name
Test status
Simulation time 277785505 ps
CPU time 2.93 seconds
Started Jun 05 04:11:28 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 207008 kb
Host smart-d1daa260-9c29-4a99-b792-231e9f1bf6eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330612084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2330612084
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1850884379
Short name T754
Test name
Test status
Simulation time 29072261 ps
CPU time 2.17 seconds
Started Jun 05 04:11:23 PM PDT 24
Finished Jun 05 04:11:26 PM PDT 24
Peak memory 214548 kb
Host smart-a07d96c0-0a65-4235-b477-c2f9c6bc0878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850884379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1850884379
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.491831712
Short name T674
Test name
Test status
Simulation time 2120068740 ps
CPU time 32.07 seconds
Started Jun 05 04:11:15 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 208904 kb
Host smart-8db84aaa-f305-4cf2-857e-b3dccb819de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491831712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.491831712
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1086280292
Short name T128
Test name
Test status
Simulation time 404967837 ps
CPU time 16.42 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:44 PM PDT 24
Peak memory 222500 kb
Host smart-31394d2e-2b01-4ec2-bdc4-a43616bad580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086280292 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1086280292
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3353870420
Short name T497
Test name
Test status
Simulation time 2599182988 ps
CPU time 29.13 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:57 PM PDT 24
Peak memory 218400 kb
Host smart-bacd98de-4698-4767-8e71-386c498eab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353870420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3353870420
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1413202599
Short name T187
Test name
Test status
Simulation time 96068537 ps
CPU time 2.28 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:30 PM PDT 24
Peak memory 209744 kb
Host smart-65b21517-03ce-44ae-a468-0e1be3a3121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413202599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1413202599
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2147564591
Short name T581
Test name
Test status
Simulation time 17760502 ps
CPU time 0.97 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:28 PM PDT 24
Peak memory 206120 kb
Host smart-51d63115-72c0-4c90-af98-b20764f7c1fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147564591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2147564591
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3134029428
Short name T717
Test name
Test status
Simulation time 285847004 ps
CPU time 1.93 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:29 PM PDT 24
Peak memory 209512 kb
Host smart-a70489b9-d810-4d3c-8318-7eaf57916515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134029428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3134029428
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1526187904
Short name T91
Test name
Test status
Simulation time 123528034 ps
CPU time 3.42 seconds
Started Jun 05 04:11:29 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 208444 kb
Host smart-50f2c511-cd24-49b3-b200-637565fdb45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526187904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1526187904
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3412147994
Short name T640
Test name
Test status
Simulation time 267925232 ps
CPU time 2.96 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:30 PM PDT 24
Peak memory 222348 kb
Host smart-1c5481d2-aea7-4c52-9ce1-e7f6a9b154ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412147994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3412147994
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3319952708
Short name T69
Test name
Test status
Simulation time 659488779 ps
CPU time 4.01 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:30 PM PDT 24
Peak memory 220188 kb
Host smart-cd65a716-c3fc-4430-ab8f-dd47e31be473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319952708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3319952708
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1009803694
Short name T885
Test name
Test status
Simulation time 299774012 ps
CPU time 3.87 seconds
Started Jun 05 04:11:28 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 209024 kb
Host smart-54a83596-5091-49de-a553-eaf5c19ce803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009803694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1009803694
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2580086565
Short name T430
Test name
Test status
Simulation time 126840171 ps
CPU time 2.62 seconds
Started Jun 05 04:11:29 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 207356 kb
Host smart-4d228f60-52ff-4c16-b3d1-defbae26bd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580086565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2580086565
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1350909620
Short name T829
Test name
Test status
Simulation time 65435998 ps
CPU time 2.89 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:30 PM PDT 24
Peak memory 206960 kb
Host smart-76db3451-4eb0-4717-9ab3-52d0ab9241d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350909620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1350909620
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1113532636
Short name T728
Test name
Test status
Simulation time 173522031 ps
CPU time 1.83 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:29 PM PDT 24
Peak memory 207364 kb
Host smart-f49af128-fc2c-45e8-901a-b53ae97147f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113532636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1113532636
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.398613496
Short name T816
Test name
Test status
Simulation time 22677731 ps
CPU time 1.78 seconds
Started Jun 05 04:11:25 PM PDT 24
Finished Jun 05 04:11:28 PM PDT 24
Peak memory 206924 kb
Host smart-ec8b581e-6f87-462e-819c-fa24a7f92fff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398613496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.398613496
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2815393251
Short name T200
Test name
Test status
Simulation time 6132850005 ps
CPU time 26.99 seconds
Started Jun 05 04:11:32 PM PDT 24
Finished Jun 05 04:11:59 PM PDT 24
Peak memory 208256 kb
Host smart-17ff6292-98b8-4a0f-9372-bbd7ac16c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815393251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2815393251
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.500469649
Short name T752
Test name
Test status
Simulation time 116883387 ps
CPU time 3.02 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:29 PM PDT 24
Peak memory 206748 kb
Host smart-090bd7b5-f9bc-4d1d-9e0b-a9610c19c969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500469649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.500469649
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1675650889
Short name T53
Test name
Test status
Simulation time 320883186 ps
CPU time 7.32 seconds
Started Jun 05 04:11:25 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 219596 kb
Host smart-52dfb236-bdfc-4260-8499-33cfe37fec52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675650889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1675650889
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2239373354
Short name T888
Test name
Test status
Simulation time 158690543 ps
CPU time 6.49 seconds
Started Jun 05 04:11:30 PM PDT 24
Finished Jun 05 04:11:38 PM PDT 24
Peak memory 220132 kb
Host smart-7eec0411-03ef-46b7-a48e-ce9f8f575f35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239373354 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2239373354
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3962342152
Short name T197
Test name
Test status
Simulation time 346014076 ps
CPU time 3.09 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 208300 kb
Host smart-fa0929bc-9cc1-426d-bb77-cbdf7faa8a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962342152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3962342152
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3490557800
Short name T592
Test name
Test status
Simulation time 331027080 ps
CPU time 3.2 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 209940 kb
Host smart-a786a2e1-8340-4588-8225-7567afcb70ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490557800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3490557800
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3699029703
Short name T892
Test name
Test status
Simulation time 36102185 ps
CPU time 0.83 seconds
Started Jun 05 04:11:29 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 205920 kb
Host smart-a3a11d9f-554e-4a58-a198-1e8fab9050ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699029703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3699029703
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.448448025
Short name T393
Test name
Test status
Simulation time 616040608 ps
CPU time 17.08 seconds
Started Jun 05 04:11:28 PM PDT 24
Finished Jun 05 04:11:46 PM PDT 24
Peak memory 222500 kb
Host smart-3c9c4bea-6581-4f29-862f-b9abdb82758b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448448025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.448448025
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2932574551
Short name T34
Test name
Test status
Simulation time 665831249 ps
CPU time 15.75 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:43 PM PDT 24
Peak memory 222732 kb
Host smart-7fc91b9b-0859-4565-aa4b-342425af09c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932574551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2932574551
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2386219336
Short name T859
Test name
Test status
Simulation time 151924609 ps
CPU time 3.65 seconds
Started Jun 05 04:11:30 PM PDT 24
Finished Jun 05 04:11:34 PM PDT 24
Peak memory 209372 kb
Host smart-bd985170-0213-420b-839a-594bcc0e369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386219336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2386219336
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1001654942
Short name T81
Test name
Test status
Simulation time 47265220 ps
CPU time 3.03 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 221912 kb
Host smart-bf2766df-15b8-409a-aea4-1157799d4a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001654942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1001654942
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2545095682
Short name T590
Test name
Test status
Simulation time 123358625 ps
CPU time 2.21 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:30 PM PDT 24
Peak memory 214464 kb
Host smart-f6b18673-8659-49ec-abe9-6dadfd1f284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545095682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2545095682
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1360992404
Short name T399
Test name
Test status
Simulation time 541400299 ps
CPU time 3.54 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:32 PM PDT 24
Peak memory 206556 kb
Host smart-ddce3da3-928b-47e3-8d20-eec4c682b8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360992404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1360992404
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.409395793
Short name T583
Test name
Test status
Simulation time 179480981 ps
CPU time 3.23 seconds
Started Jun 05 04:11:31 PM PDT 24
Finished Jun 05 04:11:35 PM PDT 24
Peak memory 218160 kb
Host smart-37a0aaca-c328-41c3-bb98-93d598e5fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409395793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.409395793
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3726693397
Short name T891
Test name
Test status
Simulation time 48263436 ps
CPU time 2.79 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:29 PM PDT 24
Peak memory 206904 kb
Host smart-f2be5aa0-f2ba-4063-bc59-dda2d57b1258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726693397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3726693397
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.674297353
Short name T896
Test name
Test status
Simulation time 77357443 ps
CPU time 3.65 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 209096 kb
Host smart-761a0660-aad3-428c-84d3-b7204f1febae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674297353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.674297353
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.33186499
Short name T13
Test name
Test status
Simulation time 509652457 ps
CPU time 3.98 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:30 PM PDT 24
Peak memory 208540 kb
Host smart-5f9455c4-fde3-4f58-a104-21aa82d09dcc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33186499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.33186499
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3240032726
Short name T381
Test name
Test status
Simulation time 302483962 ps
CPU time 3.5 seconds
Started Jun 05 04:11:29 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 208900 kb
Host smart-45bb4c72-c52d-4665-aa60-4a0a4e43be68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240032726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3240032726
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3340140491
Short name T880
Test name
Test status
Simulation time 106970564 ps
CPU time 1.68 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:28 PM PDT 24
Peak memory 208472 kb
Host smart-a2c48027-af64-4e80-b52e-daa0981b3b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340140491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3340140491
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.435888226
Short name T819
Test name
Test status
Simulation time 2753088852 ps
CPU time 12.02 seconds
Started Jun 05 04:11:31 PM PDT 24
Finished Jun 05 04:11:44 PM PDT 24
Peak memory 208656 kb
Host smart-92d6a4b5-99ed-42bc-ad01-bf6183c55136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435888226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.435888226
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3633756213
Short name T716
Test name
Test status
Simulation time 122849757 ps
CPU time 2.58 seconds
Started Jun 05 04:11:27 PM PDT 24
Finished Jun 05 04:11:31 PM PDT 24
Peak memory 216116 kb
Host smart-51865161-faab-48fb-a703-49139a60189d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633756213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3633756213
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2756822311
Short name T569
Test name
Test status
Simulation time 29436749 ps
CPU time 2.35 seconds
Started Jun 05 04:11:26 PM PDT 24
Finished Jun 05 04:11:30 PM PDT 24
Peak memory 207488 kb
Host smart-0dc2d18d-a78e-4865-bff7-952d05db8b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756822311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2756822311
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3247239154
Short name T59
Test name
Test status
Simulation time 190866795 ps
CPU time 2.51 seconds
Started Jun 05 04:11:29 PM PDT 24
Finished Jun 05 04:11:33 PM PDT 24
Peak memory 210036 kb
Host smart-e5f4b243-a88c-412f-9c76-e3ca3bc470a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247239154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3247239154
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.57849699
Short name T95
Test name
Test status
Simulation time 54903037 ps
CPU time 0.75 seconds
Started Jun 05 04:11:34 PM PDT 24
Finished Jun 05 04:11:36 PM PDT 24
Peak memory 205872 kb
Host smart-d1f05db4-3db4-49f2-92c5-209b57733f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57849699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.57849699
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1496033992
Short name T344
Test name
Test status
Simulation time 45111343 ps
CPU time 3.15 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:41 PM PDT 24
Peak memory 214792 kb
Host smart-b9b502d5-4901-467b-9cca-032cd2f64967
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496033992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1496033992
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1740305019
Short name T776
Test name
Test status
Simulation time 90073697 ps
CPU time 3.42 seconds
Started Jun 05 04:11:40 PM PDT 24
Finished Jun 05 04:11:44 PM PDT 24
Peak memory 222748 kb
Host smart-3f2cdb5a-9349-4545-8858-5ab04ccf9bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740305019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1740305019
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2025363795
Short name T477
Test name
Test status
Simulation time 160737559 ps
CPU time 1.82 seconds
Started Jun 05 04:11:35 PM PDT 24
Finished Jun 05 04:11:37 PM PDT 24
Peak memory 218368 kb
Host smart-f9aab914-69c2-4532-9eb1-cbb528151f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025363795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2025363795
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2096159324
Short name T86
Test name
Test status
Simulation time 131221111 ps
CPU time 5.58 seconds
Started Jun 05 04:11:36 PM PDT 24
Finished Jun 05 04:11:43 PM PDT 24
Peak memory 221684 kb
Host smart-059e38c1-4ef6-402f-9dc6-5e8a65b07496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096159324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2096159324
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.967824598
Short name T533
Test name
Test status
Simulation time 238021602 ps
CPU time 2.65 seconds
Started Jun 05 04:11:33 PM PDT 24
Finished Jun 05 04:11:36 PM PDT 24
Peak memory 209900 kb
Host smart-22b9cc18-78e7-4888-ac36-9c8a55394f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967824598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.967824598
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.854508253
Short name T756
Test name
Test status
Simulation time 656178762 ps
CPU time 4.85 seconds
Started Jun 05 04:11:35 PM PDT 24
Finished Jun 05 04:11:41 PM PDT 24
Peak memory 218528 kb
Host smart-be89113e-2f8c-4f65-8d0c-4f71b5a9aa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854508253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.854508253
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.507057510
Short name T291
Test name
Test status
Simulation time 103315856 ps
CPU time 2.21 seconds
Started Jun 05 04:11:35 PM PDT 24
Finished Jun 05 04:11:38 PM PDT 24
Peak memory 208924 kb
Host smart-9feef71d-bddf-4de7-a5bd-6bb35397da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507057510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.507057510
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1015093422
Short name T559
Test name
Test status
Simulation time 208128145 ps
CPU time 6.09 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:45 PM PDT 24
Peak memory 208612 kb
Host smart-bae6c87a-2b84-409c-8b5a-44b402b4c88b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015093422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1015093422
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.542817382
Short name T244
Test name
Test status
Simulation time 412829830 ps
CPU time 6.25 seconds
Started Jun 05 04:11:38 PM PDT 24
Finished Jun 05 04:11:45 PM PDT 24
Peak memory 208528 kb
Host smart-7b3594ac-c943-45d0-9a9b-50a95f8b909f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542817382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.542817382
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3910536451
Short name T517
Test name
Test status
Simulation time 130508452 ps
CPU time 3.07 seconds
Started Jun 05 04:11:38 PM PDT 24
Finished Jun 05 04:11:42 PM PDT 24
Peak memory 206860 kb
Host smart-f86c230d-7c67-4750-a55b-fc8fa50ba8db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910536451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3910536451
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.745798038
Short name T766
Test name
Test status
Simulation time 801271886 ps
CPU time 17.01 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 209908 kb
Host smart-67ca7857-e7c2-498c-9b3f-c672ea855dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745798038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.745798038
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2931223332
Short name T895
Test name
Test status
Simulation time 165104730 ps
CPU time 4.48 seconds
Started Jun 05 04:11:30 PM PDT 24
Finished Jun 05 04:11:35 PM PDT 24
Peak memory 208060 kb
Host smart-99c8a163-6a40-41a7-b631-d7e6e638a06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931223332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2931223332
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3863269673
Short name T180
Test name
Test status
Simulation time 89682939 ps
CPU time 3.34 seconds
Started Jun 05 04:11:36 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 214640 kb
Host smart-b243d757-1f47-4519-a4ce-30e3ad343ef7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863269673 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3863269673
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1157968522
Short name T246
Test name
Test status
Simulation time 237424136 ps
CPU time 5.5 seconds
Started Jun 05 04:11:35 PM PDT 24
Finished Jun 05 04:11:41 PM PDT 24
Peak memory 210052 kb
Host smart-061f5e22-7a66-48b3-a514-84e4be73cb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157968522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1157968522
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1501758321
Short name T714
Test name
Test status
Simulation time 681253766 ps
CPU time 2.32 seconds
Started Jun 05 04:11:36 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 209776 kb
Host smart-4137947a-8845-4b47-9194-c4cafb64a2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501758321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1501758321
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4248911217
Short name T614
Test name
Test status
Simulation time 36268696 ps
CPU time 0.83 seconds
Started Jun 05 04:09:00 PM PDT 24
Finished Jun 05 04:09:02 PM PDT 24
Peak memory 205928 kb
Host smart-cd38d8be-7f86-4132-87c5-a2d114d22565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248911217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4248911217
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1522338004
Short name T365
Test name
Test status
Simulation time 266807358 ps
CPU time 7.31 seconds
Started Jun 05 04:08:58 PM PDT 24
Finished Jun 05 04:09:06 PM PDT 24
Peak memory 214512 kb
Host smart-27861e4a-aa65-41d4-a6c8-2063518e87dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522338004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1522338004
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2307892207
Short name T212
Test name
Test status
Simulation time 42336816 ps
CPU time 2.84 seconds
Started Jun 05 04:08:56 PM PDT 24
Finished Jun 05 04:08:59 PM PDT 24
Peak memory 214564 kb
Host smart-b4cff644-255d-40d9-b50f-98610786ca6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307892207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2307892207
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.499044778
Short name T71
Test name
Test status
Simulation time 69158883 ps
CPU time 1.81 seconds
Started Jun 05 04:08:57 PM PDT 24
Finished Jun 05 04:09:00 PM PDT 24
Peak memory 209120 kb
Host smart-d5dc25df-73ce-4233-8ee4-f114f9b7abe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499044778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.499044778
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.679389353
Short name T337
Test name
Test status
Simulation time 98307938 ps
CPU time 4.54 seconds
Started Jun 05 04:08:56 PM PDT 24
Finished Jun 05 04:09:01 PM PDT 24
Peak memory 214344 kb
Host smart-76f2b6d3-3ea7-421d-8562-3ebed73abf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679389353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.679389353
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.199087079
Short name T257
Test name
Test status
Simulation time 158548858 ps
CPU time 4.44 seconds
Started Jun 05 04:08:56 PM PDT 24
Finished Jun 05 04:09:01 PM PDT 24
Peak memory 214704 kb
Host smart-99a68c01-d91c-43cd-8973-4081741cba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199087079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.199087079
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3641226799
Short name T529
Test name
Test status
Simulation time 84329332 ps
CPU time 2.21 seconds
Started Jun 05 04:08:59 PM PDT 24
Finished Jun 05 04:09:02 PM PDT 24
Peak memory 219072 kb
Host smart-9ac11147-8f0a-49af-8b53-d4820667c849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641226799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3641226799
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3038697097
Short name T688
Test name
Test status
Simulation time 463792697 ps
CPU time 4.95 seconds
Started Jun 05 04:08:48 PM PDT 24
Finished Jun 05 04:08:54 PM PDT 24
Peak memory 210372 kb
Host smart-8a97b4f6-9250-4b72-a9e8-38692166000f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038697097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3038697097
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1244054835
Short name T914
Test name
Test status
Simulation time 19692552 ps
CPU time 1.77 seconds
Started Jun 05 04:08:49 PM PDT 24
Finished Jun 05 04:08:51 PM PDT 24
Peak memory 206948 kb
Host smart-0f7b9132-54eb-4de7-8edb-d8d3667e97f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244054835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1244054835
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3344972160
Short name T764
Test name
Test status
Simulation time 1124595096 ps
CPU time 3.51 seconds
Started Jun 05 04:08:57 PM PDT 24
Finished Jun 05 04:09:01 PM PDT 24
Peak memory 208856 kb
Host smart-ecd43458-67ed-4aeb-a28e-d6be03ac7cb3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344972160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3344972160
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.146541836
Short name T252
Test name
Test status
Simulation time 69960556 ps
CPU time 2.62 seconds
Started Jun 05 04:08:56 PM PDT 24
Finished Jun 05 04:09:00 PM PDT 24
Peak memory 207000 kb
Host smart-7fa5f74a-a649-423b-9eae-c1fa56c846f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146541836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.146541836
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1912797818
Short name T686
Test name
Test status
Simulation time 133956511 ps
CPU time 5.24 seconds
Started Jun 05 04:08:49 PM PDT 24
Finished Jun 05 04:08:55 PM PDT 24
Peak memory 208176 kb
Host smart-95dc0e87-7216-4134-a648-8cc243c015eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912797818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1912797818
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.461822844
Short name T839
Test name
Test status
Simulation time 285027759 ps
CPU time 3.79 seconds
Started Jun 05 04:09:00 PM PDT 24
Finished Jun 05 04:09:04 PM PDT 24
Peak memory 218592 kb
Host smart-5503e2b3-64b2-47d3-b101-2e54f6ecd352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461822844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.461822844
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1321854626
Short name T732
Test name
Test status
Simulation time 806501060 ps
CPU time 8.35 seconds
Started Jun 05 04:08:58 PM PDT 24
Finished Jun 05 04:09:07 PM PDT 24
Peak memory 208896 kb
Host smart-4bfd2402-4238-459f-92c6-8685cc506c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321854626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1321854626
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2862749286
Short name T314
Test name
Test status
Simulation time 577984096 ps
CPU time 14.49 seconds
Started Jun 05 04:08:56 PM PDT 24
Finished Jun 05 04:09:11 PM PDT 24
Peak memory 209184 kb
Host smart-25fba78e-967a-48dc-9537-52b835f2a2d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862749286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2862749286
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2564848410
Short name T305
Test name
Test status
Simulation time 298595642 ps
CPU time 8.87 seconds
Started Jun 05 04:08:57 PM PDT 24
Finished Jun 05 04:09:07 PM PDT 24
Peak memory 222704 kb
Host smart-97d0a794-925c-4ff7-a505-e6d10dec2d9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564848410 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2564848410
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2456900792
Short name T192
Test name
Test status
Simulation time 779614348 ps
CPU time 8.43 seconds
Started Jun 05 04:08:57 PM PDT 24
Finished Jun 05 04:09:06 PM PDT 24
Peak memory 214288 kb
Host smart-1bebb94e-4201-49e9-8dae-65de0099e231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456900792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2456900792
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.49867558
Short name T37
Test name
Test status
Simulation time 725379551 ps
CPU time 3.77 seconds
Started Jun 05 04:08:57 PM PDT 24
Finished Jun 05 04:09:01 PM PDT 24
Peak memory 210792 kb
Host smart-37f89632-8825-4fe6-b56e-ac5cd9f427a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49867558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.49867558
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.4046144103
Short name T543
Test name
Test status
Simulation time 52281927 ps
CPU time 0.93 seconds
Started Jun 05 04:09:07 PM PDT 24
Finished Jun 05 04:09:09 PM PDT 24
Peak memory 206020 kb
Host smart-9c5a4156-5744-4829-8e3e-7e7a72d2a71f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046144103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.4046144103
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2513353215
Short name T313
Test name
Test status
Simulation time 1555869226 ps
CPU time 10.28 seconds
Started Jun 05 04:08:56 PM PDT 24
Finished Jun 05 04:09:07 PM PDT 24
Peak memory 214532 kb
Host smart-b185adc5-246e-42b8-9124-753e684439a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513353215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2513353215
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1892588948
Short name T504
Test name
Test status
Simulation time 748631201 ps
CPU time 2.71 seconds
Started Jun 05 04:08:57 PM PDT 24
Finished Jun 05 04:09:01 PM PDT 24
Peak memory 207428 kb
Host smart-e15c6560-d1f8-4a69-9cb6-81dcca820724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892588948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1892588948
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.666435321
Short name T627
Test name
Test status
Simulation time 150712458 ps
CPU time 5.32 seconds
Started Jun 05 04:08:59 PM PDT 24
Finished Jun 05 04:09:05 PM PDT 24
Peak memory 211264 kb
Host smart-9e10d140-206d-403b-9a3f-1ee0178d1c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666435321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.666435321
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3667431409
Short name T498
Test name
Test status
Simulation time 49128071 ps
CPU time 2.64 seconds
Started Jun 05 04:09:05 PM PDT 24
Finished Jun 05 04:09:09 PM PDT 24
Peak memory 219204 kb
Host smart-ab2b858e-5736-45ef-bb0f-4a1e8ed665ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667431409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3667431409
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2280595761
Short name T670
Test name
Test status
Simulation time 332931868 ps
CPU time 7.81 seconds
Started Jun 05 04:08:58 PM PDT 24
Finished Jun 05 04:09:07 PM PDT 24
Peak memory 208032 kb
Host smart-6a906e20-df63-4012-a458-de5933cc3077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280595761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2280595761
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4167474878
Short name T724
Test name
Test status
Simulation time 2881802879 ps
CPU time 15.77 seconds
Started Jun 05 04:09:00 PM PDT 24
Finished Jun 05 04:09:16 PM PDT 24
Peak memory 208200 kb
Host smart-8f655002-086e-4a5d-a8b3-3233f32f0f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167474878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4167474878
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.772889138
Short name T565
Test name
Test status
Simulation time 22071915 ps
CPU time 1.74 seconds
Started Jun 05 04:09:00 PM PDT 24
Finished Jun 05 04:09:02 PM PDT 24
Peak memory 206948 kb
Host smart-3d3c938d-2c12-438b-83bb-77f7479df472
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772889138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.772889138
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2312983885
Short name T435
Test name
Test status
Simulation time 2483287622 ps
CPU time 16.16 seconds
Started Jun 05 04:09:06 PM PDT 24
Finished Jun 05 04:09:22 PM PDT 24
Peak memory 208760 kb
Host smart-f53a6e91-7c7d-487b-b5d0-9c511804ae33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312983885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2312983885
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3102599200
Short name T837
Test name
Test status
Simulation time 536216582 ps
CPU time 5.64 seconds
Started Jun 05 04:08:59 PM PDT 24
Finished Jun 05 04:09:06 PM PDT 24
Peak memory 208900 kb
Host smart-93435614-8bfa-4163-b10f-8a30c08bec4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102599200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3102599200
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2594010688
Short name T101
Test name
Test status
Simulation time 126985845 ps
CPU time 2.32 seconds
Started Jun 05 04:08:59 PM PDT 24
Finished Jun 05 04:09:02 PM PDT 24
Peak memory 214184 kb
Host smart-8e534676-78a8-4278-b0c6-bb950bc66d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594010688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2594010688
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2890034562
Short name T821
Test name
Test status
Simulation time 138460096 ps
CPU time 4.38 seconds
Started Jun 05 04:08:58 PM PDT 24
Finished Jun 05 04:09:03 PM PDT 24
Peak memory 207984 kb
Host smart-88facb2a-1b8a-46d5-8b2b-7b58428d030e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890034562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2890034562
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3466768819
Short name T61
Test name
Test status
Simulation time 4289853648 ps
CPU time 42.29 seconds
Started Jun 05 04:09:07 PM PDT 24
Finished Jun 05 04:09:50 PM PDT 24
Peak memory 220964 kb
Host smart-c993c0b0-8430-4563-a464-c1d91e023e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466768819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3466768819
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2191280194
Short name T127
Test name
Test status
Simulation time 1465332805 ps
CPU time 11.08 seconds
Started Jun 05 04:09:05 PM PDT 24
Finished Jun 05 04:09:17 PM PDT 24
Peak memory 222628 kb
Host smart-13d259ce-a107-42c3-8a10-157e6e6b8d77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191280194 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2191280194
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3140575331
Short name T43
Test name
Test status
Simulation time 1059889943 ps
CPU time 8.14 seconds
Started Jun 05 04:09:08 PM PDT 24
Finished Jun 05 04:09:17 PM PDT 24
Peak memory 211028 kb
Host smart-5ff83454-3104-47f5-b90c-886aa09bf59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140575331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3140575331
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1716553544
Short name T411
Test name
Test status
Simulation time 40825541 ps
CPU time 0.74 seconds
Started Jun 05 04:09:06 PM PDT 24
Finished Jun 05 04:09:08 PM PDT 24
Peak memory 205916 kb
Host smart-98a2f736-1493-495e-b8a9-e1389d5feb70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716553544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1716553544
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3907681305
Short name T325
Test name
Test status
Simulation time 189102649 ps
CPU time 10.21 seconds
Started Jun 05 04:09:04 PM PDT 24
Finished Jun 05 04:09:15 PM PDT 24
Peak memory 214544 kb
Host smart-9d4096cc-5c02-4d10-bc1b-86d336336c87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3907681305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3907681305
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3788092006
Short name T751
Test name
Test status
Simulation time 121795753 ps
CPU time 1.71 seconds
Started Jun 05 04:09:06 PM PDT 24
Finished Jun 05 04:09:08 PM PDT 24
Peak memory 219420 kb
Host smart-7863afa2-6078-4657-bbe7-2c3863afdc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788092006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3788092006
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.17291270
Short name T273
Test name
Test status
Simulation time 759857949 ps
CPU time 3.7 seconds
Started Jun 05 04:09:11 PM PDT 24
Finished Jun 05 04:09:15 PM PDT 24
Peak memory 210228 kb
Host smart-aa2f4de4-f93a-4aef-abf2-e1ea98609a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17291270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.17291270
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3081638744
Short name T845
Test name
Test status
Simulation time 132867936 ps
CPU time 2.68 seconds
Started Jun 05 04:09:09 PM PDT 24
Finished Jun 05 04:09:13 PM PDT 24
Peak memory 214420 kb
Host smart-12d6d3f1-5efe-4a38-bbbe-b034baafa610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081638744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3081638744
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1414380584
Short name T96
Test name
Test status
Simulation time 118383654 ps
CPU time 2.47 seconds
Started Jun 05 04:09:07 PM PDT 24
Finished Jun 05 04:09:10 PM PDT 24
Peak memory 214640 kb
Host smart-750ac407-216f-4cb7-a420-3f20f4bd7fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414380584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1414380584
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.4292984300
Short name T99
Test name
Test status
Simulation time 410016793 ps
CPU time 11.33 seconds
Started Jun 05 04:09:05 PM PDT 24
Finished Jun 05 04:09:17 PM PDT 24
Peak memory 221348 kb
Host smart-c647dc9b-f726-4886-8a8b-ab5ff9d07d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292984300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.4292984300
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2080136702
Short name T460
Test name
Test status
Simulation time 58772153 ps
CPU time 4.01 seconds
Started Jun 05 04:09:06 PM PDT 24
Finished Jun 05 04:09:10 PM PDT 24
Peak memory 210272 kb
Host smart-88ab7ea8-a35f-4cb1-bc11-30a20b94e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080136702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2080136702
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.625171675
Short name T808
Test name
Test status
Simulation time 1327488317 ps
CPU time 39.84 seconds
Started Jun 05 04:09:07 PM PDT 24
Finished Jun 05 04:09:47 PM PDT 24
Peak memory 207036 kb
Host smart-e68242cb-cfbf-44ef-a5e0-a90c115fe8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625171675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.625171675
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3969458128
Short name T599
Test name
Test status
Simulation time 193079130 ps
CPU time 2.26 seconds
Started Jun 05 04:09:05 PM PDT 24
Finished Jun 05 04:09:08 PM PDT 24
Peak memory 206988 kb
Host smart-57c2af83-0951-449f-a29e-c7a60d4439bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969458128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3969458128
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1284327130
Short name T270
Test name
Test status
Simulation time 133118229 ps
CPU time 4.86 seconds
Started Jun 05 04:09:07 PM PDT 24
Finished Jun 05 04:09:13 PM PDT 24
Peak memory 208428 kb
Host smart-d501a381-b5ac-403a-8871-cc7172e5347a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284327130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1284327130
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3238182506
Short name T789
Test name
Test status
Simulation time 82361591 ps
CPU time 2.84 seconds
Started Jun 05 04:09:07 PM PDT 24
Finished Jun 05 04:09:11 PM PDT 24
Peak memory 206912 kb
Host smart-9c92408f-0373-4f4b-b89e-708e576c34fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238182506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3238182506
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1849011461
Short name T750
Test name
Test status
Simulation time 503579911 ps
CPU time 3.14 seconds
Started Jun 05 04:09:07 PM PDT 24
Finished Jun 05 04:09:11 PM PDT 24
Peak memory 218488 kb
Host smart-b90a5b82-240b-4dae-9c94-91986fe80d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849011461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1849011461
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.738814238
Short name T573
Test name
Test status
Simulation time 164073483 ps
CPU time 3.98 seconds
Started Jun 05 04:09:09 PM PDT 24
Finished Jun 05 04:09:13 PM PDT 24
Peak memory 208476 kb
Host smart-e06622fe-9b35-430c-aae7-4f0027f9dccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738814238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.738814238
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.366572110
Short name T324
Test name
Test status
Simulation time 1896079354 ps
CPU time 39.33 seconds
Started Jun 05 04:09:06 PM PDT 24
Finished Jun 05 04:09:46 PM PDT 24
Peak memory 216172 kb
Host smart-cf454c50-9cb8-4d23-adeb-f93d5ea42217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366572110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.366572110
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3025051506
Short name T178
Test name
Test status
Simulation time 355346028 ps
CPU time 8.42 seconds
Started Jun 05 04:09:09 PM PDT 24
Finished Jun 05 04:09:18 PM PDT 24
Peak memory 220128 kb
Host smart-484d663e-0cc2-4a31-9e89-71ffdb11b2ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025051506 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3025051506
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1631470520
Short name T593
Test name
Test status
Simulation time 1781901239 ps
CPU time 10.78 seconds
Started Jun 05 04:09:06 PM PDT 24
Finished Jun 05 04:09:18 PM PDT 24
Peak memory 209932 kb
Host smart-767298c9-9400-40cc-a4ae-ed2fc5e198fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631470520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1631470520
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3314557817
Short name T704
Test name
Test status
Simulation time 51126825 ps
CPU time 2.41 seconds
Started Jun 05 04:09:09 PM PDT 24
Finished Jun 05 04:09:12 PM PDT 24
Peak memory 210104 kb
Host smart-8f992728-5e18-42af-9dcf-11bf9cb506aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314557817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3314557817
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1094749115
Short name T432
Test name
Test status
Simulation time 28409265 ps
CPU time 0.79 seconds
Started Jun 05 04:09:15 PM PDT 24
Finished Jun 05 04:09:16 PM PDT 24
Peak memory 205972 kb
Host smart-cc2de2a2-2384-4694-9d1f-d0cfdf2d9675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094749115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1094749115
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1495544820
Short name T48
Test name
Test status
Simulation time 35482348 ps
CPU time 1.58 seconds
Started Jun 05 04:09:17 PM PDT 24
Finished Jun 05 04:09:19 PM PDT 24
Peak memory 208064 kb
Host smart-767b9151-844b-4b09-9e9e-870acce7e943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495544820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1495544820
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2759911952
Short name T92
Test name
Test status
Simulation time 246998687 ps
CPU time 3.58 seconds
Started Jun 05 04:09:13 PM PDT 24
Finished Jun 05 04:09:17 PM PDT 24
Peak memory 220336 kb
Host smart-5875f0db-6c2d-4cc9-b1a3-c9f333f7cc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759911952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2759911952
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3121891257
Short name T877
Test name
Test status
Simulation time 137818355 ps
CPU time 3.14 seconds
Started Jun 05 04:09:15 PM PDT 24
Finished Jun 05 04:09:19 PM PDT 24
Peak memory 214404 kb
Host smart-d8e6afd5-f703-4e35-91d1-62dae0d8d438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121891257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3121891257
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.127117851
Short name T2
Test name
Test status
Simulation time 419427008 ps
CPU time 3.83 seconds
Started Jun 05 04:09:10 PM PDT 24
Finished Jun 05 04:09:14 PM PDT 24
Peak memory 210052 kb
Host smart-6dae8b1e-804f-4581-a758-ec7f57b91a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127117851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.127117851
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.634644943
Short name T844
Test name
Test status
Simulation time 216129313 ps
CPU time 6.11 seconds
Started Jun 05 04:09:05 PM PDT 24
Finished Jun 05 04:09:11 PM PDT 24
Peak memory 208176 kb
Host smart-86ab75af-ccb9-42e8-a4eb-2cef43056e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634644943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.634644943
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4151786227
Short name T644
Test name
Test status
Simulation time 3307909413 ps
CPU time 20.74 seconds
Started Jun 05 04:09:08 PM PDT 24
Finished Jun 05 04:09:29 PM PDT 24
Peak memory 208512 kb
Host smart-76e2ab99-7e79-40c5-8aeb-14f194b4c8b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151786227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4151786227
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3446010820
Short name T903
Test name
Test status
Simulation time 201012642 ps
CPU time 6.93 seconds
Started Jun 05 04:09:06 PM PDT 24
Finished Jun 05 04:09:14 PM PDT 24
Peak memory 208148 kb
Host smart-33ab2d28-0746-4a39-9eb7-0f64f3ff0f47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446010820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3446010820
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.676938633
Short name T551
Test name
Test status
Simulation time 1985810083 ps
CPU time 5.37 seconds
Started Jun 05 04:09:07 PM PDT 24
Finished Jun 05 04:09:13 PM PDT 24
Peak memory 208796 kb
Host smart-d95bb00e-a7fc-418a-8f47-86005059ac47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676938633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.676938633
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3718560512
Short name T464
Test name
Test status
Simulation time 63437089 ps
CPU time 2.73 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:20 PM PDT 24
Peak memory 214300 kb
Host smart-99562537-19aa-4852-a5a9-9d5959c0d00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718560512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3718560512
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1511264251
Short name T455
Test name
Test status
Simulation time 327287317 ps
CPU time 4.41 seconds
Started Jun 05 04:09:05 PM PDT 24
Finished Jun 05 04:09:10 PM PDT 24
Peak memory 206828 kb
Host smart-07e2f79c-7c06-4987-afe9-5ba2ffa87076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511264251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1511264251
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1108252885
Short name T193
Test name
Test status
Simulation time 1057748480 ps
CPU time 11.2 seconds
Started Jun 05 04:09:15 PM PDT 24
Finished Jun 05 04:09:27 PM PDT 24
Peak memory 216532 kb
Host smart-a1bca979-1755-455e-b4b5-67ca635d33b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108252885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1108252885
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3855594353
Short name T179
Test name
Test status
Simulation time 577365792 ps
CPU time 13.57 seconds
Started Jun 05 04:09:13 PM PDT 24
Finished Jun 05 04:09:28 PM PDT 24
Peak memory 222724 kb
Host smart-c4e6f470-9348-4e68-bed8-98a27fc94f41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855594353 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3855594353
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3300579897
Short name T382
Test name
Test status
Simulation time 74586214 ps
CPU time 3.97 seconds
Started Jun 05 04:09:14 PM PDT 24
Finished Jun 05 04:09:18 PM PDT 24
Peak memory 207600 kb
Host smart-6747ff0f-d1f2-4e7f-a979-835ac1879c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300579897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3300579897
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1640915456
Short name T858
Test name
Test status
Simulation time 159073866 ps
CPU time 3.25 seconds
Started Jun 05 04:09:17 PM PDT 24
Finished Jun 05 04:09:22 PM PDT 24
Peak memory 210052 kb
Host smart-10808066-dc98-42af-a4a0-7aeb5ecf4360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640915456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1640915456
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3578655348
Short name T743
Test name
Test status
Simulation time 13370134 ps
CPU time 0.73 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:18 PM PDT 24
Peak memory 205940 kb
Host smart-4a73d610-7360-4f18-98a3-37825d14e10b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578655348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3578655348
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3183989881
Short name T251
Test name
Test status
Simulation time 67980384 ps
CPU time 4.14 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:21 PM PDT 24
Peak memory 215588 kb
Host smart-f598ae29-e23d-48cd-853b-9233a6c2898a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183989881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3183989881
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1138596355
Short name T554
Test name
Test status
Simulation time 96388047 ps
CPU time 2.56 seconds
Started Jun 05 04:09:15 PM PDT 24
Finished Jun 05 04:09:18 PM PDT 24
Peak memory 214332 kb
Host smart-ca57ae04-fa98-4bca-9f21-58ae6deb86e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138596355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1138596355
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.594747339
Short name T228
Test name
Test status
Simulation time 165073062 ps
CPU time 5.87 seconds
Started Jun 05 04:09:18 PM PDT 24
Finished Jun 05 04:09:25 PM PDT 24
Peak memory 220972 kb
Host smart-144f06c9-4579-4524-bf6f-2472c852a3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594747339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.594747339
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.131878532
Short name T83
Test name
Test status
Simulation time 34677078 ps
CPU time 2.2 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:19 PM PDT 24
Peak memory 214272 kb
Host smart-8e84ff05-ed64-42f1-81b0-b7f50d6fd55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131878532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.131878532
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3493795976
Short name T729
Test name
Test status
Simulation time 88706767 ps
CPU time 2.65 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:20 PM PDT 24
Peak memory 207520 kb
Host smart-3deecb54-2f44-4ca6-91c5-ef9818371f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493795976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3493795976
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1995395511
Short name T459
Test name
Test status
Simulation time 2339446193 ps
CPU time 28.5 seconds
Started Jun 05 04:09:18 PM PDT 24
Finished Jun 05 04:09:48 PM PDT 24
Peak memory 218480 kb
Host smart-cf238fe7-88f9-4738-bd0b-4bd270acbb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995395511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1995395511
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.412587808
Short name T753
Test name
Test status
Simulation time 376820606 ps
CPU time 3.76 seconds
Started Jun 05 04:09:17 PM PDT 24
Finished Jun 05 04:09:21 PM PDT 24
Peak memory 208484 kb
Host smart-3323030a-5e86-41d7-a761-90aff36e8a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412587808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.412587808
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2472517532
Short name T548
Test name
Test status
Simulation time 407750108 ps
CPU time 3.18 seconds
Started Jun 05 04:09:14 PM PDT 24
Finished Jun 05 04:09:18 PM PDT 24
Peak memory 206792 kb
Host smart-d5ae8bb3-e69b-417b-8513-0955b35ac303
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472517532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2472517532
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3348638270
Short name T600
Test name
Test status
Simulation time 157055379 ps
CPU time 3.06 seconds
Started Jun 05 04:09:17 PM PDT 24
Finished Jun 05 04:09:21 PM PDT 24
Peak memory 207524 kb
Host smart-16f544d1-b768-428b-bd75-85e096f5a397
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348638270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3348638270
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1507595419
Short name T913
Test name
Test status
Simulation time 179645201 ps
CPU time 3.63 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:21 PM PDT 24
Peak memory 208900 kb
Host smart-de3745b8-b398-49c4-a92d-a29745f187b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507595419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1507595419
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2935242702
Short name T667
Test name
Test status
Simulation time 162082051 ps
CPU time 2.52 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:20 PM PDT 24
Peak memory 208336 kb
Host smart-71f9c73e-5171-406f-850c-d74b7a40a39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935242702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2935242702
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3259907359
Short name T383
Test name
Test status
Simulation time 98407771 ps
CPU time 2.55 seconds
Started Jun 05 04:09:15 PM PDT 24
Finished Jun 05 04:09:19 PM PDT 24
Peak memory 208448 kb
Host smart-84dd92d9-0704-4855-85af-b30f6ddd1762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259907359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3259907359
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1315263279
Short name T277
Test name
Test status
Simulation time 678674134 ps
CPU time 24.26 seconds
Started Jun 05 04:09:18 PM PDT 24
Finished Jun 05 04:09:43 PM PDT 24
Peak memory 215216 kb
Host smart-55aa0ab7-7f27-4213-9142-6d96e6dfdc4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315263279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1315263279
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2214100580
Short name T156
Test name
Test status
Simulation time 476780637 ps
CPU time 20.75 seconds
Started Jun 05 04:09:17 PM PDT 24
Finished Jun 05 04:09:39 PM PDT 24
Peak memory 222632 kb
Host smart-4eb1de33-ca41-4e3f-bacc-922a19bf0164
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214100580 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2214100580
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.213094520
Short name T16
Test name
Test status
Simulation time 475812444 ps
CPU time 4.94 seconds
Started Jun 05 04:09:16 PM PDT 24
Finished Jun 05 04:09:22 PM PDT 24
Peak memory 210164 kb
Host smart-809781c0-a20e-42b5-bc95-145937cb4cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213094520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.213094520
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2604788835
Short name T129
Test name
Test status
Simulation time 8932423605 ps
CPU time 47.73 seconds
Started Jun 05 04:09:15 PM PDT 24
Finished Jun 05 04:10:04 PM PDT 24
Peak memory 211616 kb
Host smart-89928a94-1a0c-46c9-b62e-1a88a0e6c5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604788835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2604788835
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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