Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	47	1			T4	1		T44	1		T45	1
auto[OpGenId]	13	1			T5	1		T6	1		T7	1
auto[OpGenSwOut]	25	1			T2	1		T8	1		T60	1
auto[OpGenHwOut]	22	1			T5	1		T6	2		T38	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1708	1			T5	4		T88	1		T6	1
auto[StInit]	84	1			T14	1		T34	1		T57	1
auto[StCreatorRootKey]	61	1			T4	1		T15	1		T61	1
auto[StOwnerIntKey]	50	1			T73	1		T66	1		T68	1
auto[StOwnerKey]	33	1			T44	1		T36	1		T72	1
auto[StDisabled]	483	1			T2	1		T49	2		T75	1
auto[StInvalid]	48	1			T35	1		T65	1		T51	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3444

1

T1

1

T2

1

T3

1

auto[1]

107

1

T2

1

T4

1

T44

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1699	1			T5	4		T88	1		T6	1
auto[StReset]	auto[1]	9	1			T39	1		T53	1		T54	1
auto[StInit]	auto[0]	37	1			T14	1		T34	1		T57	1
auto[StInit]	auto[1]	47	1			T8	1		T6	1		T38	1
auto[StCreatorRootKey]	auto[0]	42	1			T15	1		T61	1		T59	1
auto[StCreatorRootKey]	auto[1]	19	1			T4	1		T60	1		T243	1
auto[StOwnerIntKey]	auto[0]	38	1			T73	1		T66	1		T68	1
auto[StOwnerIntKey]	auto[1]	12	1			T70	1		T244	1		T245	1
auto[StOwnerKey]	auto[0]	23	1			T36	1		T72	1		T122	2
auto[StOwnerKey]	auto[1]	10	1			T44	1		T6	1		T46	1
auto[StDisabled]	auto[0]	473	1			T49	2		T75	1		T5	10
auto[StDisabled]	auto[1]	10	1			T2	1		T5	2		T6	1
auto[StInvalid]	auto[0]	48	1			T35	1		T65	1		T51	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	6	1			T53	1		T54	1		T55	1
auto[StReset]	auto[OpGenSwOut]	2	1			T246	1		T247	1		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T39	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	17	1			T208	1		T70	1		T248	1
auto[StInit]	auto[OpGenId]	5	1			T7	1		T58	1		T136	1
auto[StInit]	auto[OpGenSwOut]	11	1			T8	1		T208	1		T249	1
auto[StInit]	auto[OpGenHwOut]	14	1			T6	1		T38	1		T47	1
auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T4	1		T243	1		T83	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T250	1		T251	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T60	1		T252	1		T209	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T253	1		T254	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T244	1		T245	1		T255	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T256	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T70	1		T187	1		T257	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T255	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	4	1			T44	1		T46	1		T258	1
auto[StOwnerKey]	auto[OpGenId]	3	1			T259	2		T260	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	3	1			T6	1		T261	1		T255	1
auto[StDisabled]	auto[OpAdvance]	4	1			T45	1		T262	1		T263	1
auto[StDisabled]	auto[OpGenId]	2	1			T5	1		T6	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T2	1		T262	1		T256	1
auto[StDisabled]	auto[OpGenHwOut]	1	1			T5	1		-	-		-	-