Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4910

1

T1

8

T2

4

T3

8

auto[1]

577

1

T16

1

T41

4

T112

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4910

1

T1

8

T2

4

T3

8

auto[1]

577

1

T16

1

T41

4

T112

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4928

1

T1

2

T2

2

T3

8

auto[1]

559

1

T1

6

T2

2

T13

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4928

1

T1

2

T2

2

T3

8

auto[1]

559

1

T1

6

T2

2

T13

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	393	1			T2	1		T13	1		T16	2
auto[OpGenId]	1157	1			T2	1		T3	3		T4	3
auto[OpGenSwOut]	1214	1			T2	1		T12	2		T13	1
auto[OpGenHwOut]	2652	1			T1	8		T2	1		T3	5
auto[OpDisable]	71	1			T64	1		T5	1		T71	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	393	1			T2	1		T13	1		T16	2
auto[OpGenId]	1157	1			T2	1		T3	3		T4	3
auto[OpGenSwOut]	1214	1			T2	1		T12	2		T13	1
auto[OpGenHwOut]	2652	1			T1	8		T2	1		T3	5
auto[OpDisable]	71	1			T64	1		T5	1		T71	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4898

1

T1

8

T2

4

T3

7

auto[1]

589

1

T3

1

T12

1

T17

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4898

1

T1

8

T2

4

T3

7

auto[1]

589

1

T3

1

T12

1

T17

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5219

1

T1

8

T2

4

T3

8

auto[1]

268

1

T17

4

T129

3

T130

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1950	1			T1	2		T2	2		T3	2
auto[1]	699	1			T1	4		T3	1		T4	1
auto[2]	680	1			T1	1		T3	1		T4	1
auto[3]	722	1			T1	1		T2	1		T3	3
auto[4]	338	1			T2	1		T12	1		T13	1
auto[5]	398	1			T3	1		T16	2		T94	1
auto[6]	347	1			T112	2		T234	1		T223	1
auto[7]	353	1			T16	1		T42	1		T94	3

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1436	1			T2	1		T3	1		T12	1
clear_one[1]	699	1			T1	4		T3	1		T4	1
clear_one[2]	680	1			T1	1		T3	1		T4	1
clear_one[3]	722	1			T1	1		T2	1		T3	3
clear_none	1950	1			T1	2		T2	2		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1074	1			T2	1		T3	4		T4	2
auto[StInit]	677	1			T1	1		T2	1		T4	1
auto[StCreatorRootKey]	577	1			T1	1		T2	1		T13	1
auto[StOwnerIntKey]	537	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	478	1			T1	1		T3	1		T16	1
auto[StDisabled]	1884	1			T1	4		T3	2		T12	3
auto[StInvalid]	260	1			T35	6		T65	2		T51	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1074	1			T2	1		T3	4		T4	2
auto[StInit]	677	1			T1	1		T2	1		T4	1
auto[StCreatorRootKey]	577	1			T1	1		T2	1		T13	1
auto[StOwnerIntKey]	537	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	478	1			T1	1		T3	1		T16	1
auto[StDisabled]	1884	1			T1	4		T3	2		T12	3
auto[StInvalid]	260	1			T35	6		T65	2		T51	1

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[1] - auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[1] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5
[auto[6]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T264	1		T265	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	164	1			T4	1		T42	1		T95	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	172	1			T16	1		T129	1		T35	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	285	1			T2	1		T3	1		T16	1
auto[0]	auto[StInit]	auto[OpAdvance]	32	1			T17	1		T41	1		T230	1
auto[0]	auto[StInit]	auto[OpGenId]	92	1			T12	1		T13	1		T65	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	99	1			T49	2		T229	1		T162	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	191	1			T1	1		T94	1		T112	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	25	1			T59	1		T21	1		T73	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	64	1			T2	1		T48	1		T225	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	55	1			T17	1		T27	1		T65	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	81	1			T94	1		T112	1		T221	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T75	1		T266	1		T267	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	36	1			T3	1		T44	1		T5	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	30	1			T227	1		T184	1		T58	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	66	1			T17	1		T64	1		T71	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T129	1		T268	1		T149	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	20	1			T223	1		T220	1		T212	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	25	1			T42	1		T224	1		T184	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T1	1		T234	1		T221	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	30	1			T41	1		T227	1		T162	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T17	1		T130	1		T162	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	72	1			T12	1		T17	1		T26	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	192	1			T17	1		T112	1		T234	2
auto[0]	auto[StDisabled]	auto[OpDisable]	16	1			T73	1		T184	1		T70	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	13	1			T269	1		T270	1		T271	1
auto[0]	auto[StInvalid]	auto[OpGenId]	18	1			T35	1		T269	1		T272	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T52	1		T269	1		T273	2
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T35	1		T51	1		T100	1
auto[1]	auto[StReset]	auto[OpGenId]	23	1			T4	1		T5	1		T56	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	13	1			T274	1		T59	1		T58	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	62	1			T3	1		T94	1		T95	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T275	1		T150	1		T276	1
auto[1]	auto[StInit]	auto[OpGenId]	13	1			T5	1		T58	1		T153	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T149	1		T277	1		T278	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	18	1			T227	1		T134	1		T70	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T82	1		T279	1		T280	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T73	1		T258	1		T281	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T73	1		T275	1		T282	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T1	1		T222	1		T283	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T129	1		T284	1		T199	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T285	1		T70	1		T286	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T42	1		T59	1		T6	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	31	1			T1	1		T234	1		T5	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T208	1		T287	1		T288	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	14	1			T208	1		T211	1		T258	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T6	1		T184	1		T289	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T222	1		T90	1		T6	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	27	1			T5	1		T134	1		T209	1
auto[1]	auto[StDisabled]	auto[OpGenId]	37	1			T12	1		T5	1		T73	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T225	1		T49	1		T162	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	166	1			T1	2		T13	1		T112	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T6	1		T134	1		T290	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T273	1		T291	1		T292	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T98	1		T293	1		T294	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T35	1		T65	1		T295	2
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T52	1		T99	1		T271	1
auto[2]	auto[StReset]	auto[OpGenId]	18	1			T227	1		T6	1		T122	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	18	1			T133	1		T70	1		T149	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	54	1			T3	1		T234	1		T45	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T129	1		T236	1		T296	1
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T4	1		T56	1		T297	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	18	1			T59	1		T73	1		T6	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	17	1			T235	1		T222	1		T151	2
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T205	1		T258	1		T298	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T26	1		T21	1		T134	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T5	1		T59	1		T299	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T129	2		T235	1		T93	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T162	1		T5	1		T300	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T41	1		T225	1		T58	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T88	1		T208	2		T290	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T12	1		T301	1		T302	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T41	1		T162	2		T70	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	20	1			T16	1		T162	1		T297	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T26	1		T299	1		T134	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T27	1		T59	1		T303	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	18	1			T208	1		T252	1		T202	1
auto[2]	auto[StDisabled]	auto[OpGenId]	58	1			T225	1		T223	1		T27	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T41	1		T225	1		T162	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	134	1			T1	1		T94	1		T95	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T201	1		T249	1		T209	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T304	2		T305	1		T306	1
auto[2]	auto[StInvalid]	auto[OpGenId]	5	1			T101	1		T307	1		T308	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T307	1		T270	1		T272	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T100	1		T295	1		T309	3
auto[3]	auto[StReset]	auto[OpGenId]	20	1			T42	1		T45	1		T310	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	17	1			T5	1		T258	2		T311	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	54	1			T236	1		T5	1		T93	2
auto[3]	auto[StInit]	auto[OpAdvance]	11	1			T300	2		T312	1		T208	1
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T208	1		T313	1		T107	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T137	1		T314	3		T315	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	23	1			T27	1		T6	2		T316	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T291	1		T317	2		T318	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T13	1		T45	1		T208	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T81	1		T319	1		T320	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T89	1		T321	1		T322	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T2	1		T323	1		T87	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T27	1		T300	1		T258	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T6	1		T70	1		T258	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	49	1			T230	1		T221	1		T59	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T300	2		T314	1		T324	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	19	1			T3	1		T6	1		T199	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T49	1		T73	1		T184	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T94	1		T129	1		T89	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	23	1			T73	1		T325	1		T208	1
auto[3]	auto[StDisabled]	auto[OpGenId]	62	1			T3	1		T95	1		T139	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	70	1			T13	1		T223	1		T227	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	142	1			T1	1		T3	1		T112	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T59	1		T326	1		T70	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	7	1			T99	1		T272	1		T327	1
auto[3]	auto[StInvalid]	auto[OpGenId]	9	1			T239	1		T118	1		T328	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T101	1		T99	1		T329	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T35	1		T52	1		T308	1
auto[4]	auto[StReset]	auto[OpGenId]	11	1			T6	1		T258	1		T330	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	11	1			T95	1		T70	1		T137	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	19	1			T234	1		T303	1		T310	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T106	1		T240	1		T331	1
auto[4]	auto[StInit]	auto[OpGenId]	6	1			T332	1		T329	1		T97	2
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T2	1		T333	1		T334	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	17	1			T321	1		T335	1		T336	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T337	1		T185	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T338	1		T279	1		T339	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T340	1		T107	1		T105	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T213	1		T341	1		T200	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T13	1		T67	1		T134	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T65	1		T299	1		T342	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T122	1		T144	1		T343	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T235	1		T321	1		T344	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T225	1		T70	1		T345	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	4	1			T261	1		T346	1		T347	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T5	1		T107	1		T330	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T348	1		T335	1		T70	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	12	1			T5	1		T333	1		T153	1
auto[4]	auto[StDisabled]	auto[OpGenId]	26	1			T6	1		T233	1		T134	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	37	1			T12	1		T5	1		T73	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T94	1		T48	1		T235	1
auto[4]	auto[StDisabled]	auto[OpDisable]	4	1			T214	1		T349	1		T257	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T35	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	12	1			T52	1		T270	1		T239	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T271	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T65	1		T100	2		T350	1
auto[5]	auto[StReset]	auto[OpGenId]	13	1			T59	1		T285	1		T134	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T274	1		T310	1		T70	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	30	1			T3	1		T222	2		T56	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T351	1		T352	1		T259	1
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T26	1		T133	1		T353	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T199	1		T255	1		T354	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	8	1			T16	1		T322	1		T203	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T16	1		T338	1		T209	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T355	1		T258	1		T356	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T6	1		T134	1		T290	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T357	1		T184	1		T358	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T359	1		T22	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T49	1		T80	1		T326	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T232	1		T360	1		T70	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T94	1		T5	1		T59	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T6	1		T361	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T362	1		T244	2		T298	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T134	1		T363	1		T364	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T44	1		T93	1		T145	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	12	1			T302	1		T300	1		T325	1
auto[5]	auto[StDisabled]	auto[OpGenId]	39	1			T365	1		T184	2		T300	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T88	1		T73	1		T6	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	87	1			T59	1		T232	1		T89	2
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T5	1		T71	1		T133	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T292	1		T366	1		T328	2
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T307	1		T308	1		T367	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T329	1		T305	2		T368	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T304	1		T327	1		T292	1
auto[6]	auto[StReset]	auto[OpAdvance]	2	1			T369	1		T281	1		-	-
auto[6]	auto[StReset]	auto[OpGenId]	5	1			T208	1		T315	1		T370	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	6	1			T269	1		T70	1		T371	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	24	1			T38	1		T58	1		T70	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T162	1		T268	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T289	1		T372	1		T373	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T374	1		T375	1		T82	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	9	1			T59	1		T376	1		T377	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T149	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T236	1		T332	1		T378	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T302	1		T149	1		T379	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T234	1		T162	1		T303	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T369	1		-	-		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T49	1		T162	1		T184	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T6	1		T380	1		T381	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T112	1		T145	1		T382	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T59	1		T383	1		T384	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	2	1			T70	1		T153	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T6	1		T258	1		T278	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T112	1		T92	1		T385	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	6	1			T90	1		T153	1		T386	2
auto[6]	auto[StDisabled]	auto[OpGenId]	32	1			T49	2		T387	1		T184	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T223	1		T26	1		T5	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	92	1			T49	1		T27	1		T222	1
auto[6]	auto[StDisabled]	auto[OpDisable]	8	1			T64	1		T388	1		T389	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T35	1		T307	1		T390	1
auto[6]	auto[StInvalid]	auto[OpGenId]	3	1			T272	1		T391	1		T368	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T269	1		T307	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T99	1		T291	1		T392	1
auto[7]	auto[StReset]	auto[OpGenId]	11	1			T35	1		T342	1		T258	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T42	1		T52	1		T58	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	20	1			T94	1		T51	1		T56	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T16	1		T152	1		T256	1
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T252	1		T393	1		T394	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T122	1		T208	1		T103	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	18	1			T59	1		T283	1		T58	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T229	1		-	-		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T395	1		T396	1		T397	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T79	1		T209	1		T398	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T88	1		T21	1		T203	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T399	1		-	-		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T184	1		T332	1		T24	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T275	1		T400	1		T401	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T222	1		T92	1		T402	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T233	1		T403	1		T404	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	7	1			T134	1		T405	1		T406	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T71	1		T332	1		T262	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T235	1		T301	1		T382	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	9	1			T5	2		T407	1		T408	1
auto[7]	auto[StDisabled]	auto[OpGenId]	24	1			T302	1		T233	1		T70	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T232	1		T88	1		T299	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T94	2		T112	1		T49	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T357	1		T208	1		T217	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T304	1		T271	1		T293	1
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T52	1		T99	1		T329	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T67	1		T272	1		T409	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T366	1		T294	1		T410	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1436

1

T2

1

T3

1

T12

1

clear_one[1]

auto[0]

auto[0]

auto[0]

416

1

T3

1

T4

1

T94

1

clear_one[1]

auto[0]

auto[0]

auto[1]

123

1

T12

1

T234

1

T129

1

clear_one[1]

auto[0]

auto[1]

auto[0]

123

1

T1

4

T13

1

T42

1

clear_one[1]

auto[0]

auto[1]

auto[1]

37

1

T90

1

T275

1

T184

1

clear_one[2]

auto[0]

auto[0]

auto[0]

393

1

T1

1

T3

1

T4

1

clear_one[2]

auto[0]

auto[0]

auto[1]

123

1

T95

1

T234

1

T129

1

clear_one[2]

auto[1]

auto[0]

auto[0]

121

1

T16

1

T225

1

T26

1

clear_one[2]

auto[1]

auto[0]

auto[1]

43

1

T41

3

T6

1

T208

1

clear_one[3]

auto[0]

auto[0]

auto[0]

415

1

T3

3

T13

1

T42

1

clear_one[3]

auto[0]

auto[1]

auto[0]

117

1

T1

1

T2

1

T13

1

clear_one[3]

auto[1]

auto[0]

auto[0]

147

1

T112

1

T129

1

T223

1

clear_one[3]

auto[1]

auto[1]

auto[0]

43

1

T59

2

T411

1

T300

2

clear_none

auto[0]

auto[0]

auto[0]

1391

1

T1

1

T2

1

T3

1

clear_none

auto[0]

auto[0]

auto[1]

161

1

T3

1

T234

3

T130

1

clear_none

auto[0]

auto[1]

auto[0]

125

1

T1

1

T2

1

T17

1

clear_none

auto[0]

auto[1]

auto[1]

50

1

T17

4

T139

2

T73

2

clear_none

auto[1]

auto[0]

auto[0]

132

1

T112

2

T225

1

T129

1

clear_none

auto[1]

auto[0]

auto[1]

27

1

T41

1

T227

2

T411

1

clear_none

auto[1]

auto[1]

auto[0]

39

1

T129

1

T71

1

T46

1

clear_none

auto[1]

auto[1]

auto[1]

25

1

T71

1

T387

1

T184

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1363	1			T2	1		T3	1		T12	1
clear_all	auto[1]	73	1			T162	2		T300	4		T359	3
clear_one[1]	auto[0]	672	1			T1	4		T3	1		T4	1
clear_one[1]	auto[1]	27	1			T162	1		T276	1		T287	2
clear_one[2]	auto[0]	652	1			T1	1		T3	1		T4	1
clear_one[2]	auto[1]	28	1			T129	2		T162	4		T300	3
clear_one[3]	auto[0]	666	1			T1	1		T2	1		T3	3
clear_one[3]	auto[1]	56	1			T300	4		T151	8		T202	2
clear_none	auto[0]	1866	1			T1	2		T2	2		T3	2
clear_none	auto[1]	84	1			T17	4		T129	1		T130	4