Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11775

1

T1

4

T2

6

T3

13

auto[Attestation]

8053

1

T1

4

T2

6

T3

7

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2934	1			T3	4		T4	1		T13	4
auto[Aes]	3559	1			T3	2		T13	2		T14	1
auto[Kmac]	3532	1			T1	8		T2	6		T3	2
auto[Otbn]	3604	1			T2	2		T3	6		T12	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7982	1			T1	8		T2	5		T3	8
auto[OpGenId]	6199	1			T2	4		T3	6		T4	5
auto[OpGenSwOut]	6259	1			T2	3		T3	5		T4	1
auto[OpGenHwOut]	7370	1			T1	8		T2	5		T3	9
auto[OpDisable]	140	1			T48	1		T49	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11121

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

16829

1

T1

8

T2

9

T3

20

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6801	1			T1	1		T2	6		T3	13
auto[StInit]	3990	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3360	1			T1	2		T2	4		T3	2
auto[StOwnerIntKey]	2933	1			T1	2		T2	1		T3	2
auto[StOwnerKey]	2545	1			T1	2		T2	1		T3	2
auto[StDisabled]	8321	1			T1	7		T2	3		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	315	1			T3	2		T16	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	137	1			T223	1		T36	1		T140	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T17	1		T36	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	74	1			T17	1		T223	1		T224	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T42	1		T5	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	243	1			T17	1		T225	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	331	1			T3	1		T16	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	96	1			T75	1		T56	1		T226	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	97	1			T41	1		T44	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	73	1			T227	1		T5	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T42	1		T129	2		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	227	1			T41	2		T129	1		T228	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	365	1			T42	1		T129	4		T35	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	91	1			T229	1		T64	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T2	1		T49	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T42	1		T229	1		T139	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	72	1			T17	1		T230	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	237	1			T13	1		T41	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	360	1			T129	1		T35	2		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	125	1			T15	1		T16	2		T95	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	78	1			T13	1		T42	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	60	1			T42	1		T231	1		T232	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	51	1			T49	1		T140	1		T72	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	243	1			T12	1		T225	1		T129	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	89	1			T59	3		T73	3		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	140	1			T3	1		T16	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	93	1			T4	1		T5	2		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	75	1			T16	1		T17	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	87	1			T95	1		T139	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	215	1			T17	1		T41	1		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	84	1			T59	1		T88	1		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	133	1			T15	1		T49	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	92	1			T27	1		T64	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	59	1			T26	1		T139	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	64	1			T42	1		T71	1		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	234	1			T13	1		T95	1		T223	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	77	1			T88	1		T6	1		T233	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	94	1			T2	1		T220	1		T162	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	70	1			T13	1		T44	1		T227	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T16	1		T223	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	57	1			T231	1		T220	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	233	1			T12	1		T17	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	85	1			T59	3		T88	1		T73	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T16	1		T34	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T225	1		T228	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T228	1		T140	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	53	1			T129	1		T228	1		T141	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	224	1			T2	1		T3	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	305	1			T3	1		T13	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T42	1		T95	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	74	1			T36	1		T162	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	62	1			T17	1		T230	1		T73	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T162	1		T6	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	188	1			T13	1		T95	1		T225	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	503	1			T3	1		T16	3		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	113	1			T14	1		T16	1		T223	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	122	1			T41	1		T112	1		T225	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	97	1			T42	1		T223	1		T229	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	99	1			T112	1		T27	1		T222	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	312	1			T13	1		T48	1		T112	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	512	1			T2	3		T3	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	119	1			T94	1		T140	2		T59	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T4	1		T15	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	117	1			T1	1		T12	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	97	1			T1	1		T42	2		T94	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	285	1			T1	2		T13	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	521	1			T3	3		T13	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	122	1			T15	1		T48	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	122	1			T3	1		T17	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T234	1		T229	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	90	1			T13	2		T42	2		T234	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	278	1			T13	1		T41	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	73	1			T59	5		T88	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	101	1			T14	1		T27	1		T162	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	81	1			T223	1		T162	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T229	1		T162	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T13	1		T230	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	174	1			T13	1		T17	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	55	1			T59	4		T88	1		T184	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	126	1			T16	1		T95	1		T112	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	106	1			T227	1		T75	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	105	1			T16	1		T41	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	87	1			T42	1		T129	2		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	285	1			T112	3		T225	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	69	1			T59	1		T122	2		T184	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	126	1			T1	1		T16	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T1	1		T2	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	102	1			T17	2		T94	1		T235	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	80	1			T13	1		T95	1		T230	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	285	1			T1	2		T17	1		T94	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	59	1			T208	5		T134	3		T70	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	114	1			T16	2		T95	1		T234	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	123	1			T41	1		T234	1		T236	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	113	1			T41	1		T221	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	90	1			T44	1		T27	1		T162	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	296	1			T2	1		T3	1		T12	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	202	1			T17	2		T42	1		T223	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	704	1			T3	2		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	210	1			T41	1		T42	1		T129	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	673	1			T3	1		T16	1		T41	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	221	1			T2	1		T17	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	712	1			T13	1		T41	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	182	1			T13	1		T42	2		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	735	1			T12	1		T15	1		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	231	1			T4	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	468	1			T3	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	192	1			T42	1		T26	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	474	1			T13	1		T15	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	179	1			T13	1		T16	1		T223	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	418	1			T2	1		T12	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	220	1			T225	1		T129	1		T228	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	438	1			T2	1		T3	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	184	1			T17	1		T230	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	595	1			T3	1		T13	2		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	302	1			T41	1		T42	1		T112	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	944	1			T3	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	301	1			T1	2		T4	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	929	1			T1	2		T2	3		T3	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	301	1			T3	1		T13	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	933	1			T3	3		T13	3		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	177	1			T13	1		T223	1		T230	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	373	1			T13	1		T14	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	285	1			T16	1		T41	1		T42	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	479	1			T16	1		T95	1		T112	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	279	1			T1	1		T2	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	493	1			T1	3		T16	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	308	1			T41	2		T234	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	487	1			T2	1		T3	1		T12	1