Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34008

1

T1

20

T2

21

T3

32

auto[1]

299

1

T17

4

T129

3

T130

16

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	34012	1			T1	20		T2	21		T3	32
auto[134217728:268435455]	8	1			T129	1		T151	1		T202	1
auto[268435456:402653183]	11	1			T130	3		T300	1		T338	1
auto[402653184:536870911]	14	1			T17	1		T300	3		T276	1
auto[536870912:671088639]	10	1			T300	2		T408	1		T428	1
auto[671088640:805306367]	12	1			T129	1		T130	1		T300	1
auto[805306368:939524095]	7	1			T17	1		T130	1		T287	1
auto[939524096:1073741823]	9	1			T162	1		T205	1		T324	1
auto[1073741824:1207959551]	6	1			T276	1		T429	1		T383	1
auto[1207959552:1342177279]	8	1			T300	1		T151	1		T314	1
auto[1342177280:1476395007]	15	1			T130	2		T162	1		T287	1
auto[1476395008:1610612735]	6	1			T276	1		T394	1		T314	1
auto[1610612736:1744830463]	11	1			T162	1		T151	1		T430	1
auto[1744830464:1879048191]	4	1			T287	1		T264	1		T280	1
auto[1879048192:2013265919]	12	1			T130	2		T205	1		T276	1
auto[2013265920:2147483647]	10	1			T300	1		T276	1		T430	1
auto[2147483648:2281701375]	9	1			T202	1		T430	1		T408	1
auto[2281701376:2415919103]	16	1			T162	1		T151	2		T287	2
auto[2415919104:2550136831]	7	1			T162	1		T202	2		T338	1
auto[2550136832:2684354559]	14	1			T17	1		T162	1		T287	1
auto[2684354560:2818572287]	7	1			T130	1		T300	1		T338	1
auto[2818572288:2952790015]	7	1			T151	1		T430	1		T394	1
auto[2952790016:3087007743]	9	1			T130	1		T338	2		T314	1
auto[3087007744:3221225471]	7	1			T338	1		T369	1		T431	1
auto[3221225472:3355443199]	9	1			T130	3		T300	1		T205	1
auto[3355443200:3489660927]	7	1			T300	1		T113	1		T280	1
auto[3489660928:3623878655]	10	1			T202	1		T276	2		T430	1
auto[3623878656:3758096383]	12	1			T130	1		T205	1		T430	2
auto[3758096384:3892314111]	4	1			T202	1		T431	1		T432	1
auto[3892314112:4026531839]	12	1			T369	1		T281	1		T386	1
auto[4026531840:4160749567]	8	1			T17	1		T205	1		T276	1
auto[4160749568:4294967295]	14	1			T129	1		T130	1		T151	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	34008	1			T1	20		T2	21		T3	32
auto[0:134217727]	auto[1]	4	1			T338	1		T433	1		T317	1
auto[134217728:268435455]	auto[1]	8	1			T129	1		T151	1		T202	1
auto[268435456:402653183]	auto[1]	11	1			T130	3		T300	1		T338	1
auto[402653184:536870911]	auto[1]	14	1			T17	1		T300	3		T276	1
auto[536870912:671088639]	auto[1]	10	1			T300	2		T408	1		T428	1
auto[671088640:805306367]	auto[1]	12	1			T129	1		T130	1		T300	1
auto[805306368:939524095]	auto[1]	7	1			T17	1		T130	1		T287	1
auto[939524096:1073741823]	auto[1]	9	1			T162	1		T205	1		T324	1
auto[1073741824:1207959551]	auto[1]	6	1			T276	1		T429	1		T383	1
auto[1207959552:1342177279]	auto[1]	8	1			T300	1		T151	1		T314	1
auto[1342177280:1476395007]	auto[1]	15	1			T130	2		T162	1		T287	1
auto[1476395008:1610612735]	auto[1]	6	1			T276	1		T394	1		T314	1
auto[1610612736:1744830463]	auto[1]	11	1			T162	1		T151	1		T430	1
auto[1744830464:1879048191]	auto[1]	4	1			T287	1		T264	1		T280	1
auto[1879048192:2013265919]	auto[1]	12	1			T130	2		T205	1		T276	1
auto[2013265920:2147483647]	auto[1]	10	1			T300	1		T276	1		T430	1
auto[2147483648:2281701375]	auto[1]	9	1			T202	1		T430	1		T408	1
auto[2281701376:2415919103]	auto[1]	16	1			T162	1		T151	2		T287	2
auto[2415919104:2550136831]	auto[1]	7	1			T162	1		T202	2		T338	1
auto[2550136832:2684354559]	auto[1]	14	1			T17	1		T162	1		T287	1
auto[2684354560:2818572287]	auto[1]	7	1			T130	1		T300	1		T338	1
auto[2818572288:2952790015]	auto[1]	7	1			T151	1		T430	1		T394	1
auto[2952790016:3087007743]	auto[1]	9	1			T130	1		T338	2		T314	1
auto[3087007744:3221225471]	auto[1]	7	1			T338	1		T369	1		T431	1
auto[3221225472:3355443199]	auto[1]	9	1			T130	3		T300	1		T205	1
auto[3355443200:3489660927]	auto[1]	7	1			T300	1		T113	1		T280	1
auto[3489660928:3623878655]	auto[1]	10	1			T202	1		T276	2		T430	1
auto[3623878656:3758096383]	auto[1]	12	1			T130	1		T205	1		T430	2
auto[3758096384:3892314111]	auto[1]	4	1			T202	1		T431	1		T432	1
auto[3892314112:4026531839]	auto[1]	12	1			T369	1		T281	1		T386	1
auto[4026531840:4160749567]	auto[1]	8	1			T17	1		T205	1		T276	1
auto[4160749568:4294967295]	auto[1]	14	1			T129	1		T130	1		T151	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1678

1

T2

5

T4

1

T16

2

auto[1]

1800

1

T2

2

T4

3

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T17	1		T5	1		T60	1
auto[134217728:268435455]	102	1			T17	1		T129	1		T140	1
auto[268435456:402653183]	113	1			T44	1		T236	1		T139	1
auto[402653184:536870911]	119	1			T16	1		T42	1		T5	1
auto[536870912:671088639]	119	1			T44	1		T49	1		T140	1
auto[671088640:805306367]	110	1			T4	1		T26	1		T49	1
auto[805306368:939524095]	112	1			T41	1		T95	1		T129	1
auto[939524096:1073741823]	109	1			T44	1		T35	1		T227	1
auto[1073741824:1207959551]	114	1			T2	1		T44	1		T26	1
auto[1207959552:1342177279]	103	1			T13	1		T17	1		T225	1
auto[1342177280:1476395007]	83	1			T26	2		T64	1		T5	1
auto[1476395008:1610612735]	128	1			T16	1		T220	1		T65	1
auto[1610612736:1744830463]	115	1			T2	1		T50	1		T5	1
auto[1744830464:1879048191]	106	1			T2	1		T130	1		T162	1
auto[1879048192:2013265919]	109	1			T41	1		T44	1		T35	1
auto[2013265920:2147483647]	90	1			T220	1		T65	1		T73	2
auto[2147483648:2281701375]	108	1			T4	1		T130	1		T5	1
auto[2281701376:2415919103]	103	1			T16	1		T230	1		T35	1
auto[2415919104:2550136831]	118	1			T42	1		T95	1		T229	1
auto[2550136832:2684354559]	102	1			T48	1		T130	2		T220	1
auto[2684354560:2818572287]	118	1			T2	1		T16	1		T44	1
auto[2818572288:2952790015]	93	1			T13	1		T227	1		T236	1
auto[2952790016:3087007743]	122	1			T13	1		T48	1		T95	1
auto[3087007744:3221225471]	97	1			T41	1		T35	1		T65	1
auto[3221225472:3355443199]	136	1			T225	1		T129	1		T35	2
auto[3355443200:3489660927]	106	1			T4	1		T42	1		T95	1
auto[3489660928:3623878655]	103	1			T51	2		T73	1		T360	1
auto[3623878656:3758096383]	93	1			T2	2		T95	1		T225	1
auto[3758096384:3892314111]	117	1			T4	1		T51	1		T59	1
auto[3892314112:4026531839]	92	1			T2	1		T17	1		T35	1
auto[4026531840:4160749567]	100	1			T129	1		T223	1		T230	1
auto[4160749568:4294967295]	125	1			T95	1		T35	1		T26	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T5	1		T73	1		T6	1
auto[0:134217727]	auto[1]	57	1			T17	1		T60	1		T73	1
auto[134217728:268435455]	auto[0]	44	1			T17	1		T69	1		T233	1
auto[134217728:268435455]	auto[1]	58	1			T129	1		T140	1		T73	1
auto[268435456:402653183]	auto[0]	60	1			T236	1		T139	1		T5	1
auto[268435456:402653183]	auto[1]	53	1			T44	1		T140	1		T6	1
auto[402653184:536870911]	auto[0]	61	1			T16	1		T6	1		T208	2
auto[402653184:536870911]	auto[1]	58	1			T42	1		T5	1		T59	1
auto[536870912:671088639]	auto[0]	66	1			T44	1		T140	1		T80	1
auto[536870912:671088639]	auto[1]	53	1			T49	1		T90	1		T122	4
auto[671088640:805306367]	auto[0]	59	1			T26	1		T51	1		T274	1
auto[671088640:805306367]	auto[1]	51	1			T4	1		T49	1		T220	1
auto[805306368:939524095]	auto[0]	55	1			T129	1		T26	1		T227	1
auto[805306368:939524095]	auto[1]	57	1			T41	1		T95	1		T44	1
auto[939524096:1073741823]	auto[0]	56	1			T227	1		T5	2		T51	1
auto[939524096:1073741823]	auto[1]	53	1			T44	1		T35	1		T5	1
auto[1073741824:1207959551]	auto[0]	50	1			T44	1		T26	1		T274	1
auto[1073741824:1207959551]	auto[1]	64	1			T2	1		T227	1		T64	1
auto[1207959552:1342177279]	auto[0]	51	1			T21	1		T360	1		T434	1
auto[1207959552:1342177279]	auto[1]	52	1			T13	1		T17	1		T225	1
auto[1342177280:1476395007]	auto[0]	46	1			T26	1		T64	1		T59	1
auto[1342177280:1476395007]	auto[1]	37	1			T26	1		T5	1		T269	1
auto[1476395008:1610612735]	auto[0]	54	1			T65	1		T357	1		T411	1
auto[1476395008:1610612735]	auto[1]	74	1			T16	1		T220	1		T5	1
auto[1610612736:1744830463]	auto[0]	62	1			T2	1		T274	1		T59	1
auto[1610612736:1744830463]	auto[1]	53	1			T50	1		T5	1		T59	1
auto[1744830464:1879048191]	auto[0]	53	1			T2	1		T73	1		T233	1
auto[1744830464:1879048191]	auto[1]	53	1			T130	1		T162	1		T64	1
auto[1879048192:2013265919]	auto[0]	39	1			T41	1		T35	1		T162	1
auto[1879048192:2013265919]	auto[1]	70	1			T44	1		T75	1		T59	1
auto[2013265920:2147483647]	auto[0]	49	1			T65	1		T73	1		T6	2
auto[2013265920:2147483647]	auto[1]	41	1			T220	1		T73	1		T184	1
auto[2147483648:2281701375]	auto[0]	50	1			T4	1		T52	1		T67	1
auto[2147483648:2281701375]	auto[1]	58	1			T130	1		T5	1		T6	1
auto[2281701376:2415919103]	auto[0]	50	1			T274	1		T80	1		T88	1
auto[2281701376:2415919103]	auto[1]	53	1			T16	1		T230	1		T35	1
auto[2415919104:2550136831]	auto[0]	60	1			T42	1		T95	1		T5	1
auto[2415919104:2550136831]	auto[1]	58	1			T229	1		T71	1		T73	1
auto[2550136832:2684354559]	auto[0]	43	1			T130	1		T21	1		T184	1
auto[2550136832:2684354559]	auto[1]	59	1			T48	1		T130	1		T220	1
auto[2684354560:2818572287]	auto[0]	57	1			T2	1		T16	1		T44	1
auto[2684354560:2818572287]	auto[1]	61	1			T411	1		T184	1		T58	1
auto[2818572288:2952790015]	auto[0]	39	1			T227	1		T326	1		T122	1
auto[2818572288:2952790015]	auto[1]	54	1			T13	1		T236	1		T51	1
auto[2952790016:3087007743]	auto[0]	57	1			T223	1		T162	1		T75	1
auto[2952790016:3087007743]	auto[1]	65	1			T13	1		T48	1		T95	1
auto[3087007744:3221225471]	auto[0]	44	1			T65	1		T5	2		T269	1
auto[3087007744:3221225471]	auto[1]	53	1			T41	1		T35	1		T5	1
auto[3221225472:3355443199]	auto[0]	66	1			T35	1		T227	1		T5	3
auto[3221225472:3355443199]	auto[1]	70	1			T225	1		T129	1		T35	1
auto[3355443200:3489660927]	auto[0]	50	1			T42	1		T129	1		T162	1
auto[3355443200:3489660927]	auto[1]	56	1			T4	1		T95	1		T49	2
auto[3489660928:3623878655]	auto[0]	46	1			T51	1		T224	1		T74	1
auto[3489660928:3623878655]	auto[1]	57	1			T51	1		T73	1		T360	1
auto[3623878656:3758096383]	auto[0]	46	1			T2	1		T220	1		T139	1
auto[3623878656:3758096383]	auto[1]	47	1			T2	1		T95	1		T225	1
auto[3758096384:3892314111]	auto[0]	58	1			T51	1		T59	1		T28	1
auto[3758096384:3892314111]	auto[1]	59	1			T4	1		T28	1		T6	1
auto[3892314112:4026531839]	auto[0]	39	1			T2	1		T35	1		T59	1
auto[3892314112:4026531839]	auto[1]	53	1			T17	1		T27	1		T5	1
auto[4026531840:4160749567]	auto[0]	49	1			T130	1		T220	2		T139	1
auto[4026531840:4160749567]	auto[1]	51	1			T129	1		T223	1		T230	1
auto[4160749568:4294967295]	auto[0]	63	1			T236	1		T122	1		T47	1
auto[4160749568:4294967295]	auto[1]	62	1			T95	1		T35	1		T26	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1710

1

T2

6

T4

1

T16

2

auto[1]

1767

1

T2

1

T4

3

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T41	1		T44	2		T26	1
auto[134217728:268435455]	85	1			T13	1		T44	1		T35	1
auto[268435456:402653183]	106	1			T225	1		T35	1		T49	1
auto[402653184:536870911]	116	1			T27	1		T220	1		T75	1
auto[536870912:671088639]	98	1			T95	1		T5	1		T59	1
auto[671088640:805306367]	99	1			T16	1		T42	1		T48	1
auto[805306368:939524095]	119	1			T2	1		T130	2		T35	1
auto[939524096:1073741823]	99	1			T16	1		T17	1		T129	1
auto[1073741824:1207959551]	92	1			T17	1		T44	1		T220	1
auto[1207959552:1342177279]	119	1			T2	1		T35	1		T274	1
auto[1342177280:1476395007]	111	1			T5	1		T274	1		T59	1
auto[1476395008:1610612735]	110	1			T95	1		T65	1		T71	1
auto[1610612736:1744830463]	104	1			T26	1		T274	1		T59	1
auto[1744830464:1879048191]	110	1			T4	1		T48	1		T26	1
auto[1879048192:2013265919]	120	1			T42	1		T129	1		T26	1
auto[2013265920:2147483647]	98	1			T13	1		T16	1		T129	1
auto[2147483648:2281701375]	112	1			T236	1		T220	1		T162	1
auto[2281701376:2415919103]	101	1			T16	1		T95	2		T75	1
auto[2415919104:2550136831]	113	1			T4	1		T17	1		T220	1
auto[2550136832:2684354559]	112	1			T49	2		T162	1		T139	1
auto[2684354560:2818572287]	105	1			T44	1		T230	2		T35	1
auto[2818572288:2952790015]	101	1			T4	1		T95	1		T35	1
auto[2952790016:3087007743]	100	1			T2	1		T13	1		T44	1
auto[3087007744:3221225471]	114	1			T95	1		T129	1		T227	1
auto[3221225472:3355443199]	126	1			T2	2		T225	1		T223	1
auto[3355443200:3489660927]	95	1			T2	1		T41	1		T225	1
auto[3489660928:3623878655]	95	1			T5	1		T274	1		T6	3
auto[3623878656:3758096383]	122	1			T5	1		T51	2		T73	1
auto[3758096384:3892314111]	147	1			T17	1		T41	1		T44	1
auto[3892314112:4026531839]	112	1			T2	1		T42	1		T129	1
auto[4026531840:4160749567]	113	1			T4	1		T35	1		T220	1
auto[4160749568:4294967295]	118	1			T130	1		T35	1		T227	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T26	1		T227	1		T233	1
auto[0:134217727]	auto[1]	50	1			T41	1		T44	2		T5	1
auto[134217728:268435455]	auto[0]	42	1			T44	1		T73	1		T6	1
auto[134217728:268435455]	auto[1]	43	1			T13	1		T35	1		T5	1
auto[268435456:402653183]	auto[0]	51	1			T75	1		T6	3		T434	1
auto[268435456:402653183]	auto[1]	55	1			T225	1		T35	1		T49	1
auto[402653184:536870911]	auto[0]	46	1			T59	1		T420	1		T282	1
auto[402653184:536870911]	auto[1]	70	1			T27	1		T220	1		T75	1
auto[536870912:671088639]	auto[0]	52	1			T5	1		T21	1		T282	1
auto[536870912:671088639]	auto[1]	46	1			T95	1		T59	1		T73	1
auto[671088640:805306367]	auto[0]	49	1			T16	1		T42	1		T227	1
auto[671088640:805306367]	auto[1]	50	1			T48	1		T5	1		T73	1
auto[805306368:939524095]	auto[0]	55	1			T130	1		T35	1		T236	1
auto[805306368:939524095]	auto[1]	64	1			T2	1		T130	1		T220	1
auto[939524096:1073741823]	auto[0]	58	1			T17	1		T5	3		T80	1
auto[939524096:1073741823]	auto[1]	41	1			T16	1		T129	1		T5	1
auto[1073741824:1207959551]	auto[0]	45	1			T17	1		T44	1		T220	1
auto[1073741824:1207959551]	auto[1]	47	1			T56	1		T6	2		T420	2
auto[1207959552:1342177279]	auto[0]	62	1			T2	1		T274	1		T52	1
auto[1207959552:1342177279]	auto[1]	57	1			T35	1		T355	1		T224	1
auto[1342177280:1476395007]	auto[0]	48	1			T274	1		T6	1		T47	1
auto[1342177280:1476395007]	auto[1]	63	1			T5	1		T59	1		T88	1
auto[1476395008:1610612735]	auto[0]	54	1			T90	1		T38	1		T233	1
auto[1476395008:1610612735]	auto[1]	56	1			T95	1		T65	1		T71	1
auto[1610612736:1744830463]	auto[0]	54	1			T26	1		T274	1		T6	1
auto[1610612736:1744830463]	auto[1]	50	1			T59	1		T6	1		T233	1
auto[1744830464:1879048191]	auto[0]	57	1			T236	1		T64	1		T59	1
auto[1744830464:1879048191]	auto[1]	53	1			T4	1		T48	1		T26	1
auto[1879048192:2013265919]	auto[0]	59	1			T42	1		T26	1		T236	1
auto[1879048192:2013265919]	auto[1]	61	1			T129	1		T5	1		T90	1
auto[2013265920:2147483647]	auto[0]	49	1			T129	1		T162	1		T5	2
auto[2013265920:2147483647]	auto[1]	49	1			T13	1		T16	1		T35	1
auto[2147483648:2281701375]	auto[0]	56	1			T236	1		T220	1		T162	1
auto[2147483648:2281701375]	auto[1]	56	1			T140	1		T5	2		T275	1
auto[2281701376:2415919103]	auto[0]	53	1			T16	1		T95	1		T51	1
auto[2281701376:2415919103]	auto[1]	48	1			T95	1		T75	1		T21	1
auto[2415919104:2550136831]	auto[0]	59	1			T4	1		T5	1		T6	1
auto[2415919104:2550136831]	auto[1]	54	1			T17	1		T220	1		T51	1
auto[2550136832:2684354559]	auto[0]	47	1			T162	1		T139	1		T274	1
auto[2550136832:2684354559]	auto[1]	65	1			T49	2		T5	1		T6	1
auto[2684354560:2818572287]	auto[0]	57	1			T230	2		T140	1		T73	1
auto[2684354560:2818572287]	auto[1]	48	1			T44	1		T35	1		T69	1
auto[2818572288:2952790015]	auto[0]	39	1			T35	1		T229	1		T50	1
auto[2818572288:2952790015]	auto[1]	62	1			T4	1		T95	1		T49	1
auto[2952790016:3087007743]	auto[0]	51	1			T2	1		T5	2		T59	2
auto[2952790016:3087007743]	auto[1]	49	1			T13	1		T44	1		T64	1
auto[3087007744:3221225471]	auto[0]	57	1			T95	1		T129	1		T227	1
auto[3087007744:3221225471]	auto[1]	57	1			T139	1		T5	1		T8	1
auto[3221225472:3355443199]	auto[0]	66	1			T2	2		T65	1		T51	1
auto[3221225472:3355443199]	auto[1]	60	1			T225	1		T223	1		T26	1
auto[3355443200:3489660927]	auto[0]	40	1			T2	1		T41	1		T223	1
auto[3355443200:3489660927]	auto[1]	55	1			T225	1		T26	1		T52	1
auto[3489660928:3623878655]	auto[0]	40	1			T5	1		T274	1		T6	1
auto[3489660928:3623878655]	auto[1]	55	1			T6	2		T122	1		T68	1
auto[3623878656:3758096383]	auto[0]	59	1			T5	1		T51	1		T6	1
auto[3623878656:3758096383]	auto[1]	63	1			T51	1		T73	1		T6	1
auto[3758096384:3892314111]	auto[0]	76	1			T44	1		T65	1		T139	1
auto[3758096384:3892314111]	auto[1]	71	1			T17	1		T41	1		T130	2
auto[3892314112:4026531839]	auto[0]	58	1			T2	1		T129	1		T73	1
auto[3892314112:4026531839]	auto[1]	54	1			T42	1		T130	1		T27	1
auto[4026531840:4160749567]	auto[0]	57	1			T35	1		T360	1		T100	1
auto[4026531840:4160749567]	auto[1]	56	1			T4	1		T220	1		T139	1
auto[4160749568:4294967295]	auto[0]	59	1			T227	1		T5	1		T184	1
auto[4160749568:4294967295]	auto[1]	59	1			T130	1		T35	1		T220	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1709

1

T2

5

T4

1

T16

2

auto[1]

1767

1

T2

2

T4

3

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T2	1		T13	1		T16	1
auto[134217728:268435455]	117	1			T13	1		T44	1		T227	1
auto[268435456:402653183]	113	1			T2	1		T139	1		T140	1
auto[402653184:536870911]	105	1			T35	1		T51	1		T59	1
auto[536870912:671088639]	91	1			T41	1		T44	1		T49	1
auto[671088640:805306367]	94	1			T2	1		T95	1		T129	1
auto[805306368:939524095]	122	1			T17	1		T44	1		T5	1
auto[939524096:1073741823]	125	1			T13	1		T225	1		T129	1
auto[1073741824:1207959551]	108	1			T95	1		T130	1		T26	1
auto[1207959552:1342177279]	104	1			T48	1		T35	1		T51	1
auto[1342177280:1476395007]	98	1			T17	2		T41	1		T95	1
auto[1476395008:1610612735]	93	1			T4	1		T44	1		T5	1
auto[1610612736:1744830463]	107	1			T227	1		T220	1		T162	1
auto[1744830464:1879048191]	110	1			T95	1		T130	1		T88	1
auto[1879048192:2013265919]	109	1			T2	1		T4	1		T130	2
auto[2013265920:2147483647]	111	1			T225	1		T35	1		T229	1
auto[2147483648:2281701375]	118	1			T16	1		T129	1		T130	1
auto[2281701376:2415919103]	103	1			T42	1		T48	1		T64	1
auto[2415919104:2550136831]	103	1			T236	1		T5	2		T90	1
auto[2550136832:2684354559]	114	1			T44	1		T130	1		T227	1
auto[2684354560:2818572287]	116	1			T2	1		T4	1		T49	2
auto[2818572288:2952790015]	107	1			T2	1		T223	1		T44	1
auto[2952790016:3087007743]	115	1			T16	1		T95	1		T230	1
auto[3087007744:3221225471]	107	1			T5	1		T56	1		T71	1
auto[3221225472:3355443199]	114	1			T220	1		T5	1		T59	1
auto[3355443200:3489660927]	117	1			T129	1		T75	1		T140	1
auto[3489660928:3623878655]	107	1			T35	1		T27	1		T139	1
auto[3623878656:3758096383]	111	1			T236	1		T220	2		T75	1
auto[3758096384:3892314111]	96	1			T129	1		T35	1		T26	1
auto[3892314112:4026531839]	113	1			T225	1		T35	1		T227	1
auto[4026531840:4160749567]	120	1			T2	1		T16	1		T42	1
auto[4160749568:4294967295]	106	1			T4	1		T41	1		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T2	1		T42	1		T88	1
auto[0:134217727]	auto[1]	48	1			T13	1		T16	1		T17	1
auto[134217728:268435455]	auto[0]	48	1			T51	1		T6	1		T269	1
auto[134217728:268435455]	auto[1]	69	1			T13	1		T44	1		T227	1
auto[268435456:402653183]	auto[0]	56	1			T2	1		T274	1		T6	1
auto[268435456:402653183]	auto[1]	57	1			T139	1		T140	1		T71	1
auto[402653184:536870911]	auto[0]	55	1			T35	1		T51	1		T90	1
auto[402653184:536870911]	auto[1]	50	1			T59	1		T6	1		T208	1
auto[536870912:671088639]	auto[0]	41	1			T44	1		T59	1		T6	1
auto[536870912:671088639]	auto[1]	50	1			T41	1		T49	1		T5	1
auto[671088640:805306367]	auto[0]	46	1			T95	1		T274	1		T80	1
auto[671088640:805306367]	auto[1]	48	1			T2	1		T129	1		T71	1
auto[805306368:939524095]	auto[0]	62	1			T44	1		T5	1		T6	1
auto[805306368:939524095]	auto[1]	60	1			T17	1		T73	1		T6	2
auto[939524096:1073741823]	auto[0]	62	1			T223	1		T51	1		T59	1
auto[939524096:1073741823]	auto[1]	63	1			T13	1		T225	1		T129	1
auto[1073741824:1207959551]	auto[0]	59	1			T95	1		T130	1		T139	1
auto[1073741824:1207959551]	auto[1]	49	1			T26	1		T5	3		T6	1
auto[1207959552:1342177279]	auto[0]	50	1			T35	1		T51	1		T59	1
auto[1207959552:1342177279]	auto[1]	54	1			T48	1		T73	1		T122	1
auto[1342177280:1476395007]	auto[0]	50	1			T17	1		T59	1		T90	1
auto[1342177280:1476395007]	auto[1]	48	1			T17	1		T41	1		T95	1
auto[1476395008:1610612735]	auto[0]	43	1			T5	1		T51	1		T6	1
auto[1476395008:1610612735]	auto[1]	50	1			T4	1		T44	1		T6	1
auto[1610612736:1744830463]	auto[0]	52	1			T65	2		T5	1		T52	1
auto[1610612736:1744830463]	auto[1]	55	1			T227	1		T220	1		T162	1
auto[1744830464:1879048191]	auto[0]	54	1			T90	1		T46	1		T122	1
auto[1744830464:1879048191]	auto[1]	56	1			T95	1		T130	1		T88	1
auto[1879048192:2013265919]	auto[0]	49	1			T4	1		T130	2		T35	1
auto[1879048192:2013265919]	auto[1]	60	1			T2	1		T140	1		T5	1
auto[2013265920:2147483647]	auto[0]	62	1			T139	1		T5	1		T73	1
auto[2013265920:2147483647]	auto[1]	49	1			T225	1		T35	1		T229	1
auto[2147483648:2281701375]	auto[0]	60	1			T16	1		T26	1		T139	1
auto[2147483648:2281701375]	auto[1]	58	1			T129	1		T130	1		T50	1
auto[2281701376:2415919103]	auto[0]	51	1			T5	2		T59	1		T21	1
auto[2281701376:2415919103]	auto[1]	52	1			T42	1		T48	1		T64	1
auto[2415919104:2550136831]	auto[0]	48	1			T236	1		T67	1		T208	1
auto[2415919104:2550136831]	auto[1]	55	1			T5	2		T90	1		T6	2
auto[2550136832:2684354559]	auto[0]	56	1			T122	1		T268	1		T184	1
auto[2550136832:2684354559]	auto[1]	58	1			T44	1		T130	1		T227	1
auto[2684354560:2818572287]	auto[0]	58	1			T2	1		T162	1		T5	1
auto[2684354560:2818572287]	auto[1]	58	1			T4	1		T49	2		T73	1
auto[2818572288:2952790015]	auto[0]	45	1			T2	1		T75	1		T28	1
auto[2818572288:2952790015]	auto[1]	62	1			T223	1		T44	1		T64	1
auto[2952790016:3087007743]	auto[0]	56	1			T162	1		T64	1		T5	1
auto[2952790016:3087007743]	auto[1]	59	1			T16	1		T95	1		T230	1
auto[3087007744:3221225471]	auto[0]	55	1			T5	1		T274	1		T73	1
auto[3087007744:3221225471]	auto[1]	52	1			T56	1		T71	1		T360	1
auto[3221225472:3355443199]	auto[0]	52	1			T59	1		T28	1		T73	1
auto[3221225472:3355443199]	auto[1]	62	1			T220	1		T5	1		T269	1
auto[3355443200:3489660927]	auto[0]	57	1			T129	1		T140	1		T6	1
auto[3355443200:3489660927]	auto[1]	60	1			T75	1		T5	1		T59	1
auto[3489660928:3623878655]	auto[0]	53	1			T27	1		T51	1		T73	1
auto[3489660928:3623878655]	auto[1]	54	1			T35	1		T139	1		T21	1
auto[3623878656:3758096383]	auto[0]	50	1			T236	1		T220	1		T73	1
auto[3623878656:3758096383]	auto[1]	61	1			T220	1		T75	1		T51	1
auto[3758096384:3892314111]	auto[0]	47	1			T26	1		T5	1		T59	1
auto[3758096384:3892314111]	auto[1]	49	1			T129	1		T35	1		T5	3
auto[3892314112:4026531839]	auto[0]	56	1			T227	1		T274	1		T6	1
auto[3892314112:4026531839]	auto[1]	57	1			T225	1		T35	1		T71	1
auto[4026531840:4160749567]	auto[0]	66	1			T2	1		T16	1		T42	1
auto[4026531840:4160749567]	auto[1]	54	1			T220	1		T73	2		T233	2
auto[4160749568:4294967295]	auto[0]	56	1			T41	1		T26	1		T220	1
auto[4160749568:4294967295]	auto[1]	50	1			T4	1		T44	1		T35	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1708

1

T2

5

T4

1

T16

2

auto[1]

1768

1

T2

2

T4

3

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T95	1		T225	1		T223	1
auto[134217728:268435455]	113	1			T16	1		T42	1		T44	1
auto[268435456:402653183]	105	1			T2	1		T4	1		T17	1
auto[402653184:536870911]	118	1			T17	2		T41	1		T95	2
auto[536870912:671088639]	101	1			T2	1		T129	1		T35	2
auto[671088640:805306367]	102	1			T13	1		T35	1		T51	1
auto[805306368:939524095]	113	1			T130	1		T26	1		T229	1
auto[939524096:1073741823]	117	1			T48	1		T26	1		T139	1
auto[1073741824:1207959551]	101	1			T4	1		T35	1		T27	1
auto[1207959552:1342177279]	113	1			T35	1		T26	1		T5	1
auto[1342177280:1476395007]	124	1			T41	1		T236	1		T220	1
auto[1476395008:1610612735]	105	1			T35	1		T227	2		T64	1
auto[1610612736:1744830463]	113	1			T230	1		T51	1		T90	1
auto[1744830464:1879048191]	105	1			T95	1		T44	2		T230	1
auto[1879048192:2013265919]	101	1			T223	1		T220	1		T75	1
auto[2013265920:2147483647]	115	1			T13	1		T17	1		T26	1
auto[2147483648:2281701375]	116	1			T2	2		T16	1		T225	1
auto[2281701376:2415919103]	100	1			T44	1		T35	1		T26	1
auto[2415919104:2550136831]	112	1			T2	1		T130	1		T35	1
auto[2550136832:2684354559]	110	1			T48	1		T225	1		T129	1
auto[2684354560:2818572287]	106	1			T65	1		T139	1		T5	1
auto[2818572288:2952790015]	104	1			T4	1		T16	1		T42	1
auto[2952790016:3087007743]	111	1			T2	1		T65	1		T51	2
auto[3087007744:3221225471]	111	1			T42	1		T5	1		T71	1
auto[3221225472:3355443199]	111	1			T13	1		T49	1		T5	1
auto[3355443200:3489660927]	108	1			T236	1		T65	1		T5	2
auto[3489660928:3623878655]	123	1			T95	1		T236	1		T162	1
auto[3623878656:3758096383]	96	1			T41	1		T44	1		T130	1
auto[3758096384:3892314111]	109	1			T49	1		T64	1		T59	3
auto[3892314112:4026531839]	92	1			T16	1		T220	2		T75	1
auto[4026531840:4160749567]	109	1			T220	1		T5	2		T122	1
auto[4160749568:4294967295]	101	1			T2	1		T4	1		T129	1