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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4720 1 T2 14 T4 8 T17 6
auto[1] 2232 1 T13 6 T16 8 T17 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 196 1 T95 2 T49 2 T236 2
auto[134217728:268435455] 194 1 T13 2 T129 2 T44 2
auto[268435456:402653183] 224 1 T35 4 T26 2 T71 2
auto[402653184:536870911] 264 1 T95 2 T49 2 T139 4
auto[536870912:671088639] 208 1 T230 2 T35 2 T26 2
auto[671088640:805306367] 220 1 T35 2 T75 2 T5 4
auto[805306368:939524095] 180 1 T44 2 T130 2 T227 2
auto[939524096:1073741823] 188 1 T229 2 T5 2 T274 2
auto[1073741824:1207959551] 248 1 T129 2 T44 4 T90 2
auto[1207959552:1342177279] 220 1 T225 2 T130 2 T35 2
auto[1342177280:1476395007] 218 1 T17 2 T75 2 T65 2
auto[1476395008:1610612735] 192 1 T13 2 T26 2 T227 2
auto[1610612736:1744830463] 258 1 T2 2 T95 2 T230 2
auto[1744830464:1879048191] 234 1 T41 2 T129 2 T223 2
auto[1879048192:2013265919] 194 1 T2 2 T16 2 T17 2
auto[2013265920:2147483647] 194 1 T16 4 T95 2 T130 2
auto[2147483648:2281701375] 240 1 T130 2 T5 2 T51 2
auto[2281701376:2415919103] 248 1 T42 2 T64 2 T140 2
auto[2415919104:2550136831] 208 1 T2 4 T129 2 T35 2
auto[2550136832:2684354559] 244 1 T35 2 T26 2 T236 2
auto[2684354560:2818572287] 232 1 T4 2 T225 2 T44 2
auto[2818572288:2952790015] 242 1 T17 2 T41 2 T130 2
auto[2952790016:3087007743] 224 1 T4 2 T27 2 T139 2
auto[3087007744:3221225471] 244 1 T2 2 T17 2 T44 2
auto[3221225472:3355443199] 180 1 T42 2 T225 2 T35 2
auto[3355443200:3489660927] 210 1 T4 2 T236 2 T50 2
auto[3489660928:3623878655] 190 1 T13 2 T130 2 T162 2
auto[3623878656:3758096383] 222 1 T16 2 T95 2 T220 2
auto[3758096384:3892314111] 216 1 T4 2 T5 2 T73 2
auto[3892314112:4026531839] 208 1 T2 2 T48 2 T223 2
auto[4026531840:4160749567] 196 1 T129 2 T227 2 T220 2
auto[4160749568:4294967295] 216 1 T2 2 T41 2 T236 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 136 1 T95 2 T236 2 T5 2
auto[0:134217727] auto[1] 60 1 T49 2 T355 2 T273 2
auto[134217728:268435455] auto[0] 128 1 T129 2 T44 2 T49 2
auto[134217728:268435455] auto[1] 66 1 T13 2 T8 2 T6 2
auto[268435456:402653183] auto[0] 156 1 T35 4 T59 2 T6 2
auto[268435456:402653183] auto[1] 68 1 T26 2 T71 2 T59 2
auto[402653184:536870911] auto[0] 180 1 T95 2 T139 4 T5 2
auto[402653184:536870911] auto[1] 84 1 T49 2 T51 2 T6 2
auto[536870912:671088639] auto[0] 122 1 T230 2 T26 2 T220 2
auto[536870912:671088639] auto[1] 86 1 T35 2 T49 2 T65 2
auto[671088640:805306367] auto[0] 156 1 T75 2 T5 2 T73 4
auto[671088640:805306367] auto[1] 64 1 T35 2 T5 2 T46 2
auto[805306368:939524095] auto[0] 112 1 T44 2 T130 2 T227 2
auto[805306368:939524095] auto[1] 68 1 T5 2 T51 4 T73 2
auto[939524096:1073741823] auto[0] 136 1 T229 2 T5 2 T6 2
auto[939524096:1073741823] auto[1] 52 1 T274 2 T80 2 T45 2
auto[1073741824:1207959551] auto[0] 196 1 T129 2 T44 4 T6 2
auto[1073741824:1207959551] auto[1] 52 1 T90 2 T73 2 T6 2
auto[1207959552:1342177279] auto[0] 138 1 T130 2 T35 2 T140 2
auto[1207959552:1342177279] auto[1] 82 1 T225 2 T64 2 T5 2
auto[1342177280:1476395007] auto[0] 136 1 T17 2 T65 2 T5 4
auto[1342177280:1476395007] auto[1] 82 1 T75 2 T6 6 T269 2
auto[1476395008:1610612735] auto[0] 120 1 T26 2 T5 2 T21 2
auto[1476395008:1610612735] auto[1] 72 1 T13 2 T227 2 T6 2
auto[1610612736:1744830463] auto[0] 172 1 T2 2 T95 2 T230 2
auto[1610612736:1744830463] auto[1] 86 1 T59 2 T6 2 T122 2
auto[1744830464:1879048191] auto[0] 148 1 T41 2 T129 2 T223 2
auto[1744830464:1879048191] auto[1] 86 1 T35 2 T52 2 T6 4
auto[1879048192:2013265919] auto[0] 118 1 T2 2 T48 2 T95 2
auto[1879048192:2013265919] auto[1] 76 1 T16 2 T17 2 T42 2
auto[2013265920:2147483647] auto[0] 132 1 T95 2 T130 2 T27 2
auto[2013265920:2147483647] auto[1] 62 1 T16 4 T6 2 T184 2
auto[2147483648:2281701375] auto[0] 172 1 T130 2 T5 2 T59 2
auto[2147483648:2281701375] auto[1] 68 1 T51 2 T67 2 T341 2
auto[2281701376:2415919103] auto[0] 186 1 T42 2 T64 2 T5 4
auto[2281701376:2415919103] auto[1] 62 1 T140 2 T6 2 T268 2
auto[2415919104:2550136831] auto[0] 144 1 T2 4 T129 2 T35 2
auto[2415919104:2550136831] auto[1] 64 1 T227 2 T5 4 T51 2
auto[2550136832:2684354559] auto[0] 180 1 T35 2 T26 2 T236 2
auto[2550136832:2684354559] auto[1] 64 1 T56 2 T59 2 T21 2
auto[2684354560:2818572287] auto[0] 148 1 T4 2 T44 2 T27 2
auto[2684354560:2818572287] auto[1] 84 1 T225 2 T52 2 T6 2
auto[2818572288:2952790015] auto[0] 160 1 T17 2 T130 2 T26 2
auto[2818572288:2952790015] auto[1] 82 1 T41 2 T357 2 T420 2
auto[2952790016:3087007743] auto[0] 144 1 T4 2 T139 2 T73 2
auto[2952790016:3087007743] auto[1] 80 1 T27 2 T59 2 T233 2
auto[3087007744:3221225471] auto[0] 172 1 T2 2 T17 2 T44 2
auto[3087007744:3221225471] auto[1] 72 1 T5 2 T67 2 T233 2
auto[3221225472:3355443199] auto[0] 130 1 T42 2 T35 2 T26 2
auto[3221225472:3355443199] auto[1] 50 1 T225 2 T162 2 T326 2
auto[3355443200:3489660927] auto[0] 146 1 T4 2 T236 2 T64 2
auto[3355443200:3489660927] auto[1] 64 1 T50 2 T51 2 T100 2
auto[3489660928:3623878655] auto[0] 124 1 T130 2 T90 2 T28 2
auto[3489660928:3623878655] auto[1] 66 1 T13 2 T162 2 T45 2
auto[3623878656:3758096383] auto[0] 142 1 T95 2 T220 2 T140 2
auto[3623878656:3758096383] auto[1] 80 1 T16 2 T5 2 T80 2
auto[3758096384:3892314111] auto[0] 144 1 T4 2 T5 2 T73 2
auto[3758096384:3892314111] auto[1] 72 1 T6 2 T357 2 T184 2
auto[3892314112:4026531839] auto[0] 154 1 T2 2 T223 2 T44 2
auto[3892314112:4026531839] auto[1] 54 1 T48 2 T139 2 T5 2
auto[4026531840:4160749567] auto[0] 130 1 T129 2 T220 2 T274 2
auto[4026531840:4160749567] auto[1] 66 1 T227 2 T162 2 T80 2
auto[4160749568:4294967295] auto[0] 158 1 T2 2 T41 2 T274 2
auto[4160749568:4294967295] auto[1] 58 1 T236 2 T75 2 T73 2

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