Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3039

1

T2

4

T4

3

T13

3

auto[1]

325

1

T17

11

T129

2

T130

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T17	1		T95	1		T129	1
auto[134217728:268435455]	114	1			T17	1		T44	1		T130	1
auto[268435456:402653183]	113	1			T17	2		T35	1		T26	2
auto[402653184:536870911]	109	1			T49	1		T5	3		T274	1
auto[536870912:671088639]	107	1			T2	1		T17	2		T130	1
auto[671088640:805306367]	118	1			T129	1		T130	2		T27	1
auto[805306368:939524095]	110	1			T16	1		T17	2		T49	1
auto[939524096:1073741823]	117	1			T13	2		T17	1		T35	1
auto[1073741824:1207959551]	109	1			T17	1		T95	1		T225	1
auto[1207959552:1342177279]	120	1			T2	1		T95	1		T129	1
auto[1342177280:1476395007]	100	1			T48	1		T225	1		T227	1
auto[1476395008:1610612735]	106	1			T95	2		T225	1		T26	1
auto[1610612736:1744830463]	103	1			T4	1		T162	2		T5	4
auto[1744830464:1879048191]	109	1			T13	1		T129	2		T44	1
auto[1879048192:2013265919]	94	1			T48	1		T51	1		T59	1
auto[2013265920:2147483647]	103	1			T17	1		T130	1		T26	1
auto[2147483648:2281701375]	121	1			T4	1		T42	1		T130	1
auto[2281701376:2415919103]	102	1			T16	1		T230	1		T35	1
auto[2415919104:2550136831]	97	1			T16	1		T229	1		T220	1
auto[2550136832:2684354559]	87	1			T41	1		T162	1		T64	1
auto[2684354560:2818572287]	106	1			T130	3		T227	1		T5	2
auto[2818572288:2952790015]	107	1			T17	1		T227	1		T220	1
auto[2952790016:3087007743]	118	1			T2	1		T4	1		T41	1
auto[3087007744:3221225471]	92	1			T129	1		T236	1		T220	1
auto[3221225472:3355443199]	89	1			T42	1		T5	2		T59	1
auto[3355443200:3489660927]	97	1			T44	1		T227	1		T122	1
auto[3489660928:3623878655]	110	1			T16	1		T223	1		T35	1
auto[3623878656:3758096383]	108	1			T223	1		T26	1		T49	1
auto[3758096384:3892314111]	100	1			T17	1		T95	1		T49	1
auto[3892314112:4026531839]	98	1			T17	2		T41	1		T42	1
auto[4026531840:4160749567]	94	1			T2	1		T130	1		T35	1
auto[4160749568:4294967295]	93	1			T44	1		T130	1		T35	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	108	1			T17	1		T95	1		T129	1
auto[0:134217727]	auto[1]	5	1			T151	1		T408	1		T314	1
auto[134217728:268435455]	auto[0]	105	1			T44	1		T130	1		T59	1
auto[134217728:268435455]	auto[1]	9	1			T17	1		T430	1		T369	1
auto[268435456:402653183]	auto[0]	103	1			T35	1		T26	2		T139	1
auto[268435456:402653183]	auto[1]	10	1			T17	2		T287	1		T430	1
auto[402653184:536870911]	auto[0]	105	1			T49	1		T5	3		T274	1
auto[402653184:536870911]	auto[1]	4	1			T383	2		T265	1		T432	1
auto[536870912:671088639]	auto[0]	91	1			T2	1		T130	1		T5	1
auto[536870912:671088639]	auto[1]	16	1			T17	2		T287	1		T430	1
auto[671088640:805306367]	auto[0]	103	1			T129	1		T27	1		T5	1
auto[671088640:805306367]	auto[1]	15	1			T130	2		T300	1		T202	1
auto[805306368:939524095]	auto[0]	98	1			T16	1		T49	1		T236	1
auto[805306368:939524095]	auto[1]	12	1			T17	2		T150	1		T369	1
auto[939524096:1073741823]	auto[0]	109	1			T13	2		T17	1		T35	1
auto[939524096:1073741823]	auto[1]	8	1			T394	1		T429	1		T433	1
auto[1073741824:1207959551]	auto[0]	99	1			T17	1		T95	1		T225	1
auto[1073741824:1207959551]	auto[1]	10	1			T162	1		T202	1		T276	1
auto[1207959552:1342177279]	auto[0]	105	1			T2	1		T95	1		T130	1
auto[1207959552:1342177279]	auto[1]	15	1			T129	1		T202	2		T287	1
auto[1342177280:1476395007]	auto[0]	85	1			T48	1		T225	1		T227	1
auto[1342177280:1476395007]	auto[1]	15	1			T150	1		T276	1		T430	1
auto[1476395008:1610612735]	auto[0]	92	1			T95	2		T225	1		T26	1
auto[1476395008:1610612735]	auto[1]	14	1			T300	1		T276	3		T338	1
auto[1610612736:1744830463]	auto[0]	96	1			T4	1		T162	2		T5	4
auto[1610612736:1744830463]	auto[1]	7	1			T300	1		T287	1		T386	1
auto[1744830464:1879048191]	auto[0]	98	1			T13	1		T129	1		T44	1
auto[1744830464:1879048191]	auto[1]	11	1			T129	1		T130	1		T430	1
auto[1879048192:2013265919]	auto[0]	85	1			T48	1		T51	1		T59	1
auto[1879048192:2013265919]	auto[1]	9	1			T202	1		T205	1		T369	1
auto[2013265920:2147483647]	auto[0]	92	1			T130	1		T26	1		T27	1
auto[2013265920:2147483647]	auto[1]	11	1			T17	1		T324	1		T120	1
auto[2147483648:2281701375]	auto[0]	111	1			T4	1		T42	1		T35	1
auto[2147483648:2281701375]	auto[1]	10	1			T130	1		T151	2		T276	1
auto[2281701376:2415919103]	auto[0]	90	1			T16	1		T230	1		T35	1
auto[2281701376:2415919103]	auto[1]	12	1			T151	1		T369	2		T429	1
auto[2415919104:2550136831]	auto[0]	90	1			T16	1		T229	1		T220	1
auto[2415919104:2550136831]	auto[1]	7	1			T369	3		T354	1		T435	1
auto[2550136832:2684354559]	auto[0]	78	1			T41	1		T64	1		T6	1
auto[2550136832:2684354559]	auto[1]	9	1			T162	1		T359	1		T430	1
auto[2684354560:2818572287]	auto[0]	95	1			T227	1		T5	2		T51	1
auto[2684354560:2818572287]	auto[1]	11	1			T130	3		T202	2		T408	1
auto[2818572288:2952790015]	auto[0]	97	1			T227	1		T220	1		T162	1
auto[2818572288:2952790015]	auto[1]	10	1			T17	1		T162	1		T287	1
auto[2952790016:3087007743]	auto[0]	108	1			T2	1		T4	1		T41	1
auto[2952790016:3087007743]	auto[1]	10	1			T276	1		T369	1		T394	1
auto[3087007744:3221225471]	auto[0]	85	1			T129	1		T236	1		T220	1
auto[3087007744:3221225471]	auto[1]	7	1			T300	1		T369	1		T429	2
auto[3221225472:3355443199]	auto[0]	85	1			T42	1		T5	2		T59	1
auto[3221225472:3355443199]	auto[1]	4	1			T386	1		T433	1		T437	1
auto[3355443200:3489660927]	auto[0]	86	1			T44	1		T227	1		T122	1
auto[3355443200:3489660927]	auto[1]	11	1			T300	1		T430	1		T394	1
auto[3489660928:3623878655]	auto[0]	99	1			T16	1		T223	1		T35	1
auto[3489660928:3623878655]	auto[1]	11	1			T359	1		T151	1		T202	1
auto[3623878656:3758096383]	auto[0]	98	1			T223	1		T26	1		T49	1
auto[3623878656:3758096383]	auto[1]	10	1			T300	1		T431	1		T429	1
auto[3758096384:3892314111]	auto[0]	86	1			T95	1		T49	1		T140	1
auto[3758096384:3892314111]	auto[1]	14	1			T17	1		T162	1		T300	2
auto[3892314112:4026531839]	auto[0]	90	1			T17	1		T41	1		T42	1
auto[3892314112:4026531839]	auto[1]	8	1			T17	1		T408	1		T428	1
auto[4026531840:4160749567]	auto[0]	85	1			T2	1		T35	1		T236	1
auto[4026531840:4160749567]	auto[1]	9	1			T130	1		T162	1		T300	1
auto[4160749568:4294967295]	auto[0]	82	1			T44	1		T130	1		T35	2
auto[4160749568:4294967295]	auto[1]	11	1			T300	1		T151	2		T386	1