Unified Coverage Report :: Group Instance : sealing_sw_binding_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1708

1

T2

4

T4

1

T16

2

auto[1]

1769

1

T2

3

T4

3

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T2	1		T13	1		T17	1
auto[134217728:268435455]	117	1			T48	1		T95	1		T225	1
auto[268435456:402653183]	122	1			T2	1		T35	1		T26	1
auto[402653184:536870911]	88	1			T2	1		T220	1		T5	2
auto[536870912:671088639]	98	1			T162	1		T64	1		T5	1
auto[671088640:805306367]	119	1			T44	1		T227	1		T75	1
auto[805306368:939524095]	109	1			T230	1		T130	1		T35	2
auto[939524096:1073741823]	121	1			T41	1		T129	1		T227	1
auto[1073741824:1207959551]	112	1			T59	1		T28	1		T184	1
auto[1207959552:1342177279]	98	1			T2	1		T4	1		T42	1
auto[1342177280:1476395007]	95	1			T5	2		T21	1		T6	2
auto[1476395008:1610612735]	102	1			T44	1		T49	1		T140	1
auto[1610612736:1744830463]	88	1			T13	1		T130	1		T49	1
auto[1744830464:1879048191]	97	1			T16	1		T17	1		T236	1
auto[1879048192:2013265919]	108	1			T2	1		T16	1		T17	1
auto[2013265920:2147483647]	125	1			T225	1		T129	1		T139	1
auto[2147483648:2281701375]	114	1			T223	1		T230	1		T35	1
auto[2281701376:2415919103]	118	1			T35	2		T88	1		T21	1
auto[2415919104:2550136831]	118	1			T13	1		T16	1		T129	1
auto[2550136832:2684354559]	91	1			T130	1		T35	1		T26	1
auto[2684354560:2818572287]	99	1			T16	1		T41	1		T225	1
auto[2818572288:2952790015]	124	1			T2	1		T129	1		T44	2
auto[2952790016:3087007743]	109	1			T4	1		T41	1		T27	1
auto[3087007744:3221225471]	117	1			T4	1		T139	1		T5	1
auto[3221225472:3355443199]	128	1			T44	1		T236	2		T65	1
auto[3355443200:3489660927]	108	1			T17	1		T220	1		T59	1
auto[3489660928:3623878655]	95	1			T5	1		T90	1		T28	1
auto[3623878656:3758096383]	115	1			T95	1		T26	2		T227	1
auto[3758096384:3892314111]	103	1			T95	1		T220	1		T5	1
auto[3892314112:4026531839]	94	1			T4	1		T48	1		T95	2
auto[4026531840:4160749567]	122	1			T2	1		T95	1		T129	1
auto[4160749568:4294967295]	109	1			T42	1		T75	1		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T2	1		T42	1		T162	1
auto[0:134217727]	auto[1]	58	1			T13	1		T17	1		T49	1
auto[134217728:268435455]	auto[0]	57	1			T26	2		T27	1		T59	1
auto[134217728:268435455]	auto[1]	60	1			T48	1		T95	1		T225	1
auto[268435456:402653183]	auto[0]	55	1			T2	1		T35	1		T139	1
auto[268435456:402653183]	auto[1]	67	1			T26	1		T139	1		T5	1
auto[402653184:536870911]	auto[0]	41	1			T220	1		T5	1		T274	1
auto[402653184:536870911]	auto[1]	47	1			T2	1		T5	1		T420	1
auto[536870912:671088639]	auto[0]	48	1			T162	1		T64	1		T73	1
auto[536870912:671088639]	auto[1]	50	1			T5	1		T60	1		T70	1
auto[671088640:805306367]	auto[0]	63	1			T75	1		T64	1		T122	1
auto[671088640:805306367]	auto[1]	56	1			T44	1		T227	1		T140	1
auto[805306368:939524095]	auto[0]	56	1			T35	1		T51	1		T233	1
auto[805306368:939524095]	auto[1]	53	1			T230	1		T130	1		T35	1
auto[939524096:1073741823]	auto[0]	60	1			T227	1		T357	1		T45	1
auto[939524096:1073741823]	auto[1]	61	1			T41	1		T129	1		T6	3
auto[1073741824:1207959551]	auto[0]	51	1			T59	1		T333	1		T98	1
auto[1073741824:1207959551]	auto[1]	61	1			T28	1		T184	1		T325	1
auto[1207959552:1342177279]	auto[0]	48	1			T4	1		T42	1		T44	1
auto[1207959552:1342177279]	auto[1]	50	1			T2	1		T223	1		T130	1
auto[1342177280:1476395007]	auto[0]	47	1			T5	1		T21	1		T6	1
auto[1342177280:1476395007]	auto[1]	48	1			T5	1		T6	1		T420	1
auto[1476395008:1610612735]	auto[0]	45	1			T140	1		T73	2		T269	1
auto[1476395008:1610612735]	auto[1]	57	1			T44	1		T49	1		T5	1
auto[1610612736:1744830463]	auto[0]	44	1			T130	1		T65	1		T51	1
auto[1610612736:1744830463]	auto[1]	44	1			T13	1		T49	1		T220	1
auto[1744830464:1879048191]	auto[0]	54	1			T236	1		T52	1		T28	1
auto[1744830464:1879048191]	auto[1]	43	1			T16	1		T17	1		T162	1
auto[1879048192:2013265919]	auto[0]	49	1			T2	1		T17	1		T50	1
auto[1879048192:2013265919]	auto[1]	59	1			T16	1		T130	1		T434	1
auto[2013265920:2147483647]	auto[0]	68	1			T129	1		T274	1		T59	1
auto[2013265920:2147483647]	auto[1]	57	1			T225	1		T139	1		T59	1
auto[2147483648:2281701375]	auto[0]	40	1			T223	1		T230	1		T5	1
auto[2147483648:2281701375]	auto[1]	74	1			T35	1		T75	1		T59	2
auto[2281701376:2415919103]	auto[0]	68	1			T88	1		T21	1		T6	1
auto[2281701376:2415919103]	auto[1]	50	1			T35	2		T6	2		T233	1
auto[2415919104:2550136831]	auto[0]	56	1			T16	1		T236	1		T5	1
auto[2415919104:2550136831]	auto[1]	62	1			T13	1		T129	1		T139	1
auto[2550136832:2684354559]	auto[0]	51	1			T130	1		T6	2		T357	1
auto[2550136832:2684354559]	auto[1]	40	1			T35	1		T26	1		T229	1
auto[2684354560:2818572287]	auto[0]	54	1			T16	1		T41	1		T5	1
auto[2684354560:2818572287]	auto[1]	45	1			T225	1		T35	1		T5	1
auto[2818572288:2952790015]	auto[0]	62	1			T2	1		T129	1		T44	1
auto[2818572288:2952790015]	auto[1]	62	1			T44	1		T5	1		T71	1
auto[2952790016:3087007743]	auto[0]	54	1			T65	1		T59	1		T122	1
auto[2952790016:3087007743]	auto[1]	55	1			T4	1		T41	1		T27	1
auto[3087007744:3221225471]	auto[0]	57	1			T274	1		T282	1		T18	1
auto[3087007744:3221225471]	auto[1]	60	1			T4	1		T139	1		T5	1
auto[3221225472:3355443199]	auto[0]	59	1			T236	1		T65	1		T6	2
auto[3221225472:3355443199]	auto[1]	69	1			T44	1		T236	1		T5	1
auto[3355443200:3489660927]	auto[0]	54	1			T220	1		T52	1		T73	1
auto[3355443200:3489660927]	auto[1]	54	1			T17	1		T59	1		T73	1
auto[3489660928:3623878655]	auto[0]	52	1			T5	1		T28	1		T73	1
auto[3489660928:3623878655]	auto[1]	43	1			T90	1		T73	1		T184	1
auto[3623878656:3758096383]	auto[0]	53	1			T95	1		T26	1		T5	1
auto[3623878656:3758096383]	auto[1]	62	1			T26	1		T227	1		T64	1
auto[3758096384:3892314111]	auto[0]	50	1			T5	1		T6	1		T69	1
auto[3758096384:3892314111]	auto[1]	53	1			T95	1		T220	1		T73	1
auto[3892314112:4026531839]	auto[0]	45	1			T48	1		T95	1		T80	1
auto[3892314112:4026531839]	auto[1]	49	1			T4	1		T95	1		T44	1
auto[4026531840:4160749567]	auto[0]	50	1			T35	1		T220	1		T28	1
auto[4026531840:4160749567]	auto[1]	72	1			T2	1		T95	1		T129	1
auto[4160749568:4294967295]	auto[0]	61	1			T42	1		T5	1		T6	1
auto[4160749568:4294967295]	auto[1]	48	1			T75	1		T71	1		T6	3