Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7098

1

T2

7

T4

6

T13

5

auto[1]

285

1

T17

8

T129

2

T130

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2977	1			T2	3		T4	4		T13	2
auto[134217728:268435455]	178	1			T16	1		T95	1		T27	1
auto[268435456:402653183]	152	1			T42	1		T129	1		T230	1
auto[402653184:536870911]	147	1			T16	1		T130	2		T35	1
auto[536870912:671088639]	143	1			T17	1		T5	2		T6	2
auto[671088640:805306367]	160	1			T13	1		T17	2		T42	1
auto[805306368:939524095]	140	1			T26	1		T49	1		T227	1
auto[939524096:1073741823]	170	1			T41	1		T225	1		T129	1
auto[1073741824:1207959551]	146	1			T225	1		T139	1		T5	1
auto[1207959552:1342177279]	164	1			T26	1		T49	1		T27	1
auto[1342177280:1476395007]	131	1			T13	1		T44	2		T35	1
auto[1476395008:1610612735]	142	1			T2	1		T17	2		T95	1
auto[1610612736:1744830463]	143	1			T129	1		T35	1		T139	2
auto[1744830464:1879048191]	145	1			T227	1		T65	1		T5	2
auto[1879048192:2013265919]	141	1			T16	1		T220	2		T274	1
auto[2013265920:2147483647]	118	1			T16	1		T223	1		T230	1
auto[2147483648:2281701375]	135	1			T17	1		T129	1		T130	1
auto[2281701376:2415919103]	123	1			T17	1		T95	2		T130	1
auto[2415919104:2550136831]	165	1			T2	1		T13	1		T95	1
auto[2550136832:2684354559]	117	1			T16	1		T26	1		T220	1
auto[2684354560:2818572287]	136	1			T17	1		T41	1		T35	2
auto[2818572288:2952790015]	116	1			T95	1		T223	1		T230	1
auto[2952790016:3087007743]	134	1			T4	1		T48	1		T44	1
auto[3087007744:3221225471]	144	1			T2	2		T48	1		T49	1
auto[3221225472:3355443199]	131	1			T162	1		T64	1		T65	1
auto[3355443200:3489660927]	160	1			T41	1		T129	1		T44	1
auto[3489660928:3623878655]	131	1			T42	1		T35	1		T26	2
auto[3623878656:3758096383]	146	1			T225	1		T26	1		T236	1
auto[3758096384:3892314111]	129	1			T16	2		T17	1		T225	1
auto[3892314112:4026531839]	129	1			T35	1		T27	1		T64	1
auto[4026531840:4160749567]	141	1			T17	2		T230	1		T27	1
auto[4160749568:4294967295]	149	1			T4	1		T17	1		T130	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2969	1			T2	3		T4	4		T13	2
auto[0:134217727]	auto[1]	8	1			T17	1		T369	1		T314	1
auto[134217728:268435455]	auto[0]	171	1			T16	1		T95	1		T27	1
auto[134217728:268435455]	auto[1]	7	1			T202	1		T276	1		T287	1
auto[268435456:402653183]	auto[0]	139	1			T42	1		T230	1		T130	1
auto[268435456:402653183]	auto[1]	13	1			T129	1		T150	2		T338	1
auto[402653184:536870911]	auto[0]	142	1			T16	1		T130	2		T35	1
auto[402653184:536870911]	auto[1]	5	1			T205	1		T369	1		T264	1
auto[536870912:671088639]	auto[0]	136	1			T17	1		T5	2		T6	2
auto[536870912:671088639]	auto[1]	7	1			T386	1		T433	1		T264	1
auto[671088640:805306367]	auto[0]	153	1			T13	1		T17	1		T42	1
auto[671088640:805306367]	auto[1]	7	1			T17	1		T129	1		T130	1
auto[805306368:939524095]	auto[0]	133	1			T26	1		T49	1		T227	1
auto[805306368:939524095]	auto[1]	7	1			T151	1		T431	1		T354	2
auto[939524096:1073741823]	auto[0]	159	1			T41	1		T225	1		T129	1
auto[939524096:1073741823]	auto[1]	11	1			T162	1		T151	1		T430	1
auto[1073741824:1207959551]	auto[0]	133	1			T225	1		T139	1		T5	1
auto[1073741824:1207959551]	auto[1]	13	1			T300	2		T151	1		T276	1
auto[1207959552:1342177279]	auto[0]	152	1			T26	1		T49	1		T27	1
auto[1207959552:1342177279]	auto[1]	12	1			T150	1		T151	1		T287	1
auto[1342177280:1476395007]	auto[0]	125	1			T13	1		T44	2		T35	1
auto[1342177280:1476395007]	auto[1]	6	1			T430	1		T280	1		T435	1
auto[1476395008:1610612735]	auto[0]	135	1			T2	1		T17	1		T95	1
auto[1476395008:1610612735]	auto[1]	7	1			T17	1		T369	1		T394	2
auto[1610612736:1744830463]	auto[0]	138	1			T129	1		T35	1		T139	2
auto[1610612736:1744830463]	auto[1]	5	1			T268	1		T408	2		T431	1
auto[1744830464:1879048191]	auto[0]	136	1			T227	1		T65	1		T5	2
auto[1744830464:1879048191]	auto[1]	9	1			T300	1		T369	1		T314	1
auto[1879048192:2013265919]	auto[0]	130	1			T16	1		T220	2		T274	1
auto[1879048192:2013265919]	auto[1]	11	1			T300	2		T430	1		T338	1
auto[2013265920:2147483647]	auto[0]	113	1			T16	1		T223	1		T230	1
auto[2013265920:2147483647]	auto[1]	5	1			T162	2		T428	1		T354	1
auto[2147483648:2281701375]	auto[0]	120	1			T129	1		T35	1		T139	1
auto[2147483648:2281701375]	auto[1]	15	1			T17	1		T130	1		T162	1
auto[2281701376:2415919103]	auto[0]	106	1			T17	1		T95	2		T5	2
auto[2281701376:2415919103]	auto[1]	17	1			T130	1		T359	1		T150	1
auto[2415919104:2550136831]	auto[0]	154	1			T2	1		T13	1		T95	1
auto[2415919104:2550136831]	auto[1]	11	1			T314	1		T324	1		T354	2
auto[2550136832:2684354559]	auto[0]	111	1			T16	1		T26	1		T220	1
auto[2550136832:2684354559]	auto[1]	6	1			T300	1		T151	1		T287	1
auto[2684354560:2818572287]	auto[0]	127	1			T41	1		T35	2		T227	1
auto[2684354560:2818572287]	auto[1]	9	1			T17	1		T430	1		T369	1
auto[2818572288:2952790015]	auto[0]	109	1			T95	1		T223	1		T230	1
auto[2818572288:2952790015]	auto[1]	7	1			T268	1		T300	1		T369	2
auto[2952790016:3087007743]	auto[0]	126	1			T4	1		T48	1		T44	1
auto[2952790016:3087007743]	auto[1]	8	1			T162	1		T300	2		T202	1
auto[3087007744:3221225471]	auto[0]	132	1			T2	2		T48	1		T49	1
auto[3087007744:3221225471]	auto[1]	12	1			T202	1		T287	2		T369	1
auto[3221225472:3355443199]	auto[0]	129	1			T162	1		T64	1		T65	1
auto[3221225472:3355443199]	auto[1]	2	1			T354	1		T383	1		-	-
auto[3355443200:3489660927]	auto[0]	150	1			T41	1		T129	1		T44	1
auto[3355443200:3489660927]	auto[1]	10	1			T130	1		T162	1		T359	1
auto[3489660928:3623878655]	auto[0]	120	1			T42	1		T35	1		T26	2
auto[3489660928:3623878655]	auto[1]	11	1			T408	1		T386	1		T394	1
auto[3623878656:3758096383]	auto[0]	139	1			T225	1		T26	1		T236	1
auto[3623878656:3758096383]	auto[1]	7	1			T430	1		T281	1		T386	1
auto[3758096384:3892314111]	auto[0]	123	1			T16	2		T225	1		T26	2
auto[3758096384:3892314111]	auto[1]	6	1			T17	1		T268	1		T287	1
auto[3892314112:4026531839]	auto[0]	120	1			T35	1		T27	1		T64	1
auto[3892314112:4026531839]	auto[1]	9	1			T287	1		T433	1		T436	1
auto[4026531840:4160749567]	auto[0]	134	1			T17	1		T230	1		T27	1
auto[4026531840:4160749567]	auto[1]	7	1			T17	1		T162	1		T151	1
auto[4160749568:4294967295]	auto[0]	134	1			T4	1		T130	1		T35	1
auto[4160749568:4294967295]	auto[1]	15	1			T17	1		T202	1		T430	1