Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.04 98.15 98.52 100.00 99.02 98.41 91.24


Total test records in report: 1084
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T1010 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2917769131 Jun 06 12:47:16 PM PDT 24 Jun 06 12:47:18 PM PDT 24 12955022 ps
T1011 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3684138882 Jun 06 12:46:34 PM PDT 24 Jun 06 12:46:50 PM PDT 24 1146311292 ps
T1012 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.106721957 Jun 06 12:46:33 PM PDT 24 Jun 06 12:46:36 PM PDT 24 154704424 ps
T1013 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2939656440 Jun 06 12:47:13 PM PDT 24 Jun 06 12:47:18 PM PDT 24 767173195 ps
T1014 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3242313335 Jun 06 12:46:57 PM PDT 24 Jun 06 12:47:02 PM PDT 24 192312769 ps
T1015 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3191488344 Jun 06 12:46:45 PM PDT 24 Jun 06 12:46:49 PM PDT 24 308683730 ps
T1016 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.55135395 Jun 06 12:47:08 PM PDT 24 Jun 06 12:47:12 PM PDT 24 242538424 ps
T1017 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2239515989 Jun 06 12:46:35 PM PDT 24 Jun 06 12:46:48 PM PDT 24 261049086 ps
T1018 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3704434780 Jun 06 12:46:53 PM PDT 24 Jun 06 12:46:55 PM PDT 24 53427222 ps
T1019 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1135140120 Jun 06 12:47:27 PM PDT 24 Jun 06 12:47:30 PM PDT 24 36513165 ps
T1020 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1041102195 Jun 06 12:46:37 PM PDT 24 Jun 06 12:46:39 PM PDT 24 49649071 ps
T1021 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1468125295 Jun 06 12:46:55 PM PDT 24 Jun 06 12:46:58 PM PDT 24 11808944 ps
T1022 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.762424557 Jun 06 12:46:53 PM PDT 24 Jun 06 12:46:57 PM PDT 24 345959080 ps
T1023 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2477974954 Jun 06 12:47:19 PM PDT 24 Jun 06 12:47:21 PM PDT 24 52520574 ps
T1024 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2495276071 Jun 06 12:46:56 PM PDT 24 Jun 06 12:47:08 PM PDT 24 1879752191 ps
T1025 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2903584943 Jun 06 12:47:09 PM PDT 24 Jun 06 12:47:12 PM PDT 24 100608026 ps
T1026 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1483113362 Jun 06 12:46:24 PM PDT 24 Jun 06 12:46:41 PM PDT 24 3459530385 ps
T1027 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1555895414 Jun 06 12:46:33 PM PDT 24 Jun 06 12:46:36 PM PDT 24 179732589 ps
T1028 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.624863885 Jun 06 12:46:46 PM PDT 24 Jun 06 12:46:48 PM PDT 24 55234400 ps
T1029 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4097631079 Jun 06 12:47:25 PM PDT 24 Jun 06 12:47:26 PM PDT 24 19660330 ps
T1030 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3327863048 Jun 06 12:47:27 PM PDT 24 Jun 06 12:47:29 PM PDT 24 25034217 ps
T1031 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4112918032 Jun 06 12:47:15 PM PDT 24 Jun 06 12:47:18 PM PDT 24 69912075 ps
T1032 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.18566509 Jun 06 12:47:19 PM PDT 24 Jun 06 12:47:21 PM PDT 24 92573706 ps
T1033 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3757184256 Jun 06 12:46:49 PM PDT 24 Jun 06 12:46:51 PM PDT 24 180139437 ps
T1034 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3455172246 Jun 06 12:47:10 PM PDT 24 Jun 06 12:47:11 PM PDT 24 32472183 ps
T174 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2516123518 Jun 06 12:46:56 PM PDT 24 Jun 06 12:47:09 PM PDT 24 2134548033 ps
T1035 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3521495016 Jun 06 12:46:55 PM PDT 24 Jun 06 12:46:59 PM PDT 24 94448919 ps
T1036 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3871996577 Jun 06 12:46:34 PM PDT 24 Jun 06 12:46:42 PM PDT 24 458595985 ps
T1037 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2918396621 Jun 06 12:47:15 PM PDT 24 Jun 06 12:47:17 PM PDT 24 23431184 ps
T1038 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1633312931 Jun 06 12:47:26 PM PDT 24 Jun 06 12:47:28 PM PDT 24 10320387 ps
T167 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1322745574 Jun 06 12:46:54 PM PDT 24 Jun 06 12:47:00 PM PDT 24 246719574 ps
T1039 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.364959012 Jun 06 12:47:28 PM PDT 24 Jun 06 12:47:30 PM PDT 24 14034302 ps
T172 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.512913055 Jun 06 12:46:42 PM PDT 24 Jun 06 12:46:45 PM PDT 24 205263435 ps
T1040 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.306357540 Jun 06 12:46:44 PM PDT 24 Jun 06 12:46:46 PM PDT 24 52684040 ps
T1041 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1364464777 Jun 06 12:46:48 PM PDT 24 Jun 06 12:46:50 PM PDT 24 34342255 ps
T1042 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3454420804 Jun 06 12:46:26 PM PDT 24 Jun 06 12:46:29 PM PDT 24 187617811 ps
T176 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1789374676 Jun 06 12:46:36 PM PDT 24 Jun 06 12:46:40 PM PDT 24 104042880 ps
T1043 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1683512265 Jun 06 12:47:16 PM PDT 24 Jun 06 12:47:18 PM PDT 24 96658399 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3741667830 Jun 06 12:46:36 PM PDT 24 Jun 06 12:46:46 PM PDT 24 241025370 ps
T1045 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.520828014 Jun 06 12:46:44 PM PDT 24 Jun 06 12:46:58 PM PDT 24 400839330 ps
T1046 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2339486370 Jun 06 12:46:32 PM PDT 24 Jun 06 12:46:40 PM PDT 24 159564197 ps
T183 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1344461049 Jun 06 12:46:42 PM PDT 24 Jun 06 12:46:47 PM PDT 24 131922709 ps
T1047 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2816093307 Jun 06 12:46:22 PM PDT 24 Jun 06 12:46:25 PM PDT 24 377485191 ps
T1048 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.952225461 Jun 06 12:46:35 PM PDT 24 Jun 06 12:46:38 PM PDT 24 40988620 ps
T1049 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3578044510 Jun 06 12:47:07 PM PDT 24 Jun 06 12:47:12 PM PDT 24 165274348 ps
T1050 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1823474517 Jun 06 12:46:36 PM PDT 24 Jun 06 12:46:39 PM PDT 24 211464468 ps
T1051 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.93769472 Jun 06 12:46:35 PM PDT 24 Jun 06 12:46:37 PM PDT 24 32214048 ps
T1052 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.959337364 Jun 06 12:46:56 PM PDT 24 Jun 06 12:46:59 PM PDT 24 42803394 ps
T1053 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.531057819 Jun 06 12:46:23 PM PDT 24 Jun 06 12:46:25 PM PDT 24 37327867 ps
T1054 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2204047514 Jun 06 12:47:26 PM PDT 24 Jun 06 12:47:27 PM PDT 24 35119322 ps
T178 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.650908182 Jun 06 12:46:58 PM PDT 24 Jun 06 12:47:07 PM PDT 24 314457479 ps
T1055 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1890480668 Jun 06 12:46:40 PM PDT 24 Jun 06 12:46:43 PM PDT 24 113049358 ps
T182 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.4230537833 Jun 06 12:47:10 PM PDT 24 Jun 06 12:47:17 PM PDT 24 269560860 ps
T1056 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1360930698 Jun 06 12:46:49 PM PDT 24 Jun 06 12:46:50 PM PDT 24 17456756 ps
T1057 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3278124536 Jun 06 12:47:14 PM PDT 24 Jun 06 12:47:17 PM PDT 24 48178914 ps
T1058 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2953157958 Jun 06 12:46:55 PM PDT 24 Jun 06 12:46:59 PM PDT 24 44280361 ps
T1059 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2983472002 Jun 06 12:47:05 PM PDT 24 Jun 06 12:47:08 PM PDT 24 193970761 ps
T168 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3897965115 Jun 06 12:47:08 PM PDT 24 Jun 06 12:47:12 PM PDT 24 186497827 ps
T1060 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2011443509 Jun 06 12:46:34 PM PDT 24 Jun 06 12:46:37 PM PDT 24 53639448 ps
T1061 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2341103640 Jun 06 12:47:13 PM PDT 24 Jun 06 12:47:16 PM PDT 24 283748394 ps
T1062 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1612751904 Jun 06 12:46:35 PM PDT 24 Jun 06 12:46:37 PM PDT 24 40282621 ps
T1063 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1615861863 Jun 06 12:47:18 PM PDT 24 Jun 06 12:47:23 PM PDT 24 426742776 ps
T1064 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4284012741 Jun 06 12:46:42 PM PDT 24 Jun 06 12:46:44 PM PDT 24 56692152 ps
T1065 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2050043265 Jun 06 12:46:42 PM PDT 24 Jun 06 12:46:44 PM PDT 24 106627731 ps
T175 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1611968198 Jun 06 12:46:53 PM PDT 24 Jun 06 12:46:57 PM PDT 24 83815017 ps
T1066 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.76129640 Jun 06 12:46:32 PM PDT 24 Jun 06 12:46:35 PM PDT 24 70238866 ps
T1067 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.159888138 Jun 06 12:46:36 PM PDT 24 Jun 06 12:46:39 PM PDT 24 75272607 ps
T1068 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3342575481 Jun 06 12:47:06 PM PDT 24 Jun 06 12:47:11 PM PDT 24 87541255 ps
T1069 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3015125353 Jun 06 12:47:06 PM PDT 24 Jun 06 12:47:17 PM PDT 24 836226147 ps
T1070 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.355392000 Jun 06 12:47:10 PM PDT 24 Jun 06 12:47:15 PM PDT 24 101984177 ps
T1071 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2749079514 Jun 06 12:46:52 PM PDT 24 Jun 06 12:46:55 PM PDT 24 271661882 ps
T1072 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1102509360 Jun 06 12:46:45 PM PDT 24 Jun 06 12:46:48 PM PDT 24 1375922282 ps
T1073 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1266086525 Jun 06 12:46:58 PM PDT 24 Jun 06 12:47:00 PM PDT 24 37811577 ps
T1074 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2898170525 Jun 06 12:46:56 PM PDT 24 Jun 06 12:46:59 PM PDT 24 24780711 ps
T1075 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4130692228 Jun 06 12:46:58 PM PDT 24 Jun 06 12:47:03 PM PDT 24 103640546 ps
T1076 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.995770785 Jun 06 12:47:06 PM PDT 24 Jun 06 12:47:08 PM PDT 24 12926750 ps
T1077 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2589665267 Jun 06 12:46:34 PM PDT 24 Jun 06 12:46:36 PM PDT 24 28135992 ps
T1078 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2922054914 Jun 06 12:46:44 PM PDT 24 Jun 06 12:46:54 PM PDT 24 3745556892 ps
T1079 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2535555379 Jun 06 12:46:43 PM PDT 24 Jun 06 12:46:48 PM PDT 24 403870600 ps
T1080 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.419492130 Jun 06 12:47:25 PM PDT 24 Jun 06 12:47:27 PM PDT 24 8525847 ps
T1081 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2960973776 Jun 06 12:47:07 PM PDT 24 Jun 06 12:47:09 PM PDT 24 26722675 ps
T1082 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3437738674 Jun 06 12:47:27 PM PDT 24 Jun 06 12:47:29 PM PDT 24 10047287 ps
T1083 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1602743323 Jun 06 12:46:35 PM PDT 24 Jun 06 12:46:41 PM PDT 24 768680303 ps
T1084 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.204632478 Jun 06 12:47:25 PM PDT 24 Jun 06 12:47:27 PM PDT 24 22328949 ps

Test location /workspace/coverage/default/34.keymgr_lc_disable.22827927
Short name T2
Test name
Test status
Simulation time 157931991 ps
CPU time 2.8 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 214328 kb
Host smart-6691107e-dd7f-4e2f-825d-8a9965b67354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22827927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.22827927
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.587435168
Short name T6
Test name
Test status
Simulation time 1060844116 ps
CPU time 35.66 seconds
Started Jun 06 01:55:47 PM PDT 24
Finished Jun 06 01:56:24 PM PDT 24
Peak memory 215860 kb
Host smart-6ed51c5b-c9d1-4c38-9baf-4a56c8cfa234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587435168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.587435168
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.4134230629
Short name T17
Test name
Test status
Simulation time 3025981976 ps
CPU time 15.97 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:30 PM PDT 24
Peak memory 214664 kb
Host smart-0285f242-169d-467f-9187-6c311abeaf5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4134230629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.4134230629
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.4180490408
Short name T73
Test name
Test status
Simulation time 996726723 ps
CPU time 16.89 seconds
Started Jun 06 01:55:38 PM PDT 24
Finished Jun 06 01:55:56 PM PDT 24
Peak memory 222484 kb
Host smart-071ce9b5-b418-422a-9ad5-d53f1436e5a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180490408 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.4180490408
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.80174850
Short name T9
Test name
Test status
Simulation time 1863819200 ps
CPU time 13.12 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 234708 kb
Host smart-ed6ee0ea-8853-4c4e-8b74-a2ba260862ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80174850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.80174850
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3461214920
Short name T70
Test name
Test status
Simulation time 9686195025 ps
CPU time 62.51 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:55:51 PM PDT 24
Peak memory 222580 kb
Host smart-1087024a-c7f3-4bae-9188-c527b35eb272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461214920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3461214920
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3400879404
Short name T195
Test name
Test status
Simulation time 55978621 ps
CPU time 1.66 seconds
Started Jun 06 12:46:44 PM PDT 24
Finished Jun 06 12:46:47 PM PDT 24
Peak memory 213860 kb
Host smart-9b67444e-7a27-4be8-baf8-abcbb0a1d954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400879404 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3400879404
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.563951568
Short name T59
Test name
Test status
Simulation time 517688418 ps
CPU time 12.98 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:56:01 PM PDT 24
Peak memory 219768 kb
Host smart-d41fd67f-cc69-473f-8995-12cdd8861d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563951568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.563951568
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.596536560
Short name T35
Test name
Test status
Simulation time 394843764 ps
CPU time 3.61 seconds
Started Jun 06 01:54:45 PM PDT 24
Finished Jun 06 01:54:50 PM PDT 24
Peak memory 214232 kb
Host smart-b747e186-677a-4776-a78c-702644bf4a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596536560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.596536560
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1631784230
Short name T8
Test name
Test status
Simulation time 125008414 ps
CPU time 2.09 seconds
Started Jun 06 01:55:17 PM PDT 24
Finished Jun 06 01:55:20 PM PDT 24
Peak memory 222640 kb
Host smart-affead5b-5968-42be-8399-b08cf1968a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631784230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1631784230
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.201554208
Short name T5
Test name
Test status
Simulation time 2006047001 ps
CPU time 27.02 seconds
Started Jun 06 01:54:57 PM PDT 24
Finished Jun 06 01:55:26 PM PDT 24
Peak memory 220756 kb
Host smart-d8d03bd2-61cd-4da9-8ce1-c7f1eabde024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201554208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.201554208
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1144888207
Short name T124
Test name
Test status
Simulation time 180518779 ps
CPU time 6.34 seconds
Started Jun 06 12:47:05 PM PDT 24
Finished Jun 06 12:47:12 PM PDT 24
Peak memory 214184 kb
Host smart-f1249e12-8f05-43a2-bcc5-907b4d238678
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144888207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1144888207
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3170098799
Short name T435
Test name
Test status
Simulation time 14964603615 ps
CPU time 64.15 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:57:11 PM PDT 24
Peak memory 216016 kb
Host smart-f566e76a-b504-428e-9b6b-d93f0fe8e558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170098799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3170098799
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.194775801
Short name T16
Test name
Test status
Simulation time 143151368 ps
CPU time 5.57 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 220612 kb
Host smart-f80a334e-e5d7-4722-af84-d459afd8c298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194775801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.194775801
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2983926384
Short name T130
Test name
Test status
Simulation time 419073463 ps
CPU time 10.31 seconds
Started Jun 06 01:55:48 PM PDT 24
Finished Jun 06 01:55:59 PM PDT 24
Peak memory 214336 kb
Host smart-51b67f8c-a6ee-436f-a34b-e80846f7cbec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983926384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2983926384
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1001082638
Short name T300
Test name
Test status
Simulation time 17949468064 ps
CPU time 60.75 seconds
Started Jun 06 01:55:34 PM PDT 24
Finished Jun 06 01:56:36 PM PDT 24
Peak memory 217608 kb
Host smart-5d36e89f-142b-4838-818a-e1b50b041bdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001082638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1001082638
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2891968568
Short name T36
Test name
Test status
Simulation time 452810966 ps
CPU time 2.97 seconds
Started Jun 06 01:54:57 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 209876 kb
Host smart-beba2831-36e2-4073-a708-ba1452592a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891968568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2891968568
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3052695442
Short name T208
Test name
Test status
Simulation time 38885790473 ps
CPU time 220.54 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:58:38 PM PDT 24
Peak memory 222580 kb
Host smart-9db86827-1d51-4f9e-b2d5-74d94e6e2f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052695442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3052695442
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1952745629
Short name T4
Test name
Test status
Simulation time 898595803 ps
CPU time 5.19 seconds
Started Jun 06 01:55:11 PM PDT 24
Finished Jun 06 01:55:17 PM PDT 24
Peak memory 218252 kb
Host smart-549fed3c-18b8-4cbb-afc6-a850e9034245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952745629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1952745629
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3397677367
Short name T317
Test name
Test status
Simulation time 124350160 ps
CPU time 7.06 seconds
Started Jun 06 01:54:27 PM PDT 24
Finished Jun 06 01:54:35 PM PDT 24
Peak memory 214880 kb
Host smart-f59d1832-7e37-4076-b4d2-121bd8881d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397677367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3397677367
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3280674827
Short name T184
Test name
Test status
Simulation time 3939438295 ps
CPU time 31.07 seconds
Started Jun 06 01:54:35 PM PDT 24
Finished Jun 06 01:55:08 PM PDT 24
Peak memory 215480 kb
Host smart-4dd4388d-5b3e-46e6-94b0-717d3268f252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280674827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3280674827
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3867360050
Short name T96
Test name
Test status
Simulation time 40526514 ps
CPU time 2.67 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:08 PM PDT 24
Peak memory 214296 kb
Host smart-71c63d64-e5fb-4072-9263-323d1df3eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867360050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3867360050
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1796305605
Short name T162
Test name
Test status
Simulation time 181987130 ps
CPU time 4.42 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 222480 kb
Host smart-d6a1deb4-140c-47a9-8612-e2ca351ad8c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796305605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1796305605
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1689068511
Short name T39
Test name
Test status
Simulation time 1062477010 ps
CPU time 3.41 seconds
Started Jun 06 01:54:19 PM PDT 24
Finished Jun 06 01:54:24 PM PDT 24
Peak memory 222360 kb
Host smart-d6e49491-5fdf-4011-8784-48714e616d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689068511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1689068511
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.262383551
Short name T28
Test name
Test status
Simulation time 67121853 ps
CPU time 3.27 seconds
Started Jun 06 01:54:05 PM PDT 24
Finished Jun 06 01:54:10 PM PDT 24
Peak memory 210040 kb
Host smart-5b07517e-d051-47ee-8894-51bf90855ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262383551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.262383551
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1367837817
Short name T123
Test name
Test status
Simulation time 326009587 ps
CPU time 4.48 seconds
Started Jun 06 12:47:15 PM PDT 24
Finished Jun 06 12:47:20 PM PDT 24
Peak memory 214184 kb
Host smart-a173f8aa-9afb-4b98-aa00-7ba4589ca945
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367837817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1367837817
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2007697096
Short name T25
Test name
Test status
Simulation time 161485944 ps
CPU time 3.36 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 222660 kb
Host smart-62c2c991-24a3-4cea-aced-d0ea7dcc713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007697096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2007697096
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1420041450
Short name T21
Test name
Test status
Simulation time 181380761 ps
CPU time 3.12 seconds
Started Jun 06 01:56:02 PM PDT 24
Finished Jun 06 01:56:06 PM PDT 24
Peak memory 217668 kb
Host smart-aec1c89c-602c-4e3f-aa31-f659012eb3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420041450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1420041450
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2557902231
Short name T431
Test name
Test status
Simulation time 9416099869 ps
CPU time 111.9 seconds
Started Jun 06 01:55:52 PM PDT 24
Finished Jun 06 01:57:45 PM PDT 24
Peak memory 215060 kb
Host smart-19fa9021-0a27-4a09-80bd-c657a2cca6e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557902231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2557902231
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.144460253
Short name T209
Test name
Test status
Simulation time 1550946066 ps
CPU time 56.45 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:56:47 PM PDT 24
Peak memory 221252 kb
Host smart-f913c15f-40ff-4626-9211-227f6e86f7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144460253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.144460253
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1911250157
Short name T406
Test name
Test status
Simulation time 2865075429 ps
CPU time 12.78 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:10 PM PDT 24
Peak memory 222588 kb
Host smart-5a9ea4da-d6d9-45be-a201-484cf392e473
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911250157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1911250157
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.625152031
Short name T76
Test name
Test status
Simulation time 324063304 ps
CPU time 3.96 seconds
Started Jun 06 01:56:05 PM PDT 24
Finished Jun 06 01:56:10 PM PDT 24
Peak memory 221572 kb
Host smart-d2ca3fe5-d8a1-48f1-b13f-f2098ee5c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625152031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.625152031
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3795093256
Short name T233
Test name
Test status
Simulation time 419133016 ps
CPU time 19.14 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:19 PM PDT 24
Peak memory 215104 kb
Host smart-8cd6eb37-d4a8-4d98-b254-1b3f44fb74f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795093256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3795093256
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1380067247
Short name T109
Test name
Test status
Simulation time 29449592 ps
CPU time 0.76 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 205764 kb
Host smart-8f574e05-bf40-4931-b02b-99f9d54b24cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380067247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1380067247
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3398474295
Short name T280
Test name
Test status
Simulation time 560050848 ps
CPU time 30.92 seconds
Started Jun 06 01:54:05 PM PDT 24
Finished Jun 06 01:54:37 PM PDT 24
Peak memory 215404 kb
Host smart-48fa128d-cbb0-4535-81a3-612bd0b7596b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398474295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3398474295
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.37806021
Short name T255
Test name
Test status
Simulation time 306184375 ps
CPU time 15.54 seconds
Started Jun 06 01:54:52 PM PDT 24
Finished Jun 06 01:55:10 PM PDT 24
Peak memory 223296 kb
Host smart-cd2900c0-e77b-45e4-8f36-ed44297a73d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37806021 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.37806021
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.976985365
Short name T99
Test name
Test status
Simulation time 45539801 ps
CPU time 2.91 seconds
Started Jun 06 01:54:26 PM PDT 24
Finished Jun 06 01:54:30 PM PDT 24
Peak memory 214268 kb
Host smart-f965398a-fe48-4546-8818-da3c6ebc8be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976985365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.976985365
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1293504007
Short name T74
Test name
Test status
Simulation time 256175239 ps
CPU time 5.44 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:55:57 PM PDT 24
Peak memory 222668 kb
Host smart-396e6eb2-1051-4d70-9773-6b75fa16bca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293504007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1293504007
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.929968892
Short name T394
Test name
Test status
Simulation time 96199624 ps
CPU time 4.92 seconds
Started Jun 06 01:56:07 PM PDT 24
Finished Jun 06 01:56:13 PM PDT 24
Peak memory 214444 kb
Host smart-b86389e4-10e3-420c-b2b0-9dff345c8d22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929968892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.929968892
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.508596498
Short name T144
Test name
Test status
Simulation time 1505920205 ps
CPU time 20.58 seconds
Started Jun 06 01:54:50 PM PDT 24
Finished Jun 06 01:55:12 PM PDT 24
Peak memory 222628 kb
Host smart-12b223b6-3d60-470c-8163-9932a4d6edda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508596498 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.508596498
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2947195041
Short name T165
Test name
Test status
Simulation time 183360927 ps
CPU time 4.87 seconds
Started Jun 06 12:46:32 PM PDT 24
Finished Jun 06 12:46:38 PM PDT 24
Peak memory 213768 kb
Host smart-52d604f5-4a47-45f3-ac63-82bbc1a68185
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947195041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2947195041
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2268711676
Short name T173
Test name
Test status
Simulation time 1307479255 ps
CPU time 6.86 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:50 PM PDT 24
Peak memory 213776 kb
Host smart-d5d66203-49fc-4cf1-8b27-dafdc3785752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268711676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2268711676
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3543150161
Short name T259
Test name
Test status
Simulation time 1281268012 ps
CPU time 50.95 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:59 PM PDT 24
Peak memory 222548 kb
Host smart-bcab5df4-d54e-4118-92ad-adb0c5666960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543150161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3543150161
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1430918991
Short name T49
Test name
Test status
Simulation time 167912093 ps
CPU time 6.86 seconds
Started Jun 06 01:54:26 PM PDT 24
Finished Jun 06 01:54:34 PM PDT 24
Peak memory 209048 kb
Host smart-2d8b0982-e218-4ecf-b837-6b1c0ab87719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430918991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1430918991
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2309654765
Short name T292
Test name
Test status
Simulation time 61261136 ps
CPU time 2.27 seconds
Started Jun 06 01:53:55 PM PDT 24
Finished Jun 06 01:53:58 PM PDT 24
Peak memory 214364 kb
Host smart-063e1b3d-24ae-4c4a-b4ed-df0571f179aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309654765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2309654765
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.211196449
Short name T384
Test name
Test status
Simulation time 202383193 ps
CPU time 10.66 seconds
Started Jun 06 01:54:40 PM PDT 24
Finished Jun 06 01:54:52 PM PDT 24
Peak memory 214332 kb
Host smart-808442e1-e09f-4fbc-9bc8-c4c546569b6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211196449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.211196449
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.4171685654
Short name T238
Test name
Test status
Simulation time 133651558 ps
CPU time 5.48 seconds
Started Jun 06 01:55:44 PM PDT 24
Finished Jun 06 01:55:51 PM PDT 24
Peak memory 214364 kb
Host smart-1112252e-ef84-472b-87ea-4a6a5cd83d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171685654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4171685654
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1946943101
Short name T169
Test name
Test status
Simulation time 165666233 ps
CPU time 5.79 seconds
Started Jun 06 12:47:19 PM PDT 24
Finished Jun 06 12:47:26 PM PDT 24
Peak memory 213596 kb
Host smart-8d2a2d1b-8f38-486e-ab57-c6e618056b19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946943101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1946943101
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3635223892
Short name T177
Test name
Test status
Simulation time 85230913 ps
CPU time 2.3 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 210020 kb
Host smart-cfc872c9-3eaf-4d34-b86b-838e4a5e9691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635223892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3635223892
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3815875675
Short name T189
Test name
Test status
Simulation time 55984910 ps
CPU time 2.65 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:54:52 PM PDT 24
Peak memory 222652 kb
Host smart-e2f52a57-c0af-4859-b606-b655bb47c20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815875675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3815875675
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3172118993
Short name T188
Test name
Test status
Simulation time 73591082 ps
CPU time 3.57 seconds
Started Jun 06 01:54:58 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 217340 kb
Host smart-f9260017-1d83-47bc-8ad2-0304d6305e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172118993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3172118993
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.273896875
Short name T880
Test name
Test status
Simulation time 114832667 ps
CPU time 2.32 seconds
Started Jun 06 01:55:04 PM PDT 24
Finished Jun 06 01:55:07 PM PDT 24
Peak memory 220996 kb
Host smart-d3fba322-b1d5-4495-b80e-65bfc287cd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273896875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.273896875
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.488987045
Short name T305
Test name
Test status
Simulation time 297730465 ps
CPU time 2.94 seconds
Started Jun 06 01:55:44 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 215532 kb
Host smart-8b8b1d1a-823c-47d6-b2b9-94dd2c105b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488987045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.488987045
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3567522259
Short name T186
Test name
Test status
Simulation time 153248542 ps
CPU time 3.78 seconds
Started Jun 06 01:56:26 PM PDT 24
Finished Jun 06 01:56:33 PM PDT 24
Peak memory 217260 kb
Host smart-491b689a-3cfa-4cc3-9db8-363356c8b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567522259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3567522259
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.479166351
Short name T303
Test name
Test status
Simulation time 1253069849 ps
CPU time 39.6 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:39 PM PDT 24
Peak memory 209132 kb
Host smart-b89ff41e-47fd-4cc1-bcf1-0833497e1e1f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479166351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.479166351
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1322745574
Short name T167
Test name
Test status
Simulation time 246719574 ps
CPU time 5.1 seconds
Started Jun 06 12:46:54 PM PDT 24
Finished Jun 06 12:47:00 PM PDT 24
Peak memory 206024 kb
Host smart-ac1cbcd0-b647-4d0e-bbeb-32285ca837b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322745574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1322745574
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1343012374
Short name T132
Test name
Test status
Simulation time 582306565 ps
CPU time 4.29 seconds
Started Jun 06 12:46:57 PM PDT 24
Finished Jun 06 12:47:02 PM PDT 24
Peak memory 214220 kb
Host smart-40a21dbf-8f9c-4da3-a3b0-e6c6e26e324e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343012374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1343012374
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1611968198
Short name T175
Test name
Test status
Simulation time 83815017 ps
CPU time 2.68 seconds
Started Jun 06 12:46:53 PM PDT 24
Finished Jun 06 12:46:57 PM PDT 24
Peak memory 213700 kb
Host smart-8457e6a7-4a8f-46f2-8723-450ff4039bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611968198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1611968198
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1258446005
Short name T163
Test name
Test status
Simulation time 1616739636 ps
CPU time 8.95 seconds
Started Jun 06 12:47:09 PM PDT 24
Finished Jun 06 12:47:19 PM PDT 24
Peak memory 213784 kb
Host smart-8fa428cc-4a3b-4437-9dfb-09a3b18a12c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258446005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1258446005
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.4190679240
Short name T383
Test name
Test status
Simulation time 264925266 ps
CPU time 4.51 seconds
Started Jun 06 01:54:00 PM PDT 24
Finished Jun 06 01:54:06 PM PDT 24
Peak memory 214328 kb
Host smart-24b09415-c0d4-4821-934a-b00734a34718
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190679240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.4190679240
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1528839937
Short name T531
Test name
Test status
Simulation time 221916830 ps
CPU time 2.48 seconds
Started Jun 06 01:53:55 PM PDT 24
Finished Jun 06 01:53:58 PM PDT 24
Peak memory 210508 kb
Host smart-542e85f8-b670-4ffb-b1c9-e1b94e61de5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528839937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1528839937
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3985376043
Short name T832
Test name
Test status
Simulation time 1541484300 ps
CPU time 15.01 seconds
Started Jun 06 01:54:20 PM PDT 24
Finished Jun 06 01:54:36 PM PDT 24
Peak memory 215176 kb
Host smart-eb2deefb-4460-4423-99e2-0ee2af3e55db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985376043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3985376043
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1146982541
Short name T332
Test name
Test status
Simulation time 92560918 ps
CPU time 5.19 seconds
Started Jun 06 01:54:49 PM PDT 24
Finished Jun 06 01:54:56 PM PDT 24
Peak memory 214244 kb
Host smart-a59acf67-81f8-4852-ba7d-119a78454334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146982541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1146982541
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2755124667
Short name T258
Test name
Test status
Simulation time 4096643930 ps
CPU time 41.54 seconds
Started Jun 06 01:55:04 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 222568 kb
Host smart-6bbb85b0-99bb-4a06-89a1-230665fa9e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755124667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2755124667
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2960518947
Short name T83
Test name
Test status
Simulation time 2076384716 ps
CPU time 16.86 seconds
Started Jun 06 01:56:01 PM PDT 24
Finished Jun 06 01:56:19 PM PDT 24
Peak memory 222580 kb
Host smart-7657ae95-6a98-435b-ae6c-84ec58fd9c56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960518947 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2960518947
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2987669465
Short name T187
Test name
Test status
Simulation time 264878144 ps
CPU time 6.87 seconds
Started Jun 06 01:55:06 PM PDT 24
Finished Jun 06 01:55:14 PM PDT 24
Peak memory 218508 kb
Host smart-c9fb14b4-eee1-4b25-83c9-e3d67d502515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987669465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2987669465
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.41717421
Short name T293
Test name
Test status
Simulation time 91590278 ps
CPU time 2.74 seconds
Started Jun 06 01:54:04 PM PDT 24
Finished Jun 06 01:54:07 PM PDT 24
Peak memory 222484 kb
Host smart-693024bb-754e-4458-a54a-b6f0054905a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41717421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.41717421
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3325775281
Short name T369
Test name
Test status
Simulation time 163047076 ps
CPU time 8.86 seconds
Started Jun 06 01:54:22 PM PDT 24
Finished Jun 06 01:54:32 PM PDT 24
Peak memory 215344 kb
Host smart-fb6a387d-48d4-4a89-bdde-15fcccef7103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325775281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3325775281
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.664857389
Short name T93
Test name
Test status
Simulation time 184066907 ps
CPU time 2.7 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:54:41 PM PDT 24
Peak memory 208728 kb
Host smart-b49c8c16-7798-4466-9c93-e91714c9454f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664857389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.664857389
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_random.1939361073
Short name T95
Test name
Test status
Simulation time 133962912 ps
CPU time 4.62 seconds
Started Jun 06 01:54:47 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 218412 kb
Host smart-62e247c5-719e-4e9c-830a-1fe8eb318440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939361073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1939361073
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.42314461
Short name T272
Test name
Test status
Simulation time 76372413 ps
CPU time 2.81 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:50 PM PDT 24
Peak memory 214264 kb
Host smart-3839f2b2-a560-49ce-9343-f2b31d564507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42314461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.42314461
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.254877808
Short name T436
Test name
Test status
Simulation time 512522172 ps
CPU time 6.47 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:06 PM PDT 24
Peak memory 215236 kb
Host smart-ef7ff08e-2f30-4ade-a3fc-107ce77546a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254877808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.254877808
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1533275674
Short name T237
Test name
Test status
Simulation time 2258785130 ps
CPU time 24.98 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 222616 kb
Host smart-ae7864b1-4f9f-4c6f-ba77-f73dc3bb9718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533275674 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1533275674
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3692622985
Short name T359
Test name
Test status
Simulation time 289307827 ps
CPU time 4.74 seconds
Started Jun 06 01:55:03 PM PDT 24
Finished Jun 06 01:55:08 PM PDT 24
Peak memory 214280 kb
Host smart-5752077b-41b9-4e68-afb1-5d71ef740ddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692622985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3692622985
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1813171711
Short name T386
Test name
Test status
Simulation time 71725050 ps
CPU time 4.09 seconds
Started Jun 06 01:55:06 PM PDT 24
Finished Jun 06 01:55:10 PM PDT 24
Peak memory 215408 kb
Host smart-dcba803c-790f-4c6d-b05c-8d3759ee611e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813171711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1813171711
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1753644880
Short name T149
Test name
Test status
Simulation time 1286591303 ps
CPU time 26.22 seconds
Started Jun 06 01:55:08 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 221088 kb
Host smart-09fdbe8d-de11-4237-a7fe-69f1da81c86f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753644880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1753644880
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1348739028
Short name T279
Test name
Test status
Simulation time 3335923538 ps
CPU time 32.71 seconds
Started Jun 06 01:55:34 PM PDT 24
Finished Jun 06 01:56:08 PM PDT 24
Peak memory 222408 kb
Host smart-f2e7613e-b405-4f4c-b3dc-d5e349e0806d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348739028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1348739028
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3565625234
Short name T241
Test name
Test status
Simulation time 1721131891 ps
CPU time 8.46 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 219916 kb
Host smart-f13cf0ea-3f9e-4baf-9245-cab6aca06c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565625234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3565625234
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.4230537833
Short name T182
Test name
Test status
Simulation time 269560860 ps
CPU time 5.68 seconds
Started Jun 06 12:47:10 PM PDT 24
Finished Jun 06 12:47:17 PM PDT 24
Peak memory 215000 kb
Host smart-72da22fd-5f2d-4a59-a0b1-279c0daf9c35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230537833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.4230537833
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2154810803
Short name T179
Test name
Test status
Simulation time 98902845 ps
CPU time 2.61 seconds
Started Jun 06 12:47:05 PM PDT 24
Finished Jun 06 12:47:09 PM PDT 24
Peak memory 213880 kb
Host smart-1e676cf6-c5d2-4299-8397-c840fb8fc65f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154810803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2154810803
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3083723690
Short name T171
Test name
Test status
Simulation time 79667531 ps
CPU time 3.47 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:47 PM PDT 24
Peak memory 213676 kb
Host smart-560b86c9-5476-413e-a4fa-3a282a849c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083723690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3083723690
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1015951454
Short name T170
Test name
Test status
Simulation time 606324609 ps
CPU time 4.11 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:48 PM PDT 24
Peak memory 213824 kb
Host smart-c5fc9df9-81dd-4624-8de3-faa317ca22b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015951454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1015951454
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1561439400
Short name T181
Test name
Test status
Simulation time 63874063 ps
CPU time 2.6 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 210212 kb
Host smart-074a1bfc-8d3c-4956-bf06-b70cf389ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561439400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1561439400
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2756299190
Short name T190
Test name
Test status
Simulation time 97313031 ps
CPU time 3.15 seconds
Started Jun 06 01:54:53 PM PDT 24
Finished Jun 06 01:54:58 PM PDT 24
Peak memory 215000 kb
Host smart-ae23f8c0-886f-44f0-ab9f-1edcfe3232ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756299190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2756299190
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1483055290
Short name T510
Test name
Test status
Simulation time 110730509 ps
CPU time 2.12 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 208788 kb
Host smart-3c611192-4aa4-4718-a75c-1e05de298162
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483055290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1483055290
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1477477336
Short name T100
Test name
Test status
Simulation time 183187337 ps
CPU time 4.6 seconds
Started Jun 06 01:54:25 PM PDT 24
Finished Jun 06 01:54:30 PM PDT 24
Peak memory 214172 kb
Host smart-e6d4f200-0fe4-4dec-a905-9cd356343717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477477336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1477477336
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.407777973
Short name T837
Test name
Test status
Simulation time 110518066 ps
CPU time 4.16 seconds
Started Jun 06 01:54:17 PM PDT 24
Finished Jun 06 01:54:21 PM PDT 24
Peak memory 208504 kb
Host smart-f6749b19-9369-472a-9f47-b5d1bc8d3387
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407777973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.407777973
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.43896522
Short name T229
Test name
Test status
Simulation time 59044068 ps
CPU time 2.68 seconds
Started Jun 06 01:54:25 PM PDT 24
Finished Jun 06 01:54:28 PM PDT 24
Peak memory 215988 kb
Host smart-7a4a38f4-5e20-42a1-9a6a-3973a6e2be6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43896522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.43896522
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2979325050
Short name T263
Test name
Test status
Simulation time 234996273 ps
CPU time 3.63 seconds
Started Jun 06 01:54:25 PM PDT 24
Finished Jun 06 01:54:30 PM PDT 24
Peak memory 209148 kb
Host smart-5efa6f28-38af-49b8-af5c-9167983a4315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979325050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2979325050
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.189334586
Short name T636
Test name
Test status
Simulation time 227478319 ps
CPU time 3.71 seconds
Started Jun 06 01:54:37 PM PDT 24
Finished Jun 06 01:54:43 PM PDT 24
Peak memory 209180 kb
Host smart-ccdb866a-509d-4ad0-8e75-0f5eeca5b3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189334586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.189334586
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1500995684
Short name T331
Test name
Test status
Simulation time 414945359 ps
CPU time 4.93 seconds
Started Jun 06 01:54:38 PM PDT 24
Finished Jun 06 01:54:44 PM PDT 24
Peak memory 222520 kb
Host smart-f9a3496f-248e-4828-a5a5-3447c5ecf170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500995684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1500995684
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1100830615
Short name T372
Test name
Test status
Simulation time 84526986 ps
CPU time 3.16 seconds
Started Jun 06 01:54:51 PM PDT 24
Finished Jun 06 01:54:56 PM PDT 24
Peak memory 214292 kb
Host smart-091fe360-f530-4988-bc11-3b9c6f38144f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100830615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1100830615
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1910613181
Short name T337
Test name
Test status
Simulation time 167167161 ps
CPU time 2.19 seconds
Started Jun 06 01:54:53 PM PDT 24
Finished Jun 06 01:54:57 PM PDT 24
Peak memory 210136 kb
Host smart-efddfb03-c682-44bc-b6ff-b982adada801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910613181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1910613181
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2259177384
Short name T366
Test name
Test status
Simulation time 65314914 ps
CPU time 2.47 seconds
Started Jun 06 01:54:49 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 214360 kb
Host smart-41665480-ffe4-41d7-986a-91fd28b77866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259177384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2259177384
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1383345581
Short name T257
Test name
Test status
Simulation time 3232751217 ps
CPU time 21.17 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:19 PM PDT 24
Peak memory 222576 kb
Host smart-142d9c12-33b9-4918-9081-f9c4491bebde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383345581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1383345581
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3888924248
Short name T298
Test name
Test status
Simulation time 1672403565 ps
CPU time 43.32 seconds
Started Jun 06 01:53:59 PM PDT 24
Finished Jun 06 01:54:44 PM PDT 24
Peak memory 217136 kb
Host smart-e91c3fad-8503-4a50-a21e-47fe4a624eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888924248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3888924248
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3719880769
Short name T254
Test name
Test status
Simulation time 157607470 ps
CPU time 4.6 seconds
Started Jun 06 01:54:59 PM PDT 24
Finished Jun 06 01:55:05 PM PDT 24
Peak memory 222444 kb
Host smart-47686eb0-f7f0-4dcd-9904-dfc4b0606206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719880769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3719880769
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.4092233735
Short name T667
Test name
Test status
Simulation time 118247147 ps
CPU time 3.92 seconds
Started Jun 06 01:55:06 PM PDT 24
Finished Jun 06 01:55:10 PM PDT 24
Peak memory 209748 kb
Host smart-c838ec78-05c2-4f36-be96-a4e14bbfc3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092233735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.4092233735
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.4028892965
Short name T269
Test name
Test status
Simulation time 44655209 ps
CPU time 2.46 seconds
Started Jun 06 01:55:07 PM PDT 24
Finished Jun 06 01:55:10 PM PDT 24
Peak memory 214212 kb
Host smart-129d20c6-9a62-469b-8a27-b428efcb07ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028892965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.4028892965
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2035570684
Short name T251
Test name
Test status
Simulation time 772030765 ps
CPU time 4.04 seconds
Started Jun 06 01:55:02 PM PDT 24
Finished Jun 06 01:55:07 PM PDT 24
Peak memory 214364 kb
Host smart-26240609-83d4-44df-a8dd-91e22b4b8654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035570684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2035570684
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3076631111
Short name T246
Test name
Test status
Simulation time 1396414771 ps
CPU time 10.23 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:24 PM PDT 24
Peak memory 214472 kb
Host smart-536dde3c-b61b-4867-a654-edc40d358f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076631111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3076631111
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.4258003865
Short name T271
Test name
Test status
Simulation time 189372606 ps
CPU time 2.76 seconds
Started Jun 06 01:55:27 PM PDT 24
Finished Jun 06 01:55:30 PM PDT 24
Peak memory 210364 kb
Host smart-1c29e68b-6199-436c-881d-5868e4809ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258003865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.4258003865
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2899974964
Short name T264
Test name
Test status
Simulation time 74279083 ps
CPU time 4.13 seconds
Started Jun 06 01:55:34 PM PDT 24
Finished Jun 06 01:55:40 PM PDT 24
Peak memory 214388 kb
Host smart-5469ac97-10de-47e5-a5b4-df4688a7e829
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899974964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2899974964
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2759853019
Short name T399
Test name
Test status
Simulation time 2003231071 ps
CPU time 23.13 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:56 PM PDT 24
Peak memory 222684 kb
Host smart-0e263b21-6f07-4f7c-be4e-f33ebb3a74db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759853019 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2759853019
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1114823213
Short name T256
Test name
Test status
Simulation time 2576647198 ps
CPU time 38.7 seconds
Started Jun 06 01:56:01 PM PDT 24
Finished Jun 06 01:56:41 PM PDT 24
Peak memory 222564 kb
Host smart-e72a366b-0906-42a1-94dc-a61dc59a0f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114823213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1114823213
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1623547669
Short name T1003
Test name
Test status
Simulation time 140592745 ps
CPU time 4.41 seconds
Started Jun 06 12:46:25 PM PDT 24
Finished Jun 06 12:46:30 PM PDT 24
Peak memory 205620 kb
Host smart-8af94d11-0399-48a4-926b-b08da4d6bfda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623547669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
623547669
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1483113362
Short name T1026
Test name
Test status
Simulation time 3459530385 ps
CPU time 15.27 seconds
Started Jun 06 12:46:24 PM PDT 24
Finished Jun 06 12:46:41 PM PDT 24
Peak memory 205664 kb
Host smart-7f06bdab-423e-4b25-96aa-bfd3e6cfa702
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483113362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
483113362
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1612751904
Short name T1062
Test name
Test status
Simulation time 40282621 ps
CPU time 1.1 seconds
Started Jun 06 12:46:35 PM PDT 24
Finished Jun 06 12:46:37 PM PDT 24
Peak memory 205552 kb
Host smart-6f7975e6-b70a-4bba-8dac-afdd23ce6f1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612751904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
612751904
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4033963017
Short name T985
Test name
Test status
Simulation time 31821295 ps
CPU time 1.48 seconds
Started Jun 06 12:46:35 PM PDT 24
Finished Jun 06 12:46:37 PM PDT 24
Peak memory 213784 kb
Host smart-2bba8fc7-6567-4ecc-baee-4ea86b32b519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033963017 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.4033963017
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2674485172
Short name T156
Test name
Test status
Simulation time 9420640 ps
CPU time 0.97 seconds
Started Jun 06 12:46:24 PM PDT 24
Finished Jun 06 12:46:26 PM PDT 24
Peak memory 205376 kb
Host smart-aada1bde-970c-4453-a8dd-d534e4564a2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674485172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2674485172
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.531057819
Short name T1053
Test name
Test status
Simulation time 37327867 ps
CPU time 0.81 seconds
Started Jun 06 12:46:23 PM PDT 24
Finished Jun 06 12:46:25 PM PDT 24
Peak memory 205216 kb
Host smart-3a17144d-4fad-4310-bb49-19e2bb9e3e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531057819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.531057819
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3454420804
Short name T1042
Test name
Test status
Simulation time 187617811 ps
CPU time 2.52 seconds
Started Jun 06 12:46:26 PM PDT 24
Finished Jun 06 12:46:29 PM PDT 24
Peak memory 205548 kb
Host smart-2629b74e-508e-4238-84dd-6802e30a6404
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454420804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3454420804
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2691321533
Short name T987
Test name
Test status
Simulation time 681945810 ps
CPU time 3.43 seconds
Started Jun 06 12:46:34 PM PDT 24
Finished Jun 06 12:46:38 PM PDT 24
Peak memory 214160 kb
Host smart-f3efa8f2-1548-44c7-ab2a-a2b3374f4a67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691321533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2691321533
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1602743323
Short name T1083
Test name
Test status
Simulation time 768680303 ps
CPU time 4.66 seconds
Started Jun 06 12:46:35 PM PDT 24
Finished Jun 06 12:46:41 PM PDT 24
Peak memory 214176 kb
Host smart-70ca82a6-eaad-4de6-978a-e072793d3381
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602743323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1602743323
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2056932889
Short name T194
Test name
Test status
Simulation time 2400878947 ps
CPU time 3.77 seconds
Started Jun 06 12:46:24 PM PDT 24
Finished Jun 06 12:46:29 PM PDT 24
Peak memory 213880 kb
Host smart-2aa5566d-2ea4-46f3-8061-06e9cdca4c64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056932889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2056932889
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1789374676
Short name T176
Test name
Test status
Simulation time 104042880 ps
CPU time 3.15 seconds
Started Jun 06 12:46:36 PM PDT 24
Finished Jun 06 12:46:40 PM PDT 24
Peak memory 213928 kb
Host smart-caa28127-4c98-4e91-9f4f-912e18a90ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789374676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1789374676
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3242313335
Short name T1014
Test name
Test status
Simulation time 192312769 ps
CPU time 4.58 seconds
Started Jun 06 12:46:57 PM PDT 24
Finished Jun 06 12:47:02 PM PDT 24
Peak memory 205592 kb
Host smart-06f5da55-62ca-4cbb-ae47-d01ffc8c030f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242313335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
242313335
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3684138882
Short name T1011
Test name
Test status
Simulation time 1146311292 ps
CPU time 14.4 seconds
Started Jun 06 12:46:34 PM PDT 24
Finished Jun 06 12:46:50 PM PDT 24
Peak memory 205660 kb
Host smart-87b01031-5b5d-402a-bb7b-a469872634b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684138882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
684138882
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4154258976
Short name T944
Test name
Test status
Simulation time 108312906 ps
CPU time 1.17 seconds
Started Jun 06 12:46:36 PM PDT 24
Finished Jun 06 12:46:38 PM PDT 24
Peak memory 205608 kb
Host smart-9f91569b-2f94-42c5-970b-88fdf46d330c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154258976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.4
154258976
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1555895414
Short name T1027
Test name
Test status
Simulation time 179732589 ps
CPU time 1.9 seconds
Started Jun 06 12:46:33 PM PDT 24
Finished Jun 06 12:46:36 PM PDT 24
Peak memory 213768 kb
Host smart-26a395f1-9c3f-4cf1-b767-1e0d7ea4f3ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555895414 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1555895414
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.757128760
Short name T989
Test name
Test status
Simulation time 21261509 ps
CPU time 1.01 seconds
Started Jun 06 12:46:35 PM PDT 24
Finished Jun 06 12:46:36 PM PDT 24
Peak memory 205432 kb
Host smart-dee6eb93-8dbb-4ddc-aca5-1d0c385e483d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757128760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.757128760
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1782539255
Short name T924
Test name
Test status
Simulation time 20382032 ps
CPU time 0.71 seconds
Started Jun 06 12:46:35 PM PDT 24
Finished Jun 06 12:46:38 PM PDT 24
Peak memory 205208 kb
Host smart-873d0020-0ebb-4e64-ac49-f5c72efa83a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782539255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1782539255
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1823474517
Short name T1050
Test name
Test status
Simulation time 211464468 ps
CPU time 2.12 seconds
Started Jun 06 12:46:36 PM PDT 24
Finished Jun 06 12:46:39 PM PDT 24
Peak memory 205592 kb
Host smart-8226595d-33d8-437f-bcee-78e90150680d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823474517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1823474517
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2816093307
Short name T1047
Test name
Test status
Simulation time 377485191 ps
CPU time 2.3 seconds
Started Jun 06 12:46:22 PM PDT 24
Finished Jun 06 12:46:25 PM PDT 24
Peak memory 214160 kb
Host smart-59b700df-a6de-4e46-8f96-c9e581149a73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816093307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2816093307
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2630498475
Short name T981
Test name
Test status
Simulation time 739728388 ps
CPU time 8.02 seconds
Started Jun 06 12:46:23 PM PDT 24
Finished Jun 06 12:46:32 PM PDT 24
Peak memory 214184 kb
Host smart-9981afc7-624a-467b-a48e-039a79293a0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630498475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2630498475
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2011443509
Short name T1060
Test name
Test status
Simulation time 53639448 ps
CPU time 1.81 seconds
Started Jun 06 12:46:34 PM PDT 24
Finished Jun 06 12:46:37 PM PDT 24
Peak memory 213780 kb
Host smart-cd738e25-6974-43bf-972b-d239db53048e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011443509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2011443509
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2192207671
Short name T968
Test name
Test status
Simulation time 29772932 ps
CPU time 1.99 seconds
Started Jun 06 12:46:53 PM PDT 24
Finished Jun 06 12:46:56 PM PDT 24
Peak memory 213800 kb
Host smart-154e4625-33fb-4c13-a7ee-f90be5dbbbbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192207671 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2192207671
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4264596058
Short name T933
Test name
Test status
Simulation time 50167748 ps
CPU time 1.19 seconds
Started Jun 06 12:46:54 PM PDT 24
Finished Jun 06 12:46:57 PM PDT 24
Peak memory 205592 kb
Host smart-27e65ec8-8335-4b16-bc62-4fc745e14942
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264596058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4264596058
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1266086525
Short name T1073
Test name
Test status
Simulation time 37811577 ps
CPU time 0.8 seconds
Started Jun 06 12:46:58 PM PDT 24
Finished Jun 06 12:47:00 PM PDT 24
Peak memory 205324 kb
Host smart-4a512214-21ae-4764-a390-b1faa7972cde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266086525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1266086525
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1064987916
Short name T965
Test name
Test status
Simulation time 93608816 ps
CPU time 2.14 seconds
Started Jun 06 12:46:56 PM PDT 24
Finished Jun 06 12:47:00 PM PDT 24
Peak memory 205480 kb
Host smart-c930c0ec-b0fc-41d8-8685-a86b71581f68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064987916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1064987916
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.762424557
Short name T1022
Test name
Test status
Simulation time 345959080 ps
CPU time 3.43 seconds
Started Jun 06 12:46:53 PM PDT 24
Finished Jun 06 12:46:57 PM PDT 24
Peak memory 214052 kb
Host smart-40289122-59c7-4432-aed3-84ac5d3d23df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762424557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.762424557
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.313886125
Short name T953
Test name
Test status
Simulation time 142852140 ps
CPU time 4.44 seconds
Started Jun 06 12:46:54 PM PDT 24
Finished Jun 06 12:47:00 PM PDT 24
Peak memory 214108 kb
Host smart-00b62aca-165f-40bf-b378-b4fd30838f7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313886125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.313886125
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2953157958
Short name T1058
Test name
Test status
Simulation time 44280361 ps
CPU time 2.67 seconds
Started Jun 06 12:46:55 PM PDT 24
Finished Jun 06 12:46:59 PM PDT 24
Peak memory 213788 kb
Host smart-1d2f5601-4cd9-4044-8a94-cc2bf8d6a298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953157958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2953157958
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2995926072
Short name T976
Test name
Test status
Simulation time 54204058 ps
CPU time 1.69 seconds
Started Jun 06 12:46:55 PM PDT 24
Finished Jun 06 12:46:59 PM PDT 24
Peak memory 213948 kb
Host smart-8b741c08-8cad-4197-a220-8b3d565318ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995926072 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2995926072
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4109101440
Short name T159
Test name
Test status
Simulation time 40623069 ps
CPU time 1.06 seconds
Started Jun 06 12:46:58 PM PDT 24
Finished Jun 06 12:47:00 PM PDT 24
Peak memory 205564 kb
Host smart-353f42f9-5780-4a62-962b-b322da64020a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109101440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4109101440
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2334038983
Short name T950
Test name
Test status
Simulation time 49195079 ps
CPU time 0.76 seconds
Started Jun 06 12:46:53 PM PDT 24
Finished Jun 06 12:46:55 PM PDT 24
Peak memory 205284 kb
Host smart-cff80a35-5d1a-44d8-9707-a0ffe9182279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334038983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2334038983
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3516295322
Short name T198
Test name
Test status
Simulation time 258252179 ps
CPU time 2.76 seconds
Started Jun 06 12:46:56 PM PDT 24
Finished Jun 06 12:47:00 PM PDT 24
Peak memory 205604 kb
Host smart-56f9dead-5477-445e-bde5-f89f82f7e8b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516295322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3516295322
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2495276071
Short name T1024
Test name
Test status
Simulation time 1879752191 ps
CPU time 10.63 seconds
Started Jun 06 12:46:56 PM PDT 24
Finished Jun 06 12:47:08 PM PDT 24
Peak memory 214200 kb
Host smart-306b92e8-47af-45f6-895a-4f5b595d126f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495276071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2495276071
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1293693139
Short name T967
Test name
Test status
Simulation time 128418076 ps
CPU time 1.7 seconds
Started Jun 06 12:46:53 PM PDT 24
Finished Jun 06 12:46:56 PM PDT 24
Peak memory 214108 kb
Host smart-6a91d0b6-9062-4ece-ae34-d6c72fea6a59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293693139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1293693139
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2898170525
Short name T1074
Test name
Test status
Simulation time 24780711 ps
CPU time 1.42 seconds
Started Jun 06 12:46:56 PM PDT 24
Finished Jun 06 12:46:59 PM PDT 24
Peak memory 213848 kb
Host smart-53d314af-6398-40c4-9560-310c126dce39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898170525 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2898170525
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3704434780
Short name T1018
Test name
Test status
Simulation time 53427222 ps
CPU time 1.05 seconds
Started Jun 06 12:46:53 PM PDT 24
Finished Jun 06 12:46:55 PM PDT 24
Peak memory 205600 kb
Host smart-58c13161-bf43-4ce4-bd39-1e4be1da1f87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704434780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3704434780
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1468125295
Short name T1021
Test name
Test status
Simulation time 11808944 ps
CPU time 0.84 seconds
Started Jun 06 12:46:55 PM PDT 24
Finished Jun 06 12:46:58 PM PDT 24
Peak memory 205172 kb
Host smart-b35af9b5-2daf-4744-a791-76e95c0fd730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468125295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1468125295
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3694612148
Short name T1005
Test name
Test status
Simulation time 61775530 ps
CPU time 1.69 seconds
Started Jun 06 12:46:57 PM PDT 24
Finished Jun 06 12:47:00 PM PDT 24
Peak memory 205520 kb
Host smart-0664404b-58f0-43a3-a50c-8fc1d74739e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694612148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3694612148
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3298170293
Short name T984
Test name
Test status
Simulation time 459080234 ps
CPU time 2 seconds
Started Jun 06 12:46:55 PM PDT 24
Finished Jun 06 12:46:59 PM PDT 24
Peak memory 214140 kb
Host smart-b36af1a7-2242-447b-a822-12a1d1ff758b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298170293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3298170293
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.307965866
Short name T966
Test name
Test status
Simulation time 442499958 ps
CPU time 8.95 seconds
Started Jun 06 12:46:55 PM PDT 24
Finished Jun 06 12:47:05 PM PDT 24
Peak memory 214212 kb
Host smart-6350885c-a4d8-4f89-b56e-25971427aff8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307965866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.307965866
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2170604412
Short name T961
Test name
Test status
Simulation time 81533045 ps
CPU time 2.62 seconds
Started Jun 06 12:46:54 PM PDT 24
Finished Jun 06 12:46:58 PM PDT 24
Peak memory 213768 kb
Host smart-982858b7-758d-46c7-8104-c88028f953bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170604412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2170604412
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2516123518
Short name T174
Test name
Test status
Simulation time 2134548033 ps
CPU time 11.06 seconds
Started Jun 06 12:46:56 PM PDT 24
Finished Jun 06 12:47:09 PM PDT 24
Peak memory 205788 kb
Host smart-c0fc2e58-016b-4d96-8593-7d5a78c2935b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516123518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2516123518
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2190677941
Short name T931
Test name
Test status
Simulation time 139317465 ps
CPU time 1.38 seconds
Started Jun 06 12:47:06 PM PDT 24
Finished Jun 06 12:47:09 PM PDT 24
Peak memory 213728 kb
Host smart-17b6745b-8f54-4c42-b79b-e604ef9561eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190677941 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2190677941
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2324605299
Short name T991
Test name
Test status
Simulation time 208878601 ps
CPU time 1.42 seconds
Started Jun 06 12:47:08 PM PDT 24
Finished Jun 06 12:47:11 PM PDT 24
Peak memory 205588 kb
Host smart-825ce361-1421-4b5d-8624-28c5884850ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324605299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2324605299
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3707886300
Short name T934
Test name
Test status
Simulation time 23574819 ps
CPU time 0.79 seconds
Started Jun 06 12:47:07 PM PDT 24
Finished Jun 06 12:47:09 PM PDT 24
Peak memory 205280 kb
Host smart-eaceff34-5022-4484-9639-ab57e00c66aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707886300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3707886300
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3342575481
Short name T1068
Test name
Test status
Simulation time 87541255 ps
CPU time 3.6 seconds
Started Jun 06 12:47:06 PM PDT 24
Finished Jun 06 12:47:11 PM PDT 24
Peak memory 205532 kb
Host smart-c452541b-3402-41d1-b8e6-3a823330d916
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342575481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3342575481
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3521495016
Short name T1035
Test name
Test status
Simulation time 94448919 ps
CPU time 3.13 seconds
Started Jun 06 12:46:55 PM PDT 24
Finished Jun 06 12:46:59 PM PDT 24
Peak memory 214092 kb
Host smart-9df92de8-c0e0-4cbf-a0c6-b1dd5505203d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521495016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3521495016
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2439166548
Short name T131
Test name
Test status
Simulation time 850005789 ps
CPU time 10.32 seconds
Started Jun 06 12:47:07 PM PDT 24
Finished Jun 06 12:47:18 PM PDT 24
Peak memory 214084 kb
Host smart-f90bd4b3-6044-4faf-ab19-b6f91e10c6a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439166548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2439166548
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3129124280
Short name T946
Test name
Test status
Simulation time 111929816 ps
CPU time 1.88 seconds
Started Jun 06 12:47:06 PM PDT 24
Finished Jun 06 12:47:09 PM PDT 24
Peak memory 213892 kb
Host smart-74b64438-8e62-418f-ab6f-791e535e66d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129124280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3129124280
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2983472002
Short name T1059
Test name
Test status
Simulation time 193970761 ps
CPU time 1.91 seconds
Started Jun 06 12:47:05 PM PDT 24
Finished Jun 06 12:47:08 PM PDT 24
Peak memory 213752 kb
Host smart-342807ad-3e34-456f-978c-e7fa864e6892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983472002 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2983472002
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2903584943
Short name T1025
Test name
Test status
Simulation time 100608026 ps
CPU time 1.47 seconds
Started Jun 06 12:47:09 PM PDT 24
Finished Jun 06 12:47:12 PM PDT 24
Peak memory 205440 kb
Host smart-81a98a55-b931-45d1-b5c1-e8d2c1b3a508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903584943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2903584943
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.995770785
Short name T1076
Test name
Test status
Simulation time 12926750 ps
CPU time 0.87 seconds
Started Jun 06 12:47:06 PM PDT 24
Finished Jun 06 12:47:08 PM PDT 24
Peak memory 205152 kb
Host smart-8a3f7877-f0a6-4a47-9b98-29fb68ed5e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995770785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.995770785
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3135632463
Short name T197
Test name
Test status
Simulation time 110517199 ps
CPU time 2.87 seconds
Started Jun 06 12:47:08 PM PDT 24
Finished Jun 06 12:47:12 PM PDT 24
Peak memory 205620 kb
Host smart-4d623067-99c8-4ce1-8e07-ec8bbab04a37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135632463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3135632463
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2123384128
Short name T980
Test name
Test status
Simulation time 101061847 ps
CPU time 2.22 seconds
Started Jun 06 12:47:05 PM PDT 24
Finished Jun 06 12:47:08 PM PDT 24
Peak memory 214176 kb
Host smart-09018181-9d7d-41f4-a166-1bec6c4c7ac9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123384128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2123384128
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.355392000
Short name T1070
Test name
Test status
Simulation time 101984177 ps
CPU time 4.77 seconds
Started Jun 06 12:47:10 PM PDT 24
Finished Jun 06 12:47:15 PM PDT 24
Peak memory 222388 kb
Host smart-d2d67fa8-e972-437e-b295-cb92a635a9dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355392000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.355392000
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3861635365
Short name T937
Test name
Test status
Simulation time 419196317 ps
CPU time 3.29 seconds
Started Jun 06 12:47:10 PM PDT 24
Finished Jun 06 12:47:14 PM PDT 24
Peak memory 214704 kb
Host smart-efbb99af-5a44-4e45-ad46-2b253db0d5e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861635365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3861635365
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3340929410
Short name T1006
Test name
Test status
Simulation time 30006951 ps
CPU time 1.17 seconds
Started Jun 06 12:47:09 PM PDT 24
Finished Jun 06 12:47:11 PM PDT 24
Peak memory 205396 kb
Host smart-7f92b313-380c-4166-a003-c168562d075e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340929410 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3340929410
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3924028883
Short name T960
Test name
Test status
Simulation time 47415463 ps
CPU time 0.9 seconds
Started Jun 06 12:47:10 PM PDT 24
Finished Jun 06 12:47:12 PM PDT 24
Peak memory 205332 kb
Host smart-297dbf53-3e05-4b11-8941-e36b4a9989e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924028883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3924028883
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2960973776
Short name T1081
Test name
Test status
Simulation time 26722675 ps
CPU time 0.74 seconds
Started Jun 06 12:47:07 PM PDT 24
Finished Jun 06 12:47:09 PM PDT 24
Peak memory 205160 kb
Host smart-9adcffe0-9228-4792-9c6a-00b5e01577e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960973776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2960973776
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3276369413
Short name T962
Test name
Test status
Simulation time 234180633 ps
CPU time 2.17 seconds
Started Jun 06 12:47:05 PM PDT 24
Finished Jun 06 12:47:09 PM PDT 24
Peak memory 205452 kb
Host smart-e202cb46-7ac3-4c6c-9c88-43e8e9e4b081
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276369413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3276369413
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3271602078
Short name T128
Test name
Test status
Simulation time 71142044 ps
CPU time 2.36 seconds
Started Jun 06 12:47:10 PM PDT 24
Finished Jun 06 12:47:13 PM PDT 24
Peak memory 214184 kb
Host smart-c8aa0752-b2ea-4f4c-b43b-e9ae6980196b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271602078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3271602078
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3015125353
Short name T1069
Test name
Test status
Simulation time 836226147 ps
CPU time 9.46 seconds
Started Jun 06 12:47:06 PM PDT 24
Finished Jun 06 12:47:17 PM PDT 24
Peak memory 214168 kb
Host smart-71ab126b-e032-446b-b9fb-e271f48bd6e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015125353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3015125353
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2885113404
Short name T932
Test name
Test status
Simulation time 34169279 ps
CPU time 1.37 seconds
Started Jun 06 12:47:08 PM PDT 24
Finished Jun 06 12:47:10 PM PDT 24
Peak memory 221868 kb
Host smart-7e2ec603-f267-4a62-af9e-edca89cd15c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885113404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2885113404
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3723149503
Short name T997
Test name
Test status
Simulation time 62151197 ps
CPU time 1.5 seconds
Started Jun 06 12:47:06 PM PDT 24
Finished Jun 06 12:47:09 PM PDT 24
Peak memory 213796 kb
Host smart-f302a07a-acb6-416d-936c-3fec0d135056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723149503 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3723149503
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.504676685
Short name T157
Test name
Test status
Simulation time 26279897 ps
CPU time 1.19 seconds
Started Jun 06 12:47:09 PM PDT 24
Finished Jun 06 12:47:11 PM PDT 24
Peak memory 205676 kb
Host smart-cbbc331f-3ccb-4ff9-851f-27a4c257bfae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504676685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.504676685
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3420402908
Short name T935
Test name
Test status
Simulation time 16762155 ps
CPU time 0.93 seconds
Started Jun 06 12:47:06 PM PDT 24
Finished Jun 06 12:47:08 PM PDT 24
Peak memory 205364 kb
Host smart-e613c338-8a88-479d-8a9e-e9a965e26406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420402908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3420402908
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1260869829
Short name T161
Test name
Test status
Simulation time 1706567427 ps
CPU time 3.85 seconds
Started Jun 06 12:47:07 PM PDT 24
Finished Jun 06 12:47:12 PM PDT 24
Peak memory 205632 kb
Host smart-5944ab76-ccdc-463f-a79f-7282ac85598d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260869829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1260869829
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.55135395
Short name T1016
Test name
Test status
Simulation time 242538424 ps
CPU time 2.56 seconds
Started Jun 06 12:47:08 PM PDT 24
Finished Jun 06 12:47:12 PM PDT 24
Peak memory 214072 kb
Host smart-d035f809-3a8d-49f9-80e8-659f67cbffee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55135395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow
_reg_errors.55135395
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2564399667
Short name T125
Test name
Test status
Simulation time 388872996 ps
CPU time 3.55 seconds
Started Jun 06 12:47:05 PM PDT 24
Finished Jun 06 12:47:10 PM PDT 24
Peak memory 214176 kb
Host smart-83de9f13-d920-457c-a73f-448f182e3a36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564399667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2564399667
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3538952594
Short name T995
Test name
Test status
Simulation time 57954386 ps
CPU time 3.53 seconds
Started Jun 06 12:47:06 PM PDT 24
Finished Jun 06 12:47:11 PM PDT 24
Peak memory 213860 kb
Host smart-977816e6-9bce-4667-ad63-b77a11b2bbb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538952594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3538952594
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3897965115
Short name T168
Test name
Test status
Simulation time 186497827 ps
CPU time 2.47 seconds
Started Jun 06 12:47:08 PM PDT 24
Finished Jun 06 12:47:12 PM PDT 24
Peak memory 213784 kb
Host smart-2b9bbca6-e4bf-4847-b345-4a50c7494959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897965115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3897965115
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1683512265
Short name T1043
Test name
Test status
Simulation time 96658399 ps
CPU time 1.55 seconds
Started Jun 06 12:47:16 PM PDT 24
Finished Jun 06 12:47:18 PM PDT 24
Peak memory 214236 kb
Host smart-682c3043-cbd1-4278-aa77-fd6a24865736
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683512265 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1683512265
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.551833652
Short name T936
Test name
Test status
Simulation time 17762772 ps
CPU time 1.3 seconds
Started Jun 06 12:47:16 PM PDT 24
Finished Jun 06 12:47:19 PM PDT 24
Peak memory 205572 kb
Host smart-6aced35d-5661-4acc-942b-cdb9017428f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551833652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.551833652
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3455172246
Short name T1034
Test name
Test status
Simulation time 32472183 ps
CPU time 0.72 seconds
Started Jun 06 12:47:10 PM PDT 24
Finished Jun 06 12:47:11 PM PDT 24
Peak memory 205312 kb
Host smart-7203d8e1-5707-425e-b7c0-c96de1fcd89c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455172246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3455172246
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1615861863
Short name T1063
Test name
Test status
Simulation time 426742776 ps
CPU time 3.84 seconds
Started Jun 06 12:47:18 PM PDT 24
Finished Jun 06 12:47:23 PM PDT 24
Peak memory 205508 kb
Host smart-3b19390e-9f1e-45ca-a28f-da36aaa033dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615861863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1615861863
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3578044510
Short name T1049
Test name
Test status
Simulation time 165274348 ps
CPU time 2.99 seconds
Started Jun 06 12:47:07 PM PDT 24
Finished Jun 06 12:47:12 PM PDT 24
Peak memory 214104 kb
Host smart-2b77013f-6712-4902-b074-485bb6f7d229
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578044510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3578044510
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3273013729
Short name T193
Test name
Test status
Simulation time 77661241 ps
CPU time 2.49 seconds
Started Jun 06 12:47:09 PM PDT 24
Finished Jun 06 12:47:13 PM PDT 24
Peak memory 213664 kb
Host smart-987a31d5-5db6-4d6d-8a6f-41b968f31d87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273013729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3273013729
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2013200248
Short name T963
Test name
Test status
Simulation time 215098432 ps
CPU time 3.4 seconds
Started Jun 06 12:47:11 PM PDT 24
Finished Jun 06 12:47:17 PM PDT 24
Peak memory 205492 kb
Host smart-2ead1c0a-daef-42b7-8a97-48e1b148a37f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013200248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2013200248
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2341103640
Short name T1061
Test name
Test status
Simulation time 283748394 ps
CPU time 1.33 seconds
Started Jun 06 12:47:13 PM PDT 24
Finished Jun 06 12:47:16 PM PDT 24
Peak memory 205616 kb
Host smart-e105dec0-d246-4b47-a6e7-f112198869ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341103640 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2341103640
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2918396621
Short name T1037
Test name
Test status
Simulation time 23431184 ps
CPU time 1.2 seconds
Started Jun 06 12:47:15 PM PDT 24
Finished Jun 06 12:47:17 PM PDT 24
Peak memory 205604 kb
Host smart-5511b344-44d6-4c7b-b387-7b499bd6d9da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918396621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2918396621
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3217280958
Short name T940
Test name
Test status
Simulation time 32449285 ps
CPU time 0.77 seconds
Started Jun 06 12:47:16 PM PDT 24
Finished Jun 06 12:47:18 PM PDT 24
Peak memory 205196 kb
Host smart-32685f34-e40c-4b5a-bae5-3fca29cae7d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217280958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3217280958
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1656457360
Short name T158
Test name
Test status
Simulation time 36415063 ps
CPU time 2.13 seconds
Started Jun 06 12:47:15 PM PDT 24
Finished Jun 06 12:47:19 PM PDT 24
Peak memory 205636 kb
Host smart-144bea29-614f-4d71-94b5-e88f1ebd72ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656457360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1656457360
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2013321100
Short name T127
Test name
Test status
Simulation time 282178428 ps
CPU time 4.26 seconds
Started Jun 06 12:47:14 PM PDT 24
Finished Jun 06 12:47:20 PM PDT 24
Peak memory 214120 kb
Host smart-dd52ac90-a3dc-47ac-941c-558d92b89626
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013321100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2013321100
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1977598611
Short name T971
Test name
Test status
Simulation time 38890621 ps
CPU time 2.38 seconds
Started Jun 06 12:47:13 PM PDT 24
Finished Jun 06 12:47:17 PM PDT 24
Peak memory 216144 kb
Host smart-50b8a97f-6abf-45ae-8d1c-cf8690c9e375
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977598611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1977598611
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2626750526
Short name T164
Test name
Test status
Simulation time 134980921 ps
CPU time 5.97 seconds
Started Jun 06 12:47:15 PM PDT 24
Finished Jun 06 12:47:22 PM PDT 24
Peak memory 213768 kb
Host smart-5205ee44-6a91-4442-b854-67d0915de714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626750526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2626750526
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3278124536
Short name T1057
Test name
Test status
Simulation time 48178914 ps
CPU time 1.23 seconds
Started Jun 06 12:47:14 PM PDT 24
Finished Jun 06 12:47:17 PM PDT 24
Peak memory 205644 kb
Host smart-ea2af9e2-d2ed-4dab-aec5-b9166a855e96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278124536 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3278124536
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2917769131
Short name T1010
Test name
Test status
Simulation time 12955022 ps
CPU time 1.08 seconds
Started Jun 06 12:47:16 PM PDT 24
Finished Jun 06 12:47:18 PM PDT 24
Peak memory 205548 kb
Host smart-76a1c36c-e466-41e3-8cb8-5188fe96fcdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917769131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2917769131
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3171421221
Short name T949
Test name
Test status
Simulation time 51682852 ps
CPU time 0.76 seconds
Started Jun 06 12:47:16 PM PDT 24
Finished Jun 06 12:47:18 PM PDT 24
Peak memory 205316 kb
Host smart-12dae744-a68b-4813-a08e-40704012e5ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171421221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3171421221
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2939656440
Short name T1013
Test name
Test status
Simulation time 767173195 ps
CPU time 3.47 seconds
Started Jun 06 12:47:13 PM PDT 24
Finished Jun 06 12:47:18 PM PDT 24
Peak memory 205572 kb
Host smart-2c4bc7f1-cc17-4d3e-a311-3ae6529fafb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939656440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2939656440
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3987657736
Short name T975
Test name
Test status
Simulation time 162518190 ps
CPU time 2.05 seconds
Started Jun 06 12:47:26 PM PDT 24
Finished Jun 06 12:47:29 PM PDT 24
Peak memory 214124 kb
Host smart-0a549590-b50d-44ec-8f44-5099af89e7b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987657736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3987657736
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.641009487
Short name T983
Test name
Test status
Simulation time 641498630 ps
CPU time 7.45 seconds
Started Jun 06 12:47:14 PM PDT 24
Finished Jun 06 12:47:23 PM PDT 24
Peak memory 220348 kb
Host smart-5bb1f4b5-f413-4df4-a001-0509f6b7c9fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641009487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.641009487
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4112918032
Short name T1031
Test name
Test status
Simulation time 69912075 ps
CPU time 2.43 seconds
Started Jun 06 12:47:15 PM PDT 24
Finished Jun 06 12:47:18 PM PDT 24
Peak memory 215760 kb
Host smart-762bb6ba-ea39-488f-9754-298c7915efc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112918032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4112918032
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3871996577
Short name T1036
Test name
Test status
Simulation time 458595985 ps
CPU time 7.19 seconds
Started Jun 06 12:46:34 PM PDT 24
Finished Jun 06 12:46:42 PM PDT 24
Peak memory 205556 kb
Host smart-7a76dbeb-c926-41c6-9e9c-18ceaf533b77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871996577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
871996577
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.791682931
Short name T926
Test name
Test status
Simulation time 931692198 ps
CPU time 15.74 seconds
Started Jun 06 12:46:36 PM PDT 24
Finished Jun 06 12:46:52 PM PDT 24
Peak memory 205620 kb
Host smart-5c4de3e8-79ad-45b3-a458-05f453756064
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791682931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.791682931
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3501293939
Short name T957
Test name
Test status
Simulation time 24070264 ps
CPU time 1.17 seconds
Started Jun 06 12:46:34 PM PDT 24
Finished Jun 06 12:46:35 PM PDT 24
Peak memory 205600 kb
Host smart-a81587e4-0911-4921-9e2c-dd475e37253c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501293939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
501293939
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1041102195
Short name T1020
Test name
Test status
Simulation time 49649071 ps
CPU time 1.51 seconds
Started Jun 06 12:46:37 PM PDT 24
Finished Jun 06 12:46:39 PM PDT 24
Peak memory 216340 kb
Host smart-01c4cdcb-ec2e-428d-9b9a-d8bb57c91aa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041102195 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1041102195
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1334767733
Short name T972
Test name
Test status
Simulation time 34028167 ps
CPU time 1.58 seconds
Started Jun 06 12:46:33 PM PDT 24
Finished Jun 06 12:46:35 PM PDT 24
Peak memory 205584 kb
Host smart-72132773-6c1f-4ea7-8f82-b7385479b3ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334767733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1334767733
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2589665267
Short name T1077
Test name
Test status
Simulation time 28135992 ps
CPU time 0.77 seconds
Started Jun 06 12:46:34 PM PDT 24
Finished Jun 06 12:46:36 PM PDT 24
Peak memory 205232 kb
Host smart-2a753466-9953-4e67-82ce-01a3ad96e71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589665267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2589665267
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.952225461
Short name T1048
Test name
Test status
Simulation time 40988620 ps
CPU time 1.93 seconds
Started Jun 06 12:46:35 PM PDT 24
Finished Jun 06 12:46:38 PM PDT 24
Peak memory 205600 kb
Host smart-e3218878-b935-4396-966d-b16892425107
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952225461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.952225461
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2535555379
Short name T1079
Test name
Test status
Simulation time 403870600 ps
CPU time 3.31 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:48 PM PDT 24
Peak memory 214164 kb
Host smart-1c0b957a-db6c-4351-9d7f-f236135da09f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535555379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2535555379
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2339486370
Short name T1046
Test name
Test status
Simulation time 159564197 ps
CPU time 7.81 seconds
Started Jun 06 12:46:32 PM PDT 24
Finished Jun 06 12:46:40 PM PDT 24
Peak memory 214104 kb
Host smart-0551b1a3-24f3-4176-a392-9e3f812b2ccd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339486370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2339486370
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.106721957
Short name T1012
Test name
Test status
Simulation time 154704424 ps
CPU time 3.21 seconds
Started Jun 06 12:46:33 PM PDT 24
Finished Jun 06 12:46:36 PM PDT 24
Peak memory 213792 kb
Host smart-99c2b2db-e7cc-4a5d-b18f-04f3281eb246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106721957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.106721957
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.76129640
Short name T1066
Test name
Test status
Simulation time 70238866 ps
CPU time 2.92 seconds
Started Jun 06 12:46:32 PM PDT 24
Finished Jun 06 12:46:35 PM PDT 24
Peak memory 205588 kb
Host smart-38c3c374-8e69-4631-b1b0-3153cc8db0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76129640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.76129640
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3707305288
Short name T923
Test name
Test status
Simulation time 37518410 ps
CPU time 0.71 seconds
Started Jun 06 12:47:12 PM PDT 24
Finished Jun 06 12:47:15 PM PDT 24
Peak memory 205212 kb
Host smart-d66c1575-521a-4eaf-9193-5c9057488bcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707305288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3707305288
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2477974954
Short name T1023
Test name
Test status
Simulation time 52520574 ps
CPU time 0.86 seconds
Started Jun 06 12:47:19 PM PDT 24
Finished Jun 06 12:47:21 PM PDT 24
Peak memory 205156 kb
Host smart-db2e4e7b-a11f-463d-a0ec-bea39e6434ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477974954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2477974954
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.430252078
Short name T951
Test name
Test status
Simulation time 38920489 ps
CPU time 0.71 seconds
Started Jun 06 12:47:15 PM PDT 24
Finished Jun 06 12:47:17 PM PDT 24
Peak memory 205192 kb
Host smart-e8479413-592a-4932-837c-2240dc1ce8fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430252078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.430252078
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.18566509
Short name T1032
Test name
Test status
Simulation time 92573706 ps
CPU time 0.73 seconds
Started Jun 06 12:47:19 PM PDT 24
Finished Jun 06 12:47:21 PM PDT 24
Peak memory 205224 kb
Host smart-f60a6005-c265-4ac1-9631-7e016d06f622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18566509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.18566509
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3235393930
Short name T996
Test name
Test status
Simulation time 11371002 ps
CPU time 0.71 seconds
Started Jun 06 12:47:26 PM PDT 24
Finished Jun 06 12:47:29 PM PDT 24
Peak memory 205272 kb
Host smart-32de1fd1-ef4f-4eea-954e-4c9d77fa6e21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235393930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3235393930
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4097631079
Short name T1029
Test name
Test status
Simulation time 19660330 ps
CPU time 0.68 seconds
Started Jun 06 12:47:25 PM PDT 24
Finished Jun 06 12:47:26 PM PDT 24
Peak memory 205264 kb
Host smart-3d0f2436-db66-40cb-b738-598bace8da5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097631079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4097631079
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1135140120
Short name T1019
Test name
Test status
Simulation time 36513165 ps
CPU time 0.87 seconds
Started Jun 06 12:47:27 PM PDT 24
Finished Jun 06 12:47:30 PM PDT 24
Peak memory 205124 kb
Host smart-31031c2b-b1a2-4154-b7e3-f99f9fd55005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135140120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1135140120
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2202732927
Short name T999
Test name
Test status
Simulation time 41733841 ps
CPU time 0.77 seconds
Started Jun 06 12:47:27 PM PDT 24
Finished Jun 06 12:47:30 PM PDT 24
Peak memory 205296 kb
Host smart-097b83e4-9337-4704-a3ea-1ed55a234d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202732927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2202732927
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2094513080
Short name T970
Test name
Test status
Simulation time 90287881 ps
CPU time 0.72 seconds
Started Jun 06 12:47:26 PM PDT 24
Finished Jun 06 12:47:28 PM PDT 24
Peak memory 205196 kb
Host smart-cceb5191-e93b-42ad-925e-68e4674e862f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094513080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2094513080
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2730732252
Short name T973
Test name
Test status
Simulation time 12084548 ps
CPU time 0.75 seconds
Started Jun 06 12:47:27 PM PDT 24
Finished Jun 06 12:47:29 PM PDT 24
Peak memory 205172 kb
Host smart-4805cf60-b639-4e06-8fca-2352cd82acfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730732252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2730732252
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3741667830
Short name T1044
Test name
Test status
Simulation time 241025370 ps
CPU time 8.82 seconds
Started Jun 06 12:46:36 PM PDT 24
Finished Jun 06 12:46:46 PM PDT 24
Peak memory 205556 kb
Host smart-182a5c1f-816d-4395-8929-556314e1efed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741667830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
741667830
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2239515989
Short name T1017
Test name
Test status
Simulation time 261049086 ps
CPU time 11.8 seconds
Started Jun 06 12:46:35 PM PDT 24
Finished Jun 06 12:46:48 PM PDT 24
Peak memory 205552 kb
Host smart-9b4f445f-5769-4469-adc2-13f029d5d7c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239515989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
239515989
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.137536695
Short name T956
Test name
Test status
Simulation time 139345285 ps
CPU time 1.25 seconds
Started Jun 06 12:46:34 PM PDT 24
Finished Jun 06 12:46:36 PM PDT 24
Peak memory 205556 kb
Host smart-5fe4c013-4f2a-4bb7-aa1c-774739805e21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137536695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.137536695
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.177290274
Short name T418
Test name
Test status
Simulation time 49872976 ps
CPU time 1.68 seconds
Started Jun 06 12:46:35 PM PDT 24
Finished Jun 06 12:46:38 PM PDT 24
Peak memory 218720 kb
Host smart-929cd57e-d665-4102-bdd1-64938e8cb7ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177290274 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.177290274
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.93769472
Short name T1051
Test name
Test status
Simulation time 32214048 ps
CPU time 1.11 seconds
Started Jun 06 12:46:35 PM PDT 24
Finished Jun 06 12:46:37 PM PDT 24
Peak memory 205548 kb
Host smart-409f5060-2e6c-476b-95e2-cd5ef5ddce80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93769472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.93769472
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1641888658
Short name T942
Test name
Test status
Simulation time 13142652 ps
CPU time 0.85 seconds
Started Jun 06 12:46:36 PM PDT 24
Finished Jun 06 12:46:38 PM PDT 24
Peak memory 205392 kb
Host smart-32da0150-15d0-42d4-991e-11dacfc29871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641888658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1641888658
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2740642795
Short name T938
Test name
Test status
Simulation time 366704618 ps
CPU time 2.27 seconds
Started Jun 06 12:46:34 PM PDT 24
Finished Jun 06 12:46:37 PM PDT 24
Peak memory 205632 kb
Host smart-2130936d-b030-49ec-ba18-576af7b15c91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740642795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2740642795
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.159888138
Short name T1067
Test name
Test status
Simulation time 75272607 ps
CPU time 1.95 seconds
Started Jun 06 12:46:36 PM PDT 24
Finished Jun 06 12:46:39 PM PDT 24
Peak memory 214096 kb
Host smart-c180aa8a-0901-4ee6-b67b-cf10f2566e54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159888138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.159888138
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3928324984
Short name T1009
Test name
Test status
Simulation time 348889840 ps
CPU time 12.35 seconds
Started Jun 06 12:46:36 PM PDT 24
Finished Jun 06 12:46:50 PM PDT 24
Peak memory 214184 kb
Host smart-f5028f6e-6167-4082-9c12-8e2f24b93346
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928324984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3928324984
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3316717115
Short name T1004
Test name
Test status
Simulation time 541411819 ps
CPU time 3.1 seconds
Started Jun 06 12:46:38 PM PDT 24
Finished Jun 06 12:46:42 PM PDT 24
Peak memory 213796 kb
Host smart-1a76c7b2-cc24-464c-a126-31296e82a0ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316717115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3316717115
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2643024433
Short name T180
Test name
Test status
Simulation time 100641051 ps
CPU time 3.8 seconds
Started Jun 06 12:46:33 PM PDT 24
Finished Jun 06 12:46:38 PM PDT 24
Peak memory 213700 kb
Host smart-46a2a174-037f-42c4-b02d-72d4b9362948
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643024433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2643024433
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2085188828
Short name T939
Test name
Test status
Simulation time 33794368 ps
CPU time 0.7 seconds
Started Jun 06 12:47:24 PM PDT 24
Finished Jun 06 12:47:25 PM PDT 24
Peak memory 205260 kb
Host smart-f2294c29-2941-42c2-baa4-ca1e965f8561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085188828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2085188828
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3764562404
Short name T986
Test name
Test status
Simulation time 35441749 ps
CPU time 0.72 seconds
Started Jun 06 12:47:27 PM PDT 24
Finished Jun 06 12:47:29 PM PDT 24
Peak memory 205256 kb
Host smart-61d97c81-a4c5-41c8-b83d-82532013f52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764562404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3764562404
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.572426168
Short name T954
Test name
Test status
Simulation time 8386492 ps
CPU time 0.68 seconds
Started Jun 06 12:47:28 PM PDT 24
Finished Jun 06 12:47:31 PM PDT 24
Peak memory 205268 kb
Host smart-d5c36255-1ded-430b-8e13-28adcad33152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572426168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.572426168
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.262413117
Short name T927
Test name
Test status
Simulation time 25678987 ps
CPU time 0.76 seconds
Started Jun 06 12:47:26 PM PDT 24
Finished Jun 06 12:47:28 PM PDT 24
Peak memory 205244 kb
Host smart-92523baf-7e53-4184-b883-bada4851a8af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262413117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.262413117
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1403243461
Short name T948
Test name
Test status
Simulation time 44084292 ps
CPU time 0.88 seconds
Started Jun 06 12:47:29 PM PDT 24
Finished Jun 06 12:47:32 PM PDT 24
Peak memory 205196 kb
Host smart-436b85c6-c00c-41c5-bab2-0e13e351874d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403243461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1403243461
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2799513621
Short name T930
Test name
Test status
Simulation time 25240956 ps
CPU time 1.04 seconds
Started Jun 06 12:47:25 PM PDT 24
Finished Jun 06 12:47:28 PM PDT 24
Peak memory 205432 kb
Host smart-2110add2-0c06-4f0b-a741-695cbfeee2ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799513621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2799513621
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3327863048
Short name T1030
Test name
Test status
Simulation time 25034217 ps
CPU time 0.72 seconds
Started Jun 06 12:47:27 PM PDT 24
Finished Jun 06 12:47:29 PM PDT 24
Peak memory 205208 kb
Host smart-96f458ae-fe0e-4582-953b-6ca006a5d067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327863048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3327863048
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2752753387
Short name T955
Test name
Test status
Simulation time 27525300 ps
CPU time 0.86 seconds
Started Jun 06 12:47:26 PM PDT 24
Finished Jun 06 12:47:29 PM PDT 24
Peak memory 205328 kb
Host smart-bcd2b7c6-5311-40cd-af8e-ee87ec04d457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752753387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2752753387
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.364959012
Short name T1039
Test name
Test status
Simulation time 14034302 ps
CPU time 0.92 seconds
Started Jun 06 12:47:28 PM PDT 24
Finished Jun 06 12:47:30 PM PDT 24
Peak memory 205316 kb
Host smart-a0fa6f95-8467-43ad-b68c-035d7abef747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364959012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.364959012
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1608278534
Short name T993
Test name
Test status
Simulation time 41893085 ps
CPU time 0.71 seconds
Started Jun 06 12:47:24 PM PDT 24
Finished Jun 06 12:47:26 PM PDT 24
Peak memory 205324 kb
Host smart-ba7582bc-7eeb-4b5b-a735-b17ff037e2f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608278534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1608278534
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2305475046
Short name T160
Test name
Test status
Simulation time 75775076 ps
CPU time 3.97 seconds
Started Jun 06 12:46:42 PM PDT 24
Finished Jun 06 12:46:47 PM PDT 24
Peak memory 205504 kb
Host smart-ffff6049-c482-4ad1-a699-5394a8a74c24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305475046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
305475046
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1910308451
Short name T974
Test name
Test status
Simulation time 675237981 ps
CPU time 9.48 seconds
Started Jun 06 12:46:42 PM PDT 24
Finished Jun 06 12:46:52 PM PDT 24
Peak memory 205628 kb
Host smart-6c6a349d-7b48-47a9-a3c6-cd501882e605
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910308451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
910308451
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3757184256
Short name T1033
Test name
Test status
Simulation time 180139437 ps
CPU time 1.18 seconds
Started Jun 06 12:46:49 PM PDT 24
Finished Jun 06 12:46:51 PM PDT 24
Peak memory 205608 kb
Host smart-883d808f-70a2-458d-bb81-f4446a3f8279
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757184256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
757184256
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2113725337
Short name T925
Test name
Test status
Simulation time 152312770 ps
CPU time 1.26 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:45 PM PDT 24
Peak memory 205556 kb
Host smart-ad9953e0-bf20-48a8-9ff1-0a75c13a7951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113725337 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2113725337
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2118671045
Short name T959
Test name
Test status
Simulation time 85078033 ps
CPU time 1.15 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:46 PM PDT 24
Peak memory 205536 kb
Host smart-c868c561-bb79-47f6-8116-117657a530a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118671045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2118671045
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4284012741
Short name T1064
Test name
Test status
Simulation time 56692152 ps
CPU time 0.8 seconds
Started Jun 06 12:46:42 PM PDT 24
Finished Jun 06 12:46:44 PM PDT 24
Peak memory 205232 kb
Host smart-fa00d3e5-111d-4849-88e8-0bc50476f7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284012741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4284012741
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3696369058
Short name T979
Test name
Test status
Simulation time 76888412 ps
CPU time 2.17 seconds
Started Jun 06 12:46:45 PM PDT 24
Finished Jun 06 12:46:48 PM PDT 24
Peak memory 205596 kb
Host smart-e8b2df06-d2d5-41b0-b88d-16675f748bd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696369058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3696369058
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.516895997
Short name T126
Test name
Test status
Simulation time 42346015 ps
CPU time 1.7 seconds
Started Jun 06 12:46:31 PM PDT 24
Finished Jun 06 12:46:33 PM PDT 24
Peak memory 214476 kb
Host smart-10bafa32-1212-4624-bcb4-9a6516e7ccad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516895997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.516895997
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.520828014
Short name T1045
Test name
Test status
Simulation time 400839330 ps
CPU time 12.63 seconds
Started Jun 06 12:46:44 PM PDT 24
Finished Jun 06 12:46:58 PM PDT 24
Peak memory 220388 kb
Host smart-1989953f-2a8b-493b-a04e-c49b2ccad6cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520828014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.520828014
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2864984576
Short name T1001
Test name
Test status
Simulation time 49937718 ps
CPU time 1.68 seconds
Started Jun 06 12:46:41 PM PDT 24
Finished Jun 06 12:46:43 PM PDT 24
Peak memory 205580 kb
Host smart-230b2c4e-b6d3-4678-836d-b8e6ea05fd0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864984576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2864984576
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1344461049
Short name T183
Test name
Test status
Simulation time 131922709 ps
CPU time 3.74 seconds
Started Jun 06 12:46:42 PM PDT 24
Finished Jun 06 12:46:47 PM PDT 24
Peak memory 213820 kb
Host smart-85894b65-be92-46d3-9d36-d546344ae8ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344461049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1344461049
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2204047514
Short name T1054
Test name
Test status
Simulation time 35119322 ps
CPU time 0.68 seconds
Started Jun 06 12:47:26 PM PDT 24
Finished Jun 06 12:47:27 PM PDT 24
Peak memory 205096 kb
Host smart-93bc9f2f-705b-438c-831d-30ec97bfd1e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204047514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2204047514
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.592546069
Short name T1007
Test name
Test status
Simulation time 23192853 ps
CPU time 0.69 seconds
Started Jun 06 12:47:25 PM PDT 24
Finished Jun 06 12:47:26 PM PDT 24
Peak memory 205288 kb
Host smart-3368f016-682f-49e5-ac2a-efb286eba4a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592546069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.592546069
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.510429645
Short name T952
Test name
Test status
Simulation time 25843587 ps
CPU time 0.75 seconds
Started Jun 06 12:47:26 PM PDT 24
Finished Jun 06 12:47:28 PM PDT 24
Peak memory 205296 kb
Host smart-764f2826-a9d2-4745-83f6-4b70fe44162a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510429645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.510429645
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1644460362
Short name T958
Test name
Test status
Simulation time 20936760 ps
CPU time 0.74 seconds
Started Jun 06 12:47:27 PM PDT 24
Finished Jun 06 12:47:30 PM PDT 24
Peak memory 205240 kb
Host smart-c2b2d6ce-21fe-4410-928d-6a6f7622f025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644460362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1644460362
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2776899338
Short name T943
Test name
Test status
Simulation time 33634343 ps
CPU time 0.72 seconds
Started Jun 06 12:47:26 PM PDT 24
Finished Jun 06 12:47:28 PM PDT 24
Peak memory 205208 kb
Host smart-61667963-ddba-4ff8-a4c4-a23fbc135333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776899338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2776899338
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.419492130
Short name T1080
Test name
Test status
Simulation time 8525847 ps
CPU time 0.78 seconds
Started Jun 06 12:47:25 PM PDT 24
Finished Jun 06 12:47:27 PM PDT 24
Peak memory 205212 kb
Host smart-ffffdfe8-c657-4f66-aa6c-d52e7b6dfc01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419492130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.419492130
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.204632478
Short name T1084
Test name
Test status
Simulation time 22328949 ps
CPU time 0.71 seconds
Started Jun 06 12:47:25 PM PDT 24
Finished Jun 06 12:47:27 PM PDT 24
Peak memory 205252 kb
Host smart-5347e7fc-86c5-4ef0-963c-1bd002c351ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204632478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.204632478
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1633312931
Short name T1038
Test name
Test status
Simulation time 10320387 ps
CPU time 0.88 seconds
Started Jun 06 12:47:26 PM PDT 24
Finished Jun 06 12:47:28 PM PDT 24
Peak memory 205308 kb
Host smart-05649605-9a25-4b7d-bd9e-275e64752528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633312931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1633312931
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3437738674
Short name T1082
Test name
Test status
Simulation time 10047287 ps
CPU time 0.75 seconds
Started Jun 06 12:47:27 PM PDT 24
Finished Jun 06 12:47:29 PM PDT 24
Peak memory 205236 kb
Host smart-915595c4-ec02-4691-bb4a-72c616a8d6ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437738674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3437738674
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.468024822
Short name T1000
Test name
Test status
Simulation time 13991878 ps
CPU time 0.87 seconds
Started Jun 06 12:47:25 PM PDT 24
Finished Jun 06 12:47:26 PM PDT 24
Peak memory 205440 kb
Host smart-8e9e1452-c2ae-405b-91f6-6bf8f91ddd9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468024822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.468024822
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3343019670
Short name T417
Test name
Test status
Simulation time 22963310 ps
CPU time 1.31 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:45 PM PDT 24
Peak memory 205544 kb
Host smart-baaf9bb6-5645-4f90-b432-a6bbcca3f3e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343019670 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3343019670
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3899856947
Short name T154
Test name
Test status
Simulation time 20536528 ps
CPU time 0.9 seconds
Started Jun 06 12:46:44 PM PDT 24
Finished Jun 06 12:46:46 PM PDT 24
Peak memory 205164 kb
Host smart-ebf8ba5b-5e36-417f-a0df-afa48ca6d741
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899856947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3899856947
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3603064705
Short name T998
Test name
Test status
Simulation time 30380721 ps
CPU time 0.85 seconds
Started Jun 06 12:46:44 PM PDT 24
Finished Jun 06 12:46:46 PM PDT 24
Peak memory 205276 kb
Host smart-28057ddc-19d9-480c-8eb0-7956bdea5bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603064705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3603064705
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1555038364
Short name T964
Test name
Test status
Simulation time 144203734 ps
CPU time 2.37 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:46 PM PDT 24
Peak memory 205596 kb
Host smart-7c0891f4-374b-456c-b14c-7658edf7868a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555038364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1555038364
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3191488344
Short name T1015
Test name
Test status
Simulation time 308683730 ps
CPU time 3.17 seconds
Started Jun 06 12:46:45 PM PDT 24
Finished Jun 06 12:46:49 PM PDT 24
Peak memory 214148 kb
Host smart-6d15ee75-0b3d-4986-b622-e3f5448a535a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191488344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3191488344
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1808346692
Short name T990
Test name
Test status
Simulation time 310038173 ps
CPU time 3.64 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:47 PM PDT 24
Peak memory 214120 kb
Host smart-2a24de36-99c5-4700-af29-7db1e1db5b28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808346692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1808346692
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2050043265
Short name T1065
Test name
Test status
Simulation time 106627731 ps
CPU time 1.99 seconds
Started Jun 06 12:46:42 PM PDT 24
Finished Jun 06 12:46:44 PM PDT 24
Peak memory 213824 kb
Host smart-d15873c5-04f5-4818-b720-e83f345b2915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050043265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2050043265
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1890480668
Short name T1055
Test name
Test status
Simulation time 113049358 ps
CPU time 1.82 seconds
Started Jun 06 12:46:40 PM PDT 24
Finished Jun 06 12:46:43 PM PDT 24
Peak memory 213912 kb
Host smart-66662ec6-2206-41c0-b675-8af1a938fe1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890480668 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1890480668
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3513362295
Short name T945
Test name
Test status
Simulation time 288357448 ps
CPU time 1.48 seconds
Started Jun 06 12:46:44 PM PDT 24
Finished Jun 06 12:46:46 PM PDT 24
Peak memory 205568 kb
Host smart-3ee8707d-02fc-4260-89e7-cbb44df1dd57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513362295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3513362295
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2613939944
Short name T941
Test name
Test status
Simulation time 20082566 ps
CPU time 0.71 seconds
Started Jun 06 12:46:44 PM PDT 24
Finished Jun 06 12:46:46 PM PDT 24
Peak memory 205232 kb
Host smart-dfc265e7-80d3-451f-8b7f-b1f85b85e5c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613939944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2613939944
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3004886555
Short name T947
Test name
Test status
Simulation time 49167917 ps
CPU time 1.44 seconds
Started Jun 06 12:46:45 PM PDT 24
Finished Jun 06 12:46:47 PM PDT 24
Peak memory 205632 kb
Host smart-0f8be2cc-4450-4338-822e-15d8d68450fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004886555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3004886555
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.152023113
Short name T969
Test name
Test status
Simulation time 177733233 ps
CPU time 3.12 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:46 PM PDT 24
Peak memory 214124 kb
Host smart-e992b9b2-8790-47a5-8e15-fc988d127330
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152023113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.152023113
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3557959073
Short name T1002
Test name
Test status
Simulation time 711017737 ps
CPU time 4.82 seconds
Started Jun 06 12:46:41 PM PDT 24
Finished Jun 06 12:46:47 PM PDT 24
Peak memory 214004 kb
Host smart-211ad448-fe31-46f7-b243-529d868d486e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557959073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3557959073
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.624863885
Short name T1028
Test name
Test status
Simulation time 55234400 ps
CPU time 1.84 seconds
Started Jun 06 12:46:46 PM PDT 24
Finished Jun 06 12:46:48 PM PDT 24
Peak memory 213716 kb
Host smart-75d1642d-a510-45bb-8d79-0979cda3837d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624863885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.624863885
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1530756928
Short name T928
Test name
Test status
Simulation time 281842963 ps
CPU time 1.19 seconds
Started Jun 06 12:46:48 PM PDT 24
Finished Jun 06 12:46:49 PM PDT 24
Peak memory 205544 kb
Host smart-e5bc013e-fbdb-46df-9245-c9636372da21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530756928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1530756928
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1360930698
Short name T1056
Test name
Test status
Simulation time 17456756 ps
CPU time 0.9 seconds
Started Jun 06 12:46:49 PM PDT 24
Finished Jun 06 12:46:50 PM PDT 24
Peak memory 205432 kb
Host smart-bf80a73e-7b57-4668-ae5b-3c8fd22d45f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360930698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1360930698
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1362260565
Short name T988
Test name
Test status
Simulation time 85808424 ps
CPU time 1.72 seconds
Started Jun 06 12:46:41 PM PDT 24
Finished Jun 06 12:46:43 PM PDT 24
Peak memory 205448 kb
Host smart-64d63300-4086-4ad1-ac18-24a9353dd46c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362260565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1362260565
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2032441885
Short name T977
Test name
Test status
Simulation time 108319293 ps
CPU time 2.03 seconds
Started Jun 06 12:46:46 PM PDT 24
Finished Jun 06 12:46:48 PM PDT 24
Peak memory 214152 kb
Host smart-43dad2fd-25bf-4e34-b0e8-d8044ce4dc5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032441885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2032441885
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2922054914
Short name T1078
Test name
Test status
Simulation time 3745556892 ps
CPU time 8.69 seconds
Started Jun 06 12:46:44 PM PDT 24
Finished Jun 06 12:46:54 PM PDT 24
Peak memory 214196 kb
Host smart-3a977aec-b678-48c9-8ed9-a7b59c39f8bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922054914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2922054914
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1348397160
Short name T994
Test name
Test status
Simulation time 23098234 ps
CPU time 1.79 seconds
Started Jun 06 12:46:43 PM PDT 24
Finished Jun 06 12:46:46 PM PDT 24
Peak memory 216072 kb
Host smart-59e6bcdf-32ad-466c-b0e7-d3eafd9f1e55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348397160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1348397160
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2749079514
Short name T1071
Test name
Test status
Simulation time 271661882 ps
CPU time 1.88 seconds
Started Jun 06 12:46:52 PM PDT 24
Finished Jun 06 12:46:55 PM PDT 24
Peak memory 213840 kb
Host smart-03a335f9-3bcc-40e6-95aa-bda59664ebcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749079514 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2749079514
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3377778876
Short name T155
Test name
Test status
Simulation time 15701500 ps
CPU time 1.01 seconds
Started Jun 06 12:46:48 PM PDT 24
Finished Jun 06 12:46:50 PM PDT 24
Peak memory 205544 kb
Host smart-77c80038-4d57-424a-a9b8-bf6fab91ef67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377778876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3377778876
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.306357540
Short name T1040
Test name
Test status
Simulation time 52684040 ps
CPU time 0.78 seconds
Started Jun 06 12:46:44 PM PDT 24
Finished Jun 06 12:46:46 PM PDT 24
Peak memory 205160 kb
Host smart-15c4576c-576c-4fd9-882f-7ca45870e332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306357540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.306357540
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2427754220
Short name T982
Test name
Test status
Simulation time 51988379 ps
CPU time 2.12 seconds
Started Jun 06 12:46:53 PM PDT 24
Finished Jun 06 12:46:57 PM PDT 24
Peak memory 205468 kb
Host smart-118da12c-bac9-48b5-9866-a64e19ebddfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427754220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2427754220
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1102509360
Short name T1072
Test name
Test status
Simulation time 1375922282 ps
CPU time 2.49 seconds
Started Jun 06 12:46:45 PM PDT 24
Finished Jun 06 12:46:48 PM PDT 24
Peak memory 214216 kb
Host smart-1daa6837-a4a0-412f-967d-55d7fbca6f62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102509360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1102509360
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3047457537
Short name T992
Test name
Test status
Simulation time 331614233 ps
CPU time 8.34 seconds
Started Jun 06 12:46:44 PM PDT 24
Finished Jun 06 12:46:54 PM PDT 24
Peak memory 214212 kb
Host smart-dfaf3153-a2d9-4fd0-a8d6-df13d57adce0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047457537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3047457537
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1364464777
Short name T1041
Test name
Test status
Simulation time 34342255 ps
CPU time 1.26 seconds
Started Jun 06 12:46:48 PM PDT 24
Finished Jun 06 12:46:50 PM PDT 24
Peak memory 213776 kb
Host smart-8bb0b942-bcb2-4085-979e-2f55fbcbdd5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364464777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1364464777
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.512913055
Short name T172
Test name
Test status
Simulation time 205263435 ps
CPU time 2.92 seconds
Started Jun 06 12:46:42 PM PDT 24
Finished Jun 06 12:46:45 PM PDT 24
Peak memory 213676 kb
Host smart-31e9e8fa-5c96-44b8-9893-08a1d5166282
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512913055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
512913055
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.632227954
Short name T196
Test name
Test status
Simulation time 211994247 ps
CPU time 1.55 seconds
Started Jun 06 12:46:57 PM PDT 24
Finished Jun 06 12:46:59 PM PDT 24
Peak memory 213688 kb
Host smart-f902c387-a0a5-430f-bbc9-fcf315526c48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632227954 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.632227954
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.959337364
Short name T1052
Test name
Test status
Simulation time 42803394 ps
CPU time 1.18 seconds
Started Jun 06 12:46:56 PM PDT 24
Finished Jun 06 12:46:59 PM PDT 24
Peak memory 205600 kb
Host smart-f8f8fc23-fb01-419b-9964-04e16d683c4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959337364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.959337364
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1760339231
Short name T922
Test name
Test status
Simulation time 55913952 ps
CPU time 0.82 seconds
Started Jun 06 12:46:52 PM PDT 24
Finished Jun 06 12:46:53 PM PDT 24
Peak memory 205316 kb
Host smart-882711ba-da40-45c0-b5d6-159295bdff9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760339231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1760339231
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3850174529
Short name T1008
Test name
Test status
Simulation time 243075089 ps
CPU time 1.53 seconds
Started Jun 06 12:46:56 PM PDT 24
Finished Jun 06 12:46:59 PM PDT 24
Peak memory 205700 kb
Host smart-4082296b-a0a8-4cab-9b78-d440c96fd537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850174529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3850174529
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1536611827
Short name T978
Test name
Test status
Simulation time 74986724 ps
CPU time 1.3 seconds
Started Jun 06 12:46:55 PM PDT 24
Finished Jun 06 12:46:58 PM PDT 24
Peak memory 214252 kb
Host smart-1f168b8c-610d-4183-9067-74216a151ce6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536611827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1536611827
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2389038532
Short name T929
Test name
Test status
Simulation time 110907725 ps
CPU time 4.35 seconds
Started Jun 06 12:46:56 PM PDT 24
Finished Jun 06 12:47:02 PM PDT 24
Peak memory 214268 kb
Host smart-b06ab9a4-4b65-4cf2-9ae3-839462bb0bdf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389038532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2389038532
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4130692228
Short name T1075
Test name
Test status
Simulation time 103640546 ps
CPU time 2.8 seconds
Started Jun 06 12:46:58 PM PDT 24
Finished Jun 06 12:47:03 PM PDT 24
Peak memory 216068 kb
Host smart-ef267016-db07-4444-bc2a-5e19f1a4d852
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130692228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.4130692228
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.650908182
Short name T178
Test name
Test status
Simulation time 314457479 ps
CPU time 8.47 seconds
Started Jun 06 12:46:58 PM PDT 24
Finished Jun 06 12:47:07 PM PDT 24
Peak memory 213836 kb
Host smart-a59742bc-1105-4f4f-9d68-8516e5078ec3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650908182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
650908182
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.682602618
Short name T863
Test name
Test status
Simulation time 54984945 ps
CPU time 2.59 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:54:00 PM PDT 24
Peak memory 209648 kb
Host smart-99cee49b-1c57-482e-8cda-546c1b819545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682602618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.682602618
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2753888640
Short name T48
Test name
Test status
Simulation time 332722550 ps
CPU time 1.82 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 208076 kb
Host smart-4f91fc38-7813-4b6f-90aa-2733e074c760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753888640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2753888640
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.286509784
Short name T60
Test name
Test status
Simulation time 82077037 ps
CPU time 2.52 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 214284 kb
Host smart-fb49974a-3f85-492c-81a0-0e8695d2fe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286509784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.286509784
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1652694782
Short name T320
Test name
Test status
Simulation time 107735726 ps
CPU time 4.91 seconds
Started Jun 06 01:53:59 PM PDT 24
Finished Jun 06 01:54:06 PM PDT 24
Peak memory 208696 kb
Host smart-aa25949a-09a1-4a38-acf3-555f27401eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652694782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1652694782
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4247916672
Short name T43
Test name
Test status
Simulation time 583944431 ps
CPU time 12.27 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:12 PM PDT 24
Peak memory 235328 kb
Host smart-c9ab48b9-4ffb-4ac6-8cc2-bcc36c9dd5ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247916672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4247916672
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.261344297
Short name T603
Test name
Test status
Simulation time 77976448 ps
CPU time 3.56 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 208744 kb
Host smart-937aa9a3-ade0-4bac-a7cb-b1052adf60ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261344297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.261344297
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.317188669
Short name T640
Test name
Test status
Simulation time 156399284 ps
CPU time 2.57 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 207516 kb
Host smart-ba6e6512-f3ec-485e-85df-7bff0583e946
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317188669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.317188669
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2818623138
Short name T617
Test name
Test status
Simulation time 130809232 ps
CPU time 2.93 seconds
Started Jun 06 01:54:02 PM PDT 24
Finished Jun 06 01:54:05 PM PDT 24
Peak memory 208560 kb
Host smart-d2b283de-d2e5-4161-9df5-a3a71cc57530
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818623138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2818623138
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.760922043
Short name T858
Test name
Test status
Simulation time 336502482 ps
CPU time 2.76 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:54:00 PM PDT 24
Peak memory 208680 kb
Host smart-d2aedb15-7972-431e-a4eb-84ec95350be4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760922043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.760922043
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2784750774
Short name T42
Test name
Test status
Simulation time 557359139 ps
CPU time 5.04 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:05 PM PDT 24
Peak memory 209828 kb
Host smart-81ae9ea4-9938-4d15-80a8-dbf1a9e3fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784750774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2784750774
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.293674320
Short name T527
Test name
Test status
Simulation time 342280014 ps
CPU time 5.52 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:04 PM PDT 24
Peak memory 207944 kb
Host smart-c70a7406-63d3-4fe2-962e-2c55b0e28223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293674320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.293674320
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3187966119
Short name T353
Test name
Test status
Simulation time 3602293862 ps
CPU time 10.68 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 214428 kb
Host smart-a0587aec-b14a-47b8-9f28-7065391979d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187966119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3187966119
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1253373945
Short name T224
Test name
Test status
Simulation time 395541812 ps
CPU time 12.91 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 209588 kb
Host smart-7d1ff3f7-5959-4006-9af4-1ac42cadc2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253373945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1253373945
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2128353783
Short name T448
Test name
Test status
Simulation time 43752060 ps
CPU time 0.77 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:00 PM PDT 24
Peak memory 205968 kb
Host smart-042f723f-5ce4-403f-92ad-ef3cb9e326a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128353783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2128353783
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1447132270
Short name T314
Test name
Test status
Simulation time 779191527 ps
CPU time 10.8 seconds
Started Jun 06 01:53:59 PM PDT 24
Finished Jun 06 01:54:12 PM PDT 24
Peak memory 222504 kb
Host smart-a2eb76e1-d0ca-4665-ad17-c7fdc02429ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447132270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1447132270
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.4045039930
Short name T601
Test name
Test status
Simulation time 144966426 ps
CPU time 3.31 seconds
Started Jun 06 01:54:00 PM PDT 24
Finished Jun 06 01:54:05 PM PDT 24
Peak memory 210012 kb
Host smart-2fa63758-a4d2-41a1-b006-107b34db2a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045039930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.4045039930
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1451725067
Short name T85
Test name
Test status
Simulation time 56119353 ps
CPU time 2.55 seconds
Started Jun 06 01:53:55 PM PDT 24
Finished Jun 06 01:53:59 PM PDT 24
Peak memory 207620 kb
Host smart-cca8ee70-5128-4c15-a4cf-4b898ef5f016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451725067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1451725067
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1278675413
Short name T104
Test name
Test status
Simulation time 214631621 ps
CPU time 4.94 seconds
Started Jun 06 01:53:55 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 209000 kb
Host smart-f828a70b-88aa-4701-a9cf-73035f77dca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278675413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1278675413
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1480892312
Short name T736
Test name
Test status
Simulation time 100779634 ps
CPU time 4.56 seconds
Started Jun 06 01:53:55 PM PDT 24
Finished Jun 06 01:54:00 PM PDT 24
Peak memory 222460 kb
Host smart-d1bb6a83-f8b9-45f5-a417-15b9bab04794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480892312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1480892312
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.4090612128
Short name T563
Test name
Test status
Simulation time 460267249 ps
CPU time 4.24 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 220296 kb
Host smart-3261e261-0963-45db-9b2e-b8f36485d59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090612128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.4090612128
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3838933068
Short name T223
Test name
Test status
Simulation time 168959952 ps
CPU time 3.12 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:54:00 PM PDT 24
Peak memory 207228 kb
Host smart-b48da582-0452-4c2f-8687-dc96053b41a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838933068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3838933068
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.46534524
Short name T11
Test name
Test status
Simulation time 1396165422 ps
CPU time 10.05 seconds
Started Jun 06 01:54:04 PM PDT 24
Finished Jun 06 01:54:15 PM PDT 24
Peak memory 229828 kb
Host smart-f33e6a36-e1a0-417e-baab-a2d0cd73bbb0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46534524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.46534524
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1032980284
Short name T277
Test name
Test status
Simulation time 296078621 ps
CPU time 3.52 seconds
Started Jun 06 01:54:01 PM PDT 24
Finished Jun 06 01:54:05 PM PDT 24
Peak memory 208584 kb
Host smart-e4664083-22d9-4f78-827b-21c56b0bb0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032980284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1032980284
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.550464186
Short name T215
Test name
Test status
Simulation time 114850002 ps
CPU time 3.1 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 208784 kb
Host smart-ebd5f93d-0a54-4c86-b595-8eb49cb6dd13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550464186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.550464186
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.109403355
Short name T674
Test name
Test status
Simulation time 165113574 ps
CPU time 2.51 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:02 PM PDT 24
Peak memory 206776 kb
Host smart-842ee66e-ee68-4eb8-b4ea-7f810d7079ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109403355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.109403355
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4180230285
Short name T451
Test name
Test status
Simulation time 22318657 ps
CPU time 1.63 seconds
Started Jun 06 01:54:01 PM PDT 24
Finished Jun 06 01:54:04 PM PDT 24
Peak memory 208512 kb
Host smart-e35266a5-76fa-47ca-9094-aba8308211dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180230285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4180230285
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.774119685
Short name T870
Test name
Test status
Simulation time 3459390568 ps
CPU time 17.27 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:18 PM PDT 24
Peak memory 208316 kb
Host smart-d5eb6f8b-ea78-4190-a4ee-134b1611a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774119685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.774119685
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2347526009
Short name T502
Test name
Test status
Simulation time 254752814 ps
CPU time 17.7 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:17 PM PDT 24
Peak memory 222540 kb
Host smart-5ab701ba-63a2-4e36-b198-deb6ef4c7253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347526009 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2347526009
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.990494008
Short name T266
Test name
Test status
Simulation time 103830745 ps
CPU time 3.46 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:02 PM PDT 24
Peak memory 208044 kb
Host smart-241b89b9-f30e-4eba-bd4a-d95085acb8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990494008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.990494008
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1543889897
Short name T553
Test name
Test status
Simulation time 296722618 ps
CPU time 5.18 seconds
Started Jun 06 01:54:02 PM PDT 24
Finished Jun 06 01:54:08 PM PDT 24
Peak memory 210560 kb
Host smart-8030c982-40b6-4084-8811-54b3917ca140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543889897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1543889897
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3156152875
Short name T528
Test name
Test status
Simulation time 20036769 ps
CPU time 0.77 seconds
Started Jun 06 01:54:25 PM PDT 24
Finished Jun 06 01:54:27 PM PDT 24
Peak memory 205856 kb
Host smart-9bb05d09-97d7-45c0-944a-430fd8134c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156152875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3156152875
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2651208133
Short name T433
Test name
Test status
Simulation time 391482803 ps
CPU time 9.75 seconds
Started Jun 06 01:54:16 PM PDT 24
Finished Jun 06 01:54:27 PM PDT 24
Peak memory 214892 kb
Host smart-c36ae6fd-2c87-484e-823c-7cc645b6126d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651208133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2651208133
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1252007783
Short name T882
Test name
Test status
Simulation time 91703646 ps
CPU time 4.05 seconds
Started Jun 06 01:54:25 PM PDT 24
Finished Jun 06 01:54:31 PM PDT 24
Peak memory 208988 kb
Host smart-960a03ff-5460-433b-bd3f-be7377cbb777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252007783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1252007783
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3080715785
Short name T581
Test name
Test status
Simulation time 2230893284 ps
CPU time 3.86 seconds
Started Jun 06 01:54:13 PM PDT 24
Finished Jun 06 01:54:18 PM PDT 24
Peak memory 214400 kb
Host smart-db1a211f-ad0b-4ee5-84b5-c71d0df7799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080715785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3080715785
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1204190756
Short name T643
Test name
Test status
Simulation time 754930458 ps
CPU time 13.71 seconds
Started Jun 06 01:54:26 PM PDT 24
Finished Jun 06 01:54:40 PM PDT 24
Peak memory 222164 kb
Host smart-08d10ae9-0809-43cc-883f-067f7899e9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204190756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1204190756
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1078520740
Short name T702
Test name
Test status
Simulation time 835494377 ps
CPU time 6.59 seconds
Started Jun 06 01:54:16 PM PDT 24
Finished Jun 06 01:54:23 PM PDT 24
Peak memory 210164 kb
Host smart-b3558f49-902f-45fb-80fe-41d0e9b776fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078520740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1078520740
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3296509969
Short name T743
Test name
Test status
Simulation time 126372011 ps
CPU time 6.14 seconds
Started Jun 06 01:54:26 PM PDT 24
Finished Jun 06 01:54:33 PM PDT 24
Peak memory 214244 kb
Host smart-439860f3-5b6b-4e82-98a2-a0fee3add72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296509969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3296509969
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.581102559
Short name T819
Test name
Test status
Simulation time 722458505 ps
CPU time 9.21 seconds
Started Jun 06 01:54:14 PM PDT 24
Finished Jun 06 01:54:24 PM PDT 24
Peak memory 208464 kb
Host smart-f42a3cd7-56d5-4578-a927-c02b53805dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581102559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.581102559
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1143988757
Short name T857
Test name
Test status
Simulation time 3075453224 ps
CPU time 21.64 seconds
Started Jun 06 01:54:12 PM PDT 24
Finished Jun 06 01:54:35 PM PDT 24
Peak memory 208272 kb
Host smart-1d2c4146-93df-474d-b931-ce34390505ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143988757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1143988757
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2577380105
Short name T221
Test name
Test status
Simulation time 333990909 ps
CPU time 2.36 seconds
Started Jun 06 01:54:14 PM PDT 24
Finished Jun 06 01:54:18 PM PDT 24
Peak memory 206944 kb
Host smart-fcb7d821-c5ae-4f9a-9385-243836874d59
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577380105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2577380105
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3499166965
Short name T866
Test name
Test status
Simulation time 625090742 ps
CPU time 4.5 seconds
Started Jun 06 01:54:26 PM PDT 24
Finished Jun 06 01:54:32 PM PDT 24
Peak memory 209496 kb
Host smart-3c5e59f8-2e4b-46ff-b805-956dda151fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499166965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3499166965
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2187619196
Short name T708
Test name
Test status
Simulation time 2745954377 ps
CPU time 24.49 seconds
Started Jun 06 01:54:12 PM PDT 24
Finished Jun 06 01:54:38 PM PDT 24
Peak memory 208400 kb
Host smart-7987db2b-4178-4c24-be94-704cc148043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187619196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2187619196
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.44426532
Short name T647
Test name
Test status
Simulation time 1187591557 ps
CPU time 11.17 seconds
Started Jun 06 01:54:25 PM PDT 24
Finished Jun 06 01:54:38 PM PDT 24
Peak memory 222480 kb
Host smart-161a7b79-dd92-4b69-b79c-2fc137b6c0ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44426532 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.44426532
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1209755189
Short name T861
Test name
Test status
Simulation time 317998113 ps
CPU time 3.46 seconds
Started Jun 06 01:54:16 PM PDT 24
Finished Jun 06 01:54:20 PM PDT 24
Peak memory 207964 kb
Host smart-4cad7375-3941-441a-a559-7386279269e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209755189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1209755189
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3178680607
Short name T461
Test name
Test status
Simulation time 129595648 ps
CPU time 2.88 seconds
Started Jun 06 01:54:26 PM PDT 24
Finished Jun 06 01:54:30 PM PDT 24
Peak memory 210148 kb
Host smart-7377f31e-5a4b-41b2-9c21-8037eb1f622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178680607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3178680607
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.478185990
Short name T712
Test name
Test status
Simulation time 10854047 ps
CPU time 0.73 seconds
Started Jun 06 01:54:32 PM PDT 24
Finished Jun 06 01:54:33 PM PDT 24
Peak memory 205940 kb
Host smart-b1c441bd-d3f6-4f12-b530-a5384f51e64e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478185990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.478185990
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1932987587
Short name T201
Test name
Test status
Simulation time 73833223 ps
CPU time 1.69 seconds
Started Jun 06 01:54:26 PM PDT 24
Finished Jun 06 01:54:29 PM PDT 24
Peak memory 214340 kb
Host smart-969f07a5-f49b-480e-8dd3-b9786103ff28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932987587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1932987587
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2282965603
Short name T306
Test name
Test status
Simulation time 53229100 ps
CPU time 2.63 seconds
Started Jun 06 01:54:25 PM PDT 24
Finished Jun 06 01:54:28 PM PDT 24
Peak memory 214344 kb
Host smart-bc474cb2-ce68-41bf-bd65-aa091fecc8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282965603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2282965603
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2350908832
Short name T677
Test name
Test status
Simulation time 51733091 ps
CPU time 3.08 seconds
Started Jun 06 01:54:23 PM PDT 24
Finished Jun 06 01:54:27 PM PDT 24
Peak memory 222488 kb
Host smart-a50fd515-b711-45d1-b57f-4555546beb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350908832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2350908832
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3725333129
Short name T800
Test name
Test status
Simulation time 1131154612 ps
CPU time 23.19 seconds
Started Jun 06 01:54:24 PM PDT 24
Finished Jun 06 01:54:48 PM PDT 24
Peak memory 218808 kb
Host smart-8bbd36a9-ce19-473b-bc82-22e27b7c0599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725333129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3725333129
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.529446334
Short name T397
Test name
Test status
Simulation time 140843435 ps
CPU time 4.89 seconds
Started Jun 06 01:54:25 PM PDT 24
Finished Jun 06 01:54:31 PM PDT 24
Peak memory 207380 kb
Host smart-bdf3e76a-59e3-470e-8eb1-3361c9a45cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529446334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.529446334
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1351646156
Short name T687
Test name
Test status
Simulation time 73828875 ps
CPU time 3.4 seconds
Started Jun 06 01:54:26 PM PDT 24
Finished Jun 06 01:54:30 PM PDT 24
Peak memory 208432 kb
Host smart-e7dc681d-4d37-4dce-9289-376175505df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351646156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1351646156
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1506680687
Short name T580
Test name
Test status
Simulation time 119493738 ps
CPU time 2.42 seconds
Started Jun 06 01:54:27 PM PDT 24
Finished Jun 06 01:54:30 PM PDT 24
Peak memory 207560 kb
Host smart-7b799ecc-060c-4b32-97c6-f92dd8fa75f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506680687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1506680687
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.908325014
Short name T651
Test name
Test status
Simulation time 777376576 ps
CPU time 3.76 seconds
Started Jun 06 01:54:21 PM PDT 24
Finished Jun 06 01:54:26 PM PDT 24
Peak memory 206916 kb
Host smart-4382c4b6-e7bb-43a4-a9c5-6765fa2287b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908325014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.908325014
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2197242680
Short name T822
Test name
Test status
Simulation time 380954550 ps
CPU time 3.48 seconds
Started Jun 06 01:54:23 PM PDT 24
Finished Jun 06 01:54:28 PM PDT 24
Peak memory 206892 kb
Host smart-07ecb581-33da-4297-8c02-e182ac71c23a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197242680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2197242680
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3762753873
Short name T503
Test name
Test status
Simulation time 811858981 ps
CPU time 4.3 seconds
Started Jun 06 01:54:22 PM PDT 24
Finished Jun 06 01:54:27 PM PDT 24
Peak memory 206708 kb
Host smart-7de4c912-ca86-45b6-a08b-a70fb3aa136c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762753873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3762753873
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.966655094
Short name T278
Test name
Test status
Simulation time 481921380 ps
CPU time 8.11 seconds
Started Jun 06 01:54:22 PM PDT 24
Finished Jun 06 01:54:32 PM PDT 24
Peak memory 209620 kb
Host smart-9694e255-b587-44a3-8389-d981f79aa691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966655094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.966655094
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3132965448
Short name T637
Test name
Test status
Simulation time 240211250 ps
CPU time 2.47 seconds
Started Jun 06 01:54:24 PM PDT 24
Finished Jun 06 01:54:28 PM PDT 24
Peak memory 210496 kb
Host smart-d4126dd0-26d7-42ab-84d7-fbb472a895fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132965448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3132965448
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.84859432
Short name T716
Test name
Test status
Simulation time 12539633 ps
CPU time 0.9 seconds
Started Jun 06 01:54:35 PM PDT 24
Finished Jun 06 01:54:38 PM PDT 24
Peak memory 205960 kb
Host smart-66875435-160b-4060-b362-6491fcaa9817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84859432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.84859432
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1047295854
Short name T19
Test name
Test status
Simulation time 100682689 ps
CPU time 4.68 seconds
Started Jun 06 01:54:20 PM PDT 24
Finished Jun 06 01:54:25 PM PDT 24
Peak memory 214588 kb
Host smart-6769ea31-dd0d-4b83-9c2c-1d15041ea166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047295854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1047295854
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1038915331
Short name T893
Test name
Test status
Simulation time 251304183 ps
CPU time 3.23 seconds
Started Jun 06 01:54:27 PM PDT 24
Finished Jun 06 01:54:31 PM PDT 24
Peak memory 209852 kb
Host smart-6e9f0f7b-906b-433e-a74b-622ec2a6864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038915331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1038915331
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3621652001
Short name T24
Test name
Test status
Simulation time 191952430 ps
CPU time 3.32 seconds
Started Jun 06 01:54:21 PM PDT 24
Finished Jun 06 01:54:25 PM PDT 24
Peak memory 222512 kb
Host smart-96e2490c-d5ed-4b2e-adf4-db807d694b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621652001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3621652001
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3112507060
Short name T773
Test name
Test status
Simulation time 125240523 ps
CPU time 3.06 seconds
Started Jun 06 01:54:19 PM PDT 24
Finished Jun 06 01:54:23 PM PDT 24
Peak memory 214236 kb
Host smart-90f41bb0-ca4e-4547-b0d0-59ab1921b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112507060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3112507060
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.2841899174
Short name T633
Test name
Test status
Simulation time 302536551 ps
CPU time 4.45 seconds
Started Jun 06 01:54:32 PM PDT 24
Finished Jun 06 01:54:37 PM PDT 24
Peak memory 210236 kb
Host smart-6efd6701-f030-4557-bc88-42d5c59dab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841899174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2841899174
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2754991008
Short name T600
Test name
Test status
Simulation time 362399354 ps
CPU time 3.42 seconds
Started Jun 06 01:54:19 PM PDT 24
Finished Jun 06 01:54:24 PM PDT 24
Peak memory 208488 kb
Host smart-7030aea7-7709-4fde-a5a8-5dc88198850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754991008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2754991008
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3171102156
Short name T516
Test name
Test status
Simulation time 100244395 ps
CPU time 4.23 seconds
Started Jun 06 01:54:20 PM PDT 24
Finished Jun 06 01:54:25 PM PDT 24
Peak memory 208564 kb
Host smart-cc462565-676c-4fac-95e6-23740785f9d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171102156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3171102156
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2731186403
Short name T1
Test name
Test status
Simulation time 242021819 ps
CPU time 2.72 seconds
Started Jun 06 01:54:32 PM PDT 24
Finished Jun 06 01:54:35 PM PDT 24
Peak memory 206924 kb
Host smart-9a4e2353-8d23-43d5-9ab2-b0099d7d41a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731186403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2731186403
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3548815657
Short name T684
Test name
Test status
Simulation time 68150330 ps
CPU time 3.5 seconds
Started Jun 06 01:54:26 PM PDT 24
Finished Jun 06 01:54:30 PM PDT 24
Peak memory 209008 kb
Host smart-719c83f4-88f7-4682-a601-3e15f28a526f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548815657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3548815657
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.784524138
Short name T504
Test name
Test status
Simulation time 117031231 ps
CPU time 3.16 seconds
Started Jun 06 01:54:27 PM PDT 24
Finished Jun 06 01:54:31 PM PDT 24
Peak memory 208936 kb
Host smart-7d9bad78-7391-4e29-a114-86c995682bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784524138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.784524138
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3091968739
Short name T539
Test name
Test status
Simulation time 691638903 ps
CPU time 10.32 seconds
Started Jun 06 01:54:22 PM PDT 24
Finished Jun 06 01:54:33 PM PDT 24
Peak memory 207804 kb
Host smart-7b16821c-f4e7-4e3f-9d20-6195fac2fdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091968739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3091968739
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.4022679229
Short name T865
Test name
Test status
Simulation time 417752504 ps
CPU time 5.18 seconds
Started Jun 06 01:54:27 PM PDT 24
Finished Jun 06 01:54:33 PM PDT 24
Peak memory 209388 kb
Host smart-e5683288-cbfd-42ed-9970-6cec1cb10fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022679229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.4022679229
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1936797382
Short name T714
Test name
Test status
Simulation time 3350183273 ps
CPU time 11.3 seconds
Started Jun 06 01:54:41 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 210960 kb
Host smart-891d8061-a808-42cf-9672-3c14acdd9f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936797382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1936797382
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3480281990
Short name T586
Test name
Test status
Simulation time 111570388 ps
CPU time 0.96 seconds
Started Jun 06 01:54:35 PM PDT 24
Finished Jun 06 01:54:37 PM PDT 24
Peak memory 206124 kb
Host smart-0d4f5608-71b2-4bc1-a764-0f3e2ae344cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480281990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3480281990
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.4050759765
Short name T818
Test name
Test status
Simulation time 4265726096 ps
CPU time 120.3 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:56:38 PM PDT 24
Peak memory 222400 kb
Host smart-01a11384-9354-4b8a-97b0-d52c4644e749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050759765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.4050759765
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2234277718
Short name T855
Test name
Test status
Simulation time 194449230 ps
CPU time 2.83 seconds
Started Jun 06 01:54:34 PM PDT 24
Finished Jun 06 01:54:38 PM PDT 24
Peak memory 207152 kb
Host smart-d242d0eb-d488-4d88-b23d-322ad16346bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234277718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2234277718
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1702601262
Short name T242
Test name
Test status
Simulation time 4050788771 ps
CPU time 13.31 seconds
Started Jun 06 01:54:39 PM PDT 24
Finished Jun 06 01:54:54 PM PDT 24
Peak memory 214400 kb
Host smart-e5141703-f29f-4f3e-a3c5-0a9f7fcf0293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702601262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1702601262
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3532090179
Short name T898
Test name
Test status
Simulation time 71464097 ps
CPU time 3.35 seconds
Started Jun 06 01:54:39 PM PDT 24
Finished Jun 06 01:54:44 PM PDT 24
Peak memory 222432 kb
Host smart-27069990-369e-46e6-9a71-e9f9eea9e4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532090179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3532090179
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4228894266
Short name T68
Test name
Test status
Simulation time 182935048 ps
CPU time 4.91 seconds
Started Jun 06 01:54:34 PM PDT 24
Finished Jun 06 01:54:41 PM PDT 24
Peak memory 215652 kb
Host smart-a7230068-a079-4e18-93e4-c61bb68868e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228894266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4228894266
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2695226316
Short name T360
Test name
Test status
Simulation time 4449447766 ps
CPU time 32.38 seconds
Started Jun 06 01:54:34 PM PDT 24
Finished Jun 06 01:55:08 PM PDT 24
Peak memory 208544 kb
Host smart-0fdba0bc-ec52-4666-93a0-1fa68b75a8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695226316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2695226316
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1281536523
Short name T534
Test name
Test status
Simulation time 263678131 ps
CPU time 5.49 seconds
Started Jun 06 01:54:38 PM PDT 24
Finished Jun 06 01:54:45 PM PDT 24
Peak memory 208676 kb
Host smart-9223373c-8961-4a26-aab0-0992d6241d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281536523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1281536523
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.399428595
Short name T729
Test name
Test status
Simulation time 418241706 ps
CPU time 4.96 seconds
Started Jun 06 01:54:37 PM PDT 24
Finished Jun 06 01:54:44 PM PDT 24
Peak memory 208808 kb
Host smart-6457fca7-d664-490e-b4fd-c1e7c0dab8d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399428595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.399428595
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3344952893
Short name T704
Test name
Test status
Simulation time 108757267 ps
CPU time 2.95 seconds
Started Jun 06 01:54:40 PM PDT 24
Finished Jun 06 01:54:44 PM PDT 24
Peak memory 208584 kb
Host smart-e155cffe-db50-4182-a44c-b9bd7a93b7db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344952893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3344952893
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3243330564
Short name T803
Test name
Test status
Simulation time 57217422 ps
CPU time 3.17 seconds
Started Jun 06 01:54:35 PM PDT 24
Finished Jun 06 01:54:40 PM PDT 24
Peak memory 208396 kb
Host smart-e1be6c73-e4fe-4381-8076-94dc2911eb22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243330564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3243330564
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.822471759
Short name T703
Test name
Test status
Simulation time 108331509 ps
CPU time 2.25 seconds
Started Jun 06 01:54:39 PM PDT 24
Finished Jun 06 01:54:43 PM PDT 24
Peak memory 207652 kb
Host smart-01bacd26-71dc-4f42-ba72-4cfa052830f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822471759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.822471759
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2168063055
Short name T142
Test name
Test status
Simulation time 273755072 ps
CPU time 3.04 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:54:41 PM PDT 24
Peak memory 208600 kb
Host smart-a6eb3ded-93b1-484f-b09d-d76102af42c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168063055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2168063055
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2479994012
Short name T282
Test name
Test status
Simulation time 1043330319 ps
CPU time 18.53 seconds
Started Jun 06 01:54:35 PM PDT 24
Finished Jun 06 01:54:55 PM PDT 24
Peak memory 209980 kb
Host smart-0afe8728-b402-42f1-bee5-808a607f44df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479994012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2479994012
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.815228764
Short name T398
Test name
Test status
Simulation time 4793773228 ps
CPU time 32.72 seconds
Started Jun 06 01:54:35 PM PDT 24
Finished Jun 06 01:55:10 PM PDT 24
Peak memory 222808 kb
Host smart-3c984ea4-9bb2-48e8-b1b5-9b1b0856c410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815228764 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.815228764
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2836528046
Short name T627
Test name
Test status
Simulation time 35513356 ps
CPU time 2.37 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:49 PM PDT 24
Peak memory 208568 kb
Host smart-6bd2b85b-d6a5-4d00-89e2-54fda95476af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836528046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2836528046
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4062449971
Short name T413
Test name
Test status
Simulation time 66674117 ps
CPU time 2.04 seconds
Started Jun 06 01:54:34 PM PDT 24
Finished Jun 06 01:54:38 PM PDT 24
Peak memory 209988 kb
Host smart-12bfea88-cb92-4d2e-b58e-59ba21ff1a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062449971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4062449971
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1136463337
Short name T110
Test name
Test status
Simulation time 73395457 ps
CPU time 1 seconds
Started Jun 06 01:54:35 PM PDT 24
Finished Jun 06 01:54:37 PM PDT 24
Peak memory 206176 kb
Host smart-51b31521-d998-4b2c-b0c1-f8448c3dd0cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136463337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1136463337
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2688060643
Short name T113
Test name
Test status
Simulation time 602306050 ps
CPU time 2.91 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:54:40 PM PDT 24
Peak memory 214524 kb
Host smart-e361c219-bd30-441e-befa-0c33c3b94be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2688060643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2688060643
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.470127760
Short name T29
Test name
Test status
Simulation time 65221752 ps
CPU time 1.89 seconds
Started Jun 06 01:54:35 PM PDT 24
Finished Jun 06 01:54:39 PM PDT 24
Peak memory 209512 kb
Host smart-3103335f-6417-467b-ad10-2430cd956c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470127760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.470127760
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.98520601
Short name T80
Test name
Test status
Simulation time 571039434 ps
CPU time 2.71 seconds
Started Jun 06 01:54:39 PM PDT 24
Finished Jun 06 01:54:43 PM PDT 24
Peak memory 209228 kb
Host smart-9c096068-d40a-4da6-a07b-86c7c65fd504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98520601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.98520601
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3781281936
Short name T794
Test name
Test status
Simulation time 416449101 ps
CPU time 4.52 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:54:42 PM PDT 24
Peak memory 209132 kb
Host smart-ee412880-87d5-48ce-9573-e5054d8bb33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781281936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3781281936
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_random.2052498012
Short name T296
Test name
Test status
Simulation time 52127776 ps
CPU time 3.33 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:54:42 PM PDT 24
Peak memory 209020 kb
Host smart-f7b26928-7470-46c5-824c-2c1a067ddc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052498012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2052498012
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1998100663
Short name T509
Test name
Test status
Simulation time 144802203 ps
CPU time 5.29 seconds
Started Jun 06 01:54:37 PM PDT 24
Finished Jun 06 01:54:44 PM PDT 24
Peak memory 207824 kb
Host smart-931f441d-42a3-48f6-bfd3-fe52c8635398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998100663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1998100663
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2079670971
Short name T565
Test name
Test status
Simulation time 486563085 ps
CPU time 4.55 seconds
Started Jun 06 01:54:35 PM PDT 24
Finished Jun 06 01:54:41 PM PDT 24
Peak memory 206996 kb
Host smart-57e7369f-5dfa-4020-b0a1-9ff5261894ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079670971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2079670971
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2689349696
Short name T204
Test name
Test status
Simulation time 71085593 ps
CPU time 3.36 seconds
Started Jun 06 01:54:34 PM PDT 24
Finished Jun 06 01:54:39 PM PDT 24
Peak memory 207004 kb
Host smart-9130dc10-05c7-4ccc-80d2-9565c2d75e41
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689349696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2689349696
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2569767292
Short name T529
Test name
Test status
Simulation time 292892377 ps
CPU time 3.55 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:54:42 PM PDT 24
Peak memory 208776 kb
Host smart-9a474edc-b1f2-4680-ae4a-49566580aed1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569767292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2569767292
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.728412419
Short name T776
Test name
Test status
Simulation time 154481702 ps
CPU time 4.36 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:54:42 PM PDT 24
Peak memory 214360 kb
Host smart-fb9b6cfd-db87-4159-a274-0930f98fbb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728412419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.728412419
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3219760459
Short name T472
Test name
Test status
Simulation time 39451944 ps
CPU time 1.61 seconds
Started Jun 06 01:54:39 PM PDT 24
Finished Jun 06 01:54:42 PM PDT 24
Peak memory 206824 kb
Host smart-22c01ce9-9286-47bd-8d5a-1ac7389aa2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219760459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3219760459
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.880816820
Short name T137
Test name
Test status
Simulation time 209062696 ps
CPU time 8.28 seconds
Started Jun 06 01:54:34 PM PDT 24
Finished Jun 06 01:54:43 PM PDT 24
Peak memory 222700 kb
Host smart-713f3ee2-83bb-485a-9d78-22e5fb622063
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880816820 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.880816820
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1001948241
Short name T781
Test name
Test status
Simulation time 266987045 ps
CPU time 5.85 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:54:43 PM PDT 24
Peak memory 209472 kb
Host smart-0ac9626c-f2e9-4f13-a7e9-40f28afd5daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001948241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1001948241
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.898889046
Short name T719
Test name
Test status
Simulation time 218260002 ps
CPU time 2.29 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:54:41 PM PDT 24
Peak memory 210000 kb
Host smart-afcc7060-0326-467d-a3b8-76841a277ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898889046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.898889046
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2909078781
Short name T847
Test name
Test status
Simulation time 18146090 ps
CPU time 0.74 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:54:49 PM PDT 24
Peak memory 205924 kb
Host smart-ea694a68-37dd-4cbc-8129-13132f797356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909078781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2909078781
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.113508963
Short name T713
Test name
Test status
Simulation time 2108882964 ps
CPU time 16.62 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:55:06 PM PDT 24
Peak memory 214268 kb
Host smart-ad251e73-d8fd-4b09-a718-7d35fef9f9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113508963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.113508963
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1722724641
Short name T405
Test name
Test status
Simulation time 206580800 ps
CPU time 3.38 seconds
Started Jun 06 01:54:44 PM PDT 24
Finished Jun 06 01:54:48 PM PDT 24
Peak memory 208760 kb
Host smart-412ac010-db99-4d74-8b2d-da681bcf99e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722724641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1722724641
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.846532724
Short name T368
Test name
Test status
Simulation time 37287075 ps
CPU time 2.37 seconds
Started Jun 06 01:54:45 PM PDT 24
Finished Jun 06 01:54:48 PM PDT 24
Peak memory 214768 kb
Host smart-acd893de-79e1-40e3-be5d-70624d7f3bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846532724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.846532724
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2486327818
Short name T662
Test name
Test status
Simulation time 86466236 ps
CPU time 1.93 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:49 PM PDT 24
Peak memory 214200 kb
Host smart-1246a6cc-0094-43e9-bb5f-b85619467917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486327818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2486327818
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1565962498
Short name T54
Test name
Test status
Simulation time 46740746 ps
CPU time 3.1 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 207244 kb
Host smart-42ec9cf8-f4d1-4155-bff3-02a08f279d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565962498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1565962498
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2714560039
Short name T139
Test name
Test status
Simulation time 119504111 ps
CPU time 4.68 seconds
Started Jun 06 01:54:37 PM PDT 24
Finished Jun 06 01:54:43 PM PDT 24
Peak memory 208872 kb
Host smart-9deb02e1-298b-40ec-b2aa-d2b7aaf7e199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714560039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2714560039
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1447374815
Short name T466
Test name
Test status
Simulation time 292273772 ps
CPU time 2.73 seconds
Started Jun 06 01:54:35 PM PDT 24
Finished Jun 06 01:54:39 PM PDT 24
Peak memory 208528 kb
Host smart-1a51cd6e-9a79-46b4-ae30-fc0811adbe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447374815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1447374815
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.4047252965
Short name T316
Test name
Test status
Simulation time 443115566 ps
CPU time 4.37 seconds
Started Jun 06 01:54:36 PM PDT 24
Finished Jun 06 01:54:42 PM PDT 24
Peak memory 208920 kb
Host smart-851a2783-3b02-433f-9334-8e6dcaf30cdd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047252965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4047252965
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3186718353
Short name T422
Test name
Test status
Simulation time 37235465 ps
CPU time 2.59 seconds
Started Jun 06 01:54:34 PM PDT 24
Finished Jun 06 01:54:38 PM PDT 24
Peak memory 208720 kb
Host smart-7c544bdd-9fb5-475a-9d4f-bc65f6e0baec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186718353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3186718353
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2640175561
Short name T482
Test name
Test status
Simulation time 535766729 ps
CPU time 4.97 seconds
Started Jun 06 01:54:50 PM PDT 24
Finished Jun 06 01:54:57 PM PDT 24
Peak memory 208124 kb
Host smart-e0bdefbb-b14e-458d-949d-f45b894a6e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640175561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2640175561
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3567724710
Short name T141
Test name
Test status
Simulation time 244483417 ps
CPU time 3.04 seconds
Started Jun 06 01:54:37 PM PDT 24
Finished Jun 06 01:54:42 PM PDT 24
Peak memory 208468 kb
Host smart-a9aebf5c-f590-4073-9ba6-e517914ea224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567724710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3567724710
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2496718879
Short name T901
Test name
Test status
Simulation time 1591940746 ps
CPU time 45.57 seconds
Started Jun 06 01:54:50 PM PDT 24
Finished Jun 06 01:55:37 PM PDT 24
Peak memory 216876 kb
Host smart-dbbb1f9a-fef7-468b-9d4e-c4e3788eda2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496718879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2496718879
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1599750368
Short name T14
Test name
Test status
Simulation time 82123970 ps
CPU time 1.29 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:54:51 PM PDT 24
Peak memory 208692 kb
Host smart-5e6e5872-9053-44ab-a752-125b09c9c043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599750368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1599750368
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1539664500
Short name T686
Test name
Test status
Simulation time 52120452 ps
CPU time 0.81 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:54:50 PM PDT 24
Peak memory 205960 kb
Host smart-899182a5-2744-484d-b546-c427cbffdf11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539664500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1539664500
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3696063295
Short name T432
Test name
Test status
Simulation time 39097820 ps
CPU time 2.82 seconds
Started Jun 06 01:54:44 PM PDT 24
Finished Jun 06 01:54:48 PM PDT 24
Peak memory 215496 kb
Host smart-dee557a3-066b-4477-9c6a-9678eb121305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3696063295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3696063295
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1206558295
Short name T78
Test name
Test status
Simulation time 93023148 ps
CPU time 3.46 seconds
Started Jun 06 01:54:44 PM PDT 24
Finished Jun 06 01:54:48 PM PDT 24
Peak memory 216912 kb
Host smart-7e0fd188-6e6e-498d-bdd4-28a578422d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206558295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1206558295
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3744707207
Short name T79
Test name
Test status
Simulation time 71129171 ps
CPU time 2.97 seconds
Started Jun 06 01:54:47 PM PDT 24
Finished Jun 06 01:54:51 PM PDT 24
Peak memory 208436 kb
Host smart-1892ccdd-0a90-4694-a7ca-aaec80b07fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744707207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3744707207
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3403624179
Short name T812
Test name
Test status
Simulation time 93257415 ps
CPU time 4.41 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:52 PM PDT 24
Peak memory 214272 kb
Host smart-82baf736-725d-4ef8-b4f0-0ee88e5b24b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403624179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3403624179
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1986366629
Short name T273
Test name
Test status
Simulation time 61480332 ps
CPU time 2.35 seconds
Started Jun 06 01:54:44 PM PDT 24
Finished Jun 06 01:54:47 PM PDT 24
Peak memory 220392 kb
Host smart-f0e7863e-d4f4-4bb2-8d8e-b5724ec472bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986366629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1986366629
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3408297960
Short name T846
Test name
Test status
Simulation time 40820599 ps
CPU time 2.03 seconds
Started Jun 06 01:54:44 PM PDT 24
Finished Jun 06 01:54:47 PM PDT 24
Peak memory 206612 kb
Host smart-94070e24-4b84-4146-bae3-6af18ef0b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408297960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3408297960
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.4134279285
Short name T595
Test name
Test status
Simulation time 386077049 ps
CPU time 3.47 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 207540 kb
Host smart-804fccba-8095-4410-89cc-7263727cea9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134279285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.4134279285
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2515209987
Short name T216
Test name
Test status
Simulation time 3524834507 ps
CPU time 49.5 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:55:39 PM PDT 24
Peak memory 208948 kb
Host smart-e878fdf5-5d58-4cde-84c9-d27bd45ca827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515209987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2515209987
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3315470264
Short name T632
Test name
Test status
Simulation time 544635263 ps
CPU time 3.73 seconds
Started Jun 06 01:54:52 PM PDT 24
Finished Jun 06 01:54:58 PM PDT 24
Peak memory 208948 kb
Host smart-d158ce65-6a79-4e49-8ac5-3fad5bdf4919
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315470264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3315470264
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2161603315
Short name T344
Test name
Test status
Simulation time 780312673 ps
CPU time 2.93 seconds
Started Jun 06 01:54:47 PM PDT 24
Finished Jun 06 01:54:51 PM PDT 24
Peak memory 206988 kb
Host smart-1e318015-5f17-4016-af35-b4e1252333e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161603315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2161603315
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1256836257
Short name T495
Test name
Test status
Simulation time 589072301 ps
CPU time 4.89 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:51 PM PDT 24
Peak memory 208476 kb
Host smart-d184439a-1c31-43df-a3f6-88f4ac81dc8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256836257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1256836257
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3483779248
Short name T733
Test name
Test status
Simulation time 99468608 ps
CPU time 3.11 seconds
Started Jun 06 01:54:43 PM PDT 24
Finished Jun 06 01:54:47 PM PDT 24
Peak memory 208360 kb
Host smart-ec7b704e-65ba-4e40-bd0b-9f1ac4708ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483779248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3483779248
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.4032847085
Short name T443
Test name
Test status
Simulation time 71549605 ps
CPU time 3.16 seconds
Started Jun 06 01:54:49 PM PDT 24
Finished Jun 06 01:54:54 PM PDT 24
Peak memory 207916 kb
Host smart-fabb191c-0cd2-42bc-97eb-e9286e2befc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032847085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.4032847085
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2574237368
Short name T330
Test name
Test status
Simulation time 880197450 ps
CPU time 31.5 seconds
Started Jun 06 01:54:45 PM PDT 24
Finished Jun 06 01:55:18 PM PDT 24
Peak memory 214352 kb
Host smart-10b630ab-a632-4724-9def-4dc03bca0ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574237368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2574237368
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1675314281
Short name T878
Test name
Test status
Simulation time 498018422 ps
CPU time 6.14 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 208000 kb
Host smart-d1978cb2-10a3-480c-9843-4d11d76b5c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675314281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1675314281
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.121973605
Short name T594
Test name
Test status
Simulation time 1704729377 ps
CPU time 15.35 seconds
Started Jun 06 01:54:47 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 210780 kb
Host smart-2a0ab486-1dc9-4c32-927d-8ae4799bd6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121973605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.121973605
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.339177993
Short name T616
Test name
Test status
Simulation time 33950215 ps
CPU time 0.8 seconds
Started Jun 06 01:54:45 PM PDT 24
Finished Jun 06 01:54:47 PM PDT 24
Peak memory 205928 kb
Host smart-79ce1f6b-481f-42ff-8a05-725ce0fb3c62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339177993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.339177993
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3290627850
Short name T281
Test name
Test status
Simulation time 175285539 ps
CPU time 3.9 seconds
Started Jun 06 01:54:45 PM PDT 24
Finished Jun 06 01:54:49 PM PDT 24
Peak memory 214964 kb
Host smart-fdcffa02-f334-40d4-8a1c-c049a8ff581a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290627850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3290627850
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3733570536
Short name T755
Test name
Test status
Simulation time 240762504 ps
CPU time 2.5 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:54:51 PM PDT 24
Peak memory 214436 kb
Host smart-3bd6c1c1-c9e6-4bd6-82cc-d7aa1115eb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733570536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3733570536
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2919637137
Short name T493
Test name
Test status
Simulation time 117584442 ps
CPU time 3.84 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 209596 kb
Host smart-018fb78a-48fd-4f07-9bbc-051b50ad57b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919637137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2919637137
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3241230036
Short name T551
Test name
Test status
Simulation time 1839695254 ps
CPU time 25.93 seconds
Started Jun 06 01:54:45 PM PDT 24
Finished Jun 06 01:55:12 PM PDT 24
Peak memory 208292 kb
Host smart-41a5f3b5-ba0f-49dc-88e2-ff10eb5d591f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241230036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3241230036
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3149381895
Short name T465
Test name
Test status
Simulation time 2676286840 ps
CPU time 26.28 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:55:13 PM PDT 24
Peak memory 208492 kb
Host smart-8f401b2a-5186-49bd-8ea9-cd5ab8dc8a3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149381895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3149381895
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.817325901
Short name T218
Test name
Test status
Simulation time 81851872 ps
CPU time 1.86 seconds
Started Jun 06 01:54:47 PM PDT 24
Finished Jun 06 01:54:50 PM PDT 24
Peak memory 206944 kb
Host smart-c21cdf56-6975-4468-98b3-62ead271c292
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817325901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.817325901
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.162396278
Short name T707
Test name
Test status
Simulation time 942806943 ps
CPU time 10.47 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:57 PM PDT 24
Peak memory 208136 kb
Host smart-6420df20-88d4-43f5-9129-36aa46a38a88
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162396278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.162396278
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.147495635
Short name T284
Test name
Test status
Simulation time 71934724 ps
CPU time 3.33 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 208464 kb
Host smart-25eac18d-f05e-4c9d-8ab7-0a43a283c3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147495635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.147495635
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2470699575
Short name T887
Test name
Test status
Simulation time 217899211 ps
CPU time 2.6 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:49 PM PDT 24
Peak memory 208404 kb
Host smart-fd62db9b-98ec-47bd-970e-7939705b619c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470699575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2470699575
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2032001079
Short name T403
Test name
Test status
Simulation time 7719959579 ps
CPU time 211.01 seconds
Started Jun 06 01:54:49 PM PDT 24
Finished Jun 06 01:58:22 PM PDT 24
Peak memory 217308 kb
Host smart-810baab1-8863-4534-a5fc-16eaac67bddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032001079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2032001079
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.933408000
Short name T768
Test name
Test status
Simulation time 456560039 ps
CPU time 8.76 seconds
Started Jun 06 01:54:47 PM PDT 24
Finished Jun 06 01:54:57 PM PDT 24
Peak memory 222588 kb
Host smart-20544f68-1c34-4757-b08a-547fd8a0f3ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933408000 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.933408000
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2535946833
Short name T212
Test name
Test status
Simulation time 873803827 ps
CPU time 16.52 seconds
Started Jun 06 01:54:51 PM PDT 24
Finished Jun 06 01:55:09 PM PDT 24
Peak memory 209444 kb
Host smart-e6689d33-70e7-4a6e-be89-3a9926b5f4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535946833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2535946833
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4167862847
Short name T860
Test name
Test status
Simulation time 114114568 ps
CPU time 3.36 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:50 PM PDT 24
Peak memory 210064 kb
Host smart-c0939b8a-2152-4bab-ae64-a58bfd7d914e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167862847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4167862847
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2916816648
Short name T530
Test name
Test status
Simulation time 36417393 ps
CPU time 0.94 seconds
Started Jun 06 01:54:49 PM PDT 24
Finished Jun 06 01:54:52 PM PDT 24
Peak memory 205904 kb
Host smart-0524cc36-d3d3-406a-bb5c-73e95da7fec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916816648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2916816648
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.4036062333
Short name T419
Test name
Test status
Simulation time 31204602 ps
CPU time 2.55 seconds
Started Jun 06 01:54:50 PM PDT 24
Finished Jun 06 01:54:54 PM PDT 24
Peak memory 214400 kb
Host smart-7b731f6f-c97d-4956-9242-125b8a9c36d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036062333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.4036062333
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.880129081
Short name T699
Test name
Test status
Simulation time 191317323 ps
CPU time 1.93 seconds
Started Jun 06 01:54:45 PM PDT 24
Finished Jun 06 01:54:48 PM PDT 24
Peak memory 207600 kb
Host smart-78b02872-d306-4d03-ae1a-e446101be4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880129081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.880129081
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3905398212
Short name T521
Test name
Test status
Simulation time 747758446 ps
CPU time 3.49 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:51 PM PDT 24
Peak memory 214436 kb
Host smart-6d385f0d-b4df-491b-83cc-805dca4b8df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905398212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3905398212
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.196277246
Short name T22
Test name
Test status
Simulation time 512228965 ps
CPU time 4.75 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 208660 kb
Host smart-efb2f8b5-edb1-484f-8a9d-a2a25280f7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196277246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.196277246
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3345594860
Short name T561
Test name
Test status
Simulation time 264270645 ps
CPU time 3.34 seconds
Started Jun 06 01:54:53 PM PDT 24
Finished Jun 06 01:54:59 PM PDT 24
Peak memory 220452 kb
Host smart-0b9a4393-853c-4ebd-a028-4ef6c94ab262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345594860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3345594860
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2156517335
Short name T552
Test name
Test status
Simulation time 573360230 ps
CPU time 5.1 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 207992 kb
Host smart-bbdf7e37-54ed-43ad-8506-0f159126f8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156517335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2156517335
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.452882295
Short name T685
Test name
Test status
Simulation time 756962793 ps
CPU time 5.78 seconds
Started Jun 06 01:54:46 PM PDT 24
Finished Jun 06 01:54:52 PM PDT 24
Peak memory 207984 kb
Host smart-c5164987-7b78-45bf-8bf2-210155d381b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452882295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.452882295
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.235693663
Short name T829
Test name
Test status
Simulation time 5728795353 ps
CPU time 41.21 seconds
Started Jun 06 01:54:47 PM PDT 24
Finished Jun 06 01:55:29 PM PDT 24
Peak memory 208272 kb
Host smart-adf59b69-490c-47a0-b6c1-f5cabad44ba1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235693663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.235693663
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3614605368
Short name T619
Test name
Test status
Simulation time 1410072652 ps
CPU time 7.07 seconds
Started Jun 06 01:54:47 PM PDT 24
Finished Jun 06 01:54:55 PM PDT 24
Peak memory 208060 kb
Host smart-6c91dc99-6e08-4151-815b-0c544114f7eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614605368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3614605368
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.779769365
Short name T508
Test name
Test status
Simulation time 162455295 ps
CPU time 4.92 seconds
Started Jun 06 01:54:49 PM PDT 24
Finished Jun 06 01:54:56 PM PDT 24
Peak memory 207984 kb
Host smart-8a0d7b8f-c800-473e-90bd-ce852d33fc68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779769365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.779769365
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2990004460
Short name T658
Test name
Test status
Simulation time 129984243 ps
CPU time 1.79 seconds
Started Jun 06 01:54:49 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 207196 kb
Host smart-d8dee262-86f4-4935-8574-31022fa1b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990004460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2990004460
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2143474985
Short name T58
Test name
Test status
Simulation time 2472531771 ps
CPU time 72.62 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:56:01 PM PDT 24
Peak memory 222124 kb
Host smart-076205aa-b44a-420b-90aa-cc2ff88c0d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143474985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2143474985
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2575932963
Short name T136
Test name
Test status
Simulation time 235845073 ps
CPU time 8.42 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:54:57 PM PDT 24
Peak memory 219508 kb
Host smart-dc4b7b57-86b3-4618-9db9-ffbeda0f3003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575932963 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2575932963
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.409105904
Short name T815
Test name
Test status
Simulation time 104022936 ps
CPU time 4.69 seconds
Started Jun 06 01:54:47 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 207356 kb
Host smart-b7650dff-0e65-4906-87c7-190593fd60b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409105904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.409105904
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.919934942
Short name T762
Test name
Test status
Simulation time 130327352 ps
CPU time 2.66 seconds
Started Jun 06 01:54:45 PM PDT 24
Finished Jun 06 01:54:49 PM PDT 24
Peak memory 211044 kb
Host smart-4af8eab5-9f1e-4a79-8137-ceaf98f49762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919934942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.919934942
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.894910587
Short name T615
Test name
Test status
Simulation time 13146717 ps
CPU time 0.79 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:54:58 PM PDT 24
Peak memory 205912 kb
Host smart-5e1c7294-153c-4250-8214-8cfbde4173c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894910587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.894910587
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2578708181
Short name T777
Test name
Test status
Simulation time 42288297 ps
CPU time 3.27 seconds
Started Jun 06 01:54:53 PM PDT 24
Finished Jun 06 01:54:59 PM PDT 24
Peak memory 222492 kb
Host smart-4b3e4748-9501-48cb-875a-adaed30a37ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578708181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2578708181
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3379868205
Short name T86
Test name
Test status
Simulation time 2556876487 ps
CPU time 28.11 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:25 PM PDT 24
Peak memory 214348 kb
Host smart-b38a97b7-ff34-4789-85a1-0a9701c20964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379868205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3379868205
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1776926888
Short name T560
Test name
Test status
Simulation time 464237961 ps
CPU time 2.3 seconds
Started Jun 06 01:54:50 PM PDT 24
Finished Jun 06 01:54:54 PM PDT 24
Peak memory 214452 kb
Host smart-27c40fcb-f8de-46f3-b64f-61b286304287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776926888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1776926888
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1449151346
Short name T486
Test name
Test status
Simulation time 112500529 ps
CPU time 3.66 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 209488 kb
Host smart-3a7830e6-cf8c-49f2-97cc-e3cb9fecb9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449151346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1449151346
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2815494127
Short name T340
Test name
Test status
Simulation time 66893600 ps
CPU time 3.59 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 207468 kb
Host smart-49df4169-e5b6-47a1-b161-bcbf6061bc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815494127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2815494127
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1634481014
Short name T695
Test name
Test status
Simulation time 58604015 ps
CPU time 2.89 seconds
Started Jun 06 01:54:49 PM PDT 24
Finished Jun 06 01:54:54 PM PDT 24
Peak memory 207044 kb
Host smart-add42afe-f2d5-44ed-923c-43a5ce911e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634481014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1634481014
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.25888654
Short name T793
Test name
Test status
Simulation time 91549244 ps
CPU time 4.05 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 208256 kb
Host smart-bd573aaa-c978-4d1c-9aeb-64aba5d0e00b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25888654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.25888654
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2856228039
Short name T523
Test name
Test status
Simulation time 575876850 ps
CPU time 4.73 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 208616 kb
Host smart-fb00b5d9-2008-4ca5-9717-dd6880cfdd3c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856228039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2856228039
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3147253654
Short name T492
Test name
Test status
Simulation time 337768343 ps
CPU time 5.16 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 207748 kb
Host smart-dcfaec69-c152-466d-b56f-c1c1b19cab02
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147253654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3147253654
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3709945754
Short name T711
Test name
Test status
Simulation time 347453796 ps
CPU time 4.58 seconds
Started Jun 06 01:54:48 PM PDT 24
Finished Jun 06 01:54:54 PM PDT 24
Peak memory 210124 kb
Host smart-8f0abb00-f311-4d03-aa99-8fa559d928a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709945754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3709945754
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2864871573
Short name T569
Test name
Test status
Simulation time 93906360 ps
CPU time 3.44 seconds
Started Jun 06 01:54:52 PM PDT 24
Finished Jun 06 01:54:57 PM PDT 24
Peak memory 206816 kb
Host smart-b4064c6e-97b8-46ee-bcb6-957d5958ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864871573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2864871573
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2807821460
Short name T889
Test name
Test status
Simulation time 189854267 ps
CPU time 3.62 seconds
Started Jun 06 01:54:52 PM PDT 24
Finished Jun 06 01:54:57 PM PDT 24
Peak memory 207864 kb
Host smart-1f3c302e-8b46-423e-88ad-af536a2ef7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807821460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2807821460
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2042451685
Short name T424
Test name
Test status
Simulation time 56911611 ps
CPU time 2.54 seconds
Started Jun 06 01:54:50 PM PDT 24
Finished Jun 06 01:54:55 PM PDT 24
Peak memory 209852 kb
Host smart-2b19d7b7-61da-4c71-9092-d3e52d0e8834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042451685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2042451685
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.706279810
Short name T538
Test name
Test status
Simulation time 15687572 ps
CPU time 0.92 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:00 PM PDT 24
Peak memory 206056 kb
Host smart-0ab4bec8-4179-4926-b9df-c0f4c76ff748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706279810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.706279810
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2851584192
Short name T757
Test name
Test status
Simulation time 214272987 ps
CPU time 4.69 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 209756 kb
Host smart-374c3fdb-32ec-4789-abf5-802418059529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851584192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2851584192
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3762219766
Short name T381
Test name
Test status
Simulation time 29300993 ps
CPU time 1.59 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:00 PM PDT 24
Peak memory 208076 kb
Host smart-81a4f6c5-9877-4c29-ac53-33f830cc4d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762219766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3762219766
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2765953001
Short name T780
Test name
Test status
Simulation time 27085695 ps
CPU time 2.34 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 214088 kb
Host smart-aa79c3d6-277c-40bd-acbd-0605c6e0f92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765953001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2765953001
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3532154714
Short name T653
Test name
Test status
Simulation time 124269969 ps
CPU time 3.87 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 217140 kb
Host smart-616e2d60-7f2f-4b91-9594-979c8bed814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532154714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3532154714
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1947003446
Short name T763
Test name
Test status
Simulation time 72672346 ps
CPU time 3.94 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 214484 kb
Host smart-952bbf26-18a8-487f-b57a-58e0c116309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947003446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1947003446
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1921346643
Short name T911
Test name
Test status
Simulation time 508602306 ps
CPU time 4.83 seconds
Started Jun 06 01:54:00 PM PDT 24
Finished Jun 06 01:54:06 PM PDT 24
Peak memory 208004 kb
Host smart-750037b4-308c-4f3e-a589-3f64637bfa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921346643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1921346643
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3447791094
Short name T650
Test name
Test status
Simulation time 189018824 ps
CPU time 7 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:05 PM PDT 24
Peak memory 209000 kb
Host smart-33a1488a-9ab3-4787-82dc-790035f8081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447791094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3447791094
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1337166568
Short name T477
Test name
Test status
Simulation time 358936265 ps
CPU time 3.58 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 208580 kb
Host smart-670361fa-da50-45f3-9a66-bf163ad7e7b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337166568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1337166568
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2609940157
Short name T566
Test name
Test status
Simulation time 177833510 ps
CPU time 5.11 seconds
Started Jun 06 01:54:00 PM PDT 24
Finished Jun 06 01:54:06 PM PDT 24
Peak memory 207804 kb
Host smart-75ba6fe6-494b-4711-8115-2a24f00e361e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609940157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2609940157
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2017478025
Short name T697
Test name
Test status
Simulation time 112916729 ps
CPU time 3.65 seconds
Started Jun 06 01:53:59 PM PDT 24
Finished Jun 06 01:54:04 PM PDT 24
Peak memory 214352 kb
Host smart-82e0d800-9d71-46f1-8758-f4fcccb6ee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017478025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2017478025
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2257093792
Short name T494
Test name
Test status
Simulation time 175964409 ps
CPU time 2.38 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 206624 kb
Host smart-45869df2-24f7-43d7-812c-0b810a29940e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257093792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2257093792
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2551999918
Short name T639
Test name
Test status
Simulation time 225533684 ps
CPU time 6.46 seconds
Started Jun 06 01:53:59 PM PDT 24
Finished Jun 06 01:54:07 PM PDT 24
Peak memory 209268 kb
Host smart-3457797e-bce5-4c44-9f43-c8c3242ccf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551999918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2551999918
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.381399057
Short name T533
Test name
Test status
Simulation time 50785005 ps
CPU time 2.28 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:54:00 PM PDT 24
Peak memory 210048 kb
Host smart-dc835c37-d826-4741-a39c-c67305635f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381399057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.381399057
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.194138988
Short name T718
Test name
Test status
Simulation time 12930850 ps
CPU time 0.75 seconds
Started Jun 06 01:54:53 PM PDT 24
Finished Jun 06 01:54:56 PM PDT 24
Peak memory 205948 kb
Host smart-662fb48b-c1f3-4798-8a0f-791cb15ec7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194138988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.194138988
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.67821412
Short name T408
Test name
Test status
Simulation time 972511075 ps
CPU time 4.24 seconds
Started Jun 06 01:54:53 PM PDT 24
Finished Jun 06 01:54:59 PM PDT 24
Peak memory 214320 kb
Host smart-a75d02eb-1739-4c3f-992e-59d58fc199fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67821412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.67821412
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2018338726
Short name T630
Test name
Test status
Simulation time 64057873 ps
CPU time 2.25 seconds
Started Jun 06 01:54:51 PM PDT 24
Finished Jun 06 01:54:55 PM PDT 24
Peak memory 210056 kb
Host smart-83cc8b1e-ec58-42a4-84a1-71038a534024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018338726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2018338726
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2959990685
Short name T290
Test name
Test status
Simulation time 188892806 ps
CPU time 5.16 seconds
Started Jun 06 01:54:51 PM PDT 24
Finished Jun 06 01:54:58 PM PDT 24
Peak memory 208324 kb
Host smart-3508f053-684d-41bf-91c9-1209ec4c77f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959990685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2959990685
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3331275217
Short name T288
Test name
Test status
Simulation time 142507176 ps
CPU time 5.54 seconds
Started Jun 06 01:54:47 PM PDT 24
Finished Jun 06 01:54:53 PM PDT 24
Peak memory 209308 kb
Host smart-4aede241-b66a-4fbd-87fa-650f5d5ae5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331275217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3331275217
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3578578857
Short name T390
Test name
Test status
Simulation time 189111843 ps
CPU time 5.08 seconds
Started Jun 06 01:54:52 PM PDT 24
Finished Jun 06 01:54:59 PM PDT 24
Peak memory 222328 kb
Host smart-430881de-bd21-41d2-866e-8a2bd9e86473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578578857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3578578857
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3764995641
Short name T45
Test name
Test status
Simulation time 825835862 ps
CPU time 5.12 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 210056 kb
Host smart-7ba793d3-8169-4a9b-a655-4ebdd3b17c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764995641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3764995641
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2632835997
Short name T673
Test name
Test status
Simulation time 242483338 ps
CPU time 4.65 seconds
Started Jun 06 01:54:51 PM PDT 24
Finished Jun 06 01:54:58 PM PDT 24
Peak memory 207364 kb
Host smart-5a161ab2-e645-4779-bbc3-4ee3cff57e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632835997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2632835997
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1909494618
Short name T480
Test name
Test status
Simulation time 61213629 ps
CPU time 2.6 seconds
Started Jun 06 01:54:53 PM PDT 24
Finished Jun 06 01:54:58 PM PDT 24
Peak memory 206908 kb
Host smart-ea680705-93a8-467c-9592-27780e08e75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909494618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1909494618
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1837511473
Short name T222
Test name
Test status
Simulation time 818534037 ps
CPU time 3.79 seconds
Started Jun 06 01:54:53 PM PDT 24
Finished Jun 06 01:54:59 PM PDT 24
Peak memory 208908 kb
Host smart-d94b6ff0-adf3-4f8e-b710-9fcd7ae67736
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837511473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1837511473
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2298467766
Short name T562
Test name
Test status
Simulation time 1861856908 ps
CPU time 34.92 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:31 PM PDT 24
Peak memory 209176 kb
Host smart-9b40b3ac-9677-43df-ac89-acdf7a217092
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298467766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2298467766
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.78734589
Short name T519
Test name
Test status
Simulation time 385725629 ps
CPU time 3.94 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 208588 kb
Host smart-3ea07832-fb83-4bcc-8b1b-078711af7caf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78734589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.78734589
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3212249080
Short name T921
Test name
Test status
Simulation time 223036505 ps
CPU time 4.18 seconds
Started Jun 06 01:54:52 PM PDT 24
Finished Jun 06 01:54:58 PM PDT 24
Peak memory 218156 kb
Host smart-5bcfee74-9365-4e5d-abab-c06f36751202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212249080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3212249080
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3594351861
Short name T873
Test name
Test status
Simulation time 72028922 ps
CPU time 2.81 seconds
Started Jun 06 01:54:50 PM PDT 24
Finished Jun 06 01:54:55 PM PDT 24
Peak memory 208344 kb
Host smart-d864f65c-5143-415d-b871-860b3bd1b358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594351861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3594351861
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.576824182
Short name T275
Test name
Test status
Simulation time 210567392 ps
CPU time 6.59 seconds
Started Jun 06 01:54:53 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 209564 kb
Host smart-a2f275c3-090b-49a3-893a-a10d5bffc5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576824182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.576824182
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3048982645
Short name T717
Test name
Test status
Simulation time 2304724193 ps
CPU time 5.05 seconds
Started Jun 06 01:54:51 PM PDT 24
Finished Jun 06 01:54:59 PM PDT 24
Peak memory 209976 kb
Host smart-8de140e0-3a46-4c29-9a27-fe8d2225a7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048982645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3048982645
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2386142629
Short name T454
Test name
Test status
Simulation time 155039111 ps
CPU time 0.78 seconds
Started Jun 06 01:54:59 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 205952 kb
Host smart-e2379af2-3944-4b9e-95c7-b3fcb3753019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386142629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2386142629
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2468244550
Short name T621
Test name
Test status
Simulation time 1865517526 ps
CPU time 5.64 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 209156 kb
Host smart-030c7444-3490-45ea-b0b9-2c1483e09e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468244550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2468244550
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2256944339
Short name T798
Test name
Test status
Simulation time 138107874 ps
CPU time 2.48 seconds
Started Jun 06 01:54:51 PM PDT 24
Finished Jun 06 01:54:55 PM PDT 24
Peak memory 220004 kb
Host smart-8f65d1e5-fc43-4220-a56d-dd9563d1444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256944339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2256944339
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2870130024
Short name T774
Test name
Test status
Simulation time 303574846 ps
CPU time 2.67 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 214332 kb
Host smart-c08448c2-ab7a-4699-aad0-943bae533a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870130024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2870130024
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2975957993
Short name T392
Test name
Test status
Simulation time 2344201877 ps
CPU time 23.76 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:22 PM PDT 24
Peak memory 221060 kb
Host smart-36e105a9-6cab-4228-8c77-5a5c9fb3c5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975957993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2975957993
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2545960659
Short name T53
Test name
Test status
Simulation time 114346326 ps
CPU time 2.07 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:54:58 PM PDT 24
Peak memory 214312 kb
Host smart-f9c043a5-2157-48a8-9ee4-d69532e5a6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545960659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2545960659
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2719287134
Short name T649
Test name
Test status
Simulation time 450801369 ps
CPU time 5.1 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 209264 kb
Host smart-c08e95c5-3590-47d3-a321-811d25c40775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719287134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2719287134
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2565584416
Short name T750
Test name
Test status
Simulation time 610949681 ps
CPU time 2.88 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 206856 kb
Host smart-d2ed9191-751e-4d03-8e2c-85e41f1f032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565584416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2565584416
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3921053754
Short name T481
Test name
Test status
Simulation time 71930000 ps
CPU time 1.75 seconds
Started Jun 06 01:54:53 PM PDT 24
Finished Jun 06 01:54:57 PM PDT 24
Peak memory 206916 kb
Host smart-c7bb54c6-2455-4a31-a90d-7503bfebb8c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921053754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3921053754
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.99006364
Short name T824
Test name
Test status
Simulation time 715307710 ps
CPU time 5.25 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 207940 kb
Host smart-e2bbc329-4007-4657-86f5-b88dc829fcbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99006364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.99006364
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1399698733
Short name T450
Test name
Test status
Simulation time 298715065 ps
CPU time 3.63 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 207092 kb
Host smart-2ecbc629-586d-4fd1-8502-ff7b3713f720
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399698733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1399698733
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3842539840
Short name T487
Test name
Test status
Simulation time 385935007 ps
CPU time 1.83 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 206996 kb
Host smart-08ec6cc3-4cc1-48e6-ac6a-00382d2730a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842539840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3842539840
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2159156818
Short name T756
Test name
Test status
Simulation time 128978857 ps
CPU time 3.37 seconds
Started Jun 06 01:54:52 PM PDT 24
Finished Jun 06 01:54:57 PM PDT 24
Peak memory 208076 kb
Host smart-8a3f5012-54c6-43c5-9832-f8426466a7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159156818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2159156818
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.996857352
Short name T834
Test name
Test status
Simulation time 110034577 ps
CPU time 3.12 seconds
Started Jun 06 01:54:52 PM PDT 24
Finished Jun 06 01:54:57 PM PDT 24
Peak memory 207708 kb
Host smart-77fcd265-213b-44f4-b9f0-ef8c10795f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996857352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.996857352
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2376839030
Short name T458
Test name
Test status
Simulation time 36351041 ps
CPU time 1.76 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:54:58 PM PDT 24
Peak memory 209592 kb
Host smart-7bd947dd-a103-4ddf-8bc1-140a8f06fdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376839030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2376839030
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.571733084
Short name T905
Test name
Test status
Simulation time 66536016 ps
CPU time 0.77 seconds
Started Jun 06 01:54:58 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 205936 kb
Host smart-b644f2ad-2e3f-4d14-a406-bed3b80bbd5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571733084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.571733084
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3787390605
Short name T759
Test name
Test status
Simulation time 67760025 ps
CPU time 3.76 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 214356 kb
Host smart-14f7937e-9572-4af4-8350-9929dc77f58c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787390605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3787390605
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2845986726
Short name T591
Test name
Test status
Simulation time 104087275 ps
CPU time 2.77 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 209196 kb
Host smart-200e5604-4f67-44b3-9265-4c6749bb2a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845986726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2845986726
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.862523336
Short name T346
Test name
Test status
Simulation time 2142476165 ps
CPU time 14.91 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:12 PM PDT 24
Peak memory 209304 kb
Host smart-b90f60d5-5a17-4ee8-b9de-825bb10253ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862523336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.862523336
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1909923260
Short name T767
Test name
Test status
Simulation time 182052826 ps
CPU time 4.75 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 214504 kb
Host smart-21d9b773-911f-48a2-a257-ef749a699e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909923260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1909923260
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1718081011
Short name T796
Test name
Test status
Simulation time 121713684 ps
CPU time 2.35 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 214356 kb
Host smart-9a8993cd-dee8-41cb-87ab-d28d4e05521b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718081011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1718081011
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1461712650
Short name T761
Test name
Test status
Simulation time 475998664 ps
CPU time 4.22 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 208904 kb
Host smart-126572cf-7dd7-4fb6-9023-97258baa17a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461712650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1461712650
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3350668849
Short name T376
Test name
Test status
Simulation time 406282638 ps
CPU time 5.07 seconds
Started Jun 06 01:54:57 PM PDT 24
Finished Jun 06 01:55:04 PM PDT 24
Peak memory 209420 kb
Host smart-95ba43d4-3bfe-41fa-baa7-908a2efa09fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350668849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3350668849
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4242770233
Short name T374
Test name
Test status
Simulation time 1317768830 ps
CPU time 9.31 seconds
Started Jun 06 01:54:51 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 208848 kb
Host smart-176fe8be-f13c-4b5f-bf2e-6b24614ee585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242770233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4242770233
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1255905958
Short name T787
Test name
Test status
Simulation time 389240354 ps
CPU time 2.56 seconds
Started Jun 06 01:54:58 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 207812 kb
Host smart-61c689bc-4df6-4384-87ee-37a8fd7def1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255905958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1255905958
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2109638480
Short name T836
Test name
Test status
Simulation time 1912155347 ps
CPU time 6.28 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 208516 kb
Host smart-f2b91912-52a9-4e3a-8663-e522da0d8d78
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109638480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2109638480
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.782513245
Short name T610
Test name
Test status
Simulation time 145986493 ps
CPU time 3.26 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 206756 kb
Host smart-ffdd36b7-b077-480e-977b-7bf139ddb3b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782513245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.782513245
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1753423686
Short name T199
Test name
Test status
Simulation time 379558289 ps
CPU time 6.12 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 222568 kb
Host smart-4918d080-2a91-4e6e-80bc-ae0cf3228488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753423686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1753423686
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3949052968
Short name T446
Test name
Test status
Simulation time 351786132 ps
CPU time 2.67 seconds
Started Jun 06 01:54:57 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 206796 kb
Host smart-58f9187e-5bc1-465f-9f7c-b6f3af3aa133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949052968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3949052968
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3028991877
Short name T261
Test name
Test status
Simulation time 75295150161 ps
CPU time 547.3 seconds
Started Jun 06 01:54:58 PM PDT 24
Finished Jun 06 02:04:07 PM PDT 24
Peak memory 220548 kb
Host smart-035dc366-ceeb-461f-af15-ea6407fb91ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028991877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3028991877
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1575213124
Short name T407
Test name
Test status
Simulation time 3491664438 ps
CPU time 32.28 seconds
Started Jun 06 01:54:54 PM PDT 24
Finished Jun 06 01:55:29 PM PDT 24
Peak memory 208500 kb
Host smart-ac93f630-8b82-4791-af5d-d6c2349302ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575213124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1575213124
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.989173514
Short name T723
Test name
Test status
Simulation time 630880553 ps
CPU time 2.15 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 210280 kb
Host smart-313d6439-d17e-4b5e-bf80-4ba7e8e74467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989173514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.989173514
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3280455032
Short name T206
Test name
Test status
Simulation time 60974912 ps
CPU time 0.85 seconds
Started Jun 06 01:55:01 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 205952 kb
Host smart-4b0595a8-368f-405d-a16b-590209c78693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280455032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3280455032
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.863823479
Short name T334
Test name
Test status
Simulation time 38858537 ps
CPU time 3.1 seconds
Started Jun 06 01:55:02 PM PDT 24
Finished Jun 06 01:55:06 PM PDT 24
Peak memory 215244 kb
Host smart-ca2d1835-bc0d-455f-8969-18ac5fc2c0f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=863823479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.863823479
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3376328499
Short name T7
Test name
Test status
Simulation time 1071315446 ps
CPU time 31.46 seconds
Started Jun 06 01:55:03 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 210076 kb
Host smart-e27af1e2-209e-4266-accb-b09c2730182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376328499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3376328499
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3562117601
Short name T788
Test name
Test status
Simulation time 87804651 ps
CPU time 3.97 seconds
Started Jun 06 01:54:58 PM PDT 24
Finished Jun 06 01:55:04 PM PDT 24
Peak memory 214308 kb
Host smart-22e0d551-7fe5-4190-bb32-c00bb86c61e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562117601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3562117601
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3007461925
Short name T103
Test name
Test status
Simulation time 168779649 ps
CPU time 4.32 seconds
Started Jun 06 01:55:03 PM PDT 24
Finished Jun 06 01:55:08 PM PDT 24
Peak memory 214320 kb
Host smart-5fff91cf-7c10-4253-aa98-9ae7669aa62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007461925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3007461925
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1736364373
Short name T270
Test name
Test status
Simulation time 73643097 ps
CPU time 3.38 seconds
Started Jun 06 01:55:01 PM PDT 24
Finished Jun 06 01:55:06 PM PDT 24
Peak memory 214264 kb
Host smart-2015a5fc-208b-449c-8120-425d97910382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736364373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1736364373
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1746348503
Short name T248
Test name
Test status
Simulation time 89944394 ps
CPU time 2.81 seconds
Started Jun 06 01:54:58 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 217460 kb
Host smart-db792838-a2c1-42eb-8c5d-acd79543fc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746348503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1746348503
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2421191105
Short name T325
Test name
Test status
Simulation time 71360486 ps
CPU time 3.18 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 208676 kb
Host smart-8e12d4c8-6200-4ebd-ad88-359aeafce6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421191105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2421191105
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.468039241
Short name T364
Test name
Test status
Simulation time 146410805 ps
CPU time 3.68 seconds
Started Jun 06 01:55:02 PM PDT 24
Finished Jun 06 01:55:07 PM PDT 24
Peak memory 208628 kb
Host smart-da71572d-8cea-44f3-9fbd-137309492ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468039241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.468039241
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1908553698
Short name T385
Test name
Test status
Simulation time 67168622 ps
CPU time 2.36 seconds
Started Jun 06 01:54:58 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 206932 kb
Host smart-5646f5da-ed96-48f4-8b28-1aca0d330f8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908553698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1908553698
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4248897011
Short name T693
Test name
Test status
Simulation time 6202407585 ps
CPU time 57.49 seconds
Started Jun 06 01:54:59 PM PDT 24
Finished Jun 06 01:55:58 PM PDT 24
Peak memory 206952 kb
Host smart-543bfaf4-2ed5-4901-8714-40b537b640a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248897011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4248897011
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.116321711
Short name T830
Test name
Test status
Simulation time 82736367 ps
CPU time 1.76 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 206916 kb
Host smart-17a99b6a-15a0-4d99-bab5-be500b45e04f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116321711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.116321711
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.71981277
Short name T267
Test name
Test status
Simulation time 46449727 ps
CPU time 2.31 seconds
Started Jun 06 01:55:01 PM PDT 24
Finished Jun 06 01:55:04 PM PDT 24
Peak memory 208652 kb
Host smart-122ca853-dece-4080-ae8e-38431a0fb6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71981277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.71981277
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3456322179
Short name T666
Test name
Test status
Simulation time 2568213045 ps
CPU time 14.11 seconds
Started Jun 06 01:54:57 PM PDT 24
Finished Jun 06 01:55:13 PM PDT 24
Peak memory 208808 kb
Host smart-0eb70f27-4b25-49ca-a3d6-699059441f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456322179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3456322179
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2031915773
Short name T84
Test name
Test status
Simulation time 428128757 ps
CPU time 9 seconds
Started Jun 06 01:54:57 PM PDT 24
Finished Jun 06 01:55:08 PM PDT 24
Peak memory 215396 kb
Host smart-30748ae2-25b9-48ba-b527-c27b6c45e41b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031915773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2031915773
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1538152970
Short name T771
Test name
Test status
Simulation time 188781193 ps
CPU time 5.19 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 219676 kb
Host smart-1a725b9d-a0e6-4cb6-88ca-f82b565ea959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538152970 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1538152970
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2722837182
Short name T555
Test name
Test status
Simulation time 4324391350 ps
CPU time 18 seconds
Started Jun 06 01:54:58 PM PDT 24
Finished Jun 06 01:55:18 PM PDT 24
Peak memory 210144 kb
Host smart-e0ff1343-90b6-4e8a-b59a-21454904fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722837182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2722837182
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1841430040
Short name T694
Test name
Test status
Simulation time 105326428 ps
CPU time 0.7 seconds
Started Jun 06 01:54:52 PM PDT 24
Finished Jun 06 01:54:55 PM PDT 24
Peak memory 205900 kb
Host smart-1f09c78c-cfc6-49a1-90db-a6d47391c699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841430040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1841430040
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1820078728
Short name T428
Test name
Test status
Simulation time 119203644 ps
CPU time 2.8 seconds
Started Jun 06 01:55:00 PM PDT 24
Finished Jun 06 01:55:04 PM PDT 24
Peak memory 214356 kb
Host smart-4f2d3994-1edc-48bb-bd71-74defb2207b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820078728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1820078728
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2968779254
Short name T274
Test name
Test status
Simulation time 467626329 ps
CPU time 9.62 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:55:07 PM PDT 24
Peak memory 214404 kb
Host smart-29c9681a-9cf9-4d89-81d3-3a923e96caec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968779254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2968779254
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1933624405
Short name T105
Test name
Test status
Simulation time 617980099 ps
CPU time 10.12 seconds
Started Jun 06 01:54:57 PM PDT 24
Finished Jun 06 01:55:09 PM PDT 24
Peak memory 222440 kb
Host smart-a7cd9e25-4fff-4545-8995-caa684472253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933624405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1933624405
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2009468458
Short name T721
Test name
Test status
Simulation time 182378711 ps
CPU time 3.22 seconds
Started Jun 06 01:54:57 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 214264 kb
Host smart-a6ea7d6c-5779-4ce2-a41c-5667c66c798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009468458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2009468458
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.650664924
Short name T13
Test name
Test status
Simulation time 152372122 ps
CPU time 3.68 seconds
Started Jun 06 01:54:59 PM PDT 24
Finished Jun 06 01:55:04 PM PDT 24
Peak memory 209420 kb
Host smart-714e9cec-d890-4bd7-93f9-e97666587f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650664924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.650664924
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1254554899
Short name T696
Test name
Test status
Simulation time 35027412 ps
CPU time 2.52 seconds
Started Jun 06 01:54:57 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 208476 kb
Host smart-b6825a1b-758c-4092-9152-249c9714118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254554899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1254554899
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3899545059
Short name T488
Test name
Test status
Simulation time 313518550 ps
CPU time 2.26 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 209100 kb
Host smart-37c1f0ee-8730-4452-90d7-a2672ccc188a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899545059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3899545059
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3481629229
Short name T94
Test name
Test status
Simulation time 131099285 ps
CPU time 4.04 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 208696 kb
Host smart-b4ba3a97-065e-4457-95b8-c12ef9e41ed1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481629229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3481629229
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3791589414
Short name T645
Test name
Test status
Simulation time 111352568 ps
CPU time 3.38 seconds
Started Jun 06 01:55:00 PM PDT 24
Finished Jun 06 01:55:05 PM PDT 24
Peak memory 206932 kb
Host smart-f016703c-e01e-4008-a110-8827b0503420
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791589414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3791589414
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3128948512
Short name T622
Test name
Test status
Simulation time 122747193 ps
CPU time 1.94 seconds
Started Jun 06 01:54:55 PM PDT 24
Finished Jun 06 01:54:59 PM PDT 24
Peak memory 207464 kb
Host smart-d8b7e185-d85a-424c-879f-65109e17f93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128948512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3128948512
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.4243781936
Short name T497
Test name
Test status
Simulation time 595496954 ps
CPU time 6.31 seconds
Started Jun 06 01:55:01 PM PDT 24
Finished Jun 06 01:55:08 PM PDT 24
Peak memory 208520 kb
Host smart-1f2751f8-2e34-420e-a7ab-19923da2420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243781936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.4243781936
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3822888862
Short name T312
Test name
Test status
Simulation time 652250195 ps
CPU time 8.83 seconds
Started Jun 06 01:54:59 PM PDT 24
Finished Jun 06 01:55:09 PM PDT 24
Peak memory 209596 kb
Host smart-992e96bf-b235-434c-9d99-8faffb7af1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822888862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3822888862
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2085565875
Short name T453
Test name
Test status
Simulation time 56780426 ps
CPU time 0.74 seconds
Started Jun 06 01:55:06 PM PDT 24
Finished Jun 06 01:55:07 PM PDT 24
Peak memory 205908 kb
Host smart-9cb5f484-3bed-4bd7-9b31-c38a29091e7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085565875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2085565875
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.706189140
Short name T268
Test name
Test status
Simulation time 203021564 ps
CPU time 2.49 seconds
Started Jun 06 01:55:08 PM PDT 24
Finished Jun 06 01:55:12 PM PDT 24
Peak memory 215028 kb
Host smart-47002bf1-57e9-48b1-b8d7-0848fa0a2a8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706189140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.706189140
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.4233673492
Short name T18
Test name
Test status
Simulation time 61868671 ps
CPU time 2.28 seconds
Started Jun 06 01:55:04 PM PDT 24
Finished Jun 06 01:55:08 PM PDT 24
Peak memory 222740 kb
Host smart-6b159102-dfba-4742-872a-58054e221150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233673492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.4233673492
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2903535634
Short name T114
Test name
Test status
Simulation time 4967359353 ps
CPU time 10.65 seconds
Started Jun 06 01:55:06 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 214460 kb
Host smart-43d65597-5a26-4731-a566-aa182a20811f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903535634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2903535634
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_random.3549989926
Short name T543
Test name
Test status
Simulation time 441080476 ps
CPU time 5.07 seconds
Started Jun 06 01:55:04 PM PDT 24
Finished Jun 06 01:55:10 PM PDT 24
Peak memory 207580 kb
Host smart-df5b83de-a231-40e0-abb1-b8b7d27908d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549989926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3549989926
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3093641932
Short name T342
Test name
Test status
Simulation time 315608369 ps
CPU time 3.42 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:02 PM PDT 24
Peak memory 208556 kb
Host smart-eaffadb9-76f2-448f-b53f-21190e4588e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093641932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3093641932
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3518499937
Short name T336
Test name
Test status
Simulation time 88696784 ps
CPU time 3.06 seconds
Started Jun 06 01:55:07 PM PDT 24
Finished Jun 06 01:55:11 PM PDT 24
Peak memory 208776 kb
Host smart-ea641dd2-d129-47da-978f-92114299a228
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518499937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3518499937
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2562215262
Short name T335
Test name
Test status
Simulation time 247711422 ps
CPU time 6.84 seconds
Started Jun 06 01:55:05 PM PDT 24
Finished Jun 06 01:55:13 PM PDT 24
Peak memory 208676 kb
Host smart-d2ce3162-39e3-4cc2-836b-f32af8f830b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562215262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2562215262
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2891314474
Short name T909
Test name
Test status
Simulation time 431496982 ps
CPU time 3.54 seconds
Started Jun 06 01:55:05 PM PDT 24
Finished Jun 06 01:55:09 PM PDT 24
Peak memory 208348 kb
Host smart-b51faaae-a6b2-4d36-905c-40c5bf397578
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891314474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2891314474
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2393140926
Short name T441
Test name
Test status
Simulation time 3306041949 ps
CPU time 20.92 seconds
Started Jun 06 01:55:01 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 217440 kb
Host smart-987a42e6-af5d-43fe-b882-d8ab41503c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393140926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2393140926
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2249619174
Short name T427
Test name
Test status
Simulation time 243982722 ps
CPU time 3.07 seconds
Started Jun 06 01:54:56 PM PDT 24
Finished Jun 06 01:55:01 PM PDT 24
Peak memory 208580 kb
Host smart-f729d7c3-caa1-46a5-8dfc-b8af6209b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249619174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2249619174
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2627621638
Short name T244
Test name
Test status
Simulation time 5611663940 ps
CPU time 56.08 seconds
Started Jun 06 01:55:07 PM PDT 24
Finished Jun 06 01:56:04 PM PDT 24
Peak memory 222720 kb
Host smart-290907c0-7a54-4db7-a7ef-1261d9cad5bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627621638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2627621638
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3477388119
Short name T245
Test name
Test status
Simulation time 516442528 ps
CPU time 15.48 seconds
Started Jun 06 01:55:08 PM PDT 24
Finished Jun 06 01:55:25 PM PDT 24
Peak memory 220792 kb
Host smart-9d49df59-12df-481f-a4da-691fb3ace681
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477388119 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3477388119
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2261712171
Short name T211
Test name
Test status
Simulation time 173637539 ps
CPU time 4.59 seconds
Started Jun 06 01:55:03 PM PDT 24
Finished Jun 06 01:55:08 PM PDT 24
Peak memory 207632 kb
Host smart-0abab7c7-ed66-44e8-a948-612bd1e153e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261712171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2261712171
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.458469496
Short name T416
Test name
Test status
Simulation time 55495363 ps
CPU time 2.5 seconds
Started Jun 06 01:55:06 PM PDT 24
Finished Jun 06 01:55:09 PM PDT 24
Peak memory 210160 kb
Host smart-4f39a100-0d6f-40dc-b735-47ec7b8e4cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458469496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.458469496
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1302431758
Short name T455
Test name
Test status
Simulation time 10704034 ps
CPU time 0.85 seconds
Started Jun 06 01:55:07 PM PDT 24
Finished Jun 06 01:55:09 PM PDT 24
Peak memory 205952 kb
Host smart-b1332e50-a18a-4f2f-9936-1ba52c381fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302431758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1302431758
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2508291828
Short name T577
Test name
Test status
Simulation time 70919160 ps
CPU time 2.35 seconds
Started Jun 06 01:55:04 PM PDT 24
Finished Jun 06 01:55:07 PM PDT 24
Peak memory 207420 kb
Host smart-6e0fc978-f84f-4570-8541-bf1895fae366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508291828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2508291828
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3418198765
Short name T507
Test name
Test status
Simulation time 784268634 ps
CPU time 4.1 seconds
Started Jun 06 01:55:07 PM PDT 24
Finished Jun 06 01:55:12 PM PDT 24
Peak memory 208812 kb
Host smart-87e0ca17-59ba-4b19-8b65-9806879f5b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418198765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3418198765
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2522983506
Short name T618
Test name
Test status
Simulation time 176268360 ps
CPU time 3.43 seconds
Started Jun 06 01:55:07 PM PDT 24
Finished Jun 06 01:55:12 PM PDT 24
Peak memory 215164 kb
Host smart-a10bbfba-67a5-4cb9-9de5-daa8531632cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522983506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2522983506
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3020415626
Short name T705
Test name
Test status
Simulation time 249210328 ps
CPU time 6.88 seconds
Started Jun 06 01:55:05 PM PDT 24
Finished Jun 06 01:55:13 PM PDT 24
Peak memory 208364 kb
Host smart-2ab52a34-6f8d-41db-acc9-72e8544d2b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020415626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3020415626
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.131072571
Short name T378
Test name
Test status
Simulation time 217837184 ps
CPU time 2.28 seconds
Started Jun 06 01:55:08 PM PDT 24
Finished Jun 06 01:55:12 PM PDT 24
Peak memory 206940 kb
Host smart-41d4e92d-79cf-41ff-a7f2-be6e8914d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131072571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.131072571
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1956576413
Short name T514
Test name
Test status
Simulation time 64619512 ps
CPU time 3.22 seconds
Started Jun 06 01:55:04 PM PDT 24
Finished Jun 06 01:55:09 PM PDT 24
Peak memory 207016 kb
Host smart-689afd25-6d30-4485-a053-0a750cbf1672
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956576413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1956576413
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.364837973
Short name T587
Test name
Test status
Simulation time 23619581 ps
CPU time 1.86 seconds
Started Jun 06 01:55:04 PM PDT 24
Finished Jun 06 01:55:07 PM PDT 24
Peak memory 208500 kb
Host smart-ebbe1ef5-11b3-40d2-8ad0-09e028924b04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364837973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.364837973
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2219940943
Short name T92
Test name
Test status
Simulation time 226645105 ps
CPU time 2.9 seconds
Started Jun 06 01:55:05 PM PDT 24
Finished Jun 06 01:55:09 PM PDT 24
Peak memory 207052 kb
Host smart-05765977-9d3a-46e0-873c-3780919a123d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219940943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2219940943
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.767809488
Short name T230
Test name
Test status
Simulation time 741648779 ps
CPU time 4.1 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:18 PM PDT 24
Peak memory 208744 kb
Host smart-3be67da0-c8b9-4828-88a1-2026c77e7579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767809488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.767809488
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1521551883
Short name T226
Test name
Test status
Simulation time 673917488 ps
CPU time 14.15 seconds
Started Jun 06 01:55:02 PM PDT 24
Finished Jun 06 01:55:17 PM PDT 24
Peak memory 207884 kb
Host smart-6db02127-0ee7-4e4f-a857-501eb4378351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521551883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1521551883
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1285046013
Short name T724
Test name
Test status
Simulation time 1613557071 ps
CPU time 42.18 seconds
Started Jun 06 01:55:04 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 208420 kb
Host smart-43dca1df-2a8f-42fa-b662-0d70eacdd125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285046013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1285046013
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2759883622
Short name T412
Test name
Test status
Simulation time 935522775 ps
CPU time 3.46 seconds
Started Jun 06 01:55:03 PM PDT 24
Finished Jun 06 01:55:07 PM PDT 24
Peak memory 210448 kb
Host smart-3c3242cb-1428-4b46-9cda-abd494adc79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759883622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2759883622
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.907341214
Short name T896
Test name
Test status
Simulation time 15669481 ps
CPU time 0.85 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:15 PM PDT 24
Peak memory 205860 kb
Host smart-cfe31ef0-2a5f-4c36-b117-87d0c23cc145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907341214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.907341214
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1045642786
Short name T546
Test name
Test status
Simulation time 206174212 ps
CPU time 3.95 seconds
Started Jun 06 01:55:15 PM PDT 24
Finished Jun 06 01:55:20 PM PDT 24
Peak memory 218488 kb
Host smart-cb98ce75-386b-4643-99fa-1edc1c941751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045642786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1045642786
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.418827949
Short name T350
Test name
Test status
Simulation time 31783268 ps
CPU time 2.63 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:17 PM PDT 24
Peak memory 214160 kb
Host smart-32bc04cc-e599-4a8d-8b15-9b4af814e5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418827949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.418827949
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1561025240
Short name T101
Test name
Test status
Simulation time 52131982 ps
CPU time 2.9 seconds
Started Jun 06 01:55:12 PM PDT 24
Finished Jun 06 01:55:16 PM PDT 24
Peak memory 214304 kb
Host smart-8b574dcc-e1f0-4e80-9cf8-c6115d0c3654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561025240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1561025240
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.384110838
Short name T916
Test name
Test status
Simulation time 399339385 ps
CPU time 2.85 seconds
Started Jun 06 01:55:06 PM PDT 24
Finished Jun 06 01:55:10 PM PDT 24
Peak memory 214900 kb
Host smart-a37fdfc3-6268-4809-9ce1-f9ac774e4144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384110838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.384110838
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.90187120
Short name T489
Test name
Test status
Simulation time 356039193 ps
CPU time 8.59 seconds
Started Jun 06 01:55:08 PM PDT 24
Finished Jun 06 01:55:18 PM PDT 24
Peak memory 209256 kb
Host smart-4f2f95c3-304c-4441-b868-a6252458b778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90187120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.90187120
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.741589911
Short name T585
Test name
Test status
Simulation time 224561937 ps
CPU time 5.84 seconds
Started Jun 06 01:55:06 PM PDT 24
Finished Jun 06 01:55:12 PM PDT 24
Peak memory 208076 kb
Host smart-19966347-f36c-468d-9727-4ca078459112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741589911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.741589911
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2781765266
Short name T321
Test name
Test status
Simulation time 2041620217 ps
CPU time 12.69 seconds
Started Jun 06 01:55:06 PM PDT 24
Finished Jun 06 01:55:20 PM PDT 24
Peak memory 208716 kb
Host smart-b6ed3b0c-d7eb-4344-a194-4d81807c5e4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781765266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2781765266
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3744689071
Short name T634
Test name
Test status
Simulation time 536470440 ps
CPU time 4.39 seconds
Started Jun 06 01:55:01 PM PDT 24
Finished Jun 06 01:55:07 PM PDT 24
Peak memory 208056 kb
Host smart-4bbb4885-b95a-4411-9365-7b84b867f945
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744689071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3744689071
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2300083136
Short name T602
Test name
Test status
Simulation time 194677836 ps
CPU time 1.97 seconds
Started Jun 06 01:55:04 PM PDT 24
Finished Jun 06 01:55:07 PM PDT 24
Peak memory 207656 kb
Host smart-530b00f2-01e4-42e8-8506-b28f43fc2575
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300083136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2300083136
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2993705942
Short name T341
Test name
Test status
Simulation time 174303797 ps
CPU time 6.3 seconds
Started Jun 06 01:55:16 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 208324 kb
Host smart-23f6e95c-1dad-472a-8df2-d92eee238673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993705942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2993705942
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2272058122
Short name T91
Test name
Test status
Simulation time 508197263 ps
CPU time 3.47 seconds
Started Jun 06 01:55:08 PM PDT 24
Finished Jun 06 01:55:13 PM PDT 24
Peak memory 206712 kb
Host smart-20d6e0cb-58be-402d-b400-3b2bf1ff34d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272058122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2272058122
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.661710775
Short name T881
Test name
Test status
Simulation time 1075125304 ps
CPU time 16.4 seconds
Started Jun 06 01:55:16 PM PDT 24
Finished Jun 06 01:55:33 PM PDT 24
Peak memory 222440 kb
Host smart-aaebfcd2-1be2-4e68-93e8-6a24b92be8f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661710775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.661710775
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3913436179
Short name T220
Test name
Test status
Simulation time 153717719 ps
CPU time 3.59 seconds
Started Jun 06 01:55:15 PM PDT 24
Finished Jun 06 01:55:20 PM PDT 24
Peak memory 209356 kb
Host smart-1386b5d8-fed8-4329-9537-4312e4477ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913436179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3913436179
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1735421640
Short name T135
Test name
Test status
Simulation time 647631655 ps
CPU time 3.68 seconds
Started Jun 06 01:55:15 PM PDT 24
Finished Jun 06 01:55:19 PM PDT 24
Peak memory 209976 kb
Host smart-05c5e1ad-adce-45d1-8446-ee5f555c0894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735421640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1735421640
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2212261114
Short name T471
Test name
Test status
Simulation time 31065752 ps
CPU time 0.72 seconds
Started Jun 06 01:55:16 PM PDT 24
Finished Jun 06 01:55:18 PM PDT 24
Peak memory 205868 kb
Host smart-19999096-0ad8-454b-810c-12d3f1036664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212261114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2212261114
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3996541904
Short name T765
Test name
Test status
Simulation time 129753605 ps
CPU time 1.82 seconds
Started Jun 06 01:55:06 PM PDT 24
Finished Jun 06 01:55:09 PM PDT 24
Peak memory 214252 kb
Host smart-fd3652aa-7d90-440e-9e93-ece4e203bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996541904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3996541904
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2254590449
Short name T623
Test name
Test status
Simulation time 4639668033 ps
CPU time 31.61 seconds
Started Jun 06 01:55:09 PM PDT 24
Finished Jun 06 01:55:41 PM PDT 24
Peak memory 210532 kb
Host smart-ad904f05-d9cb-4546-a24a-cb33516ebe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254590449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2254590449
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.843070448
Short name T52
Test name
Test status
Simulation time 248260348 ps
CPU time 2.09 seconds
Started Jun 06 01:55:08 PM PDT 24
Finished Jun 06 01:55:11 PM PDT 24
Peak memory 214468 kb
Host smart-3c007de3-2374-4972-a193-f3366757000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843070448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.843070448
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1248011352
Short name T291
Test name
Test status
Simulation time 576874624 ps
CPU time 5.3 seconds
Started Jun 06 01:55:11 PM PDT 24
Finished Jun 06 01:55:17 PM PDT 24
Peak memory 222312 kb
Host smart-3191c75c-bf56-4f3d-b32d-599e91703853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248011352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1248011352
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.477441493
Short name T910
Test name
Test status
Simulation time 140407556 ps
CPU time 4.26 seconds
Started Jun 06 01:55:07 PM PDT 24
Finished Jun 06 01:55:12 PM PDT 24
Peak memory 215148 kb
Host smart-4d41b092-4d7e-4bf9-9455-599a545415f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477441493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.477441493
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3466366973
Short name T470
Test name
Test status
Simulation time 1408595529 ps
CPU time 7.91 seconds
Started Jun 06 01:55:08 PM PDT 24
Finished Jun 06 01:55:17 PM PDT 24
Peak memory 214336 kb
Host smart-b9a85549-716c-4b86-8e9e-98b213a57002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466366973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3466366973
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3507796167
Short name T751
Test name
Test status
Simulation time 269150405 ps
CPU time 3.33 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:17 PM PDT 24
Peak memory 208632 kb
Host smart-a11db388-b1ad-4b96-a263-36c3190341db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507796167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3507796167
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.510975289
Short name T845
Test name
Test status
Simulation time 90138105 ps
CPU time 3.23 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:18 PM PDT 24
Peak memory 207008 kb
Host smart-85cbbab6-4c94-427f-b296-989abcb768b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510975289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.510975289
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3185347495
Short name T742
Test name
Test status
Simulation time 2164576182 ps
CPU time 29.03 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:43 PM PDT 24
Peak memory 208516 kb
Host smart-b957e3dc-5af9-48e7-86f1-5924ddfbe622
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185347495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3185347495
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1229037218
Short name T914
Test name
Test status
Simulation time 4091477697 ps
CPU time 45.6 seconds
Started Jun 06 01:55:09 PM PDT 24
Finished Jun 06 01:55:55 PM PDT 24
Peak memory 208088 kb
Host smart-a26e07ec-bbce-4941-a95d-56781bebcb7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229037218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1229037218
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1909005925
Short name T854
Test name
Test status
Simulation time 139335136 ps
CPU time 3.01 seconds
Started Jun 06 01:55:08 PM PDT 24
Finished Jun 06 01:55:12 PM PDT 24
Peak memory 214260 kb
Host smart-ff934053-8c0c-4566-9db8-1ae72479c499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909005925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1909005925
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2463499948
Short name T596
Test name
Test status
Simulation time 1429157910 ps
CPU time 26.51 seconds
Started Jun 06 01:55:12 PM PDT 24
Finished Jun 06 01:55:39 PM PDT 24
Peak memory 208216 kb
Host smart-16626325-5df6-4dc0-81ce-5a3aa9ae5aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463499948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2463499948
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1282857807
Short name T583
Test name
Test status
Simulation time 269407507 ps
CPU time 9.73 seconds
Started Jun 06 01:55:07 PM PDT 24
Finished Jun 06 01:55:18 PM PDT 24
Peak memory 222712 kb
Host smart-67c08de9-ec73-4d5b-9f9f-fb50f4ed126c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282857807 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1282857807
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2625563158
Short name T550
Test name
Test status
Simulation time 7949480405 ps
CPU time 79.52 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:56:33 PM PDT 24
Peak memory 221316 kb
Host smart-901d0e01-8367-450a-a2d4-be0beb2278f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625563158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2625563158
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2404047047
Short name T143
Test name
Test status
Simulation time 192186720 ps
CPU time 1.88 seconds
Started Jun 06 01:55:03 PM PDT 24
Finished Jun 06 01:55:06 PM PDT 24
Peak memory 210092 kb
Host smart-d9c87302-d940-4100-ac6e-5aa1f81c1604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404047047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2404047047
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.767001024
Short name T820
Test name
Test status
Simulation time 35927766 ps
CPU time 0.73 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:15 PM PDT 24
Peak memory 205900 kb
Host smart-4f43bb04-f960-4eac-b8de-cf1e2d8dd924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767001024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.767001024
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2223297147
Short name T318
Test name
Test status
Simulation time 57119243 ps
CPU time 3.82 seconds
Started Jun 06 01:55:12 PM PDT 24
Finished Jun 06 01:55:17 PM PDT 24
Peak memory 215028 kb
Host smart-3ae45fd5-0791-479e-a23d-dc5d9d7640ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223297147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2223297147
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3262955960
Short name T64
Test name
Test status
Simulation time 2166459488 ps
CPU time 36.7 seconds
Started Jun 06 01:55:14 PM PDT 24
Finished Jun 06 01:55:51 PM PDT 24
Peak memory 210032 kb
Host smart-a7506c0a-a0aa-4fea-90c4-0dcfb95b5d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262955960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3262955960
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3802511907
Short name T790
Test name
Test status
Simulation time 130270766 ps
CPU time 3.47 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:18 PM PDT 24
Peak memory 207524 kb
Host smart-f99bb14f-4bb9-4d4f-92d7-43abcf7c1b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802511907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3802511907
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3334434659
Short name T328
Test name
Test status
Simulation time 126448919 ps
CPU time 3.3 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:17 PM PDT 24
Peak memory 214260 kb
Host smart-5aae4bcf-e50f-4b12-83d7-bbeb1e535221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334434659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3334434659
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3947392700
Short name T44
Test name
Test status
Simulation time 152637618 ps
CPU time 8.17 seconds
Started Jun 06 01:55:10 PM PDT 24
Finished Jun 06 01:55:19 PM PDT 24
Peak memory 214348 kb
Host smart-535bfe0c-b94b-4734-8bcf-dfa97b5445d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947392700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3947392700
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.220275407
Short name T886
Test name
Test status
Simulation time 921099654 ps
CPU time 8.84 seconds
Started Jun 06 01:55:11 PM PDT 24
Finished Jun 06 01:55:21 PM PDT 24
Peak memory 208724 kb
Host smart-bcd4ced9-d2d7-4990-95e4-90fa8ebb233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220275407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.220275407
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3723970462
Short name T117
Test name
Test status
Simulation time 912516133 ps
CPU time 6.01 seconds
Started Jun 06 01:55:10 PM PDT 24
Finished Jun 06 01:55:17 PM PDT 24
Peak memory 208052 kb
Host smart-85239fab-7a16-47a5-84a5-52e19e4338be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723970462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3723970462
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1289407370
Short name T541
Test name
Test status
Simulation time 144492141 ps
CPU time 3.43 seconds
Started Jun 06 01:55:12 PM PDT 24
Finished Jun 06 01:55:16 PM PDT 24
Peak memory 208700 kb
Host smart-dab13c0e-a867-4571-80ba-8e3b6b7a79bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289407370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1289407370
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1235038896
Short name T894
Test name
Test status
Simulation time 5154956889 ps
CPU time 35.3 seconds
Started Jun 06 01:55:10 PM PDT 24
Finished Jun 06 01:55:46 PM PDT 24
Peak memory 208352 kb
Host smart-bd7ddb1e-1a82-4d4b-a07b-5bcb512f376a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235038896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1235038896
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2022710511
Short name T579
Test name
Test status
Simulation time 529369922 ps
CPU time 4.57 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:19 PM PDT 24
Peak memory 207004 kb
Host smart-66c365ab-b297-49a2-8dd5-5c3fb607b6ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022710511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2022710511
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.15341379
Short name T545
Test name
Test status
Simulation time 1047480361 ps
CPU time 10.75 seconds
Started Jun 06 01:55:16 PM PDT 24
Finished Jun 06 01:55:28 PM PDT 24
Peak memory 214356 kb
Host smart-ad922308-661a-474e-af1d-1b40afc61c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15341379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.15341379
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.703488179
Short name T885
Test name
Test status
Simulation time 4652257744 ps
CPU time 37.43 seconds
Started Jun 06 01:55:12 PM PDT 24
Finished Jun 06 01:55:51 PM PDT 24
Peak memory 208164 kb
Host smart-ce4660ca-670d-430a-aa97-012e0331ed02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703488179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.703488179
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2372656967
Short name T868
Test name
Test status
Simulation time 1857075965 ps
CPU time 44.52 seconds
Started Jun 06 01:55:10 PM PDT 24
Finished Jun 06 01:55:56 PM PDT 24
Peak memory 222196 kb
Host smart-05e1bab5-64bd-4ae2-a571-cc0d2ada9dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372656967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2372656967
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.4154327495
Short name T122
Test name
Test status
Simulation time 438649949 ps
CPU time 16.94 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:31 PM PDT 24
Peak memory 222660 kb
Host smart-2d000913-df00-45e0-8d2d-ac9c52ff14c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154327495 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.4154327495
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1186518638
Short name T140
Test name
Test status
Simulation time 396408889 ps
CPU time 4.66 seconds
Started Jun 06 01:55:12 PM PDT 24
Finished Jun 06 01:55:18 PM PDT 24
Peak memory 209224 kb
Host smart-2326cfe4-721a-4925-a4c4-76dfe098360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186518638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1186518638
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3008855287
Short name T720
Test name
Test status
Simulation time 307541645 ps
CPU time 2.02 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:16 PM PDT 24
Peak memory 210056 kb
Host smart-afaa1ef1-9d53-4f7e-b263-08d16e43c5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008855287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3008855287
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1734508704
Short name T505
Test name
Test status
Simulation time 18051150 ps
CPU time 0.98 seconds
Started Jun 06 01:54:11 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 206220 kb
Host smart-336cd3b5-d8f2-4605-ab47-6a1f9905319b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734508704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1734508704
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3394395061
Short name T150
Test name
Test status
Simulation time 48586898 ps
CPU time 3.04 seconds
Started Jun 06 01:54:03 PM PDT 24
Finished Jun 06 01:54:07 PM PDT 24
Peak memory 215720 kb
Host smart-2f94820b-20ea-4f03-8ba2-f9130a099cad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394395061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3394395061
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.4233403855
Short name T247
Test name
Test status
Simulation time 25221340 ps
CPU time 1.84 seconds
Started Jun 06 01:54:01 PM PDT 24
Finished Jun 06 01:54:04 PM PDT 24
Peak memory 215208 kb
Host smart-c7b38d5d-de4b-4a93-91c1-ed5364c76e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233403855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4233403855
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3806541679
Short name T469
Test name
Test status
Simulation time 131672094 ps
CPU time 4.16 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 207452 kb
Host smart-e3a3c236-1128-4521-8abb-ca894789b62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806541679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3806541679
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2514441303
Short name T102
Test name
Test status
Simulation time 334918598 ps
CPU time 3.45 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 209592 kb
Host smart-e349a22a-066b-4b2d-bb79-f80041b9ec7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514441303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2514441303
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.189748471
Short name T239
Test name
Test status
Simulation time 134976987 ps
CPU time 4.4 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:54:04 PM PDT 24
Peak memory 214060 kb
Host smart-2aa156f6-fab4-4eda-8c80-2d428e23716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189748471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.189748471
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2132090110
Short name T47
Test name
Test status
Simulation time 339359463 ps
CPU time 3.2 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 222564 kb
Host smart-65ffaa0d-40a1-4696-9f1e-0f506d48104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132090110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2132090110
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1086196023
Short name T745
Test name
Test status
Simulation time 203211479 ps
CPU time 3.37 seconds
Started Jun 06 01:53:59 PM PDT 24
Finished Jun 06 01:54:04 PM PDT 24
Peak memory 214256 kb
Host smart-9646c258-30c7-43c0-a639-a9ea002d9478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086196023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1086196023
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3220422833
Short name T40
Test name
Test status
Simulation time 451809565 ps
CPU time 10.21 seconds
Started Jun 06 01:54:05 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 230676 kb
Host smart-de64e05d-1154-4be8-b202-2a6343af0443
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220422833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3220422833
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1159395398
Short name T400
Test name
Test status
Simulation time 724759234 ps
CPU time 6.97 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:07 PM PDT 24
Peak memory 206760 kb
Host smart-805b7073-5f6b-46c1-a282-f17a0bfd2c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159395398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1159395398
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.10126679
Short name T213
Test name
Test status
Simulation time 74541393 ps
CPU time 2.56 seconds
Started Jun 06 01:53:59 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 208996 kb
Host smart-2171416b-7994-4c60-9fbc-be4cae27c841
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10126679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.10126679
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.798686220
Short name T609
Test name
Test status
Simulation time 284728197 ps
CPU time 4.59 seconds
Started Jun 06 01:54:03 PM PDT 24
Finished Jun 06 01:54:09 PM PDT 24
Peak memory 208420 kb
Host smart-c8c8ee9a-bcd8-4bcd-a7b4-3da182fd3777
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798686220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.798686220
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3574246840
Short name T547
Test name
Test status
Simulation time 70861846 ps
CPU time 2.71 seconds
Started Jun 06 01:54:03 PM PDT 24
Finished Jun 06 01:54:07 PM PDT 24
Peak memory 206840 kb
Host smart-06d81f0d-a2ad-4f77-aea8-ce5cd34353ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574246840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3574246840
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2192660202
Short name T459
Test name
Test status
Simulation time 42658008 ps
CPU time 2.29 seconds
Started Jun 06 01:54:05 PM PDT 24
Finished Jun 06 01:54:08 PM PDT 24
Peak memory 207124 kb
Host smart-f3283f68-1908-4a81-8266-fda69b1b7ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192660202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2192660202
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.138701586
Short name T442
Test name
Test status
Simulation time 117979324 ps
CPU time 4.13 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 208712 kb
Host smart-c8be4c0e-a24e-452e-b876-23e1621e3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138701586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.138701586
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3173808616
Short name T361
Test name
Test status
Simulation time 1321473856 ps
CPU time 50.09 seconds
Started Jun 06 01:54:09 PM PDT 24
Finished Jun 06 01:55:00 PM PDT 24
Peak memory 222740 kb
Host smart-5437b867-a089-4ea3-866c-2dd4dc99200a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173808616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3173808616
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.852849602
Short name T345
Test name
Test status
Simulation time 220284519 ps
CPU time 3.77 seconds
Started Jun 06 01:54:03 PM PDT 24
Finished Jun 06 01:54:08 PM PDT 24
Peak memory 214420 kb
Host smart-da6afdff-1ad2-4eb6-926b-dd44e2db3c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852849602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.852849602
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2591943236
Short name T62
Test name
Test status
Simulation time 222478702 ps
CPU time 2.39 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 209908 kb
Host smart-da0ca3fb-7771-4af1-ab7a-1504c3d9c2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591943236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2591943236
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1733997728
Short name T747
Test name
Test status
Simulation time 11067869 ps
CPU time 0.81 seconds
Started Jun 06 01:55:21 PM PDT 24
Finished Jun 06 01:55:22 PM PDT 24
Peak memory 205876 kb
Host smart-4bbbb254-b219-4ca9-bb0e-fe99be78635e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733997728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1733997728
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.454808087
Short name T430
Test name
Test status
Simulation time 595968663 ps
CPU time 15.79 seconds
Started Jun 06 01:55:12 PM PDT 24
Finished Jun 06 01:55:29 PM PDT 24
Peak memory 214280 kb
Host smart-591c0350-016c-49a9-abe0-bcee65a8be19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454808087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.454808087
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3552344605
Short name T692
Test name
Test status
Simulation time 216148450 ps
CPU time 5.48 seconds
Started Jun 06 01:55:30 PM PDT 24
Finished Jun 06 01:55:37 PM PDT 24
Peak memory 221884 kb
Host smart-b8f7ebb5-0455-46a5-bd37-c820f4e81370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552344605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3552344605
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3954697187
Short name T355
Test name
Test status
Simulation time 2439168096 ps
CPU time 17.44 seconds
Started Jun 06 01:55:12 PM PDT 24
Finished Jun 06 01:55:31 PM PDT 24
Peak memory 208696 kb
Host smart-d3437954-859b-4425-ad0a-7ae4d095fe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954697187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3954697187
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3384939664
Short name T809
Test name
Test status
Simulation time 247101119 ps
CPU time 4.25 seconds
Started Jun 06 01:55:21 PM PDT 24
Finished Jun 06 01:55:26 PM PDT 24
Peak memory 214324 kb
Host smart-ca9887c7-9ba8-494a-96b1-c348f49f4467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384939664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3384939664
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2175449146
Short name T294
Test name
Test status
Simulation time 46083777 ps
CPU time 3.12 seconds
Started Jun 06 01:55:20 PM PDT 24
Finished Jun 06 01:55:24 PM PDT 24
Peak memory 221720 kb
Host smart-f69e8b39-e389-4a63-9272-8f03bb3ae931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175449146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2175449146
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2371766834
Short name T75
Test name
Test status
Simulation time 518799138 ps
CPU time 3.21 seconds
Started Jun 06 01:55:14 PM PDT 24
Finished Jun 06 01:55:18 PM PDT 24
Peak memory 209400 kb
Host smart-aa5c1873-6ea3-4eb0-950d-347f15091f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371766834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2371766834
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1447335760
Short name T289
Test name
Test status
Simulation time 1301091466 ps
CPU time 9.3 seconds
Started Jun 06 01:55:11 PM PDT 24
Finished Jun 06 01:55:22 PM PDT 24
Peak memory 209420 kb
Host smart-2bab74a7-1016-4e9a-99ae-1eedc005b433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447335760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1447335760
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2206236638
Short name T835
Test name
Test status
Simulation time 51486646 ps
CPU time 2.04 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:16 PM PDT 24
Peak memory 208424 kb
Host smart-33f8869f-c943-4130-91a5-5e26c0d9a41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206236638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2206236638
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3070879990
Short name T513
Test name
Test status
Simulation time 119136857 ps
CPU time 2.44 seconds
Started Jun 06 01:55:16 PM PDT 24
Finished Jun 06 01:55:19 PM PDT 24
Peak memory 207056 kb
Host smart-4c5a6f8f-f245-4899-8808-a98adea1da29
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070879990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3070879990
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2552169715
Short name T753
Test name
Test status
Simulation time 31456306 ps
CPU time 2.28 seconds
Started Jun 06 01:55:12 PM PDT 24
Finished Jun 06 01:55:15 PM PDT 24
Peak memory 208800 kb
Host smart-9a865cca-53dd-47db-a6aa-096ba7990565
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552169715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2552169715
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.837563961
Short name T322
Test name
Test status
Simulation time 78349673 ps
CPU time 3.58 seconds
Started Jun 06 01:55:20 PM PDT 24
Finished Jun 06 01:55:25 PM PDT 24
Peak memory 208888 kb
Host smart-5ffb5cdd-c749-4ea3-999f-4762e792d5dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837563961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.837563961
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3674935979
Short name T641
Test name
Test status
Simulation time 8692260109 ps
CPU time 34.67 seconds
Started Jun 06 01:55:12 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 218436 kb
Host smart-5e43f0c1-d22e-42a9-a84a-c37921186744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674935979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3674935979
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2186216013
Short name T475
Test name
Test status
Simulation time 3274041721 ps
CPU time 48.74 seconds
Started Jun 06 01:55:11 PM PDT 24
Finished Jun 06 01:56:01 PM PDT 24
Peak memory 208720 kb
Host smart-2b3722c9-12b3-469c-95ad-1ef837b6bd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186216013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2186216013
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3499095826
Short name T319
Test name
Test status
Simulation time 1968239013 ps
CPU time 19.31 seconds
Started Jun 06 01:55:30 PM PDT 24
Finished Jun 06 01:55:50 PM PDT 24
Peak memory 214908 kb
Host smart-93220dbd-953f-4ec8-9746-dca2469fdb79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499095826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3499095826
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2599076032
Short name T356
Test name
Test status
Simulation time 1071353969 ps
CPU time 12.02 seconds
Started Jun 06 01:55:19 PM PDT 24
Finished Jun 06 01:55:32 PM PDT 24
Peak memory 222612 kb
Host smart-7be36bdf-a85f-4618-bcdd-86680fa90fe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599076032 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2599076032
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2564288321
Short name T841
Test name
Test status
Simulation time 472468605 ps
CPU time 7.18 seconds
Started Jun 06 01:55:13 PM PDT 24
Finished Jun 06 01:55:22 PM PDT 24
Peak memory 207712 kb
Host smart-c01594c0-048a-47bd-a63a-22af431e0dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564288321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2564288321
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3564707617
Short name T532
Test name
Test status
Simulation time 100514680 ps
CPU time 2.81 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:36 PM PDT 24
Peak memory 209916 kb
Host smart-123d0550-1366-4888-be3c-4f313625683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564707617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3564707617
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.754658873
Short name T564
Test name
Test status
Simulation time 12166602 ps
CPU time 0.84 seconds
Started Jun 06 01:55:29 PM PDT 24
Finished Jun 06 01:55:31 PM PDT 24
Peak memory 205876 kb
Host smart-61a50c59-97b5-477d-8567-d2345d30ecbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754658873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.754658873
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3160941309
Short name T287
Test name
Test status
Simulation time 1646543812 ps
CPU time 7.86 seconds
Started Jun 06 01:55:22 PM PDT 24
Finished Jun 06 01:55:30 PM PDT 24
Peak memory 215164 kb
Host smart-38607da6-2754-477d-831b-6a02add6b498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3160941309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3160941309
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3943306103
Short name T326
Test name
Test status
Simulation time 30499247 ps
CPU time 2.04 seconds
Started Jun 06 01:55:18 PM PDT 24
Finished Jun 06 01:55:21 PM PDT 24
Peak memory 207224 kb
Host smart-a43c1866-90a6-41b8-b56f-d8b90142967f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943306103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3943306103
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3577078290
Short name T373
Test name
Test status
Simulation time 306115533 ps
CPU time 4.2 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:38 PM PDT 24
Peak memory 209312 kb
Host smart-52fc49f9-887b-4682-987c-4b93a465a1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577078290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3577078290
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3183930424
Short name T904
Test name
Test status
Simulation time 271898578 ps
CPU time 3.62 seconds
Started Jun 06 01:55:18 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 220940 kb
Host smart-febec913-143e-431a-9e28-53702a9d8f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183930424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3183930424
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.962764521
Short name T821
Test name
Test status
Simulation time 553864340 ps
CPU time 6.41 seconds
Started Jun 06 01:55:30 PM PDT 24
Finished Jun 06 01:55:37 PM PDT 24
Peak memory 209764 kb
Host smart-07b602de-e972-429d-a8fb-9d203c50b06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962764521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.962764521
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2405964201
Short name T652
Test name
Test status
Simulation time 164248017 ps
CPU time 6.08 seconds
Started Jun 06 01:55:15 PM PDT 24
Finished Jun 06 01:55:22 PM PDT 24
Peak memory 219288 kb
Host smart-4222b5a7-a28a-42b7-9592-4953e884ee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405964201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2405964201
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.762603014
Short name T12
Test name
Test status
Simulation time 189011521 ps
CPU time 2.76 seconds
Started Jun 06 01:55:19 PM PDT 24
Finished Jun 06 01:55:22 PM PDT 24
Peak memory 206116 kb
Host smart-464bfbd3-155d-4186-bd5d-0a771be71648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762603014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.762603014
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4250645310
Short name T526
Test name
Test status
Simulation time 702817286 ps
CPU time 22.37 seconds
Started Jun 06 01:55:10 PM PDT 24
Finished Jun 06 01:55:33 PM PDT 24
Peak memory 208764 kb
Host smart-c55bf188-43f1-4fdb-98d7-78c88add5ec5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250645310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4250645310
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2181102485
Short name T828
Test name
Test status
Simulation time 1850607822 ps
CPU time 22.16 seconds
Started Jun 06 01:55:18 PM PDT 24
Finished Jun 06 01:55:42 PM PDT 24
Peak memory 208764 kb
Host smart-868dcec0-594b-4820-8b5d-363681a62034
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181102485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2181102485
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1719038316
Short name T506
Test name
Test status
Simulation time 346478232 ps
CPU time 7.94 seconds
Started Jun 06 01:55:15 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 208832 kb
Host smart-0eea874b-6a87-4980-94c9-6a5b58e030ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719038316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1719038316
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.351739338
Short name T631
Test name
Test status
Simulation time 231408514 ps
CPU time 3.06 seconds
Started Jun 06 01:55:15 PM PDT 24
Finished Jun 06 01:55:19 PM PDT 24
Peak memory 208660 kb
Host smart-d53efb73-4ecf-4df7-a3b6-59b62f8ccf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351739338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.351739338
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1752171932
Short name T576
Test name
Test status
Simulation time 188652925 ps
CPU time 2.78 seconds
Started Jun 06 01:55:20 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 208304 kb
Host smart-64f1bbc3-8144-473c-b179-94e5506ff3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752171932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1752171932
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3882528489
Short name T404
Test name
Test status
Simulation time 1974565745 ps
CPU time 65.76 seconds
Started Jun 06 01:55:27 PM PDT 24
Finished Jun 06 01:56:33 PM PDT 24
Peak memory 221184 kb
Host smart-cec1aa18-d3f8-4c4e-99e4-dc924be427d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882528489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3882528489
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1924220530
Short name T191
Test name
Test status
Simulation time 658191510 ps
CPU time 12 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:44 PM PDT 24
Peak memory 219688 kb
Host smart-fdbb740c-bb84-4ad4-b992-62045aa168b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924220530 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1924220530
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2921432118
Short name T789
Test name
Test status
Simulation time 841024526 ps
CPU time 8.61 seconds
Started Jun 06 01:55:18 PM PDT 24
Finished Jun 06 01:55:28 PM PDT 24
Peak memory 218192 kb
Host smart-b7089d5c-a101-4bb8-862a-dd0417c84868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921432118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2921432118
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1130044299
Short name T567
Test name
Test status
Simulation time 159110017 ps
CPU time 1.54 seconds
Started Jun 06 01:55:35 PM PDT 24
Finished Jun 06 01:55:38 PM PDT 24
Peak memory 209976 kb
Host smart-f371fedb-4e44-4edd-af91-9991fec63812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130044299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1130044299
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2520882795
Short name T700
Test name
Test status
Simulation time 11446524 ps
CPU time 0.76 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:33 PM PDT 24
Peak memory 205936 kb
Host smart-a755c933-6553-4b0b-ae84-93a969df838b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520882795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2520882795
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.769228591
Short name T895
Test name
Test status
Simulation time 71956089 ps
CPU time 2.47 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 214312 kb
Host smart-aba38740-4f07-488c-b1f5-ebdc5a7954c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769228591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.769228591
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2015557315
Short name T15
Test name
Test status
Simulation time 636604073 ps
CPU time 6.91 seconds
Started Jun 06 01:55:29 PM PDT 24
Finished Jun 06 01:55:37 PM PDT 24
Peak memory 209180 kb
Host smart-bbf19f87-76c0-4373-8b3a-a828bd3e84fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015557315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2015557315
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.439121503
Short name T883
Test name
Test status
Simulation time 1080041496 ps
CPU time 3.83 seconds
Started Jun 06 01:55:30 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 218156 kb
Host smart-ac4bfed8-e935-4ef5-81b2-a1cf43496c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439121503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.439121503
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1686658206
Short name T689
Test name
Test status
Simulation time 1341934249 ps
CPU time 11.7 seconds
Started Jun 06 01:55:30 PM PDT 24
Finished Jun 06 01:55:43 PM PDT 24
Peak memory 209728 kb
Host smart-bfab2a30-58c1-4006-9b30-a0cd587bb303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686658206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1686658206
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3246628705
Short name T69
Test name
Test status
Simulation time 187156650 ps
CPU time 4.11 seconds
Started Jun 06 01:55:29 PM PDT 24
Finished Jun 06 01:55:34 PM PDT 24
Peak memory 220356 kb
Host smart-1df97315-9acb-450e-bbc0-3990f61d8830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246628705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3246628705
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2737872076
Short name T772
Test name
Test status
Simulation time 463871130 ps
CPU time 5.02 seconds
Started Jun 06 01:55:26 PM PDT 24
Finished Jun 06 01:55:31 PM PDT 24
Peak memory 210096 kb
Host smart-1fbac0db-726c-4896-8ad4-7ba8d3a758ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737872076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2737872076
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1503160562
Short name T805
Test name
Test status
Simulation time 99958326 ps
CPU time 3.15 seconds
Started Jun 06 01:55:31 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 208056 kb
Host smart-be745e3e-de4d-4cd6-aca3-149c7d1f03a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503160562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1503160562
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.683059771
Short name T903
Test name
Test status
Simulation time 398914621 ps
CPU time 3.54 seconds
Started Jun 06 01:55:22 PM PDT 24
Finished Jun 06 01:55:26 PM PDT 24
Peak memory 206916 kb
Host smart-a0063b8a-3066-4f00-931c-dd903227fec8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683059771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.683059771
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2601053199
Short name T920
Test name
Test status
Simulation time 141441530 ps
CPU time 2.95 seconds
Started Jun 06 01:55:31 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 208560 kb
Host smart-2706a844-c1a2-4cdd-a0b1-f48f24ae1c38
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601053199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2601053199
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3646982842
Short name T499
Test name
Test status
Simulation time 372166493 ps
CPU time 5.65 seconds
Started Jun 06 01:55:19 PM PDT 24
Finished Jun 06 01:55:26 PM PDT 24
Peak memory 208700 kb
Host smart-d5232d91-254d-4ea0-a213-97822f8b3132
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646982842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3646982842
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.176394823
Short name T611
Test name
Test status
Simulation time 111861386 ps
CPU time 3.01 seconds
Started Jun 06 01:55:21 PM PDT 24
Finished Jun 06 01:55:25 PM PDT 24
Peak memory 209820 kb
Host smart-eb9c3bfa-a6c7-4bc5-b2c6-2bb2df539f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176394823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.176394823
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.596589044
Short name T635
Test name
Test status
Simulation time 144224902 ps
CPU time 2.56 seconds
Started Jun 06 01:55:26 PM PDT 24
Finished Jun 06 01:55:29 PM PDT 24
Peak memory 208088 kb
Host smart-a3450f29-ae63-4b9a-8358-3c2118632888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596589044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.596589044
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.372371396
Short name T423
Test name
Test status
Simulation time 233472410 ps
CPU time 9.76 seconds
Started Jun 06 01:55:27 PM PDT 24
Finished Jun 06 01:55:37 PM PDT 24
Peak memory 218296 kb
Host smart-a552e4c3-e621-416f-99b2-49935fd17a55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372371396 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.372371396
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1640490792
Short name T823
Test name
Test status
Simulation time 729970853 ps
CPU time 5.94 seconds
Started Jun 06 01:55:31 PM PDT 24
Finished Jun 06 01:55:38 PM PDT 24
Peak memory 210200 kb
Host smart-bda0cfad-f652-48c8-b563-85c7f623874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640490792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1640490792
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1337590094
Short name T147
Test name
Test status
Simulation time 91491441 ps
CPU time 3.62 seconds
Started Jun 06 01:55:30 PM PDT 24
Finished Jun 06 01:55:34 PM PDT 24
Peak memory 210144 kb
Host smart-b3673ad2-a815-44dd-bdad-37de7d25b729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337590094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1337590094
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.426589832
Short name T801
Test name
Test status
Simulation time 44599220 ps
CPU time 0.76 seconds
Started Jun 06 01:55:18 PM PDT 24
Finished Jun 06 01:55:20 PM PDT 24
Peak memory 205900 kb
Host smart-611cea49-7a25-4ca4-a35b-56b05211ea47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426589832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.426589832
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1036085009
Short name T38
Test name
Test status
Simulation time 115758054 ps
CPU time 4.36 seconds
Started Jun 06 01:55:30 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 210260 kb
Host smart-b0cb4219-25ce-4b7d-a93d-71ab6b070377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036085009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1036085009
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.815914350
Short name T313
Test name
Test status
Simulation time 493842813 ps
CPU time 3.07 seconds
Started Jun 06 01:55:25 PM PDT 24
Finished Jun 06 01:55:28 PM PDT 24
Peak memory 210428 kb
Host smart-5313db57-d9ed-47c2-9030-1f533fec51a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815914350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.815914350
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3739791157
Short name T106
Test name
Test status
Simulation time 102169186 ps
CPU time 4.05 seconds
Started Jun 06 01:55:30 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 209164 kb
Host smart-8f4078ad-3709-46e1-ad46-b2d58b3e5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739791157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3739791157
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1319336941
Short name T118
Test name
Test status
Simulation time 130222861 ps
CPU time 2.11 seconds
Started Jun 06 01:55:28 PM PDT 24
Finished Jun 06 01:55:30 PM PDT 24
Peak memory 214308 kb
Host smart-61139328-38f9-4638-a251-4607f09260df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319336941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1319336941
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3115172431
Short name T387
Test name
Test status
Simulation time 58264764 ps
CPU time 3.68 seconds
Started Jun 06 01:55:33 PM PDT 24
Finished Jun 06 01:55:38 PM PDT 24
Peak memory 208552 kb
Host smart-9843d6f8-b1d3-4177-b406-3fe692f94905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115172431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3115172431
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1282337090
Short name T642
Test name
Test status
Simulation time 353201374 ps
CPU time 4.23 seconds
Started Jun 06 01:55:18 PM PDT 24
Finished Jun 06 01:55:24 PM PDT 24
Peak memory 208940 kb
Host smart-ca29893d-11b0-4c75-9f58-314728ee6b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282337090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1282337090
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.733050354
Short name T425
Test name
Test status
Simulation time 102421299 ps
CPU time 2.88 seconds
Started Jun 06 01:55:30 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 206720 kb
Host smart-000461d6-2cde-4ed1-954a-559d57d3a029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733050354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.733050354
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2152728015
Short name T814
Test name
Test status
Simulation time 38622267 ps
CPU time 2.31 seconds
Started Jun 06 01:55:19 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 206964 kb
Host smart-dd478398-21f1-4402-ad36-ebf4c6d00e40
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152728015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2152728015
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2467313747
Short name T725
Test name
Test status
Simulation time 40900034 ps
CPU time 2.7 seconds
Started Jun 06 01:55:31 PM PDT 24
Finished Jun 06 01:55:34 PM PDT 24
Peak memory 208764 kb
Host smart-2c404f07-0d1f-4cfb-bd66-823cf76629cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467313747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2467313747
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3699080942
Short name T599
Test name
Test status
Simulation time 345203316 ps
CPU time 4.94 seconds
Started Jun 06 01:55:26 PM PDT 24
Finished Jun 06 01:55:31 PM PDT 24
Peak memory 208656 kb
Host smart-48233e78-716e-4c21-8f7b-8cf5f2b489af
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699080942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3699080942
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.4229560213
Short name T691
Test name
Test status
Simulation time 865904831 ps
CPU time 2.67 seconds
Started Jun 06 01:55:20 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 207808 kb
Host smart-42cc4345-be6c-43fa-9119-c19bec6abc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229560213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.4229560213
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3428356396
Short name T628
Test name
Test status
Simulation time 181045719 ps
CPU time 3.77 seconds
Started Jun 06 01:55:28 PM PDT 24
Finished Jun 06 01:55:32 PM PDT 24
Peak memory 206776 kb
Host smart-84d0b3b3-6bef-41f2-8a55-113d5c5e2416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428356396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3428356396
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1694830501
Short name T323
Test name
Test status
Simulation time 2649183762 ps
CPU time 21.56 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:55 PM PDT 24
Peak memory 222608 kb
Host smart-c8be8876-0feb-4ce1-bc78-0d64832f3766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694830501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1694830501
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1712127815
Short name T134
Test name
Test status
Simulation time 3782854361 ps
CPU time 22.8 seconds
Started Jun 06 01:55:26 PM PDT 24
Finished Jun 06 01:55:50 PM PDT 24
Peak memory 223040 kb
Host smart-74cc661f-b538-4749-99fd-2a5077b2e4c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712127815 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1712127815
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.105060761
Short name T339
Test name
Test status
Simulation time 442619723 ps
CPU time 5.48 seconds
Started Jun 06 01:55:25 PM PDT 24
Finished Jun 06 01:55:31 PM PDT 24
Peak memory 209972 kb
Host smart-6248c89c-f239-4eb2-b01b-fe47390d97e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105060761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.105060761
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3761750235
Short name T688
Test name
Test status
Simulation time 182361371 ps
CPU time 1.74 seconds
Started Jun 06 01:55:21 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 210064 kb
Host smart-ae1f3405-6be4-4cdc-b6ef-fc38824a202a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761750235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3761750235
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3719941407
Short name T657
Test name
Test status
Simulation time 47145320 ps
CPU time 0.79 seconds
Started Jun 06 01:55:35 PM PDT 24
Finished Jun 06 01:55:37 PM PDT 24
Peak memory 205924 kb
Host smart-77685d6b-3c1c-477d-82df-215d9e3dd563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719941407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3719941407
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2331536058
Short name T439
Test name
Test status
Simulation time 47805631 ps
CPU time 3.44 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:36 PM PDT 24
Peak memory 215268 kb
Host smart-aa00d803-64bc-44a8-b690-ad0d97ab21fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331536058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2331536058
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2576815198
Short name T849
Test name
Test status
Simulation time 187577814 ps
CPU time 5.06 seconds
Started Jun 06 01:55:34 PM PDT 24
Finished Jun 06 01:55:40 PM PDT 24
Peak memory 220592 kb
Host smart-49353605-8861-4056-b343-bfb4f1e5a35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576815198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2576815198
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1489692461
Short name T71
Test name
Test status
Simulation time 381788447 ps
CPU time 3.19 seconds
Started Jun 06 01:55:36 PM PDT 24
Finished Jun 06 01:55:41 PM PDT 24
Peak memory 207524 kb
Host smart-ffcfa939-a910-4758-aaba-76708e662558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489692461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1489692461
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.443444610
Short name T115
Test name
Test status
Simulation time 1037785667 ps
CPU time 22.53 seconds
Started Jun 06 01:55:38 PM PDT 24
Finished Jun 06 01:56:02 PM PDT 24
Peak memory 214328 kb
Host smart-69e9d1c3-3c79-4dfa-af5b-347a22104987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443444610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.443444610
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.235369977
Short name T913
Test name
Test status
Simulation time 48955743 ps
CPU time 2.68 seconds
Started Jun 06 01:55:38 PM PDT 24
Finished Jun 06 01:55:42 PM PDT 24
Peak memory 214204 kb
Host smart-d65698a3-b45d-4ed0-8013-4096be78ed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235369977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.235369977
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_random.3611965866
Short name T770
Test name
Test status
Simulation time 227538551 ps
CPU time 4.97 seconds
Started Jun 06 01:55:34 PM PDT 24
Finished Jun 06 01:55:41 PM PDT 24
Peak memory 208920 kb
Host smart-a1a2b9ab-dbb4-4aa9-a328-5809d0b2b60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611965866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3611965866
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2350785596
Short name T838
Test name
Test status
Simulation time 313296977 ps
CPU time 4.01 seconds
Started Jun 06 01:55:34 PM PDT 24
Finished Jun 06 01:55:40 PM PDT 24
Peak memory 207012 kb
Host smart-f43dbe19-3b43-479f-b5be-56cd00d748d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350785596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2350785596
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1807375739
Short name T452
Test name
Test status
Simulation time 134892973 ps
CPU time 2.82 seconds
Started Jun 06 01:55:34 PM PDT 24
Finished Jun 06 01:55:38 PM PDT 24
Peak memory 206880 kb
Host smart-cc8fd4b1-02b8-440f-bfbe-e3abc18c3c1a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807375739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1807375739
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.793089135
Short name T811
Test name
Test status
Simulation time 383645951 ps
CPU time 5.55 seconds
Started Jun 06 01:55:38 PM PDT 24
Finished Jun 06 01:55:44 PM PDT 24
Peak memory 208528 kb
Host smart-aae1fa94-dc26-4976-8509-a8590cdcccf2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793089135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.793089135
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.655626605
Short name T525
Test name
Test status
Simulation time 1089657036 ps
CPU time 7.12 seconds
Started Jun 06 01:55:33 PM PDT 24
Finished Jun 06 01:55:42 PM PDT 24
Peak memory 208024 kb
Host smart-deccf135-f48e-437a-a6c1-58392aa30539
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655626605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.655626605
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2951345847
Short name T491
Test name
Test status
Simulation time 81849199 ps
CPU time 3.04 seconds
Started Jun 06 01:55:37 PM PDT 24
Finished Jun 06 01:55:42 PM PDT 24
Peak memory 214412 kb
Host smart-261a3acc-bdd2-4b3f-a620-047a8057a062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951345847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2951345847
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1150190157
Short name T588
Test name
Test status
Simulation time 128134117 ps
CPU time 3.21 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:37 PM PDT 24
Peak memory 208564 kb
Host smart-ad67ed2a-7c19-4174-92d1-d3cb23107385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150190157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1150190157
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.4144030192
Short name T573
Test name
Test status
Simulation time 1825532712 ps
CPU time 23.94 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:57 PM PDT 24
Peak memory 214796 kb
Host smart-f6707468-958b-4b41-aace-6a8e5492ad91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144030192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.4144030192
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.623274826
Short name T537
Test name
Test status
Simulation time 4299174955 ps
CPU time 28.78 seconds
Started Jun 06 01:55:30 PM PDT 24
Finished Jun 06 01:56:00 PM PDT 24
Peak memory 209600 kb
Host smart-b6c54db5-37b0-49c9-8356-d260c96dd05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623274826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.623274826
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.595267499
Short name T752
Test name
Test status
Simulation time 109316743 ps
CPU time 1.67 seconds
Started Jun 06 01:55:33 PM PDT 24
Finished Jun 06 01:55:36 PM PDT 24
Peak memory 210024 kb
Host smart-bfaa192f-d743-4aea-8978-d9c27d58a6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595267499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.595267499
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2028393697
Short name T844
Test name
Test status
Simulation time 84333448 ps
CPU time 0.92 seconds
Started Jun 06 01:55:33 PM PDT 24
Finished Jun 06 01:55:36 PM PDT 24
Peak memory 206080 kb
Host smart-9711a0b2-e526-4fc1-a680-8597013880e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028393697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2028393697
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2039800769
Short name T260
Test name
Test status
Simulation time 1246639296 ps
CPU time 4.97 seconds
Started Jun 06 01:55:34 PM PDT 24
Finished Jun 06 01:55:40 PM PDT 24
Peak memory 209848 kb
Host smart-2983fc16-d631-43f1-a174-0dc343cfcb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039800769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2039800769
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3573845615
Short name T388
Test name
Test status
Simulation time 428683663 ps
CPU time 5.22 seconds
Started Jun 06 01:55:39 PM PDT 24
Finished Jun 06 01:55:45 PM PDT 24
Peak memory 207228 kb
Host smart-9e9e5bab-80ec-455d-92e2-9b0c6f57ab51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573845615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3573845615
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1501017181
Short name T778
Test name
Test status
Simulation time 75691153 ps
CPU time 2.63 seconds
Started Jun 06 01:55:35 PM PDT 24
Finished Jun 06 01:55:39 PM PDT 24
Peak memory 214312 kb
Host smart-9d0c2857-ab48-4b15-8739-a5a27d9f27c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501017181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1501017181
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3616794405
Short name T754
Test name
Test status
Simulation time 1289403409 ps
CPU time 4.25 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:37 PM PDT 24
Peak memory 214248 kb
Host smart-084b1bc3-be77-4eb7-8efa-3f56850b8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616794405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3616794405
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2131295675
Short name T396
Test name
Test status
Simulation time 111712743 ps
CPU time 3.59 seconds
Started Jun 06 01:55:35 PM PDT 24
Finished Jun 06 01:55:39 PM PDT 24
Peak memory 208148 kb
Host smart-d59daa93-1e48-466e-a1ad-4d79726f2875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131295675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2131295675
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1311191808
Short name T411
Test name
Test status
Simulation time 207676566 ps
CPU time 7.27 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:41 PM PDT 24
Peak memory 207052 kb
Host smart-55809e43-8cd3-47ea-9bf2-e5daac3fe66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311191808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1311191808
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.98737394
Short name T786
Test name
Test status
Simulation time 270166122 ps
CPU time 3.96 seconds
Started Jun 06 01:55:38 PM PDT 24
Finished Jun 06 01:55:43 PM PDT 24
Peak memory 206892 kb
Host smart-30b1e998-0216-470c-a535-2106d02e6af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98737394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.98737394
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2232800327
Short name T421
Test name
Test status
Simulation time 426935836 ps
CPU time 3.5 seconds
Started Jun 06 01:55:37 PM PDT 24
Finished Jun 06 01:55:42 PM PDT 24
Peak memory 207848 kb
Host smart-693bfed7-a5f3-4e56-920e-6e3d79670905
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232800327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2232800327
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1529283160
Short name T795
Test name
Test status
Simulation time 125968692 ps
CPU time 4.49 seconds
Started Jun 06 01:55:38 PM PDT 24
Finished Jun 06 01:55:43 PM PDT 24
Peak memory 208088 kb
Host smart-1abfeb37-edc7-44e3-a09a-a2ec5290ac95
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529283160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1529283160
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.469106946
Short name T764
Test name
Test status
Simulation time 158574946 ps
CPU time 3.71 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:37 PM PDT 24
Peak memory 206836 kb
Host smart-d2e63115-5879-48b3-8d42-e8a7d4277d6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469106946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.469106946
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1810785212
Short name T311
Test name
Test status
Simulation time 83498811 ps
CPU time 3.69 seconds
Started Jun 06 01:55:35 PM PDT 24
Finished Jun 06 01:55:40 PM PDT 24
Peak memory 220224 kb
Host smart-47bbb373-7368-4bf0-a075-1b828781e349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810785212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1810785212
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.370270915
Short name T679
Test name
Test status
Simulation time 69824752 ps
CPU time 2.84 seconds
Started Jun 06 01:55:33 PM PDT 24
Finished Jun 06 01:55:36 PM PDT 24
Peak memory 208620 kb
Host smart-85e2e96f-e5b4-4e53-bd58-050d7d9b0802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370270915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.370270915
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.390915273
Short name T624
Test name
Test status
Simulation time 1205612206 ps
CPU time 11.21 seconds
Started Jun 06 01:55:35 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 216868 kb
Host smart-02d98aea-4b10-4801-a5e7-a36133e4929d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390915273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.390915273
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.64588815
Short name T655
Test name
Test status
Simulation time 175666557 ps
CPU time 3.39 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:37 PM PDT 24
Peak memory 207532 kb
Host smart-880d932b-5fe7-4c83-b8f2-b316cd326e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64588815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.64588815
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3299427809
Short name T797
Test name
Test status
Simulation time 122045757 ps
CPU time 1.86 seconds
Started Jun 06 01:55:33 PM PDT 24
Finished Jun 06 01:55:36 PM PDT 24
Peak memory 214400 kb
Host smart-fbe8cac9-a533-4a5c-8ec2-4adc9ff12435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299427809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3299427809
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2426726392
Short name T111
Test name
Test status
Simulation time 13531791 ps
CPU time 0.97 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 206120 kb
Host smart-4c68e4cc-dd42-4779-abc6-2492894f3b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426726392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2426726392
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.4270199413
Short name T32
Test name
Test status
Simulation time 82632939 ps
CPU time 3.72 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 209376 kb
Host smart-50dbd879-913f-4bba-88da-0e795d2ad612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270199413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.4270199413
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3485199115
Short name T357
Test name
Test status
Simulation time 79880809 ps
CPU time 3.27 seconds
Started Jun 06 01:55:49 PM PDT 24
Finished Jun 06 01:55:53 PM PDT 24
Peak memory 208296 kb
Host smart-18eb4091-910e-44bb-9294-5695a0a7da9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485199115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3485199115
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3945585856
Short name T919
Test name
Test status
Simulation time 55011713 ps
CPU time 1.9 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 214436 kb
Host smart-50ef5049-d993-403a-88f7-a55cbad37405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945585856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3945585856
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3327735067
Short name T367
Test name
Test status
Simulation time 55512685 ps
CPU time 2.18 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 214228 kb
Host smart-e400450c-0924-491a-ab2f-42cb0fc24998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327735067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3327735067
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.830461816
Short name T148
Test name
Test status
Simulation time 345653211 ps
CPU time 4.11 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 206524 kb
Host smart-6b4e8e34-d9f2-44ca-8667-86d595d6c6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830461816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.830461816
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3896449061
Short name T362
Test name
Test status
Simulation time 325855087 ps
CPU time 4.6 seconds
Started Jun 06 01:55:41 PM PDT 24
Finished Jun 06 01:55:46 PM PDT 24
Peak memory 214300 kb
Host smart-bc5ade7d-d320-4642-81a1-704354843d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896449061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3896449061
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2007298300
Short name T544
Test name
Test status
Simulation time 1136443930 ps
CPU time 12.08 seconds
Started Jun 06 01:55:34 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 208708 kb
Host smart-e77e7a72-e3d0-4f24-a09e-ec2808128ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007298300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2007298300
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3550379522
Short name T749
Test name
Test status
Simulation time 68730885 ps
CPU time 1.8 seconds
Started Jun 06 01:55:32 PM PDT 24
Finished Jun 06 01:55:35 PM PDT 24
Peak memory 207040 kb
Host smart-af1decc2-9b17-4415-ad62-6feb3781b855
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550379522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3550379522
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1647923776
Short name T804
Test name
Test status
Simulation time 567440886 ps
CPU time 3.27 seconds
Started Jun 06 01:55:37 PM PDT 24
Finished Jun 06 01:55:42 PM PDT 24
Peak memory 206708 kb
Host smart-75566ce0-fae6-4c53-8a66-37522c989981
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647923776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1647923776
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.4263542049
Short name T606
Test name
Test status
Simulation time 369990334 ps
CPU time 3.23 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 208668 kb
Host smart-3087f960-5cbe-4107-aa27-c2804262726a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263542049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4263542049
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1042133211
Short name T706
Test name
Test status
Simulation time 181529661 ps
CPU time 2.28 seconds
Started Jun 06 01:55:40 PM PDT 24
Finished Jun 06 01:55:44 PM PDT 24
Peak memory 207624 kb
Host smart-491a6769-3360-4c5e-b830-0a90652067f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042133211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1042133211
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1703297533
Short name T727
Test name
Test status
Simulation time 126323615 ps
CPU time 4.35 seconds
Started Jun 06 01:55:35 PM PDT 24
Finished Jun 06 01:55:41 PM PDT 24
Peak memory 206628 kb
Host smart-98733763-7e90-4610-b513-060d383ab788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703297533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1703297533
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.631239317
Short name T26
Test name
Test status
Simulation time 109772996 ps
CPU time 4.86 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 214452 kb
Host smart-ddb3644a-13bf-4175-984e-713df938910e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631239317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.631239317
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2473759922
Short name T72
Test name
Test status
Simulation time 391479027 ps
CPU time 2.8 seconds
Started Jun 06 01:55:49 PM PDT 24
Finished Jun 06 01:55:53 PM PDT 24
Peak memory 209840 kb
Host smart-20174e75-18aa-4627-b7bc-75693cb24176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473759922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2473759922
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1694130607
Short name T474
Test name
Test status
Simulation time 34925645 ps
CPU time 0.81 seconds
Started Jun 06 01:55:42 PM PDT 24
Finished Jun 06 01:55:43 PM PDT 24
Peak memory 205876 kb
Host smart-8a3c54d8-7e8b-4988-960c-66b5c5c9a641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694130607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1694130607
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1503394031
Short name T429
Test name
Test status
Simulation time 142008589 ps
CPU time 7.75 seconds
Started Jun 06 01:55:40 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 216008 kb
Host smart-db3fa363-d4e7-4878-adee-6efe530ae68a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503394031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1503394031
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1822279224
Short name T31
Test name
Test status
Simulation time 5998589561 ps
CPU time 14.39 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:56:02 PM PDT 24
Peak memory 214664 kb
Host smart-54189316-1dec-459a-9f29-bd2eca984540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822279224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1822279224
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1794064855
Short name T734
Test name
Test status
Simulation time 194503915 ps
CPU time 2.61 seconds
Started Jun 06 01:55:44 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 214384 kb
Host smart-8570c95f-9824-40bf-b651-0efea97a2442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794064855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1794064855
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.816606869
Short name T766
Test name
Test status
Simulation time 130691245 ps
CPU time 2.78 seconds
Started Jun 06 01:55:40 PM PDT 24
Finished Jun 06 01:55:44 PM PDT 24
Peak memory 215476 kb
Host smart-4522d36c-8bfd-4123-9e00-6ca925e881ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816606869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.816606869
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1727429260
Short name T152
Test name
Test status
Simulation time 161070887 ps
CPU time 4.15 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:50 PM PDT 24
Peak memory 215616 kb
Host smart-526d5997-aac2-4ea9-8db5-7af0bf9a2adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727429260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1727429260
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1813716291
Short name T682
Test name
Test status
Simulation time 77197299 ps
CPU time 3.79 seconds
Started Jun 06 01:55:42 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 214264 kb
Host smart-f2e48556-da20-4817-b0c5-84d30c67280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813716291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1813716291
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.471792222
Short name T862
Test name
Test status
Simulation time 259463800 ps
CPU time 2.75 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 208380 kb
Host smart-2a3d49a6-fe1c-4eac-bcf1-0531988a71d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471792222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.471792222
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.926723663
Short name T646
Test name
Test status
Simulation time 71478224 ps
CPU time 3.27 seconds
Started Jun 06 01:55:44 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 208296 kb
Host smart-f1eaf3e2-3614-46d8-92bf-ca78c7d396c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926723663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.926723663
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.736969388
Short name T200
Test name
Test status
Simulation time 76664935 ps
CPU time 2.59 seconds
Started Jun 06 01:55:48 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 207296 kb
Host smart-578fc152-a7d3-4d5d-a9fc-7d7a0f61ad9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736969388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.736969388
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3277484528
Short name T426
Test name
Test status
Simulation time 1737987422 ps
CPU time 24.59 seconds
Started Jun 06 01:55:41 PM PDT 24
Finished Jun 06 01:56:07 PM PDT 24
Peak memory 208656 kb
Host smart-4c1c4ec8-99e7-46b1-b48c-e0ec4df66897
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277484528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3277484528
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3325495098
Short name T520
Test name
Test status
Simulation time 98078297 ps
CPU time 3.98 seconds
Started Jun 06 01:55:41 PM PDT 24
Finished Jun 06 01:55:46 PM PDT 24
Peak memory 209008 kb
Host smart-33565b5b-8f14-4b30-bb2f-d7c5f5ab2a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325495098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3325495098
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1464934936
Short name T737
Test name
Test status
Simulation time 62856258 ps
CPU time 2.43 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 206784 kb
Host smart-47985771-56d9-48ed-b24d-74b3ffc718a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464934936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1464934936
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1281727233
Short name T252
Test name
Test status
Simulation time 7194917932 ps
CPU time 58.69 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:56:45 PM PDT 24
Peak memory 222612 kb
Host smart-f4cea335-90f4-4c32-88ac-8853d4af0e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281727233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1281727233
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1233698465
Short name T88
Test name
Test status
Simulation time 321122542 ps
CPU time 11.1 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:56 PM PDT 24
Peak memory 222532 kb
Host smart-c40aeb3e-8f47-45c0-b369-372f9bbb85fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233698465 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1233698465
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.197375004
Short name T498
Test name
Test status
Simulation time 2501915003 ps
CPU time 17.56 seconds
Started Jun 06 01:55:44 PM PDT 24
Finished Jun 06 01:56:03 PM PDT 24
Peak memory 209336 kb
Host smart-6d3adfbc-6d63-41db-b4e9-8b8f2a5b52c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197375004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.197375004
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3854398043
Short name T825
Test name
Test status
Simulation time 411493174 ps
CPU time 2.25 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:55:50 PM PDT 24
Peak memory 210180 kb
Host smart-98e98a36-fa25-45a6-a9d5-800f3c9131e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854398043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3854398043
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1893011794
Short name T850
Test name
Test status
Simulation time 55802351 ps
CPU time 0.83 seconds
Started Jun 06 01:55:42 PM PDT 24
Finished Jun 06 01:55:43 PM PDT 24
Peak memory 205936 kb
Host smart-42c4c9e2-dc12-4a52-8610-34276b082eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893011794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1893011794
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.400193427
Short name T438
Test name
Test status
Simulation time 563507856 ps
CPU time 8.49 seconds
Started Jun 06 01:55:44 PM PDT 24
Finished Jun 06 01:55:54 PM PDT 24
Peak memory 215864 kb
Host smart-38e4bd73-2936-4840-ae57-086d66111572
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400193427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.400193427
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.840270724
Short name T500
Test name
Test status
Simulation time 128719601 ps
CPU time 2.4 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 217980 kb
Host smart-f08b0338-399b-4fe5-a16f-d1d022a799e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840270724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.840270724
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2028971730
Short name T389
Test name
Test status
Simulation time 1236355981 ps
CPU time 36.87 seconds
Started Jun 06 01:55:42 PM PDT 24
Finished Jun 06 01:56:21 PM PDT 24
Peak memory 219692 kb
Host smart-8ba059fe-398e-4454-9950-49f673db33ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028971730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2028971730
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2316410233
Short name T295
Test name
Test status
Simulation time 53305460 ps
CPU time 2.88 seconds
Started Jun 06 01:55:40 PM PDT 24
Finished Jun 06 01:55:44 PM PDT 24
Peak memory 222340 kb
Host smart-ec9f8f0f-ea4f-4cfb-990a-9ea9f3489283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316410233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2316410233
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.659973866
Short name T867
Test name
Test status
Simulation time 99829162 ps
CPU time 3.58 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 215404 kb
Host smart-67a6239a-e64c-4b8b-8ba0-78b26b3c29ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659973866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.659973866
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3933031841
Short name T908
Test name
Test status
Simulation time 350643287 ps
CPU time 7.97 seconds
Started Jun 06 01:55:42 PM PDT 24
Finished Jun 06 01:55:50 PM PDT 24
Peak memory 214424 kb
Host smart-b3a9bf7c-4273-477e-81c2-c3a09fb803d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933031841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3933031841
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.197099829
Short name T614
Test name
Test status
Simulation time 67288434 ps
CPU time 2.75 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 208268 kb
Host smart-21a6cd15-a21f-4239-8546-ef13a6d35598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197099829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.197099829
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2004947062
Short name T89
Test name
Test status
Simulation time 124819557 ps
CPU time 4.77 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 208028 kb
Host smart-ff1abe27-9d7f-4bd7-b5bd-31f64b01a8a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004947062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2004947062
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4048979805
Short name T875
Test name
Test status
Simulation time 125236916 ps
CPU time 2.4 seconds
Started Jun 06 01:55:39 PM PDT 24
Finished Jun 06 01:55:43 PM PDT 24
Peak memory 207024 kb
Host smart-79d3dbff-e90d-40e7-aae2-e9a800546234
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048979805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4048979805
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.670245371
Short name T746
Test name
Test status
Simulation time 328278287 ps
CPU time 2.76 seconds
Started Jun 06 01:55:42 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 208292 kb
Host smart-83e5a184-4012-4532-af9f-486d951681bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670245371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.670245371
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3792526209
Short name T375
Test name
Test status
Simulation time 571598932 ps
CPU time 6.61 seconds
Started Jun 06 01:55:41 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 209680 kb
Host smart-acf1117c-7941-4393-b280-f252e855b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792526209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3792526209
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.4008032785
Short name T799
Test name
Test status
Simulation time 88169857 ps
CPU time 2.21 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 206868 kb
Host smart-b6a3e9c1-4c8d-4915-b2d8-1724093d8f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008032785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.4008032785
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4196559954
Short name T701
Test name
Test status
Simulation time 1702594990 ps
CPU time 5.75 seconds
Started Jun 06 01:55:42 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 215172 kb
Host smart-2a7844df-baa2-4e40-8811-0dff1e12cad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196559954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4196559954
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1932990303
Short name T827
Test name
Test status
Simulation time 903785533 ps
CPU time 10.18 seconds
Started Jun 06 01:55:41 PM PDT 24
Finished Jun 06 01:55:53 PM PDT 24
Peak memory 222576 kb
Host smart-6e7b9338-aaa5-4ca1-a5a2-d9fe9b89ba6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932990303 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1932990303
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2262256566
Short name T393
Test name
Test status
Simulation time 213591845 ps
CPU time 4.8 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:55:56 PM PDT 24
Peak memory 214364 kb
Host smart-f9310b95-7b44-4cdb-b078-e56492b119bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262256566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2262256566
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.334545340
Short name T917
Test name
Test status
Simulation time 106195651 ps
CPU time 3.51 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 209960 kb
Host smart-bfd9bbec-ab60-4049-ae50-779aedfc3e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334545340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.334545340
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3224652748
Short name T672
Test name
Test status
Simulation time 17614861 ps
CPU time 0.7 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:45 PM PDT 24
Peak memory 205968 kb
Host smart-8633cd4b-dfbd-444f-a3c5-2c31036eebca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224652748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3224652748
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2129805917
Short name T625
Test name
Test status
Simulation time 255051273 ps
CPU time 3.15 seconds
Started Jun 06 01:55:39 PM PDT 24
Finished Jun 06 01:55:44 PM PDT 24
Peak memory 209128 kb
Host smart-9a225729-9385-4226-84ce-6ee5c891dba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129805917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2129805917
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.764636667
Short name T710
Test name
Test status
Simulation time 46041262 ps
CPU time 2.77 seconds
Started Jun 06 01:55:44 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 208688 kb
Host smart-e931c96f-b33c-426e-a64b-368bbf92cc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764636667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.764636667
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2807295842
Short name T876
Test name
Test status
Simulation time 134314599 ps
CPU time 3.32 seconds
Started Jun 06 01:55:47 PM PDT 24
Finished Jun 06 01:55:51 PM PDT 24
Peak memory 214332 kb
Host smart-1c716f1d-bb54-451e-a9a2-6c42851f98ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807295842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2807295842
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1079634169
Short name T51
Test name
Test status
Simulation time 163067692 ps
CPU time 2.92 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 214460 kb
Host smart-81e46c0c-150e-4cb0-9dc9-891a79b72830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079634169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1079634169
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3146880905
Short name T253
Test name
Test status
Simulation time 43847175 ps
CPU time 2.76 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 214296 kb
Host smart-7f6e960d-bad7-4cd1-90ed-536ab06ee5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146880905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3146880905
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3910998045
Short name T680
Test name
Test status
Simulation time 38639664 ps
CPU time 2.59 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:55:55 PM PDT 24
Peak memory 209764 kb
Host smart-1dc0a619-44fe-44d5-a1e0-040f245aa9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910998045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3910998045
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4174659281
Short name T462
Test name
Test status
Simulation time 743890459 ps
CPU time 5.66 seconds
Started Jun 06 01:55:42 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 208128 kb
Host smart-fc7e5c50-6375-4e03-80d2-6f002750a066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174659281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4174659281
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2204326280
Short name T483
Test name
Test status
Simulation time 60905407 ps
CPU time 3.21 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 206948 kb
Host smart-031d67cd-05f0-4bd2-84d6-05a5a0ffde37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204326280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2204326280
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.726579017
Short name T402
Test name
Test status
Simulation time 107459709 ps
CPU time 2.3 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 207060 kb
Host smart-2681524f-158e-4128-8d60-d3cc581b54f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726579017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.726579017
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.607269322
Short name T678
Test name
Test status
Simulation time 278955541 ps
CPU time 3.4 seconds
Started Jun 06 01:55:41 PM PDT 24
Finished Jun 06 01:55:46 PM PDT 24
Peak memory 208660 kb
Host smart-fe8091da-1b33-4790-a5f8-82461cc80493
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607269322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.607269322
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2844449791
Short name T478
Test name
Test status
Simulation time 236032932 ps
CPU time 3.05 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:55:50 PM PDT 24
Peak memory 209236 kb
Host smart-e8d585cb-9b6f-4003-92c0-395823e76f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844449791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2844449791
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.538860743
Short name T593
Test name
Test status
Simulation time 1209372165 ps
CPU time 10.77 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:57 PM PDT 24
Peak memory 207896 kb
Host smart-5c37815d-69be-42d9-ad37-bb913c25c922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538860743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.538860743
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.755112194
Short name T210
Test name
Test status
Simulation time 3717332063 ps
CPU time 26.52 seconds
Started Jun 06 01:55:43 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 215016 kb
Host smart-8d23911e-e675-4b43-b38d-77f721ab1105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755112194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.755112194
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1261167330
Short name T133
Test name
Test status
Simulation time 1199933940 ps
CPU time 12.98 seconds
Started Jun 06 01:55:41 PM PDT 24
Finished Jun 06 01:55:55 PM PDT 24
Peak memory 220636 kb
Host smart-30d5ef4c-c6af-47ce-8a18-d3117715a5cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261167330 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1261167330
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3809355506
Short name T810
Test name
Test status
Simulation time 83161143 ps
CPU time 3.2 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:50 PM PDT 24
Peak memory 208228 kb
Host smart-cdb2a172-b8a9-4c9b-8bfa-0f0cba03c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809355506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3809355506
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1225535127
Short name T542
Test name
Test status
Simulation time 8462132 ps
CPU time 0.85 seconds
Started Jun 06 01:54:04 PM PDT 24
Finished Jun 06 01:54:06 PM PDT 24
Peak memory 205948 kb
Host smart-b35df5de-7707-4054-b0a6-0fc90be6a393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225535127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1225535127
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3605682218
Short name T354
Test name
Test status
Simulation time 1266516520 ps
CPU time 67.25 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:55:16 PM PDT 24
Peak memory 215944 kb
Host smart-69548f6f-b46b-4ff5-8a24-6e5cc32c449b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605682218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3605682218
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3496353828
Short name T748
Test name
Test status
Simulation time 276621621 ps
CPU time 7.75 seconds
Started Jun 06 01:54:02 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 208556 kb
Host smart-05c4a82b-a022-4f99-b27b-a764539229d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496353828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3496353828
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2146054274
Short name T485
Test name
Test status
Simulation time 947603500 ps
CPU time 10.65 seconds
Started Jun 06 01:54:04 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 214360 kb
Host smart-b2a09242-22a5-485c-93e0-3248ae8a790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146054274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2146054274
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3145512216
Short name T67
Test name
Test status
Simulation time 666783396 ps
CPU time 4.52 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 220556 kb
Host smart-b658155e-8403-4eba-a749-33d8cca71116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145512216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3145512216
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2905852118
Short name T46
Test name
Test status
Simulation time 324119698 ps
CPU time 3.75 seconds
Started Jun 06 01:54:05 PM PDT 24
Finished Jun 06 01:54:10 PM PDT 24
Peak memory 209196 kb
Host smart-95511c3f-1446-4a01-9a70-4a948ba431c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905852118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2905852118
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3649383055
Short name T90
Test name
Test status
Simulation time 3335298476 ps
CPU time 21.11 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:31 PM PDT 24
Peak memory 208820 kb
Host smart-a92ec5d7-3b2d-44c1-b611-a840bc4a9793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649383055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3649383055
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3885732609
Short name T10
Test name
Test status
Simulation time 1542019616 ps
CPU time 11.36 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:21 PM PDT 24
Peak memory 229460 kb
Host smart-e6418c9a-d5a2-460b-a829-4faca89c26f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885732609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3885732609
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.468947730
Short name T501
Test name
Test status
Simulation time 7607701369 ps
CPU time 12.62 seconds
Started Jun 06 01:54:04 PM PDT 24
Finished Jun 06 01:54:18 PM PDT 24
Peak memory 208060 kb
Host smart-5b0fbd86-0586-4924-9a29-8195338cdc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468947730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.468947730
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2203892357
Short name T447
Test name
Test status
Simulation time 106223377 ps
CPU time 2.5 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 209144 kb
Host smart-4ef30db0-c61a-4f3a-b0d6-c59516cda592
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203892357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2203892357
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2583230430
Short name T557
Test name
Test status
Simulation time 529235840 ps
CPU time 4.56 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 209076 kb
Host smart-6faaf2cb-7807-4c84-b8aa-e8834cc49e3b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583230430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2583230430
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4229233612
Short name T234
Test name
Test status
Simulation time 194572895 ps
CPU time 6.14 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 208556 kb
Host smart-6c1541e9-56eb-4ca0-bf18-0ce573adfbe4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229233612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4229233612
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.920432106
Short name T775
Test name
Test status
Simulation time 103503132 ps
CPU time 2.57 seconds
Started Jun 06 01:54:11 PM PDT 24
Finished Jun 06 01:54:15 PM PDT 24
Peak memory 215820 kb
Host smart-f50142dd-c87f-4712-9782-9e09369b2ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920432106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.920432106
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2509216152
Short name T741
Test name
Test status
Simulation time 988300667 ps
CPU time 4.74 seconds
Started Jun 06 01:54:04 PM PDT 24
Finished Jun 06 01:54:10 PM PDT 24
Peak memory 208084 kb
Host smart-49092be7-df1e-46fb-8045-b7b4584e7f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509216152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2509216152
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.801063203
Short name T722
Test name
Test status
Simulation time 4783478906 ps
CPU time 13.73 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:54:22 PM PDT 24
Peak memory 217164 kb
Host smart-a21e08cd-cf6e-4b31-a344-3a9e937a5096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801063203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.801063203
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.701321824
Short name T915
Test name
Test status
Simulation time 763105267 ps
CPU time 20.63 seconds
Started Jun 06 01:54:05 PM PDT 24
Finished Jun 06 01:54:27 PM PDT 24
Peak memory 207968 kb
Host smart-9cd62c49-9f5f-4984-bc5c-40a1858068e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701321824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.701321824
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3003181409
Short name T34
Test name
Test status
Simulation time 57221088 ps
CPU time 2.04 seconds
Started Jun 06 01:54:04 PM PDT 24
Finished Jun 06 01:54:08 PM PDT 24
Peak memory 210036 kb
Host smart-9f40828a-7c73-440e-ae26-eed31cba1dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003181409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3003181409
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2983989768
Short name T518
Test name
Test status
Simulation time 29913970 ps
CPU time 0.77 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 205932 kb
Host smart-9d566dd0-af58-4d32-b623-9ee22ffa9f39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983989768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2983989768
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.851378449
Short name T840
Test name
Test status
Simulation time 372515988 ps
CPU time 2.65 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 208916 kb
Host smart-1a4b9db3-b6bd-4c93-80ea-dc16a95c6794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851378449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.851378449
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.177089760
Short name T902
Test name
Test status
Simulation time 818696701 ps
CPU time 4.03 seconds
Started Jun 06 01:55:48 PM PDT 24
Finished Jun 06 01:55:53 PM PDT 24
Peak memory 219584 kb
Host smart-a90f0e65-8e80-4c8e-8332-88bd775556d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177089760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.177089760
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.303082787
Short name T108
Test name
Test status
Simulation time 99316466 ps
CPU time 4.35 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 208684 kb
Host smart-8fd0d056-20fb-4e04-b4e4-655d61f12521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303082787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.303082787
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.923687237
Short name T65
Test name
Test status
Simulation time 565674141 ps
CPU time 4.5 seconds
Started Jun 06 01:55:47 PM PDT 24
Finished Jun 06 01:55:53 PM PDT 24
Peak memory 221044 kb
Host smart-54b38a8c-c03c-4194-9a76-d1d2db046ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923687237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.923687237
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.350549534
Short name T584
Test name
Test status
Simulation time 162459887 ps
CPU time 3.34 seconds
Started Jun 06 01:55:48 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 214332 kb
Host smart-15a67d1a-ff53-4c0a-bbe1-799b693334ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350549534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.350549534
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.980407951
Short name T380
Test name
Test status
Simulation time 2841388941 ps
CPU time 20.16 seconds
Started Jun 06 01:55:53 PM PDT 24
Finished Jun 06 01:56:14 PM PDT 24
Peak memory 214292 kb
Host smart-886fec92-1a2f-4367-85b7-5fd4134800a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980407951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.980407951
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.987601094
Short name T232
Test name
Test status
Simulation time 219508901 ps
CPU time 2.91 seconds
Started Jun 06 01:55:44 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 206888 kb
Host smart-27f63f0c-da20-49cf-8794-6cf6a7847b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987601094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.987601094
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.379940437
Short name T744
Test name
Test status
Simulation time 520243141 ps
CPU time 4.19 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 206980 kb
Host smart-f7ebfef2-f203-489b-b3dd-52bdec253a77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379940437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.379940437
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2674805272
Short name T879
Test name
Test status
Simulation time 2237174426 ps
CPU time 22.99 seconds
Started Jun 06 01:55:47 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 208488 kb
Host smart-417d46a5-9d76-4ec8-a523-b4a2a62bceb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674805272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2674805272
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.294464272
Short name T648
Test name
Test status
Simulation time 101484423 ps
CPU time 2.72 seconds
Started Jun 06 01:55:42 PM PDT 24
Finished Jun 06 01:55:46 PM PDT 24
Peak memory 207180 kb
Host smart-1a84294c-876c-420e-9e38-f91eb436815d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294464272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.294464272
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1111136450
Short name T556
Test name
Test status
Simulation time 54286426 ps
CPU time 2.06 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:55:53 PM PDT 24
Peak memory 209768 kb
Host smart-5ed8760c-aaa3-433a-b680-9738b653b6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111136450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1111136450
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.630484594
Short name T571
Test name
Test status
Simulation time 248275294 ps
CPU time 2.43 seconds
Started Jun 06 01:55:44 PM PDT 24
Finished Jun 06 01:55:48 PM PDT 24
Peak memory 206784 kb
Host smart-f0c38c5f-00f9-4af0-b309-46e86a609860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630484594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.630484594
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2129579489
Short name T839
Test name
Test status
Simulation time 153950554 ps
CPU time 2.85 seconds
Started Jun 06 01:55:48 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 208052 kb
Host smart-0740bafc-41d9-4552-b551-c08be035c233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129579489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2129579489
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.381111978
Short name T490
Test name
Test status
Simulation time 441109998 ps
CPU time 1.45 seconds
Started Jun 06 01:55:48 PM PDT 24
Finished Jun 06 01:55:51 PM PDT 24
Peak memory 210020 kb
Host smart-50251d90-f5f2-4104-8743-38d349d39b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381111978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.381111978
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.949859031
Short name T726
Test name
Test status
Simulation time 28327451 ps
CPU time 0.77 seconds
Started Jun 06 01:55:47 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 205920 kb
Host smart-d96e3c91-ed42-4e8d-877e-58664333f326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949859031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.949859031
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2964069867
Short name T151
Test name
Test status
Simulation time 1069956020 ps
CPU time 14.24 seconds
Started Jun 06 01:55:55 PM PDT 24
Finished Jun 06 01:56:10 PM PDT 24
Peak memory 215736 kb
Host smart-1cf74ada-1981-41f7-bd02-8f08d85bd25d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2964069867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2964069867
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2079039020
Short name T77
Test name
Test status
Simulation time 826402824 ps
CPU time 17.54 seconds
Started Jun 06 01:56:02 PM PDT 24
Finished Jun 06 01:56:21 PM PDT 24
Peak memory 222764 kb
Host smart-f97a6d6e-4dde-4898-852d-b6f91b49ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079039020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2079039020
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.637196477
Short name T464
Test name
Test status
Simulation time 84705428 ps
CPU time 1.39 seconds
Started Jun 06 01:55:57 PM PDT 24
Finished Jun 06 01:55:59 PM PDT 24
Peak memory 207272 kb
Host smart-7e2b7b01-6688-4088-b4e7-f8b2716cffb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637196477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.637196477
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2054729364
Short name T608
Test name
Test status
Simulation time 102719490 ps
CPU time 2.31 seconds
Started Jun 06 01:55:55 PM PDT 24
Finished Jun 06 01:55:59 PM PDT 24
Peak memory 214344 kb
Host smart-d7f25563-5825-49fb-be1b-8c2311e5986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054729364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2054729364
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1990120398
Short name T309
Test name
Test status
Simulation time 26203876 ps
CPU time 1.51 seconds
Started Jun 06 01:56:02 PM PDT 24
Finished Jun 06 01:56:05 PM PDT 24
Peak memory 214232 kb
Host smart-c9773ec6-0cc3-46e6-8c94-f90abc337ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990120398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1990120398
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2526765208
Short name T55
Test name
Test status
Simulation time 135741436 ps
CPU time 2.36 seconds
Started Jun 06 01:55:51 PM PDT 24
Finished Jun 06 01:55:55 PM PDT 24
Peak memory 214332 kb
Host smart-668c31ab-ec04-47ad-8e4f-b27656b583f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526765208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2526765208
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3555252548
Short name T918
Test name
Test status
Simulation time 115394395 ps
CPU time 3.78 seconds
Started Jun 06 01:56:02 PM PDT 24
Finished Jun 06 01:56:07 PM PDT 24
Peak memory 207804 kb
Host smart-f8ea2bb1-6a38-44b4-9cc4-3a43574251ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555252548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3555252548
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3586049543
Short name T842
Test name
Test status
Simulation time 23923189 ps
CPU time 1.73 seconds
Started Jun 06 01:55:46 PM PDT 24
Finished Jun 06 01:55:49 PM PDT 24
Peak memory 206768 kb
Host smart-d85c8d06-ca7d-4686-8d55-0fd08b119be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586049543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3586049543
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.939717846
Short name T698
Test name
Test status
Simulation time 75316689 ps
CPU time 2.47 seconds
Started Jun 06 01:55:47 PM PDT 24
Finished Jun 06 01:55:51 PM PDT 24
Peak memory 206936 kb
Host smart-b3256d32-9014-454e-b233-eef16419712a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939717846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.939717846
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1879376321
Short name T597
Test name
Test status
Simulation time 1326913771 ps
CPU time 3.51 seconds
Started Jun 06 01:55:47 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 208488 kb
Host smart-b7681303-a5a3-4313-95e3-e74a939b96cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879376321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1879376321
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2838633751
Short name T613
Test name
Test status
Simulation time 310323106 ps
CPU time 3.71 seconds
Started Jun 06 01:55:51 PM PDT 24
Finished Jun 06 01:55:56 PM PDT 24
Peak memory 208644 kb
Host smart-1d2c139d-1789-4836-b1ce-8856e5a89270
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838633751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2838633751
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.494195078
Short name T285
Test name
Test status
Simulation time 805075183 ps
CPU time 10.09 seconds
Started Jun 06 01:55:52 PM PDT 24
Finished Jun 06 01:56:03 PM PDT 24
Peak memory 218220 kb
Host smart-b202fd39-07d8-4462-bde5-49a9d73f0bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494195078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.494195078
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.466451972
Short name T231
Test name
Test status
Simulation time 384095618 ps
CPU time 2.83 seconds
Started Jun 06 01:55:45 PM PDT 24
Finished Jun 06 01:55:50 PM PDT 24
Peak memory 206664 kb
Host smart-4279b1dd-e447-486b-bde9-409348ced79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466451972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.466451972
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1169888143
Short name T192
Test name
Test status
Simulation time 635957830 ps
CPU time 22.72 seconds
Started Jun 06 01:55:49 PM PDT 24
Finished Jun 06 01:56:13 PM PDT 24
Peak memory 222612 kb
Host smart-809907ab-e892-47b7-b436-41e402a16002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169888143 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1169888143
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.827834617
Short name T27
Test name
Test status
Simulation time 116708140 ps
CPU time 3.94 seconds
Started Jun 06 01:56:01 PM PDT 24
Finished Jun 06 01:56:06 PM PDT 24
Peak memory 209968 kb
Host smart-7bb0226f-f3bb-41b2-ae41-29bd21eb7c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827834617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.827834617
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2109425961
Short name T735
Test name
Test status
Simulation time 276318088 ps
CPU time 3.12 seconds
Started Jun 06 01:55:48 PM PDT 24
Finished Jun 06 01:55:52 PM PDT 24
Peak memory 210988 kb
Host smart-44e28c8f-fd4c-460e-b73e-ede5dc8228b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109425961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2109425961
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3774563138
Short name T578
Test name
Test status
Simulation time 38134410 ps
CPU time 0.78 seconds
Started Jun 06 01:55:59 PM PDT 24
Finished Jun 06 01:56:01 PM PDT 24
Peak memory 205912 kb
Host smart-090df68e-131f-48c2-a868-63d290d07957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774563138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3774563138
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3828935976
Short name T202
Test name
Test status
Simulation time 3021655232 ps
CPU time 28.36 seconds
Started Jun 06 01:55:59 PM PDT 24
Finished Jun 06 01:56:28 PM PDT 24
Peak memory 222452 kb
Host smart-8282abdf-1824-477d-b996-e0ad58c85e33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828935976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3828935976
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1638518599
Short name T37
Test name
Test status
Simulation time 135803416 ps
CPU time 5.33 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:55:57 PM PDT 24
Peak memory 208772 kb
Host smart-b05917a7-f2a4-4b29-ac5c-3b9beebf9fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638518599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1638518599
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1526907587
Short name T401
Test name
Test status
Simulation time 252305848 ps
CPU time 6.33 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:55:58 PM PDT 24
Peak memory 214280 kb
Host smart-7b33a91a-1840-435e-9738-593ea3a76880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526907587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1526907587
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1211288726
Short name T912
Test name
Test status
Simulation time 68288496 ps
CPU time 3.38 seconds
Started Jun 06 01:55:56 PM PDT 24
Finished Jun 06 01:56:00 PM PDT 24
Peak memory 214408 kb
Host smart-44fe04b1-7c92-4647-a764-b8d301ab1fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211288726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1211288726
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3083260380
Short name T329
Test name
Test status
Simulation time 188632426 ps
CPU time 5.56 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:55:57 PM PDT 24
Peak memory 222680 kb
Host smart-fd1cd5d7-365b-4162-9bba-dcdcf3d03297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083260380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3083260380
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1829080726
Short name T243
Test name
Test status
Simulation time 384897641 ps
CPU time 4.07 seconds
Started Jun 06 01:55:59 PM PDT 24
Finished Jun 06 01:56:04 PM PDT 24
Peak memory 209512 kb
Host smart-51686c3c-9f76-4f84-9d45-66c1da4d50f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829080726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1829080726
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1230390406
Short name T227
Test name
Test status
Simulation time 261550010 ps
CPU time 6.95 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:55:59 PM PDT 24
Peak memory 209300 kb
Host smart-fe19ecd0-264d-4ac0-aa89-048342a41d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230390406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1230390406
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3220582654
Short name T644
Test name
Test status
Simulation time 735409783 ps
CPU time 6.43 seconds
Started Jun 06 01:55:56 PM PDT 24
Finished Jun 06 01:56:03 PM PDT 24
Peak memory 208040 kb
Host smart-81c7d37d-039c-42ca-9327-db7cc493ae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220582654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3220582654
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2865008048
Short name T784
Test name
Test status
Simulation time 144064705 ps
CPU time 2.25 seconds
Started Jun 06 01:55:55 PM PDT 24
Finished Jun 06 01:55:58 PM PDT 24
Peak memory 206992 kb
Host smart-1a1b139d-0fa0-401f-9f51-0f8fcb8f298a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865008048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2865008048
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2519907595
Short name T467
Test name
Test status
Simulation time 98439607 ps
CPU time 2.83 seconds
Started Jun 06 01:55:59 PM PDT 24
Finished Jun 06 01:56:03 PM PDT 24
Peak memory 207084 kb
Host smart-201a7d7f-edf7-4d6c-8fa4-2773e6a7bf6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519907595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2519907595
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2680154974
Short name T665
Test name
Test status
Simulation time 2987836606 ps
CPU time 32.5 seconds
Started Jun 06 01:55:49 PM PDT 24
Finished Jun 06 01:56:22 PM PDT 24
Peak memory 209048 kb
Host smart-e78eb73a-fa42-4021-adde-bcf78fb51392
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680154974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2680154974
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3291688561
Short name T236
Test name
Test status
Simulation time 56114153 ps
CPU time 2.28 seconds
Started Jun 06 01:55:51 PM PDT 24
Finished Jun 06 01:55:54 PM PDT 24
Peak memory 218484 kb
Host smart-570d9524-b8e2-4e6b-b7bc-decfc693cf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291688561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3291688561
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1482188194
Short name T449
Test name
Test status
Simulation time 5458820277 ps
CPU time 23.88 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:56:16 PM PDT 24
Peak memory 208216 kb
Host smart-5a086498-301b-406e-85c1-89af44290ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482188194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1482188194
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.370589174
Short name T81
Test name
Test status
Simulation time 359972194 ps
CPU time 13.18 seconds
Started Jun 06 01:56:00 PM PDT 24
Finished Jun 06 01:56:14 PM PDT 24
Peak memory 220032 kb
Host smart-38d6022b-5387-43e8-9f50-44309d73363d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370589174 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.370589174
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.882353794
Short name T343
Test name
Test status
Simulation time 1203653596 ps
CPU time 13.81 seconds
Started Jun 06 01:56:09 PM PDT 24
Finished Jun 06 01:56:23 PM PDT 24
Peak memory 208216 kb
Host smart-61d8c14a-f7a0-4c9d-928c-3b1af6ba993b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882353794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.882353794
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.4275146347
Short name T664
Test name
Test status
Simulation time 72859594 ps
CPU time 1.62 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:56:09 PM PDT 24
Peak memory 210336 kb
Host smart-0fdccff9-9d8a-42c3-81db-e978535aa418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275146347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.4275146347
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3446894472
Short name T146
Test name
Test status
Simulation time 18415486 ps
CPU time 0.73 seconds
Started Jun 06 01:55:51 PM PDT 24
Finished Jun 06 01:55:53 PM PDT 24
Peak memory 205912 kb
Host smart-577dba5d-78ce-417b-a1eb-91fa08b61d35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446894472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3446894472
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2663708735
Short name T20
Test name
Test status
Simulation time 426452392 ps
CPU time 5.42 seconds
Started Jun 06 01:55:52 PM PDT 24
Finished Jun 06 01:55:58 PM PDT 24
Peak memory 214508 kb
Host smart-8312c0b1-490a-4378-a0d0-7ce65f55f61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663708735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2663708735
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.233801062
Short name T56
Test name
Test status
Simulation time 49721282 ps
CPU time 2.18 seconds
Started Jun 06 01:55:54 PM PDT 24
Finished Jun 06 01:55:57 PM PDT 24
Peak memory 209792 kb
Host smart-f949b12e-ccbb-455f-a5fc-dc73336236f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233801062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.233801062
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.460835883
Short name T308
Test name
Test status
Simulation time 83460302 ps
CPU time 1.78 seconds
Started Jun 06 01:55:52 PM PDT 24
Finished Jun 06 01:55:55 PM PDT 24
Peak memory 214320 kb
Host smart-501f67a0-232f-4c29-92c2-a8d8b4550d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460835883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.460835883
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1470707738
Short name T900
Test name
Test status
Simulation time 46728032 ps
CPU time 2.05 seconds
Started Jun 06 01:56:00 PM PDT 24
Finished Jun 06 01:56:03 PM PDT 24
Peak memory 214220 kb
Host smart-ece62828-b9f4-4fcc-b970-5c85876a93c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470707738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1470707738
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3911601989
Short name T250
Test name
Test status
Simulation time 68783795 ps
CPU time 3.54 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:09 PM PDT 24
Peak memory 214296 kb
Host smart-e73d4fef-e5ad-47ef-a860-1df980be9302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911601989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3911601989
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.748383758
Short name T333
Test name
Test status
Simulation time 245167227 ps
CPU time 3.93 seconds
Started Jun 06 01:55:59 PM PDT 24
Finished Jun 06 01:56:04 PM PDT 24
Peak memory 214312 kb
Host smart-d410246b-98b8-451a-bdb4-3efc69f15dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748383758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.748383758
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.205359203
Short name T347
Test name
Test status
Simulation time 97864817 ps
CPU time 3.05 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:55:54 PM PDT 24
Peak memory 206772 kb
Host smart-84224f62-0d89-4e80-922a-a540cf827ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205359203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.205359203
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3096176620
Short name T203
Test name
Test status
Simulation time 128098389 ps
CPU time 3.89 seconds
Started Jun 06 01:55:49 PM PDT 24
Finished Jun 06 01:55:54 PM PDT 24
Peak memory 208904 kb
Host smart-ef630d0d-3f0b-440b-b1f5-b9ba42fd863e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096176620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3096176620
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1881565856
Short name T853
Test name
Test status
Simulation time 654080546 ps
CPU time 4.97 seconds
Started Jun 06 01:55:54 PM PDT 24
Finished Jun 06 01:56:00 PM PDT 24
Peak memory 208492 kb
Host smart-d8a67414-7b6d-4837-9e71-50d3d67bb684
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881565856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1881565856
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2030039671
Short name T382
Test name
Test status
Simulation time 184595159 ps
CPU time 2.69 seconds
Started Jun 06 01:55:52 PM PDT 24
Finished Jun 06 01:55:56 PM PDT 24
Peak memory 206912 kb
Host smart-d5c9151b-dd81-4151-b440-691e8a4b18e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030039671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2030039671
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.511218330
Short name T831
Test name
Test status
Simulation time 405695277 ps
CPU time 5.45 seconds
Started Jun 06 01:56:01 PM PDT 24
Finished Jun 06 01:56:08 PM PDT 24
Peak memory 215348 kb
Host smart-cf346faa-b9f0-4234-9435-f5388a5ed331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511218330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.511218330
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1084988933
Short name T535
Test name
Test status
Simulation time 66054180 ps
CPU time 2.2 seconds
Started Jun 06 01:55:49 PM PDT 24
Finished Jun 06 01:55:53 PM PDT 24
Peak memory 208368 kb
Host smart-00045bc5-7474-408b-ad1c-297da8688a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084988933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1084988933
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.730698737
Short name T732
Test name
Test status
Simulation time 2516376323 ps
CPU time 21.84 seconds
Started Jun 06 01:56:02 PM PDT 24
Finished Jun 06 01:56:25 PM PDT 24
Peak memory 222556 kb
Host smart-159f4024-0f1f-404b-9e83-2029fc724d42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730698737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.730698737
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1286919386
Short name T629
Test name
Test status
Simulation time 325192213 ps
CPU time 2.63 seconds
Started Jun 06 01:55:49 PM PDT 24
Finished Jun 06 01:55:53 PM PDT 24
Peak memory 208312 kb
Host smart-1a57924d-f823-49cf-8911-56284e63b725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286919386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1286919386
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.286440939
Short name T512
Test name
Test status
Simulation time 53520902 ps
CPU time 1.65 seconds
Started Jun 06 01:55:57 PM PDT 24
Finished Jun 06 01:55:59 PM PDT 24
Peak memory 209740 kb
Host smart-9d074b20-2f42-4911-bf1a-23a3220d0df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286440939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.286440939
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3280662784
Short name T816
Test name
Test status
Simulation time 18245638 ps
CPU time 0.75 seconds
Started Jun 06 01:56:03 PM PDT 24
Finished Jun 06 01:56:05 PM PDT 24
Peak memory 205940 kb
Host smart-9f141913-90f7-49da-a243-5b2843c2a97a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280662784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3280662784
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2624928708
Short name T338
Test name
Test status
Simulation time 244845044 ps
CPU time 8.79 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:14 PM PDT 24
Peak memory 222476 kb
Host smart-3856ae70-75ad-45dd-b08d-a97da5acf510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624928708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2624928708
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.741850801
Short name T185
Test name
Test status
Simulation time 312979412 ps
CPU time 3.64 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:56:12 PM PDT 24
Peak memory 210676 kb
Host smart-6f639646-77b6-48a2-8b12-e80cd94083b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741850801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.741850801
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.885337248
Short name T715
Test name
Test status
Simulation time 113244271 ps
CPU time 3.08 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 207480 kb
Host smart-87dd66cf-4d82-4a6c-a755-a1ab5e0ba2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885337248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.885337248
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.423361945
Short name T97
Test name
Test status
Simulation time 1837451856 ps
CPU time 10.12 seconds
Started Jun 06 01:56:00 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 214396 kb
Host smart-7d6bf7f4-97cb-4cd4-9521-05719e95f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423361945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.423361945
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1524077788
Short name T758
Test name
Test status
Simulation time 453533326 ps
CPU time 3.51 seconds
Started Jun 06 01:56:01 PM PDT 24
Finished Jun 06 01:56:05 PM PDT 24
Peak memory 214284 kb
Host smart-7b42b593-6b63-4399-b434-57dfe49ced58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524077788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1524077788
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3330126969
Short name T785
Test name
Test status
Simulation time 74732961 ps
CPU time 2.74 seconds
Started Jun 06 01:55:59 PM PDT 24
Finished Jun 06 01:56:03 PM PDT 24
Peak memory 206592 kb
Host smart-182e4e3e-b1b6-4dde-af82-d6330c9ac7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330126969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3330126969
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2079391359
Short name T310
Test name
Test status
Simulation time 223366692 ps
CPU time 5.01 seconds
Started Jun 06 01:56:01 PM PDT 24
Finished Jun 06 01:56:07 PM PDT 24
Peak memory 210472 kb
Host smart-42a1c9b9-0cd0-4688-a5aa-d6228807e308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079391359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2079391359
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1030997743
Short name T297
Test name
Test status
Simulation time 288692301 ps
CPU time 4.86 seconds
Started Jun 06 01:56:00 PM PDT 24
Finished Jun 06 01:56:06 PM PDT 24
Peak memory 208376 kb
Host smart-9c83e496-afb0-4151-83a2-578f3ef6381c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030997743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1030997743
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.357735052
Short name T145
Test name
Test status
Simulation time 956632796 ps
CPU time 5.17 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:55:57 PM PDT 24
Peak memory 207008 kb
Host smart-5cc37084-8f3f-46a7-b9ea-51752a3575ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357735052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.357735052
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.897043407
Short name T463
Test name
Test status
Simulation time 4308889126 ps
CPU time 13.59 seconds
Started Jun 06 01:56:00 PM PDT 24
Finished Jun 06 01:56:14 PM PDT 24
Peak memory 208296 kb
Host smart-263e795d-29e4-4d16-90f4-30646044b38f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897043407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.897043407
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1681505994
Short name T808
Test name
Test status
Simulation time 271408370 ps
CPU time 3.69 seconds
Started Jun 06 01:56:05 PM PDT 24
Finished Jun 06 01:56:10 PM PDT 24
Peak memory 208940 kb
Host smart-bb2f6ae7-730c-4c84-b462-94014712533e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681505994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1681505994
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1747192512
Short name T690
Test name
Test status
Simulation time 22942659 ps
CPU time 1.94 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:56:10 PM PDT 24
Peak memory 218256 kb
Host smart-2c0f2a81-56e3-4127-8f96-8fab5d8df472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747192512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1747192512
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3230598715
Short name T460
Test name
Test status
Simulation time 90287447 ps
CPU time 2.5 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:56:10 PM PDT 24
Peak memory 206872 kb
Host smart-77390073-8629-43ea-9059-9441e854aaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230598715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3230598715
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3873074377
Short name T82
Test name
Test status
Simulation time 4617115679 ps
CPU time 40.09 seconds
Started Jun 06 01:56:16 PM PDT 24
Finished Jun 06 01:56:57 PM PDT 24
Peak memory 222448 kb
Host smart-5948f249-7b30-4e75-8558-1c28eba8db66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873074377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3873074377
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3487581347
Short name T582
Test name
Test status
Simulation time 472817178 ps
CPU time 6.07 seconds
Started Jun 06 01:56:03 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 209556 kb
Host smart-ed4950f2-85c3-41c8-9e28-02036f23c9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487581347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3487581347
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1851839648
Short name T817
Test name
Test status
Simulation time 75546687 ps
CPU time 3.1 seconds
Started Jun 06 01:56:09 PM PDT 24
Finished Jun 06 01:56:13 PM PDT 24
Peak memory 210360 kb
Host smart-daf5ad21-97c7-4c5a-847d-f018d3de786f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851839648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1851839648
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.109017094
Short name T683
Test name
Test status
Simulation time 14602740 ps
CPU time 0.74 seconds
Started Jun 06 01:55:59 PM PDT 24
Finished Jun 06 01:56:01 PM PDT 24
Peak memory 205976 kb
Host smart-c94c35e4-855a-4bf4-9e3d-88bb6d0bc893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109017094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.109017094
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1355701354
Short name T324
Test name
Test status
Simulation time 649454805 ps
CPU time 9.51 seconds
Started Jun 06 01:56:07 PM PDT 24
Finished Jun 06 01:56:18 PM PDT 24
Peak memory 214412 kb
Host smart-92c474f1-d8d2-40cb-a984-076c72b7fcdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1355701354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1355701354
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.483101903
Short name T214
Test name
Test status
Simulation time 83989809 ps
CPU time 1.92 seconds
Started Jun 06 01:56:07 PM PDT 24
Finished Jun 06 01:56:10 PM PDT 24
Peak memory 210232 kb
Host smart-6acc2d58-f0ea-4bf8-896e-1afc5072746e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483101903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.483101903
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3587643937
Short name T549
Test name
Test status
Simulation time 76639317 ps
CPU time 2.72 seconds
Started Jun 06 01:55:56 PM PDT 24
Finished Jun 06 01:55:59 PM PDT 24
Peak memory 214248 kb
Host smart-fef75a5d-a666-42a9-948f-b8f7bf168f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587643937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3587643937
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3695350572
Short name T496
Test name
Test status
Simulation time 78167984 ps
CPU time 2.43 seconds
Started Jun 06 01:56:07 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 214252 kb
Host smart-5322ff53-9f6a-4d49-882e-14a456f4ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695350572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3695350572
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.235510493
Short name T907
Test name
Test status
Simulation time 49364144 ps
CPU time 2.05 seconds
Started Jun 06 01:55:57 PM PDT 24
Finished Jun 06 01:56:00 PM PDT 24
Peak memory 208084 kb
Host smart-86bb2936-9e12-4511-8cab-a3602a8d356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235510493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.235510493
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.589944029
Short name T871
Test name
Test status
Simulation time 22917563 ps
CPU time 1.67 seconds
Started Jun 06 01:56:07 PM PDT 24
Finished Jun 06 01:56:10 PM PDT 24
Peak memory 206812 kb
Host smart-cd4992ef-7846-4c31-8704-b9dbbb381247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589944029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.589944029
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.75408131
Short name T806
Test name
Test status
Simulation time 276458276 ps
CPU time 3.5 seconds
Started Jun 06 01:55:53 PM PDT 24
Finished Jun 06 01:55:57 PM PDT 24
Peak memory 208420 kb
Host smart-49bec26d-a637-4406-9272-accf4d698d3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75408131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.75408131
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1844937274
Short name T740
Test name
Test status
Simulation time 344117213 ps
CPU time 3.22 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 208672 kb
Host smart-e142611b-f648-4602-bace-7fffdd2db7f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844937274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1844937274
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3769451662
Short name T522
Test name
Test status
Simulation time 1168895733 ps
CPU time 23.59 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:56:31 PM PDT 24
Peak memory 208412 kb
Host smart-8216bde6-64ba-4096-8cd8-d8920d615451
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769451662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3769451662
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1914773337
Short name T671
Test name
Test status
Simulation time 49918534 ps
CPU time 2.53 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:08 PM PDT 24
Peak memory 207736 kb
Host smart-8923aa13-2174-413d-a3d3-3bc076180144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914773337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1914773337
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3622341504
Short name T574
Test name
Test status
Simulation time 191471229 ps
CPU time 4.1 seconds
Started Jun 06 01:56:02 PM PDT 24
Finished Jun 06 01:56:07 PM PDT 24
Peak memory 206928 kb
Host smart-3da337df-f657-49fd-8cd9-2729bc5ec068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622341504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3622341504
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2208564214
Short name T872
Test name
Test status
Simulation time 1113588500 ps
CPU time 9.67 seconds
Started Jun 06 01:56:02 PM PDT 24
Finished Jun 06 01:56:13 PM PDT 24
Peak memory 214268 kb
Host smart-7fc3df91-6b54-4c59-b35e-d7c09ff9ffcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208564214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2208564214
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1192002096
Short name T61
Test name
Test status
Simulation time 110110264 ps
CPU time 1.89 seconds
Started Jun 06 01:56:10 PM PDT 24
Finished Jun 06 01:56:13 PM PDT 24
Peak memory 209976 kb
Host smart-cc027d87-6d87-43a9-bbdd-b87a093a2fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192002096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1192002096
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3892950972
Short name T548
Test name
Test status
Simulation time 49654581 ps
CPU time 0.81 seconds
Started Jun 06 01:56:13 PM PDT 24
Finished Jun 06 01:56:15 PM PDT 24
Peak memory 205868 kb
Host smart-aebe728e-6c3d-4763-93de-0400bb4156bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892950972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3892950972
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.413993662
Short name T779
Test name
Test status
Simulation time 94727829 ps
CPU time 2.75 seconds
Started Jun 06 01:56:23 PM PDT 24
Finished Jun 06 01:56:28 PM PDT 24
Peak memory 218368 kb
Host smart-9ce8fd9a-b780-4d67-b906-7e9a41bd1aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413993662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.413993662
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2975855968
Short name T304
Test name
Test status
Simulation time 149631960 ps
CPU time 3.61 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:09 PM PDT 24
Peak memory 215532 kb
Host smart-5024ac8d-6495-4e70-9fd2-a7336dfe584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975855968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2975855968
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.4272475690
Short name T590
Test name
Test status
Simulation time 80012533 ps
CPU time 3.15 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 210100 kb
Host smart-dcab41ff-c12e-4391-9011-0b163c0ed50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272475690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.4272475690
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.669331119
Short name T792
Test name
Test status
Simulation time 156837539 ps
CPU time 3.93 seconds
Started Jun 06 01:56:11 PM PDT 24
Finished Jun 06 01:56:16 PM PDT 24
Peak memory 219236 kb
Host smart-0520bcd3-eb62-4498-9b5c-ac2f11f6ac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669331119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.669331119
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3438337238
Short name T379
Test name
Test status
Simulation time 176839526 ps
CPU time 6.43 seconds
Started Jun 06 01:56:03 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 208696 kb
Host smart-5d6183ed-50b6-44cf-b599-1fed8e9805f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438337238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3438337238
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.4017564072
Short name T112
Test name
Test status
Simulation time 2303683810 ps
CPU time 8.62 seconds
Started Jun 06 01:55:50 PM PDT 24
Finished Jun 06 01:56:00 PM PDT 24
Peak memory 208148 kb
Host smart-990f1e22-e4e6-46a3-b4b1-074317702d13
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017564072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4017564072
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2991687550
Short name T826
Test name
Test status
Simulation time 26467232 ps
CPU time 2.09 seconds
Started Jun 06 01:56:05 PM PDT 24
Finished Jun 06 01:56:08 PM PDT 24
Peak memory 208676 kb
Host smart-a72a7d81-7382-4778-92d8-71ab6e99fcee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991687550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2991687550
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.601795043
Short name T728
Test name
Test status
Simulation time 7924882699 ps
CPU time 67.72 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:57:15 PM PDT 24
Peak memory 209336 kb
Host smart-031cbc58-2903-4b7f-b907-cfdbc56101bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601795043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.601795043
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2477433061
Short name T604
Test name
Test status
Simulation time 188657693 ps
CPU time 4.65 seconds
Started Jun 06 01:56:14 PM PDT 24
Finished Jun 06 01:56:20 PM PDT 24
Peak memory 214244 kb
Host smart-669be7a5-5b07-4560-bb25-d4dd0185014b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477433061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2477433061
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2120121161
Short name T769
Test name
Test status
Simulation time 1591045730 ps
CPU time 8.95 seconds
Started Jun 06 01:55:59 PM PDT 24
Finished Jun 06 01:56:09 PM PDT 24
Peak memory 207980 kb
Host smart-c3397376-4b7c-4181-8dc7-8ca8d65451dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120121161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2120121161
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2778580047
Short name T153
Test name
Test status
Simulation time 313653898 ps
CPU time 15.87 seconds
Started Jun 06 01:56:09 PM PDT 24
Finished Jun 06 01:56:26 PM PDT 24
Peak memory 222500 kb
Host smart-15309d4b-9191-41f8-b570-3f13eeea5523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778580047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2778580047
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3430874291
Short name T420
Test name
Test status
Simulation time 4149752148 ps
CPU time 9.76 seconds
Started Jun 06 01:56:14 PM PDT 24
Finished Jun 06 01:56:24 PM PDT 24
Peak memory 214408 kb
Host smart-dadeb4c4-4aff-4a90-8069-c7f932947c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430874291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3430874291
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.214614517
Short name T219
Test name
Test status
Simulation time 336741510 ps
CPU time 2.08 seconds
Started Jun 06 01:56:02 PM PDT 24
Finished Jun 06 01:56:06 PM PDT 24
Peak memory 210100 kb
Host smart-654731f5-90d5-4564-b625-0f766d2c5912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214614517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.214614517
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3241232219
Short name T654
Test name
Test status
Simulation time 14995004 ps
CPU time 0.84 seconds
Started Jun 06 01:56:01 PM PDT 24
Finished Jun 06 01:56:03 PM PDT 24
Peak memory 205932 kb
Host smart-e713d2ce-d683-435e-add4-aa87d8dfe3bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241232219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3241232219
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3300214044
Short name T265
Test name
Test status
Simulation time 1221856057 ps
CPU time 12.88 seconds
Started Jun 06 01:56:07 PM PDT 24
Finished Jun 06 01:56:22 PM PDT 24
Peak memory 215692 kb
Host smart-9a76e7dc-6811-42c0-9c15-11205c579877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300214044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3300214044
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.581794693
Short name T50
Test name
Test status
Simulation time 112518319 ps
CPU time 1.84 seconds
Started Jun 06 01:56:01 PM PDT 24
Finished Jun 06 01:56:04 PM PDT 24
Peak memory 214332 kb
Host smart-f1ab8ecc-66f9-4ec8-89a1-46e172bd7635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581794693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.581794693
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1679988777
Short name T107
Test name
Test status
Simulation time 597628303 ps
CPU time 4.42 seconds
Started Jun 06 01:56:15 PM PDT 24
Finished Jun 06 01:56:20 PM PDT 24
Peak memory 222436 kb
Host smart-0f94834e-0238-462b-b7d2-bf8893ce0cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679988777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1679988777
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.974154066
Short name T410
Test name
Test status
Simulation time 94700805 ps
CPU time 4.19 seconds
Started Jun 06 01:56:03 PM PDT 24
Finished Jun 06 01:56:09 PM PDT 24
Peak memory 206724 kb
Host smart-593c1038-0b5d-4b21-972d-4fe619414af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974154066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.974154066
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3504183950
Short name T434
Test name
Test status
Simulation time 535525527 ps
CPU time 3.7 seconds
Started Jun 06 01:56:24 PM PDT 24
Finished Jun 06 01:56:29 PM PDT 24
Peak memory 214228 kb
Host smart-4b124095-6a2e-4b3a-84cf-8e036bb2a5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504183950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3504183950
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1500711902
Short name T225
Test name
Test status
Simulation time 238015173 ps
CPU time 4.86 seconds
Started Jun 06 01:56:13 PM PDT 24
Finished Jun 06 01:56:19 PM PDT 24
Peak memory 208800 kb
Host smart-7522fead-db88-4f34-9d06-a3f7b4fc0afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500711902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1500711902
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2041213771
Short name T782
Test name
Test status
Simulation time 155749673 ps
CPU time 4.31 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:09 PM PDT 24
Peak memory 208472 kb
Host smart-413b7136-c301-46a1-afd0-fd804554ac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041213771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2041213771
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1909111134
Short name T859
Test name
Test status
Simulation time 200670239 ps
CPU time 2.9 seconds
Started Jun 06 01:56:07 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 208988 kb
Host smart-3ae210af-566e-4ccb-bb4b-3e861dd26aa2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909111134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1909111134
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3096564391
Short name T592
Test name
Test status
Simulation time 98938701 ps
CPU time 3.64 seconds
Started Jun 06 01:56:05 PM PDT 24
Finished Jun 06 01:56:10 PM PDT 24
Peak memory 208568 kb
Host smart-949aae53-509c-4f84-a7ec-2bf2873ec05a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096564391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3096564391
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3124160291
Short name T869
Test name
Test status
Simulation time 68502042 ps
CPU time 3.17 seconds
Started Jun 06 01:56:05 PM PDT 24
Finished Jun 06 01:56:10 PM PDT 24
Peak memory 208784 kb
Host smart-ce17d597-059f-4765-bfaf-7173432d9aef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124160291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3124160291
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1083444864
Short name T395
Test name
Test status
Simulation time 3010848995 ps
CPU time 18.62 seconds
Started Jun 06 01:56:07 PM PDT 24
Finished Jun 06 01:56:27 PM PDT 24
Peak memory 208528 kb
Host smart-069b6642-3b24-4190-972c-c32e0ccbf8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083444864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1083444864
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1402387515
Short name T598
Test name
Test status
Simulation time 141473689 ps
CPU time 4.74 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:09 PM PDT 24
Peak memory 206884 kb
Host smart-6af76fdb-70e3-469c-a913-e1ef0c21a6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402387515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1402387515
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1227205047
Short name T87
Test name
Test status
Simulation time 3049799958 ps
CPU time 41.55 seconds
Started Jun 06 01:56:10 PM PDT 24
Finished Jun 06 01:56:53 PM PDT 24
Peak memory 217116 kb
Host smart-e6d84945-e272-47c3-afc5-69d4185f371b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227205047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1227205047
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2802571659
Short name T558
Test name
Test status
Simulation time 503528413 ps
CPU time 12.23 seconds
Started Jun 06 01:56:18 PM PDT 24
Finished Jun 06 01:56:32 PM PDT 24
Peak memory 220588 kb
Host smart-cc25308c-58f6-4c9e-9ba3-91b53eb60574
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802571659 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2802571659
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4202125211
Short name T709
Test name
Test status
Simulation time 303096711 ps
CPU time 5.35 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 209164 kb
Host smart-8540e68d-7fbd-4278-979a-36d0f7827fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202125211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4202125211
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1661708270
Short name T484
Test name
Test status
Simulation time 112707109 ps
CPU time 2.17 seconds
Started Jun 06 01:56:03 PM PDT 24
Finished Jun 06 01:56:07 PM PDT 24
Peak memory 210316 kb
Host smart-c5b8adef-b395-43e5-b0be-ac47d365f830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661708270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1661708270
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1206956909
Short name T515
Test name
Test status
Simulation time 47833464 ps
CPU time 0.85 seconds
Started Jun 06 01:56:11 PM PDT 24
Finished Jun 06 01:56:13 PM PDT 24
Peak memory 205948 kb
Host smart-1ca23edb-628d-45eb-8763-9aa993be817f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206956909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1206956909
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3178598633
Short name T276
Test name
Test status
Simulation time 581941044 ps
CPU time 4.35 seconds
Started Jun 06 01:56:05 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 214328 kb
Host smart-845d9147-5996-4b0a-8dc3-f9f107150c6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178598633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3178598633
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2259484315
Short name T833
Test name
Test status
Simulation time 610994641 ps
CPU time 3.02 seconds
Started Jun 06 01:56:26 PM PDT 24
Finished Jun 06 01:56:31 PM PDT 24
Peak memory 210140 kb
Host smart-eba55721-3e66-4d41-b280-76479ff3aaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259484315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2259484315
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1152895827
Short name T731
Test name
Test status
Simulation time 26469740525 ps
CPU time 51.73 seconds
Started Jun 06 01:56:05 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 214552 kb
Host smart-63b593bd-2d6a-44c2-8589-34efcf4f7824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152895827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1152895827
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3256663164
Short name T848
Test name
Test status
Simulation time 780516491 ps
CPU time 15.29 seconds
Started Jun 06 01:56:05 PM PDT 24
Finished Jun 06 01:56:21 PM PDT 24
Peak memory 214308 kb
Host smart-96f15774-bd83-482f-95ca-13046f96c71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256663164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3256663164
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.920704850
Short name T307
Test name
Test status
Simulation time 41885275 ps
CPU time 2.97 seconds
Started Jun 06 01:56:02 PM PDT 24
Finished Jun 06 01:56:06 PM PDT 24
Peak memory 222456 kb
Host smart-e8d641d3-c587-4760-bae2-7c3b7fc602d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920704850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.920704850
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1264876027
Short name T63
Test name
Test status
Simulation time 60000613 ps
CPU time 2.29 seconds
Started Jun 06 01:56:21 PM PDT 24
Finished Jun 06 01:56:25 PM PDT 24
Peak memory 208208 kb
Host smart-68785c2b-2dfd-428f-b91f-7970ddca7111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264876027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1264876027
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1915174336
Short name T41
Test name
Test status
Simulation time 204359911 ps
CPU time 6.19 seconds
Started Jun 06 01:56:14 PM PDT 24
Finished Jun 06 01:56:21 PM PDT 24
Peak memory 208472 kb
Host smart-84433726-6bdb-431b-ab00-6b58205b028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915174336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1915174336
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1184617236
Short name T572
Test name
Test status
Simulation time 216358768 ps
CPU time 6.88 seconds
Started Jun 06 01:56:01 PM PDT 24
Finished Jun 06 01:56:09 PM PDT 24
Peak memory 208436 kb
Host smart-ca46977f-7aaa-4efe-9702-6938ce9dc01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184617236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1184617236
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.528002196
Short name T358
Test name
Test status
Simulation time 7533632836 ps
CPU time 15.29 seconds
Started Jun 06 01:56:13 PM PDT 24
Finished Jun 06 01:56:29 PM PDT 24
Peak memory 208036 kb
Host smart-bb4c1667-644c-46c8-90a9-b1cc753caefa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528002196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.528002196
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.702347710
Short name T377
Test name
Test status
Simulation time 41040741 ps
CPU time 2.55 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:08 PM PDT 24
Peak memory 208340 kb
Host smart-7d96e23c-1a50-41e7-b583-9af038c23bb6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702347710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.702347710
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.555937386
Short name T843
Test name
Test status
Simulation time 156211121 ps
CPU time 4.65 seconds
Started Jun 06 01:56:11 PM PDT 24
Finished Jun 06 01:56:17 PM PDT 24
Peak memory 208908 kb
Host smart-ff521a40-88d5-4303-8817-bedd487445c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555937386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.555937386
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3776673841
Short name T656
Test name
Test status
Simulation time 148399865 ps
CPU time 2.06 seconds
Started Jun 06 01:56:12 PM PDT 24
Finished Jun 06 01:56:15 PM PDT 24
Peak memory 207712 kb
Host smart-69490ad4-46c4-4717-912b-9857f503cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776673841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3776673841
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2201472896
Short name T249
Test name
Test status
Simulation time 1319416301 ps
CPU time 41.39 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:47 PM PDT 24
Peak memory 214808 kb
Host smart-999c7788-2d85-44db-8029-445b99726560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201472896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2201472896
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1859204756
Short name T138
Test name
Test status
Simulation time 333931865 ps
CPU time 13.02 seconds
Started Jun 06 01:56:14 PM PDT 24
Finished Jun 06 01:56:28 PM PDT 24
Peak memory 222600 kb
Host smart-6d54d581-3ba9-4ab9-bf67-51867a95e551
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859204756 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1859204756
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3152417265
Short name T851
Test name
Test status
Simulation time 509356123 ps
CPU time 5.41 seconds
Started Jun 06 01:56:05 PM PDT 24
Finished Jun 06 01:56:11 PM PDT 24
Peak memory 207728 kb
Host smart-41d7fcda-cdb1-483a-8672-f07d7196ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152417265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3152417265
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1964431265
Short name T207
Test name
Test status
Simulation time 58318588 ps
CPU time 2.32 seconds
Started Jun 06 01:56:03 PM PDT 24
Finished Jun 06 01:56:07 PM PDT 24
Peak memory 210164 kb
Host smart-a165b9b1-cfc3-4607-9274-17da7a02fc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964431265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1964431265
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2347581849
Short name T119
Test name
Test status
Simulation time 17109126 ps
CPU time 0.81 seconds
Started Jun 06 01:56:13 PM PDT 24
Finished Jun 06 01:56:15 PM PDT 24
Peak memory 205936 kb
Host smart-f3ed78db-77ab-4309-989c-f58796f2dcb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347581849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2347581849
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3113340201
Short name T129
Test name
Test status
Simulation time 71638978 ps
CPU time 2.9 seconds
Started Jun 06 01:56:03 PM PDT 24
Finished Jun 06 01:56:07 PM PDT 24
Peak memory 214684 kb
Host smart-3dfeb581-990b-451a-be1e-8d68f127cf2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113340201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3113340201
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1123493639
Short name T852
Test name
Test status
Simulation time 317225740 ps
CPU time 3.91 seconds
Started Jun 06 01:56:11 PM PDT 24
Finished Jun 06 01:56:16 PM PDT 24
Peak memory 209960 kb
Host smart-c8676d7f-0ed4-412c-8a56-3e9d8ac65e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123493639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1123493639
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1453325490
Short name T240
Test name
Test status
Simulation time 421197704 ps
CPU time 3.89 seconds
Started Jun 06 01:56:20 PM PDT 24
Finished Jun 06 01:56:25 PM PDT 24
Peak memory 214320 kb
Host smart-7d5042bd-f46f-4549-9d98-f48b8b7c0c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453325490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1453325490
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.4252990803
Short name T409
Test name
Test status
Simulation time 279601994 ps
CPU time 3.2 seconds
Started Jun 06 01:56:08 PM PDT 24
Finished Jun 06 01:56:13 PM PDT 24
Peak memory 214252 kb
Host smart-2d92ca7f-d27f-4e0a-ab6e-c733838c7df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252990803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.4252990803
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.406511846
Short name T661
Test name
Test status
Simulation time 89191507 ps
CPU time 3.51 seconds
Started Jun 06 01:56:03 PM PDT 24
Finished Jun 06 01:56:08 PM PDT 24
Peak memory 218192 kb
Host smart-9d3f834c-edae-460c-a553-9d8bdad411f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406511846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.406511846
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3592881705
Short name T315
Test name
Test status
Simulation time 8046810752 ps
CPU time 73.35 seconds
Started Jun 06 01:56:02 PM PDT 24
Finished Jun 06 01:57:16 PM PDT 24
Peak memory 209864 kb
Host smart-408391f1-5ea8-40a5-b801-57b250ae711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592881705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3592881705
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.280939732
Short name T365
Test name
Test status
Simulation time 124302439 ps
CPU time 3.18 seconds
Started Jun 06 01:56:04 PM PDT 24
Finished Jun 06 01:56:08 PM PDT 24
Peak memory 208320 kb
Host smart-2d182b1d-e8d7-4638-8429-8acb5b8d5515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280939732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.280939732
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.917642074
Short name T476
Test name
Test status
Simulation time 455178950 ps
CPU time 6.96 seconds
Started Jun 06 01:56:07 PM PDT 24
Finished Jun 06 01:56:15 PM PDT 24
Peak memory 208836 kb
Host smart-261cc6b0-ceb4-4949-b80d-5629b49ea814
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917642074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.917642074
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.382570132
Short name T856
Test name
Test status
Simulation time 323913858 ps
CPU time 9.25 seconds
Started Jun 06 01:56:09 PM PDT 24
Finished Jun 06 01:56:19 PM PDT 24
Peak memory 206996 kb
Host smart-bfc8ca54-eba2-4bc9-a567-da07aa9c2d34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382570132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.382570132
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.426192028
Short name T479
Test name
Test status
Simulation time 5359789840 ps
CPU time 64.57 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:57:12 PM PDT 24
Peak memory 209036 kb
Host smart-7bf25d2f-7a2b-4421-831e-35bf8ad39aba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426192028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.426192028
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.370361769
Short name T890
Test name
Test status
Simulation time 784785040 ps
CPU time 4.67 seconds
Started Jun 06 01:56:16 PM PDT 24
Finished Jun 06 01:56:21 PM PDT 24
Peak memory 218488 kb
Host smart-2c69c90b-7aa7-464e-8bcf-a1b40f4569be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370361769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.370361769
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.854923016
Short name T228
Test name
Test status
Simulation time 147665978 ps
CPU time 2.69 seconds
Started Jun 06 01:56:13 PM PDT 24
Finished Jun 06 01:56:17 PM PDT 24
Peak memory 206744 kb
Host smart-75dd2f8e-952a-482b-acd2-5e1f7a061448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854923016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.854923016
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1487709651
Short name T352
Test name
Test status
Simulation time 1256790276 ps
CPU time 5.13 seconds
Started Jun 06 01:56:11 PM PDT 24
Finished Jun 06 01:56:17 PM PDT 24
Peak memory 218436 kb
Host smart-55aa5878-22d1-4f8e-a5b1-9a35463559a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487709651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1487709651
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3867743926
Short name T783
Test name
Test status
Simulation time 566170051 ps
CPU time 24.05 seconds
Started Jun 06 01:56:06 PM PDT 24
Finished Jun 06 01:56:31 PM PDT 24
Peak memory 222576 kb
Host smart-5bd45473-98b3-4245-8524-87f08975c6e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867743926 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3867743926
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1413443716
Short name T730
Test name
Test status
Simulation time 30954647 ps
CPU time 2.16 seconds
Started Jun 06 01:56:03 PM PDT 24
Finished Jun 06 01:56:07 PM PDT 24
Peak memory 207472 kb
Host smart-0bf8b38d-d6e1-47f6-b514-35e71522195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413443716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1413443716
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1855281486
Short name T415
Test name
Test status
Simulation time 546815367 ps
CPU time 5.61 seconds
Started Jun 06 01:56:12 PM PDT 24
Finished Jun 06 01:56:19 PM PDT 24
Peak memory 210516 kb
Host smart-47b60ab4-e28e-49d4-817e-a75aa793aa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855281486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1855281486
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.750471612
Short name T444
Test name
Test status
Simulation time 10592399 ps
CPU time 0.86 seconds
Started Jun 06 01:54:05 PM PDT 24
Finished Jun 06 01:54:07 PM PDT 24
Peak memory 205964 kb
Host smart-49f7f0e0-5d42-418d-af8b-7a1cfa538fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750471612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.750471612
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.182306544
Short name T371
Test name
Test status
Simulation time 174542887 ps
CPU time 4.44 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 220300 kb
Host smart-1236b126-a5ff-4a7a-9c61-de66c6d6c3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182306544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.182306544
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3248781354
Short name T217
Test name
Test status
Simulation time 63070219 ps
CPU time 2.93 seconds
Started Jun 06 01:54:04 PM PDT 24
Finished Jun 06 01:54:08 PM PDT 24
Peak memory 218156 kb
Host smart-43f957c7-2beb-4ca2-b4bb-fa2fab89bdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248781354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3248781354
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.46206074
Short name T391
Test name
Test status
Simulation time 91262014 ps
CPU time 2.37 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 219460 kb
Host smart-a6a01e84-9f93-4ddd-86e5-f7137d9c280f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46206074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.46206074
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3919236417
Short name T370
Test name
Test status
Simulation time 362505732 ps
CPU time 2.8 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 222256 kb
Host smart-7d9cff53-e3bd-47c5-833c-e63163e81dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919236417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3919236417
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.947368604
Short name T888
Test name
Test status
Simulation time 320910482 ps
CPU time 8.7 seconds
Started Jun 06 01:54:05 PM PDT 24
Finished Jun 06 01:54:15 PM PDT 24
Peak memory 208612 kb
Host smart-92f5eb7d-37fc-49b9-b9a7-a316dfe29482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947368604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.947368604
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2883946450
Short name T807
Test name
Test status
Simulation time 7337820992 ps
CPU time 17.19 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:25 PM PDT 24
Peak memory 208108 kb
Host smart-ae5d27e8-deb4-4b9d-b019-6cd71730cc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883946450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2883946450
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.642541738
Short name T874
Test name
Test status
Simulation time 951092652 ps
CPU time 6.63 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 206900 kb
Host smart-b7c7424a-8905-41af-9134-fa9334bd76db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642541738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.642541738
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.503774524
Short name T235
Test name
Test status
Simulation time 67766673 ps
CPU time 2.96 seconds
Started Jun 06 01:54:05 PM PDT 24
Finished Jun 06 01:54:10 PM PDT 24
Peak memory 207364 kb
Host smart-b3daa5fd-9233-4c3f-a8fe-abed8c1a6e28
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503774524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.503774524
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2395099137
Short name T669
Test name
Test status
Simulation time 614080602 ps
CPU time 10.05 seconds
Started Jun 06 01:54:11 PM PDT 24
Finished Jun 06 01:54:23 PM PDT 24
Peak memory 208504 kb
Host smart-2f316dab-2c8c-4cd0-945c-54dbd60502f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395099137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2395099137
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2657965213
Short name T456
Test name
Test status
Simulation time 100115483 ps
CPU time 1.91 seconds
Started Jun 06 01:54:11 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 208972 kb
Host smart-c47e36e3-ffe3-4746-af06-65d96a65b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657965213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2657965213
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3663146617
Short name T540
Test name
Test status
Simulation time 59391348 ps
CPU time 2.81 seconds
Started Jun 06 01:54:05 PM PDT 24
Finished Jun 06 01:54:09 PM PDT 24
Peak memory 208192 kb
Host smart-1472ad38-5b36-47ac-8057-8c3c8be860a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663146617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3663146617
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.4070709513
Short name T813
Test name
Test status
Simulation time 506479191 ps
CPU time 6.53 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 209468 kb
Host smart-6cb086ef-3a70-4838-a465-ec80a8e57658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070709513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4070709513
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2212420138
Short name T414
Test name
Test status
Simulation time 72854554 ps
CPU time 2.93 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 209924 kb
Host smart-357bcc97-752d-42b5-a317-8d8a9c73080e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212420138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2212420138
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1845529109
Short name T517
Test name
Test status
Simulation time 53236809 ps
CPU time 1.03 seconds
Started Jun 06 01:54:09 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 206328 kb
Host smart-995d7ced-d8ba-4299-91dd-eb9d3a2aedf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845529109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1845529109
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1769474031
Short name T437
Test name
Test status
Simulation time 132760958 ps
CPU time 4.38 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 214332 kb
Host smart-d4b33c85-3293-4222-a3ae-67d1e261b95b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769474031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1769474031
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.23970314
Short name T620
Test name
Test status
Simulation time 136476848 ps
CPU time 3.1 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:54:12 PM PDT 24
Peak memory 221404 kb
Host smart-e4a9321c-8663-4116-9b02-f42af4c6e033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23970314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.23970314
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3764483611
Short name T877
Test name
Test status
Simulation time 103675099 ps
CPU time 4.09 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:12 PM PDT 24
Peak memory 210280 kb
Host smart-d9125884-f4b7-43d8-ba59-83b8329a02de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764483611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3764483611
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.588177462
Short name T668
Test name
Test status
Simulation time 221656311 ps
CPU time 3.07 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 218700 kb
Host smart-9251c86f-2079-415c-838f-f64955c2b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588177462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.588177462
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2413730535
Short name T302
Test name
Test status
Simulation time 151063265 ps
CPU time 3.96 seconds
Started Jun 06 01:54:11 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 209404 kb
Host smart-65398685-5235-413b-ba29-a039852a9476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413730535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2413730535
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3383354099
Short name T299
Test name
Test status
Simulation time 51410845 ps
CPU time 2.6 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:12 PM PDT 24
Peak memory 206900 kb
Host smart-33359d02-9176-40bb-937f-62b3cfffa679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383354099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3383354099
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3796341308
Short name T670
Test name
Test status
Simulation time 6382118418 ps
CPU time 74.12 seconds
Started Jun 06 01:54:11 PM PDT 24
Finished Jun 06 01:55:27 PM PDT 24
Peak memory 209360 kb
Host smart-d075953f-804a-484b-880a-df3b68d1990f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796341308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3796341308
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1674061804
Short name T570
Test name
Test status
Simulation time 510998810 ps
CPU time 3.71 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:54:12 PM PDT 24
Peak memory 208852 kb
Host smart-ec4c2597-66ac-4887-8924-168ac43777ee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674061804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1674061804
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3652413091
Short name T301
Test name
Test status
Simulation time 66375147 ps
CPU time 3.3 seconds
Started Jun 06 01:54:10 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 206764 kb
Host smart-7bd7c637-27a3-485a-bd7e-8714c47c8898
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652413091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3652413091
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2574423477
Short name T884
Test name
Test status
Simulation time 679608039 ps
CPU time 3.04 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 207952 kb
Host smart-8d377fd3-2c11-4d16-9a52-a79c4ba5911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574423477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2574423477
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3424589694
Short name T445
Test name
Test status
Simulation time 158049203 ps
CPU time 3.28 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:12 PM PDT 24
Peak memory 207284 kb
Host smart-9d8052eb-179c-4860-ac45-4a808086866d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424589694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3424589694
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3691511301
Short name T891
Test name
Test status
Simulation time 59037176 ps
CPU time 2.85 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 206980 kb
Host smart-c56b7ac9-1072-4b48-b850-597fffdbff43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691511301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3691511301
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3087571459
Short name T638
Test name
Test status
Simulation time 2759782832 ps
CPU time 5.49 seconds
Started Jun 06 01:54:11 PM PDT 24
Finished Jun 06 01:54:18 PM PDT 24
Peak memory 208616 kb
Host smart-e290ae31-5dea-480e-ab21-aaea23af9508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087571459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3087571459
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1084600676
Short name T66
Test name
Test status
Simulation time 90611353 ps
CPU time 3.29 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 210284 kb
Host smart-ead83827-c0ad-41f9-b9e4-548fe4cc1267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084600676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1084600676
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2122133755
Short name T676
Test name
Test status
Simulation time 44878598 ps
CPU time 0.77 seconds
Started Jun 06 01:54:09 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 205940 kb
Host smart-8a424558-fd6f-42b2-ae14-6255ebdf7c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122133755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2122133755
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.4277484365
Short name T205
Test name
Test status
Simulation time 34173089 ps
CPU time 2.71 seconds
Started Jun 06 01:54:10 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 214296 kb
Host smart-91f16a1b-00be-4793-a695-692791990b1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277484365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4277484365
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3714419793
Short name T33
Test name
Test status
Simulation time 120610912 ps
CPU time 5.28 seconds
Started Jun 06 01:54:10 PM PDT 24
Finished Jun 06 01:54:17 PM PDT 24
Peak memory 210192 kb
Host smart-e1d2a2c3-2b9f-4f99-8bd7-6c9f3f9e4333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714419793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3714419793
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3807903085
Short name T802
Test name
Test status
Simulation time 371182877 ps
CPU time 2.03 seconds
Started Jun 06 01:54:10 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 218276 kb
Host smart-e6aa0a25-a222-4e4c-acaa-cf03fab707b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807903085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3807903085
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1081452021
Short name T791
Test name
Test status
Simulation time 4377508595 ps
CPU time 54.13 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:55:03 PM PDT 24
Peak memory 218840 kb
Host smart-178cc548-c152-4c5c-82fc-85e8b2a5a281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081452021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1081452021
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1419820171
Short name T892
Test name
Test status
Simulation time 32224719 ps
CPU time 2.35 seconds
Started Jun 06 01:54:10 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 211708 kb
Host smart-9468200f-3ca9-4426-b889-97dd9cbaee91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419820171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1419820171
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2786088450
Short name T626
Test name
Test status
Simulation time 113646099 ps
CPU time 6 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 210360 kb
Host smart-cce4a542-50c5-4b92-96cd-846980be1f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786088450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2786088450
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2101120731
Short name T738
Test name
Test status
Simulation time 264978668 ps
CPU time 4.87 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 209432 kb
Host smart-db0075a6-66fc-4a8a-b90b-8bbfe2c2ecf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101120731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2101120731
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2415552545
Short name T589
Test name
Test status
Simulation time 198570652 ps
CPU time 3.31 seconds
Started Jun 06 01:54:09 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 207200 kb
Host smart-06df6ae2-d3da-4438-886a-e7202b34e085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415552545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2415552545
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1038605549
Short name T659
Test name
Test status
Simulation time 74313895 ps
CPU time 3.39 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 208520 kb
Host smart-2426cc35-f66e-4a7d-81d9-080abc141d18
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038605549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1038605549
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2949513414
Short name T348
Test name
Test status
Simulation time 137835913 ps
CPU time 5.22 seconds
Started Jun 06 01:54:06 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 208004 kb
Host smart-01b9620f-22c9-40c8-8519-143327d4734a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949513414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2949513414
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1572006073
Short name T739
Test name
Test status
Simulation time 137202412 ps
CPU time 2.52 seconds
Started Jun 06 01:54:07 PM PDT 24
Finished Jun 06 01:54:11 PM PDT 24
Peak memory 206884 kb
Host smart-48052e82-3981-4749-9f13-caf5dd3b9eae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572006073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1572006073
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.499794897
Short name T457
Test name
Test status
Simulation time 109564269 ps
CPU time 2.22 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:12 PM PDT 24
Peak memory 218056 kb
Host smart-d222e046-1ac6-48d2-bfb4-f893923fef35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499794897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.499794897
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.641625794
Short name T559
Test name
Test status
Simulation time 1099505166 ps
CPU time 12.31 seconds
Started Jun 06 01:54:11 PM PDT 24
Finished Jun 06 01:54:24 PM PDT 24
Peak memory 208216 kb
Host smart-0f265609-7801-4713-8dff-aa446fb5649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641625794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.641625794
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3591931110
Short name T363
Test name
Test status
Simulation time 19292301696 ps
CPU time 110.29 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:56:00 PM PDT 24
Peak memory 217168 kb
Host smart-d6cd5f98-6a15-4ccb-95dd-c2fc870d315b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591931110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3591931110
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.776795441
Short name T116
Test name
Test status
Simulation time 3646250717 ps
CPU time 23.93 seconds
Started Jun 06 01:54:10 PM PDT 24
Finished Jun 06 01:54:35 PM PDT 24
Peak memory 222772 kb
Host smart-bd2ea957-409f-49ba-8812-992e44e8dbc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776795441 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.776795441
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.449643589
Short name T286
Test name
Test status
Simulation time 189212221 ps
CPU time 2.99 seconds
Started Jun 06 01:54:08 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 206944 kb
Host smart-8a09077e-016d-4d11-b9df-3ec777c88c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449643589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.449643589
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2277718701
Short name T166
Test name
Test status
Simulation time 75991122 ps
CPU time 1.27 seconds
Started Jun 06 01:54:10 PM PDT 24
Finished Jun 06 01:54:13 PM PDT 24
Peak memory 209568 kb
Host smart-dc847ccb-9504-4229-8ee5-3ebac44e8b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277718701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2277718701
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1582577005
Short name T575
Test name
Test status
Simulation time 40306885 ps
CPU time 0.71 seconds
Started Jun 06 01:54:15 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 205960 kb
Host smart-ae88a005-3848-402a-99fd-f0144df808cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582577005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1582577005
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3854650017
Short name T120
Test name
Test status
Simulation time 549296284 ps
CPU time 8.11 seconds
Started Jun 06 01:54:13 PM PDT 24
Finished Jun 06 01:54:22 PM PDT 24
Peak memory 214324 kb
Host smart-23b18995-888e-40af-b508-89a15ae59348
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854650017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3854650017
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2761370824
Short name T30
Test name
Test status
Simulation time 25270160 ps
CPU time 1.64 seconds
Started Jun 06 01:54:15 PM PDT 24
Finished Jun 06 01:54:17 PM PDT 24
Peak memory 207800 kb
Host smart-c38f636d-4fcd-43ed-ab97-03b524f60db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761370824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2761370824
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4145642776
Short name T524
Test name
Test status
Simulation time 135735470 ps
CPU time 4.42 seconds
Started Jun 06 01:54:13 PM PDT 24
Finished Jun 06 01:54:19 PM PDT 24
Peak memory 214244 kb
Host smart-6d475cc7-aaaf-4f85-a544-01072a34d065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145642776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4145642776
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1582100627
Short name T98
Test name
Test status
Simulation time 126386643 ps
CPU time 2.21 seconds
Started Jun 06 01:54:13 PM PDT 24
Finished Jun 06 01:54:17 PM PDT 24
Peak memory 214316 kb
Host smart-c6486176-9512-4a4f-936a-b0781c9c40ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582100627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1582100627
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.4141557880
Short name T327
Test name
Test status
Simulation time 29720950 ps
CPU time 2.36 seconds
Started Jun 06 01:54:22 PM PDT 24
Finished Jun 06 01:54:26 PM PDT 24
Peak memory 222432 kb
Host smart-715b8e2b-23d8-46af-bc71-15e62072dae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141557880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4141557880
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4162705845
Short name T906
Test name
Test status
Simulation time 251555132 ps
CPU time 7.12 seconds
Started Jun 06 01:54:12 PM PDT 24
Finished Jun 06 01:54:21 PM PDT 24
Peak memory 214348 kb
Host smart-128dbfd2-7889-4ad7-a53d-96917be127ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162705845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4162705845
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1070532095
Short name T536
Test name
Test status
Simulation time 8098556859 ps
CPU time 58.22 seconds
Started Jun 06 01:54:14 PM PDT 24
Finished Jun 06 01:55:13 PM PDT 24
Peak memory 209360 kb
Host smart-e3596bf9-e1ee-4fcb-9825-607e5bb55d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070532095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1070532095
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1901118525
Short name T3
Test name
Test status
Simulation time 154663003 ps
CPU time 2.86 seconds
Started Jun 06 01:54:14 PM PDT 24
Finished Jun 06 01:54:18 PM PDT 24
Peak memory 208472 kb
Host smart-80bdd89b-bba6-4f59-baf5-42ca655c7a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901118525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1901118525
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2812644774
Short name T511
Test name
Test status
Simulation time 837607939 ps
CPU time 6.6 seconds
Started Jun 06 01:54:13 PM PDT 24
Finished Jun 06 01:54:21 PM PDT 24
Peak memory 208048 kb
Host smart-e746f53c-95ef-4357-8e36-973484cf9aab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812644774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2812644774
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1171501703
Short name T473
Test name
Test status
Simulation time 163882720 ps
CPU time 2.41 seconds
Started Jun 06 01:54:12 PM PDT 24
Finished Jun 06 01:54:15 PM PDT 24
Peak memory 207032 kb
Host smart-6bbc3af9-cbfb-42e7-bf6f-1687fae35f42
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171501703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1171501703
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3739699074
Short name T675
Test name
Test status
Simulation time 761376466 ps
CPU time 5.3 seconds
Started Jun 06 01:54:13 PM PDT 24
Finished Jun 06 01:54:20 PM PDT 24
Peak memory 208756 kb
Host smart-5859eadc-1615-4b6d-a687-70318ed91eab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739699074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3739699074
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.628442852
Short name T568
Test name
Test status
Simulation time 392292966 ps
CPU time 6.11 seconds
Started Jun 06 01:54:15 PM PDT 24
Finished Jun 06 01:54:22 PM PDT 24
Peak memory 210004 kb
Host smart-8741810d-8d4a-4b6a-9115-da769696c615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628442852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.628442852
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.516712154
Short name T607
Test name
Test status
Simulation time 340335236 ps
CPU time 2.84 seconds
Started Jun 06 01:54:12 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 208384 kb
Host smart-3b85e475-ab97-430b-8ba0-d99e1d5f731d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516712154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.516712154
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1552108057
Short name T864
Test name
Test status
Simulation time 262598511 ps
CPU time 12.44 seconds
Started Jun 06 01:54:18 PM PDT 24
Finished Jun 06 01:54:32 PM PDT 24
Peak memory 215004 kb
Host smart-61ab8657-057c-48b3-8ea4-0e4aed806249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552108057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1552108057
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2434766147
Short name T468
Test name
Test status
Simulation time 307527434 ps
CPU time 7.41 seconds
Started Jun 06 01:54:13 PM PDT 24
Finished Jun 06 01:54:21 PM PDT 24
Peak memory 214376 kb
Host smart-37025eda-75b2-4b09-830b-b43a1a4ff463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434766147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2434766147
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.206020257
Short name T57
Test name
Test status
Simulation time 45904144 ps
CPU time 1.55 seconds
Started Jun 06 01:54:11 PM PDT 24
Finished Jun 06 01:54:14 PM PDT 24
Peak memory 209776 kb
Host smart-f690cbe1-0e2a-41d6-a95e-97818e9f9694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206020257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.206020257
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2928127961
Short name T605
Test name
Test status
Simulation time 18836182 ps
CPU time 0.74 seconds
Started Jun 06 01:54:15 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 205936 kb
Host smart-d7b5e627-43a2-4d31-9461-bc89c7c25372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928127961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2928127961
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3391972683
Short name T440
Test name
Test status
Simulation time 56271345 ps
CPU time 3.92 seconds
Started Jun 06 01:54:13 PM PDT 24
Finished Jun 06 01:54:18 PM PDT 24
Peak memory 214336 kb
Host smart-72909be3-0bf8-4965-b421-4728dfebb7c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391972683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3391972683
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1403908869
Short name T23
Test name
Test status
Simulation time 80762189 ps
CPU time 1.85 seconds
Started Jun 06 01:54:16 PM PDT 24
Finished Jun 06 01:54:19 PM PDT 24
Peak memory 216968 kb
Host smart-938ea054-5705-4b8a-afdb-b8e3d3cf9572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403908869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1403908869
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1913498703
Short name T349
Test name
Test status
Simulation time 126754768 ps
CPU time 1.89 seconds
Started Jun 06 01:54:16 PM PDT 24
Finished Jun 06 01:54:18 PM PDT 24
Peak memory 208624 kb
Host smart-9b3b0501-b279-4a0a-a4f8-24fcfb100d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913498703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1913498703
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1498587119
Short name T897
Test name
Test status
Simulation time 66604486 ps
CPU time 2.61 seconds
Started Jun 06 01:54:17 PM PDT 24
Finished Jun 06 01:54:21 PM PDT 24
Peak memory 220828 kb
Host smart-5b380ddb-963c-47db-ad2b-4b6f6709227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498587119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1498587119
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.183285152
Short name T612
Test name
Test status
Simulation time 422973678 ps
CPU time 2.74 seconds
Started Jun 06 01:54:12 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 214916 kb
Host smart-2ffd4f36-a350-419d-ab58-548590917e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183285152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.183285152
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2227605762
Short name T554
Test name
Test status
Simulation time 46038467 ps
CPU time 3.09 seconds
Started Jun 06 01:54:15 PM PDT 24
Finished Jun 06 01:54:19 PM PDT 24
Peak memory 207396 kb
Host smart-390adb87-ecc2-4d87-b30f-abcde75ce8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227605762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2227605762
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1676176504
Short name T760
Test name
Test status
Simulation time 156527317 ps
CPU time 4.57 seconds
Started Jun 06 01:54:14 PM PDT 24
Finished Jun 06 01:54:20 PM PDT 24
Peak memory 206860 kb
Host smart-39e0a94d-2a02-4a22-b8b9-15221abd29c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676176504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1676176504
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2620405644
Short name T681
Test name
Test status
Simulation time 6136231941 ps
CPU time 45.85 seconds
Started Jun 06 01:54:21 PM PDT 24
Finished Jun 06 01:55:08 PM PDT 24
Peak memory 209052 kb
Host smart-3a81fb23-6b28-4790-8246-a1a8810add01
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620405644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2620405644
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2998826793
Short name T283
Test name
Test status
Simulation time 56871939 ps
CPU time 2.8 seconds
Started Jun 06 01:54:13 PM PDT 24
Finished Jun 06 01:54:17 PM PDT 24
Peak memory 208760 kb
Host smart-2db89cfb-5895-4a86-bfab-3e2f6d12870f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998826793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2998826793
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2752411279
Short name T121
Test name
Test status
Simulation time 161563507 ps
CPU time 4.56 seconds
Started Jun 06 01:54:12 PM PDT 24
Finished Jun 06 01:54:18 PM PDT 24
Peak memory 208468 kb
Host smart-12905d68-c195-4d6b-b042-356417bc5ca3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752411279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2752411279
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.874417963
Short name T660
Test name
Test status
Simulation time 176515461 ps
CPU time 2.41 seconds
Started Jun 06 01:54:16 PM PDT 24
Finished Jun 06 01:54:19 PM PDT 24
Peak memory 208140 kb
Host smart-0a53bf22-1bd7-4da3-b96f-c151c12af01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874417963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.874417963
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1899379076
Short name T663
Test name
Test status
Simulation time 81035044 ps
CPU time 2.21 seconds
Started Jun 06 01:54:20 PM PDT 24
Finished Jun 06 01:54:23 PM PDT 24
Peak memory 206712 kb
Host smart-f2a4c268-f0d7-4256-b510-b4955f203d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899379076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1899379076
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2830421739
Short name T262
Test name
Test status
Simulation time 1439773524 ps
CPU time 29.86 seconds
Started Jun 06 01:54:16 PM PDT 24
Finished Jun 06 01:54:47 PM PDT 24
Peak memory 222524 kb
Host smart-57d2d2d9-50ca-4f90-aed9-6af51fbb4969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830421739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2830421739
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1017330953
Short name T351
Test name
Test status
Simulation time 215462002 ps
CPU time 3.88 seconds
Started Jun 06 01:54:14 PM PDT 24
Finished Jun 06 01:54:19 PM PDT 24
Peak memory 219916 kb
Host smart-a602f3f1-c3ba-4376-b138-fce0bbf17100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017330953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1017330953
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1417966771
Short name T899
Test name
Test status
Simulation time 177992659 ps
CPU time 3.47 seconds
Started Jun 06 01:54:15 PM PDT 24
Finished Jun 06 01:54:19 PM PDT 24
Peak memory 209756 kb
Host smart-4c9da7f5-6334-44f5-a1b4-f9fafcd1b237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417966771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1417966771
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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