Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11790

1

T1

15

T2

3

T3

10

auto[Attestation]

8413

1

T1

5

T2

3

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	3027	1			T1	2		T2	1		T3	4
auto[Aes]	3662	1			T1	7		T2	1		T4	1
auto[Kmac]	3565	1			T1	5		T2	1		T3	1
auto[Otbn]	3594	1			T2	2		T3	4		T4	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8068	1			T1	4		T2	3		T3	2
auto[OpGenId]	6355	1			T1	6		T2	1		T3	4
auto[OpGenSwOut]	6482	1			T1	11		T2	4		T3	4
auto[OpGenHwOut]	7366	1			T1	3		T2	1		T3	5
auto[OpDisable]	136	1			T3	1		T5	1		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11141

1

T1

10

T2

7

T3

2

auto[OpDoneFail]

17266

1

T1

14

T2

2

T3

14

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	7245	1			T1	12		T2	1		T3	9
auto[StInit]	4017	1			T1	4		T2	3		T3	4
auto[StCreatorRootKey]	3354	1			T1	5		T2	4		T4	2
auto[StOwnerIntKey]	2903	1			T1	2		T2	1		T4	2
auto[StOwnerKey]	2559	1			T1	1		T4	2		T11	2
auto[StDisabled]	8329	1			T3	3		T4	7		T11	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	367	1			T52	1		T6	2		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	121	1			T5	2		T12	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	99	1			T5	1		T13	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	82	1			T5	1		T52	2		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	77	1			T118	1		T52	3		T136	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	221	1			T52	1		T136	2		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	391	1			T1	4		T199	1		T118	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	124	1			T1	1		T35	1		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	84	1			T14	2		T119	3		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	75	1			T136	1		T6	2		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T1	1		T52	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	237	1			T5	2		T14	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	351	1			T1	3		T3	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	106	1			T2	1		T5	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T5	1		T200	1		T65	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T5	1		T52	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	76	1			T6	1		T198	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	241	1			T23	1		T52	1		T136	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	340	1			T52	1		T56	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	102	1			T119	1		T6	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	80	1			T2	1		T103	1		T57	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	67	1			T5	1		T48	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	64	1			T52	1		T6	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	227	1			T3	1		T4	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	124	1			T5	4		T52	4		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	130	1			T1	1		T3	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	101	1			T2	1		T5	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	78	1			T88	1		T199	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	76	1			T5	1		T52	1		T136	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	203	1			T5	1		T88	1		T52	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	117	1			T52	1		T6	2		T57	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	93	1			T5	2		T52	1		T57	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	95	1			T1	1		T5	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	76	1			T4	1		T88	1		T52	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	60	1			T52	1		T201	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	235	1			T52	2		T201	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	90	1			T5	2		T52	1		T103	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	116	1			T52	1		T6	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T13	1		T52	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	73	1			T199	1		T103	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	60	1			T48	1		T52	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	195	1			T4	1		T14	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	111	1			T52	1		T6	1		T57	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	138	1			T2	1		T3	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T69	1		T141	1		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	71	1			T199	1		T6	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T5	1		T52	1		T136	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	245	1			T88	1		T118	1		T52	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	296	1			T1	1		T3	2		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	98	1			T5	1		T52	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	70	1			T118	1		T48	1		T52	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T118	1		T48	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T5	1		T103	2		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	186	1			T3	1		T5	2		T118	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	482	1			T44	2		T203	10		T135	7
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	126	1			T88	1		T44	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	125	1			T2	1		T33	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	106	1			T88	3		T44	1		T199	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	77	1			T14	1		T205	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	283	1			T23	1		T44	3		T205	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	506	1			T1	2		T43	6		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	132	1			T4	1		T206	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T43	1		T52	1		T6	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T5	1		T33	2		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	87	1			T14	1		T206	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	259	1			T4	1		T5	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	510	1			T3	2		T23	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	106	1			T11	1		T52	1		T136	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	117	1			T11	1		T52	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T33	1		T52	3		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T118	1		T208	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	292	1			T11	3		T5	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	95	1			T52	4		T57	1		T7	5
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	101	1			T52	1		T201	1		T57	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	82	1			T118	1		T52	2		T133	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	66	1			T5	1		T14	1		T52	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T4	1		T6	1		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	175	1			T4	1		T5	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	91	1			T52	3		T57	1		T7	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	121	1			T205	1		T52	2		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	110	1			T14	1		T205	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	103	1			T5	1		T23	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	78	1			T5	1		T14	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	314	1			T5	1		T44	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	92	1			T52	3		T103	1		T57	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	131	1			T12	1		T43	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	122	1			T5	1		T199	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T5	1		T14	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	78	1			T5	1		T43	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	277	1			T23	2		T88	1		T118	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	84	1			T52	3		T103	2		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	121	1			T199	1		T118	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	126	1			T199	2		T138	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T11	1		T14	1		T33	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	79	1			T11	1		T52	1		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	293	1			T11	1		T5	2		T23	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	237	1			T5	2		T13	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	730	1			T5	2		T12	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	205	1			T1	1		T14	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	765	1			T1	5		T5	2		T14	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	237	1			T5	2		T52	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	719	1			T1	3		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T2	1		T5	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	684	1			T3	1		T4	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	231	1			T2	1		T5	2		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	481	1			T1	1		T3	1		T5	7
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	218	1			T1	1		T4	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	458	1			T5	2		T52	6		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	201	1			T13	1		T199	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	424	1			T4	1		T5	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	189	1			T5	1		T199	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	507	1			T2	1		T3	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	181	1			T5	1		T118	2		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	596	1			T1	1		T3	3		T5	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	290	1			T2	1		T14	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	909	1			T23	1		T88	2		T44	6
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	282	1			T5	1		T14	1		T33	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	911	1			T1	2		T4	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	288	1			T11	1		T33	1		T118	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	920	1			T3	2		T11	4		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	179	1			T4	1		T5	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	392	1			T4	1		T5	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	277	1			T5	2		T14	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	540	1			T5	1		T14	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T5	3		T14	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	514	1			T12	1		T23	2		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	295	1			T11	2		T33	2		T199	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	515	1			T11	1		T5	2		T14	1