Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34929

1

T1

26

T2

10

T3

17

auto[1]

299

1

T118

8

T119

5

T130

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	34936	1			T1	26		T2	10		T3	17
auto[134217728:268435455]	8	1			T154	2		T234	1		T294	1
auto[268435456:402653183]	12	1			T119	1		T130	1		T252	2
auto[402653184:536870911]	5	1			T347	1		T240	1		T262	1
auto[536870912:671088639]	8	1			T118	1		T141	1		T278	1
auto[671088640:805306367]	7	1			T130	1		T141	1		T142	1
auto[805306368:939524095]	8	1			T130	1		T252	1		T360	1
auto[939524096:1073741823]	10	1			T194	1		T252	1		T240	1
auto[1073741824:1207959551]	15	1			T118	1		T251	1		T239	1
auto[1207959552:1342177279]	12	1			T154	2		T82	1		T144	1
auto[1342177280:1476395007]	14	1			T118	1		T119	1		T82	1
auto[1476395008:1610612735]	7	1			T119	1		T141	1		T142	1
auto[1610612736:1744830463]	8	1			T252	1		T240	1		T353	1
auto[1744830464:1879048191]	7	1			T118	1		T277	1		T360	2
auto[1879048192:2013265919]	10	1			T154	1		T251	1		T239	1
auto[2013265920:2147483647]	6	1			T278	1		T252	1		T334	1
auto[2147483648:2281701375]	4	1			T252	1		T282	1		T360	1
auto[2281701376:2415919103]	5	1			T237	1		T328	1		T361	1
auto[2415919104:2550136831]	6	1			T347	1		T239	1		T360	1
auto[2550136832:2684354559]	10	1			T119	2		T154	1		T277	2
auto[2684354560:2818572287]	10	1			T154	2		T239	1		T261	1
auto[2818572288:2952790015]	9	1			T278	1		T277	1		T300	1
auto[2952790016:3087007743]	13	1			T130	1		T142	1		T261	1
auto[3087007744:3221225471]	7	1			T251	1		T300	2		T362	1
auto[3221225472:3355443199]	12	1			T118	3		T252	1		T262	1
auto[3355443200:3489660927]	8	1			T251	1		T334	1		T353	1
auto[3489660928:3623878655]	12	1			T278	1		T239	1		T240	1
auto[3623878656:3758096383]	14	1			T154	2		T142	1		T300	1
auto[3758096384:3892314111]	8	1			T141	1		T278	1		T334	1
auto[3892314112:4026531839]	17	1			T130	1		T154	1		T194	1
auto[4026531840:4160749567]	11	1			T118	1		T277	1		T328	1
auto[4160749568:4294967295]	9	1			T277	1		T282	1		T363	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	34929	1			T1	26		T2	10		T3	17
auto[0:134217727]	auto[1]	7	1			T130	1		T154	1		T364	1
auto[134217728:268435455]	auto[1]	8	1			T154	2		T234	1		T294	1
auto[268435456:402653183]	auto[1]	12	1			T119	1		T130	1		T252	2
auto[402653184:536870911]	auto[1]	5	1			T347	1		T240	1		T262	1
auto[536870912:671088639]	auto[1]	8	1			T118	1		T141	1		T278	1
auto[671088640:805306367]	auto[1]	7	1			T130	1		T141	1		T142	1
auto[805306368:939524095]	auto[1]	8	1			T130	1		T252	1		T360	1
auto[939524096:1073741823]	auto[1]	10	1			T194	1		T252	1		T240	1
auto[1073741824:1207959551]	auto[1]	15	1			T118	1		T251	1		T239	1
auto[1207959552:1342177279]	auto[1]	12	1			T154	2		T82	1		T144	1
auto[1342177280:1476395007]	auto[1]	14	1			T118	1		T119	1		T82	1
auto[1476395008:1610612735]	auto[1]	7	1			T119	1		T141	1		T142	1
auto[1610612736:1744830463]	auto[1]	8	1			T252	1		T240	1		T353	1
auto[1744830464:1879048191]	auto[1]	7	1			T118	1		T277	1		T360	2
auto[1879048192:2013265919]	auto[1]	10	1			T154	1		T251	1		T239	1
auto[2013265920:2147483647]	auto[1]	6	1			T278	1		T252	1		T334	1
auto[2147483648:2281701375]	auto[1]	4	1			T252	1		T282	1		T360	1
auto[2281701376:2415919103]	auto[1]	5	1			T237	1		T328	1		T361	1
auto[2415919104:2550136831]	auto[1]	6	1			T347	1		T239	1		T360	1
auto[2550136832:2684354559]	auto[1]	10	1			T119	2		T154	1		T277	2
auto[2684354560:2818572287]	auto[1]	10	1			T154	2		T239	1		T261	1
auto[2818572288:2952790015]	auto[1]	9	1			T278	1		T277	1		T300	1
auto[2952790016:3087007743]	auto[1]	13	1			T130	1		T142	1		T261	1
auto[3087007744:3221225471]	auto[1]	7	1			T251	1		T300	2		T362	1
auto[3221225472:3355443199]	auto[1]	12	1			T118	3		T252	1		T262	1
auto[3355443200:3489660927]	auto[1]	8	1			T251	1		T334	1		T353	1
auto[3489660928:3623878655]	auto[1]	12	1			T278	1		T239	1		T240	1
auto[3623878656:3758096383]	auto[1]	14	1			T154	2		T142	1		T300	1
auto[3758096384:3892314111]	auto[1]	8	1			T141	1		T278	1		T334	1
auto[3892314112:4026531839]	auto[1]	17	1			T130	1		T154	1		T194	1
auto[4026531840:4160749567]	auto[1]	11	1			T118	1		T277	1		T328	1
auto[4160749568:4294967295]	auto[1]	9	1			T277	1		T282	1		T363	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1650

1

T3

2

T5

5

T14

2

auto[1]

1870

1

T5

11

T12

1

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	116	1			T5	1		T23	1		T52	1
auto[134217728:268435455]	95	1			T118	1		T52	1		T103	2
auto[268435456:402653183]	124	1			T33	1		T52	3		T201	1
auto[402653184:536870911]	93	1			T14	1		T118	1		T52	1
auto[536870912:671088639]	92	1			T198	1		T103	1		T45	1
auto[671088640:805306367]	128	1			T5	1		T52	1		T56	1
auto[805306368:939524095]	118	1			T5	2		T52	1		T6	1
auto[939524096:1073741823]	121	1			T118	1		T52	2		T201	1
auto[1073741824:1207959551]	109	1			T23	1		T88	1		T52	1
auto[1207959552:1342177279]	102	1			T199	1		T48	1		T6	1
auto[1342177280:1476395007]	119	1			T34	1		T52	2		T136	1
auto[1476395008:1610612735]	115	1			T5	1		T6	1		T200	1
auto[1610612736:1744830463]	124	1			T33	1		T34	1		T6	2
auto[1744830464:1879048191]	94	1			T118	1		T65	1		T133	1
auto[1879048192:2013265919]	104	1			T5	2		T119	1		T136	1
auto[2013265920:2147483647]	100	1			T5	2		T34	1		T6	1
auto[2147483648:2281701375]	106	1			T14	1		T199	1		T136	1
auto[2281701376:2415919103]	111	1			T5	1		T56	1		T6	1
auto[2415919104:2550136831]	119	1			T52	1		T119	1		T49	1
auto[2550136832:2684354559]	100	1			T3	1		T5	2		T6	2
auto[2684354560:2818572287]	122	1			T199	2		T49	1		T69	1
auto[2818572288:2952790015]	114	1			T3	1		T52	1		T6	1
auto[2952790016:3087007743]	123	1			T12	1		T88	1		T56	1
auto[3087007744:3221225471]	102	1			T5	1		T14	1		T52	1
auto[3221225472:3355443199]	125	1			T34	2		T118	1		T52	1
auto[3355443200:3489660927]	88	1			T23	1		T34	1		T52	2
auto[3489660928:3623878655]	112	1			T14	1		T88	1		T56	1
auto[3623878656:3758096383]	108	1			T5	1		T52	3		T49	1
auto[3758096384:3892314111]	123	1			T5	1		T52	2		T119	1
auto[3892314112:4026531839]	110	1			T5	1		T103	1		T57	1
auto[4026531840:4160749567]	86	1			T50	1		T57	3		T69	1
auto[4160749568:4294967295]	117	1			T33	1		T23	1		T201	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T23	1		T49	1		T6	1
auto[0:134217727]	auto[1]	72	1			T5	1		T52	1		T6	2
auto[134217728:268435455]	auto[0]	49	1			T118	1		T52	1		T103	1
auto[134217728:268435455]	auto[1]	46	1			T103	1		T57	1		T66	1
auto[268435456:402653183]	auto[0]	49	1			T33	1		T52	1		T200	1
auto[268435456:402653183]	auto[1]	75	1			T52	2		T201	1		T119	1
auto[402653184:536870911]	auto[0]	36	1			T52	1		T6	1		T46	1
auto[402653184:536870911]	auto[1]	57	1			T14	1		T118	1		T141	2
auto[536870912:671088639]	auto[0]	41	1			T198	1		T45	1		T19	1
auto[536870912:671088639]	auto[1]	51	1			T103	1		T7	1		T47	1
auto[671088640:805306367]	auto[0]	71	1			T52	1		T56	1		T103	1
auto[671088640:805306367]	auto[1]	57	1			T5	1		T82	2		T142	1
auto[805306368:939524095]	auto[0]	63	1			T52	1		T62	1		T53	1
auto[805306368:939524095]	auto[1]	55	1			T5	2		T6	1		T50	1
auto[939524096:1073741823]	auto[0]	56	1			T52	1		T6	1		T245	2
auto[939524096:1073741823]	auto[1]	65	1			T118	1		T52	1		T201	1
auto[1073741824:1207959551]	auto[0]	55	1			T52	1		T201	1		T19	1
auto[1073741824:1207959551]	auto[1]	54	1			T23	1		T88	1		T119	1
auto[1207959552:1342177279]	auto[0]	48	1			T199	1		T45	1		T133	1
auto[1207959552:1342177279]	auto[1]	54	1			T48	1		T6	1		T139	1
auto[1342177280:1476395007]	auto[0]	43	1			T34	1		T52	1		T6	1
auto[1342177280:1476395007]	auto[1]	76	1			T52	1		T136	1		T6	1
auto[1476395008:1610612735]	auto[0]	49	1			T5	1		T65	1		T202	1
auto[1476395008:1610612735]	auto[1]	66	1			T6	1		T200	1		T69	1
auto[1610612736:1744830463]	auto[0]	57	1			T33	1		T34	1		T27	1
auto[1610612736:1744830463]	auto[1]	67	1			T6	2		T57	1		T62	1
auto[1744830464:1879048191]	auto[0]	47	1			T118	1		T190	1		T323	1
auto[1744830464:1879048191]	auto[1]	47	1			T65	1		T133	1		T331	1
auto[1879048192:2013265919]	auto[0]	50	1			T5	1		T136	1		T69	1
auto[1879048192:2013265919]	auto[1]	54	1			T5	1		T119	1		T57	2
auto[2013265920:2147483647]	auto[0]	47	1			T34	1		T6	1		T47	2
auto[2013265920:2147483647]	auto[1]	53	1			T5	2		T103	1		T57	1
auto[2147483648:2281701375]	auto[0]	56	1			T14	1		T57	1		T66	1
auto[2147483648:2281701375]	auto[1]	50	1			T199	1		T136	1		T6	1
auto[2281701376:2415919103]	auto[0]	51	1			T5	1		T56	1		T6	1
auto[2281701376:2415919103]	auto[1]	60	1			T45	1		T57	1		T202	1
auto[2415919104:2550136831]	auto[0]	51	1			T49	1		T245	1		T87	1
auto[2415919104:2550136831]	auto[1]	68	1			T52	1		T119	1		T6	1
auto[2550136832:2684354559]	auto[0]	45	1			T3	1		T6	1		T245	1
auto[2550136832:2684354559]	auto[1]	55	1			T5	2		T6	1		T50	1
auto[2684354560:2818572287]	auto[0]	58	1			T199	1		T49	1		T69	1
auto[2684354560:2818572287]	auto[1]	64	1			T199	1		T62	1		T139	1
auto[2818572288:2952790015]	auto[0]	59	1			T3	1		T52	1		T6	1
auto[2818572288:2952790015]	auto[1]	55	1			T200	1		T28	1		T60	1
auto[2952790016:3087007743]	auto[0]	57	1			T88	1		T56	1		T57	1
auto[2952790016:3087007743]	auto[1]	66	1			T12	1		T6	1		T37	1
auto[3087007744:3221225471]	auto[0]	50	1			T119	1		T45	1		T58	1
auto[3087007744:3221225471]	auto[1]	52	1			T5	1		T14	1		T52	1
auto[3221225472:3355443199]	auto[0]	58	1			T34	1		T57	1		T53	2
auto[3221225472:3355443199]	auto[1]	67	1			T34	1		T118	1		T52	1
auto[3355443200:3489660927]	auto[0]	41	1			T34	1		T52	1		T130	1
auto[3355443200:3489660927]	auto[1]	47	1			T23	1		T52	1		T58	1
auto[3489660928:3623878655]	auto[0]	49	1			T14	1		T56	1		T45	1
auto[3489660928:3623878655]	auto[1]	63	1			T88	1		T57	1		T331	1
auto[3623878656:3758096383]	auto[0]	53	1			T49	1		T103	1		T73	1
auto[3623878656:3758096383]	auto[1]	55	1			T5	1		T52	3		T50	1
auto[3758096384:3892314111]	auto[0]	57	1			T5	1		T52	1		T119	1
auto[3758096384:3892314111]	auto[1]	66	1			T52	1		T6	1		T272	1
auto[3892314112:4026531839]	auto[0]	56	1			T5	1		T103	1		T57	1
auto[3892314112:4026531839]	auto[1]	54	1			T69	1		T65	1		T66	1
auto[4026531840:4160749567]	auto[0]	48	1			T50	1		T57	2		T69	1
auto[4026531840:4160749567]	auto[1]	38	1			T57	1		T130	1		T154	1
auto[4160749568:4294967295]	auto[0]	56	1			T33	1		T23	1		T56	1
auto[4160749568:4294967295]	auto[1]	61	1			T201	1		T198	1		T57	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1659

1

T3

1

T5

6

T14

1

auto[1]

1861

1

T3

1

T5

10

T12

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T14	1		T23	1		T52	1
auto[134217728:268435455]	96	1			T48	1		T201	1		T6	1
auto[268435456:402653183]	120	1			T3	1		T5	1		T33	1
auto[402653184:536870911]	112	1			T118	1		T6	1		T57	1
auto[536870912:671088639]	109	1			T5	1		T23	1		T103	1
auto[671088640:805306367]	92	1			T5	1		T23	1		T52	1
auto[805306368:939524095]	123	1			T5	1		T88	1		T34	1
auto[939524096:1073741823]	106	1			T5	1		T6	1		T45	2
auto[1073741824:1207959551]	99	1			T5	1		T103	2		T57	1
auto[1207959552:1342177279]	101	1			T88	2		T56	1		T50	1
auto[1342177280:1476395007]	113	1			T201	1		T198	1		T69	1
auto[1476395008:1610612735]	102	1			T199	1		T34	1		T52	1
auto[1610612736:1744830463]	113	1			T5	1		T12	1		T199	1
auto[1744830464:1879048191]	122	1			T5	1		T14	1		T136	1
auto[1879048192:2013265919]	112	1			T14	1		T34	1		T52	1
auto[2013265920:2147483647]	98	1			T6	1		T62	1		T245	1
auto[2147483648:2281701375]	93	1			T52	1		T6	1		T103	1
auto[2281701376:2415919103]	115	1			T5	1		T52	1		T119	1
auto[2415919104:2550136831]	105	1			T119	1		T49	1		T56	1
auto[2550136832:2684354559]	132	1			T33	1		T199	1		T34	1
auto[2684354560:2818572287]	115	1			T14	1		T119	1		T6	1
auto[2818572288:2952790015]	118	1			T6	2		T27	1		T69	1
auto[2952790016:3087007743]	125	1			T34	1		T6	3		T103	1
auto[3087007744:3221225471]	105	1			T118	1		T52	1		T119	1
auto[3221225472:3355443199]	108	1			T5	1		T33	1		T118	1
auto[3355443200:3489660927]	109	1			T52	3		T136	1		T49	1
auto[3489660928:3623878655]	107	1			T5	1		T201	1		T49	2
auto[3623878656:3758096383]	143	1			T5	2		T52	2		T6	1
auto[3758096384:3892314111]	116	1			T3	1		T5	2		T52	2
auto[3892314112:4026531839]	102	1			T23	1		T118	1		T52	3
auto[4026531840:4160749567]	100	1			T5	1		T199	1		T118	1
auto[4160749568:4294967295]	112	1			T34	1		T52	2		T119	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T23	1		T198	1		T103	1
auto[0:134217727]	auto[1]	55	1			T14	1		T52	1		T201	1
auto[134217728:268435455]	auto[0]	46	1			T6	1		T103	1		T86	1
auto[134217728:268435455]	auto[1]	50	1			T48	1		T201	1		T272	1
auto[268435456:402653183]	auto[0]	54	1			T3	1		T5	1		T33	1
auto[268435456:402653183]	auto[1]	66	1			T6	1		T65	2		T141	1
auto[402653184:536870911]	auto[0]	50	1			T112	1		T64	1		T323	1
auto[402653184:536870911]	auto[1]	62	1			T118	1		T6	1		T57	1
auto[536870912:671088639]	auto[0]	50	1			T5	1		T142	1		T64	1
auto[536870912:671088639]	auto[1]	59	1			T23	1		T103	1		T200	1
auto[671088640:805306367]	auto[0]	47	1			T23	1		T52	1		T66	1
auto[671088640:805306367]	auto[1]	45	1			T5	1		T6	1		T57	2
auto[805306368:939524095]	auto[0]	54	1			T34	1		T103	1		T57	1
auto[805306368:939524095]	auto[1]	69	1			T5	1		T88	1		T331	1
auto[939524096:1073741823]	auto[0]	51	1			T45	1		T62	1		T53	1
auto[939524096:1073741823]	auto[1]	55	1			T5	1		T6	1		T45	1
auto[1073741824:1207959551]	auto[0]	41	1			T57	1		T245	1		T54	1
auto[1073741824:1207959551]	auto[1]	58	1			T5	1		T103	2		T272	1
auto[1207959552:1342177279]	auto[0]	45	1			T56	1		T57	1		T66	1
auto[1207959552:1342177279]	auto[1]	56	1			T88	2		T50	1		T57	3
auto[1342177280:1476395007]	auto[0]	47	1			T85	1		T64	1		T237	1
auto[1342177280:1476395007]	auto[1]	66	1			T201	1		T198	1		T69	1
auto[1476395008:1610612735]	auto[0]	51	1			T34	1		T52	1		T6	1
auto[1476395008:1610612735]	auto[1]	51	1			T199	1		T6	1		T57	1
auto[1610612736:1744830463]	auto[0]	60	1			T5	1		T52	1		T56	1
auto[1610612736:1744830463]	auto[1]	53	1			T12	1		T199	1		T50	1
auto[1744830464:1879048191]	auto[0]	54	1			T14	1		T56	1		T46	1
auto[1744830464:1879048191]	auto[1]	68	1			T5	1		T136	1		T19	1
auto[1879048192:2013265919]	auto[0]	57	1			T34	1		T57	1		T331	1
auto[1879048192:2013265919]	auto[1]	55	1			T14	1		T52	1		T36	1
auto[2013265920:2147483647]	auto[0]	47	1			T62	1		T245	1		T7	1
auto[2013265920:2147483647]	auto[1]	51	1			T6	1		T73	1		T47	2
auto[2147483648:2281701375]	auto[0]	41	1			T52	1		T200	1		T65	1
auto[2147483648:2281701375]	auto[1]	52	1			T6	1		T103	1		T27	1
auto[2281701376:2415919103]	auto[0]	51	1			T119	1		T130	1		T245	1
auto[2281701376:2415919103]	auto[1]	64	1			T5	1		T52	1		T133	2
auto[2415919104:2550136831]	auto[0]	52	1			T119	1		T49	1		T56	1
auto[2415919104:2550136831]	auto[1]	53	1			T198	1		T130	1		T272	1
auto[2550136832:2684354559]	auto[0]	66	1			T33	1		T199	1		T34	1
auto[2550136832:2684354559]	auto[1]	66	1			T136	1		T62	1		T28	1
auto[2684354560:2818572287]	auto[0]	50	1			T119	1		T45	2		T57	1
auto[2684354560:2818572287]	auto[1]	65	1			T14	1		T6	1		T57	1
auto[2818572288:2952790015]	auto[0]	47	1			T69	1		T245	1		T278	2
auto[2818572288:2952790015]	auto[1]	71	1			T6	2		T27	1		T202	1
auto[2952790016:3087007743]	auto[0]	63	1			T34	1		T6	2		T103	1
auto[2952790016:3087007743]	auto[1]	62	1			T6	1		T50	1		T130	1
auto[3087007744:3221225471]	auto[0]	55	1			T52	1		T119	1		T202	1
auto[3087007744:3221225471]	auto[1]	50	1			T118	1		T6	1		T50	1
auto[3221225472:3355443199]	auto[0]	61	1			T5	1		T118	1		T52	1
auto[3221225472:3355443199]	auto[1]	47	1			T33	1		T52	1		T119	1
auto[3355443200:3489660927]	auto[0]	53	1			T52	2		T49	1		T53	1
auto[3355443200:3489660927]	auto[1]	56	1			T52	1		T136	1		T200	1
auto[3489660928:3623878655]	auto[0]	45	1			T201	1		T49	1		T81	1
auto[3489660928:3623878655]	auto[1]	62	1			T5	1		T49	1		T103	1
auto[3623878656:3758096383]	auto[0]	70	1			T5	1		T6	1		T245	2
auto[3623878656:3758096383]	auto[1]	73	1			T5	1		T52	2		T45	1
auto[3758096384:3892314111]	auto[0]	51	1			T5	1		T193	1		T20	1
auto[3758096384:3892314111]	auto[1]	65	1			T3	1		T5	1		T52	2
auto[3892314112:4026531839]	auto[0]	49	1			T52	1		T57	1		T245	1
auto[3892314112:4026531839]	auto[1]	53	1			T23	1		T118	1		T52	2
auto[4026531840:4160749567]	auto[0]	48	1			T199	1		T118	1		T6	1
auto[4026531840:4160749567]	auto[1]	52	1			T5	1		T52	1		T6	1
auto[4160749568:4294967295]	auto[0]	61	1			T34	1		T52	2		T119	1
auto[4160749568:4294967295]	auto[1]	51	1			T50	1		T200	1		T143	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1670

1

T3

2

T5

5

T14

2

auto[1]

1850

1

T5

11

T12

1

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T23	1		T52	1		T49	1
auto[134217728:268435455]	130	1			T5	1		T34	1		T52	1
auto[268435456:402653183]	121	1			T52	3		T6	1		T45	1
auto[402653184:536870911]	103	1			T6	1		T103	1		T245	2
auto[536870912:671088639]	108	1			T5	1		T199	1		T130	1
auto[671088640:805306367]	103	1			T3	1		T5	1		T23	1
auto[805306368:939524095]	106	1			T49	1		T50	1		T45	1
auto[939524096:1073741823]	116	1			T12	1		T23	1		T16	1
auto[1073741824:1207959551]	121	1			T5	1		T33	1		T118	2
auto[1207959552:1342177279]	117	1			T5	1		T52	2		T6	1
auto[1342177280:1476395007]	95	1			T5	1		T14	1		T118	1
auto[1476395008:1610612735]	104	1			T6	1		T103	1		T57	2
auto[1610612736:1744830463]	110	1			T5	1		T201	1		T6	1
auto[1744830464:1879048191]	89	1			T48	1		T6	1		T103	1
auto[1879048192:2013265919]	117	1			T5	1		T14	1		T199	1
auto[2013265920:2147483647]	133	1			T199	1		T52	2		T201	1
auto[2147483648:2281701375]	108	1			T52	3		T119	1		T136	1
auto[2281701376:2415919103]	117	1			T199	1		T136	1		T103	1
auto[2415919104:2550136831]	123	1			T118	1		T52	2		T49	1
auto[2550136832:2684354559]	118	1			T5	1		T33	1		T52	3
auto[2684354560:2818572287]	81	1			T5	1		T33	1		T19	1
auto[2818572288:2952790015]	106	1			T5	1		T119	1		T6	3
auto[2952790016:3087007743]	105	1			T5	1		T52	1		T69	1
auto[3087007744:3221225471]	113	1			T34	1		T118	1		T57	1
auto[3221225472:3355443199]	103	1			T5	1		T52	1		T119	1
auto[3355443200:3489660927]	109	1			T23	1		T6	1		T198	1
auto[3489660928:3623878655]	104	1			T3	1		T56	1		T57	1
auto[3623878656:3758096383]	99	1			T14	1		T201	1		T6	1
auto[3758096384:3892314111]	122	1			T88	2		T34	1		T119	1
auto[3892314112:4026531839]	122	1			T5	1		T14	1		T52	1
auto[4026531840:4160749567]	104	1			T5	1		T52	1		T6	2
auto[4160749568:4294967295]	105	1			T5	1		T6	1		T103	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T23	1		T49	1		T56	1
auto[0:134217727]	auto[1]	50	1			T52	1		T200	1		T133	1
auto[134217728:268435455]	auto[0]	62	1			T34	1		T6	1		T103	2
auto[134217728:268435455]	auto[1]	68	1			T5	1		T52	1		T201	1
auto[268435456:402653183]	auto[0]	69	1			T52	1		T45	1		T66	1
auto[268435456:402653183]	auto[1]	52	1			T52	2		T6	1		T58	1
auto[402653184:536870911]	auto[0]	53	1			T245	2		T46	1		T38	1
auto[402653184:536870911]	auto[1]	50	1			T6	1		T103	1		T141	1
auto[536870912:671088639]	auto[0]	51	1			T245	2		T87	1		T7	1
auto[536870912:671088639]	auto[1]	57	1			T5	1		T199	1		T130	1
auto[671088640:805306367]	auto[0]	49	1			T3	1		T34	2		T53	1
auto[671088640:805306367]	auto[1]	54	1			T5	1		T23	1		T88	1
auto[805306368:939524095]	auto[0]	54	1			T49	1		T45	1		T57	2
auto[805306368:939524095]	auto[1]	52	1			T50	1		T57	1		T66	1
auto[939524096:1073741823]	auto[0]	49	1			T23	1		T57	1		T85	1
auto[939524096:1073741823]	auto[1]	67	1			T12	1		T16	1		T57	2
auto[1073741824:1207959551]	auto[0]	54	1			T33	1		T118	1		T119	1
auto[1073741824:1207959551]	auto[1]	67	1			T5	1		T118	1		T52	1
auto[1207959552:1342177279]	auto[0]	47	1			T103	1		T62	1		T133	1
auto[1207959552:1342177279]	auto[1]	70	1			T5	1		T52	2		T6	1
auto[1342177280:1476395007]	auto[0]	45	1			T14	1		T130	1		T85	1
auto[1342177280:1476395007]	auto[1]	50	1			T5	1		T118	1		T56	1
auto[1476395008:1610612735]	auto[0]	49	1			T53	1		T46	1		T7	1
auto[1476395008:1610612735]	auto[1]	55	1			T6	1		T103	1		T57	2
auto[1610612736:1744830463]	auto[0]	48	1			T6	1		T45	1		T94	1
auto[1610612736:1744830463]	auto[1]	62	1			T5	1		T201	1		T58	1
auto[1744830464:1879048191]	auto[0]	40	1			T6	1		T245	1		T190	1
auto[1744830464:1879048191]	auto[1]	49	1			T48	1		T103	1		T200	1
auto[1879048192:2013265919]	auto[0]	58	1			T5	1		T52	1		T49	1
auto[1879048192:2013265919]	auto[1]	59	1			T14	1		T199	1		T52	1
auto[2013265920:2147483647]	auto[0]	52	1			T52	1		T56	1		T245	1
auto[2013265920:2147483647]	auto[1]	81	1			T199	1		T52	1		T201	1
auto[2147483648:2281701375]	auto[0]	48	1			T52	1		T119	1		T73	1
auto[2147483648:2281701375]	auto[1]	60	1			T52	2		T136	1		T6	2
auto[2281701376:2415919103]	auto[0]	54	1			T57	1		T62	1		T66	1
auto[2281701376:2415919103]	auto[1]	63	1			T199	1		T136	1		T103	1
auto[2415919104:2550136831]	auto[0]	52	1			T118	1		T52	1		T66	1
auto[2415919104:2550136831]	auto[1]	71	1			T52	1		T49	1		T6	1
auto[2550136832:2684354559]	auto[0]	59	1			T33	1		T52	2		T119	1
auto[2550136832:2684354559]	auto[1]	59	1			T5	1		T52	1		T50	1
auto[2684354560:2818572287]	auto[0]	38	1			T5	1		T331	1		T20	1
auto[2684354560:2818572287]	auto[1]	43	1			T33	1		T19	1		T331	1
auto[2818572288:2952790015]	auto[0]	44	1			T5	1		T6	1		T57	1
auto[2818572288:2952790015]	auto[1]	62	1			T119	1		T6	2		T103	1
auto[2952790016:3087007743]	auto[0]	50	1			T52	1		T87	1		T7	1
auto[2952790016:3087007743]	auto[1]	55	1			T5	1		T69	1		T66	1
auto[3087007744:3221225471]	auto[0]	57	1			T34	1		T57	1		T69	1
auto[3087007744:3221225471]	auto[1]	56	1			T118	1		T141	1		T64	2
auto[3221225472:3355443199]	auto[0]	50	1			T52	1		T45	1		T69	1
auto[3221225472:3355443199]	auto[1]	53	1			T5	1		T119	1		T50	1
auto[3355443200:3489660927]	auto[0]	56	1			T198	1		T331	1		T46	2
auto[3355443200:3489660927]	auto[1]	53	1			T23	1		T6	1		T65	1
auto[3489660928:3623878655]	auto[0]	52	1			T3	1		T57	1		T245	1
auto[3489660928:3623878655]	auto[1]	52	1			T56	1		T331	1		T112	1
auto[3623878656:3758096383]	auto[0]	56	1			T14	1		T201	1		T6	1
auto[3623878656:3758096383]	auto[1]	43	1			T198	1		T130	1		T7	1
auto[3758096384:3892314111]	auto[0]	63	1			T88	1		T34	1		T57	1
auto[3758096384:3892314111]	auto[1]	59	1			T88	1		T119	1		T6	2
auto[3892314112:4026531839]	auto[0]	62	1			T5	1		T52	1		T202	2
auto[3892314112:4026531839]	auto[1]	60	1			T14	1		T6	2		T45	1
auto[4026531840:4160749567]	auto[0]	40	1			T52	1		T6	1		T81	1
auto[4026531840:4160749567]	auto[1]	64	1			T5	1		T6	1		T57	1
auto[4160749568:4294967295]	auto[0]	51	1			T5	1		T6	1		T103	1
auto[4160749568:4294967295]	auto[1]	54	1			T50	1		T139	1		T142	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1646

1

T3

1

T5

3

T14

2

auto[1]

1873

1

T3

1

T5

13

T12

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T34	1		T48	1		T201	1
auto[134217728:268435455]	115	1			T14	1		T52	2		T6	1
auto[268435456:402653183]	107	1			T52	2		T201	1		T6	1
auto[402653184:536870911]	107	1			T34	1		T49	1		T82	1
auto[536870912:671088639]	87	1			T199	1		T52	1		T56	1
auto[671088640:805306367]	111	1			T5	1		T23	1		T118	1
auto[805306368:939524095]	90	1			T6	1		T103	1		T57	1
auto[939524096:1073741823]	116	1			T6	2		T50	2		T45	1
auto[1073741824:1207959551]	105	1			T3	1		T52	1		T56	1
auto[1207959552:1342177279]	131	1			T5	1		T50	1		T57	1
auto[1342177280:1476395007]	118	1			T34	1		T49	1		T6	1
auto[1476395008:1610612735]	111	1			T5	2		T52	1		T119	1
auto[1610612736:1744830463]	101	1			T118	2		T50	1		T45	1
auto[1744830464:1879048191]	101	1			T52	2		T119	1		T6	2
auto[1879048192:2013265919]	107	1			T5	1		T199	1		T34	1
auto[2013265920:2147483647]	106	1			T12	1		T14	1		T88	1
auto[2147483648:2281701375]	91	1			T23	1		T6	1		T103	1
auto[2281701376:2415919103]	131	1			T5	1		T52	1		T56	1
auto[2415919104:2550136831]	100	1			T33	1		T52	1		T6	2
auto[2550136832:2684354559]	108	1			T33	1		T52	1		T6	1
auto[2684354560:2818572287]	140	1			T5	1		T23	1		T52	1
auto[2818572288:2952790015]	109	1			T3	1		T5	1		T23	1
auto[2952790016:3087007743]	114	1			T5	1		T33	1		T6	2
auto[3087007744:3221225471]	116	1			T14	1		T52	2		T16	1
auto[3221225472:3355443199]	114	1			T5	3		T14	1		T118	2
auto[3355443200:3489660927]	112	1			T52	2		T103	1		T45	1
auto[3489660928:3623878655]	118	1			T52	1		T49	1		T6	1
auto[3623878656:3758096383]	117	1			T5	2		T34	1		T119	1
auto[3758096384:3892314111]	105	1			T5	1		T52	1		T119	1
auto[3892314112:4026531839]	98	1			T88	1		T136	1		T50	1
auto[4026531840:4160749567]	132	1			T5	1		T199	1		T52	1
auto[4160749568:4294967295]	110	1			T199	1		T34	1		T49	1