Unified Coverage Report :: Group Instance : salt_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3130

1

T3

2

T5

11

T12

1

auto[1]

296

1

T118

10

T119

4

T130

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	123	1			T34	1		T118	1		T103	1
auto[134217728:268435455]	92	1			T52	1		T198	1		T45	1
auto[268435456:402653183]	110	1			T52	2		T119	1		T56	1
auto[402653184:536870911]	116	1			T5	1		T118	1		T52	1
auto[536870912:671088639]	107	1			T34	1		T52	3		T201	1
auto[671088640:805306367]	100	1			T5	2		T23	1		T200	1
auto[805306368:939524095]	106	1			T33	1		T199	1		T6	2
auto[939524096:1073741823]	97	1			T118	1		T49	1		T56	1
auto[1073741824:1207959551]	109	1			T199	1		T6	1		T57	1
auto[1207959552:1342177279]	100	1			T5	1		T52	1		T6	1
auto[1342177280:1476395007]	124	1			T23	1		T118	1		T52	1
auto[1476395008:1610612735]	109	1			T13	1		T88	1		T118	1
auto[1610612736:1744830463]	118	1			T118	1		T56	1		T57	1
auto[1744830464:1879048191]	108	1			T5	1		T118	2		T6	1
auto[1879048192:2013265919]	107	1			T5	2		T52	1		T136	1
auto[2013265920:2147483647]	113	1			T14	2		T88	1		T6	1
auto[2147483648:2281701375]	98	1			T5	1		T199	1		T52	2
auto[2281701376:2415919103]	111	1			T23	2		T118	1		T52	2
auto[2415919104:2550136831]	118	1			T14	1		T118	1		T48	1
auto[2550136832:2684354559]	104	1			T3	1		T34	1		T118	1
auto[2684354560:2818572287]	110	1			T34	2		T52	1		T6	1
auto[2818572288:2952790015]	110	1			T33	1		T52	2		T201	1
auto[2952790016:3087007743]	110	1			T5	1		T88	1		T118	1
auto[3087007744:3221225471]	102	1			T199	1		T52	1		T103	1
auto[3221225472:3355443199]	104	1			T33	1		T119	1		T6	1
auto[3355443200:3489660927]	104	1			T34	1		T103	1		T57	1
auto[3489660928:3623878655]	102	1			T118	2		T52	1		T201	1
auto[3623878656:3758096383]	101	1			T14	1		T52	1		T6	2
auto[3758096384:3892314111]	98	1			T3	1		T5	1		T57	1
auto[3892314112:4026531839]	102	1			T12	1		T118	1		T119	1
auto[4026531840:4160749567]	95	1			T5	1		T50	1		T57	1
auto[4160749568:4294967295]	118	1			T119	1		T6	1		T57	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	111	1			T34	1		T103	1		T57	1
auto[0:134217727]	auto[1]	12	1			T118	1		T130	1		T347	1
auto[134217728:268435455]	auto[0]	86	1			T52	1		T198	1		T45	1
auto[134217728:268435455]	auto[1]	6	1			T142	1		T261	1		T334	1
auto[268435456:402653183]	auto[0]	103	1			T52	2		T119	1		T56	1
auto[268435456:402653183]	auto[1]	7	1			T300	1		T234	2		T294	1
auto[402653184:536870911]	auto[0]	98	1			T5	1		T118	1		T52	1
auto[402653184:536870911]	auto[1]	18	1			T141	1		T154	1		T261	1
auto[536870912:671088639]	auto[0]	98	1			T34	1		T52	3		T201	1
auto[536870912:671088639]	auto[1]	9	1			T278	1		T251	1		T252	1
auto[671088640:805306367]	auto[0]	94	1			T5	2		T23	1		T200	1
auto[671088640:805306367]	auto[1]	6	1			T144	1		T277	1		T294	1
auto[805306368:939524095]	auto[0]	95	1			T33	1		T199	1		T6	2
auto[805306368:939524095]	auto[1]	11	1			T142	1		T251	1		T300	1
auto[939524096:1073741823]	auto[0]	88	1			T49	1		T56	1		T6	2
auto[939524096:1073741823]	auto[1]	9	1			T118	1		T251	1		T277	1
auto[1073741824:1207959551]	auto[0]	102	1			T199	1		T6	1		T57	1
auto[1073741824:1207959551]	auto[1]	7	1			T240	1		T364	1		T367	1
auto[1207959552:1342177279]	auto[0]	93	1			T5	1		T52	1		T6	1
auto[1207959552:1342177279]	auto[1]	7	1			T278	1		T239	1		T237	1
auto[1342177280:1476395007]	auto[0]	110	1			T23	1		T118	1		T52	1
auto[1342177280:1476395007]	auto[1]	14	1			T251	1		T277	1		T300	1
auto[1476395008:1610612735]	auto[0]	100	1			T13	1		T88	1		T118	1
auto[1476395008:1610612735]	auto[1]	9	1			T130	1		T144	1		T328	1
auto[1610612736:1744830463]	auto[0]	107	1			T56	1		T57	1		T58	1
auto[1610612736:1744830463]	auto[1]	11	1			T118	1		T141	1		T328	1
auto[1744830464:1879048191]	auto[0]	97	1			T5	1		T6	1		T50	1
auto[1744830464:1879048191]	auto[1]	11	1			T118	2		T142	1		T328	1
auto[1879048192:2013265919]	auto[0]	98	1			T5	2		T52	1		T136	1
auto[1879048192:2013265919]	auto[1]	9	1			T154	2		T251	2		T261	1
auto[2013265920:2147483647]	auto[0]	108	1			T14	2		T88	1		T6	1
auto[2013265920:2147483647]	auto[1]	5	1			T277	1		T300	1		T366	1
auto[2147483648:2281701375]	auto[0]	90	1			T5	1		T199	1		T52	2
auto[2147483648:2281701375]	auto[1]	8	1			T154	1		T144	1		T300	1
auto[2281701376:2415919103]	auto[0]	99	1			T23	2		T52	2		T6	2
auto[2281701376:2415919103]	auto[1]	12	1			T118	1		T194	1		T278	1
auto[2415919104:2550136831]	auto[0]	107	1			T14	1		T48	1		T52	1
auto[2415919104:2550136831]	auto[1]	11	1			T118	1		T278	1		T251	1
auto[2550136832:2684354559]	auto[0]	89	1			T3	1		T34	1		T118	1
auto[2550136832:2684354559]	auto[1]	15	1			T141	1		T154	1		T239	1
auto[2684354560:2818572287]	auto[0]	105	1			T34	2		T52	1		T6	1
auto[2684354560:2818572287]	auto[1]	5	1			T142	1		T347	1		T261	1
auto[2818572288:2952790015]	auto[0]	97	1			T33	1		T52	2		T201	1
auto[2818572288:2952790015]	auto[1]	13	1			T119	2		T144	1		T251	2
auto[2952790016:3087007743]	auto[0]	101	1			T5	1		T88	1		T201	1
auto[2952790016:3087007743]	auto[1]	9	1			T118	1		T239	1		T360	1
auto[3087007744:3221225471]	auto[0]	97	1			T199	1		T52	1		T103	1
auto[3087007744:3221225471]	auto[1]	5	1			T82	1		T194	1		T252	1
auto[3221225472:3355443199]	auto[0]	94	1			T33	1		T6	1		T57	1
auto[3221225472:3355443199]	auto[1]	10	1			T119	1		T82	1		T144	1
auto[3355443200:3489660927]	auto[0]	93	1			T34	1		T103	1		T57	1
auto[3355443200:3489660927]	auto[1]	11	1			T154	1		T300	2		T353	1
auto[3489660928:3623878655]	auto[0]	91	1			T52	1		T201	1		T119	2
auto[3489660928:3623878655]	auto[1]	11	1			T118	2		T119	1		T154	1
auto[3623878656:3758096383]	auto[0]	94	1			T14	1		T52	1		T6	2
auto[3623878656:3758096383]	auto[1]	7	1			T251	1		T252	2		T277	1
auto[3758096384:3892314111]	auto[0]	89	1			T3	1		T5	1		T57	1
auto[3758096384:3892314111]	auto[1]	9	1			T347	1		T240	2		T334	1
auto[3892314112:4026531839]	auto[0]	95	1			T12	1		T118	1		T119	1
auto[3892314112:4026531839]	auto[1]	7	1			T328	1		T334	1		T262	1
auto[4026531840:4160749567]	auto[0]	90	1			T5	1		T50	1		T57	1
auto[4026531840:4160749567]	auto[1]	5	1			T154	1		T144	1		T237	1
auto[4160749568:4294967295]	auto[0]	111	1			T119	1		T6	1		T57	2
auto[4160749568:4294967295]	auto[1]	7	1			T144	1		T239	1		T277	1