Unified Coverage Report :: Group Instance : sealing_sw_binding_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1705

1

T3

1

T5

4

T14

1

auto[1]

1815

1

T3

1

T5

12

T12

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T118	1		T52	2		T65	1
auto[134217728:268435455]	123	1			T3	1		T52	1		T119	1
auto[268435456:402653183]	105	1			T14	1		T52	2		T6	1
auto[402653184:536870911]	107	1			T23	1		T119	1		T57	2
auto[536870912:671088639]	96	1			T5	1		T52	2		T50	1
auto[671088640:805306367]	127	1			T5	1		T88	1		T34	1
auto[805306368:939524095]	124	1			T119	2		T6	3		T45	1
auto[939524096:1073741823]	113	1			T5	1		T52	1		T6	1
auto[1073741824:1207959551]	97	1			T5	2		T52	2		T6	1
auto[1207959552:1342177279]	86	1			T5	1		T118	1		T6	2
auto[1342177280:1476395007]	105	1			T5	1		T136	1		T6	2
auto[1476395008:1610612735]	116	1			T3	1		T6	3		T57	1
auto[1610612736:1744830463]	107	1			T23	1		T52	1		T201	1
auto[1744830464:1879048191]	116	1			T5	1		T52	1		T16	1
auto[1879048192:2013265919]	122	1			T5	1		T14	1		T88	2
auto[2013265920:2147483647]	103	1			T34	1		T119	1		T130	1
auto[2147483648:2281701375]	114	1			T5	2		T23	1		T199	1
auto[2281701376:2415919103]	110	1			T5	2		T199	1		T52	1
auto[2415919104:2550136831]	99	1			T14	1		T33	1		T52	1
auto[2550136832:2684354559]	106	1			T118	1		T52	1		T57	1
auto[2684354560:2818572287]	116	1			T5	1		T199	1		T34	1
auto[2818572288:2952790015]	109	1			T52	1		T69	1		T141	2
auto[2952790016:3087007743]	122	1			T5	1		T23	1		T118	1
auto[3087007744:3221225471]	128	1			T12	1		T199	1		T34	1
auto[3221225472:3355443199]	118	1			T45	1		T57	1		T69	1
auto[3355443200:3489660927]	107	1			T5	1		T33	1		T56	1
auto[3489660928:3623878655]	101	1			T34	1		T52	1		T103	1
auto[3623878656:3758096383]	117	1			T56	1		T27	1		T200	1
auto[3758096384:3892314111]	121	1			T103	1		T45	1		T27	1
auto[3892314112:4026531839]	97	1			T14	1		T34	1		T49	1
auto[4026531840:4160749567]	95	1			T103	1		T57	3		T62	1
auto[4160749568:4294967295]	101	1			T33	1		T49	1		T56	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T52	1		T272	1		T245	1
auto[0:134217727]	auto[1]	60	1			T118	1		T52	1		T65	1
auto[134217728:268435455]	auto[0]	70	1			T52	1		T119	1		T57	1
auto[134217728:268435455]	auto[1]	53	1			T3	1		T57	1		T130	1
auto[268435456:402653183]	auto[0]	49	1			T52	2		T6	1		T62	1
auto[268435456:402653183]	auto[1]	56	1			T14	1		T62	1		T19	1
auto[402653184:536870911]	auto[0]	62	1			T23	1		T119	1		T53	2
auto[402653184:536870911]	auto[1]	45	1			T57	2		T133	1		T202	1
auto[536870912:671088639]	auto[0]	48	1			T5	1		T52	1		T50	1
auto[536870912:671088639]	auto[1]	48	1			T52	1		T69	1		T141	1
auto[671088640:805306367]	auto[0]	60	1			T34	1		T52	2		T200	1
auto[671088640:805306367]	auto[1]	67	1			T5	1		T88	1		T103	1
auto[805306368:939524095]	auto[0]	63	1			T6	2		T45	1		T255	1
auto[805306368:939524095]	auto[1]	61	1			T119	2		T6	1		T272	1
auto[939524096:1073741823]	auto[0]	55	1			T5	1		T64	2		T47	1
auto[939524096:1073741823]	auto[1]	58	1			T52	1		T6	1		T198	1
auto[1073741824:1207959551]	auto[0]	42	1			T52	1		T6	1		T66	1
auto[1073741824:1207959551]	auto[1]	55	1			T5	2		T52	1		T50	1
auto[1207959552:1342177279]	auto[0]	39	1			T66	1		T112	1		T143	1
auto[1207959552:1342177279]	auto[1]	47	1			T5	1		T118	1		T6	2
auto[1342177280:1476395007]	auto[0]	50	1			T6	1		T331	1		T47	1
auto[1342177280:1476395007]	auto[1]	55	1			T5	1		T136	1		T6	1
auto[1476395008:1610612735]	auto[0]	62	1			T3	1		T6	3		T57	1
auto[1476395008:1610612735]	auto[1]	54	1			T37	1		T142	1		T64	2
auto[1610612736:1744830463]	auto[0]	48	1			T49	1		T53	1		T19	1
auto[1610612736:1744830463]	auto[1]	59	1			T23	1		T52	1		T201	1
auto[1744830464:1879048191]	auto[0]	51	1			T5	1		T6	1		T66	1
auto[1744830464:1879048191]	auto[1]	65	1			T52	1		T16	1		T136	1
auto[1879048192:2013265919]	auto[0]	61	1			T103	2		T57	1		T69	1
auto[1879048192:2013265919]	auto[1]	61	1			T5	1		T14	1		T88	2
auto[2013265920:2147483647]	auto[0]	48	1			T34	1		T62	1		T53	1
auto[2013265920:2147483647]	auto[1]	55	1			T119	1		T130	1		T86	1
auto[2147483648:2281701375]	auto[0]	51	1			T52	1		T201	1		T57	1
auto[2147483648:2281701375]	auto[1]	63	1			T5	2		T23	1		T199	1
auto[2281701376:2415919103]	auto[0]	54	1			T5	1		T57	1		T245	2
auto[2281701376:2415919103]	auto[1]	56	1			T5	1		T199	1		T52	1
auto[2415919104:2550136831]	auto[0]	60	1			T33	1		T119	1		T198	1
auto[2415919104:2550136831]	auto[1]	39	1			T14	1		T52	1		T201	1
auto[2550136832:2684354559]	auto[0]	49	1			T118	1		T57	1		T20	1
auto[2550136832:2684354559]	auto[1]	57	1			T52	1		T139	1		T58	1
auto[2684354560:2818572287]	auto[0]	66	1			T199	1		T34	1		T118	1
auto[2684354560:2818572287]	auto[1]	50	1			T5	1		T48	1		T6	1
auto[2818572288:2952790015]	auto[0]	47	1			T86	1		T87	1		T7	1
auto[2818572288:2952790015]	auto[1]	62	1			T52	1		T69	1		T141	2
auto[2952790016:3087007743]	auto[0]	56	1			T23	1		T118	1		T103	1
auto[2952790016:3087007743]	auto[1]	66	1			T5	1		T52	1		T201	1
auto[3087007744:3221225471]	auto[0]	59	1			T199	1		T34	1		T49	1
auto[3087007744:3221225471]	auto[1]	69	1			T12	1		T52	1		T6	1
auto[3221225472:3355443199]	auto[0]	57	1			T45	1		T60	1		T20	1
auto[3221225472:3355443199]	auto[1]	61	1			T57	1		T69	1		T36	1
auto[3355443200:3489660927]	auto[0]	50	1			T33	1		T56	1		T6	1
auto[3355443200:3489660927]	auto[1]	57	1			T5	1		T38	1		T92	1
auto[3489660928:3623878655]	auto[0]	51	1			T57	1		T53	1		T245	1
auto[3489660928:3623878655]	auto[1]	50	1			T34	1		T52	1		T103	1
auto[3623878656:3758096383]	auto[0]	47	1			T53	1		T58	1		T94	1
auto[3623878656:3758096383]	auto[1]	70	1			T56	1		T27	1		T200	1
auto[3758096384:3892314111]	auto[0]	59	1			T103	1		T45	1		T202	1
auto[3758096384:3892314111]	auto[1]	62	1			T27	1		T57	1		T272	1
auto[3892314112:4026531839]	auto[0]	51	1			T14	1		T34	1		T198	1
auto[3892314112:4026531839]	auto[1]	46	1			T49	1		T50	1		T57	1
auto[4026531840:4160749567]	auto[0]	39	1			T57	2		T62	1		T64	1
auto[4026531840:4160749567]	auto[1]	56	1			T103	1		T57	1		T133	1
auto[4160749568:4294967295]	auto[0]	49	1			T33	1		T49	1		T56	1
auto[4160749568:4294967295]	auto[1]	52	1			T50	1		T139	1		T28	2