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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1681 1 T3 2 T5 3 T14 2
auto[1] 1839 1 T5 13 T12 1 T14 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 131 1 T199 1 T52 1 T6 1
auto[134217728:268435455] 101 1 T5 1 T48 1 T52 1
auto[268435456:402653183] 128 1 T199 1 T119 1 T103 1
auto[402653184:536870911] 114 1 T57 1 T69 1 T133 2
auto[536870912:671088639] 113 1 T33 1 T88 1 T52 2
auto[671088640:805306367] 114 1 T14 1 T23 1 T118 1
auto[805306368:939524095] 101 1 T5 1 T14 1 T49 1
auto[939524096:1073741823] 107 1 T23 2 T52 1 T201 1
auto[1073741824:1207959551] 132 1 T14 1 T201 1 T103 1
auto[1207959552:1342177279] 120 1 T199 1 T52 4 T119 1
auto[1342177280:1476395007] 113 1 T5 1 T52 2 T6 3
auto[1476395008:1610612735] 85 1 T5 2 T14 1 T118 1
auto[1610612736:1744830463] 95 1 T5 1 T118 1 T52 1
auto[1744830464:1879048191] 121 1 T5 1 T103 1 T50 1
auto[1879048192:2013265919] 128 1 T5 2 T201 1 T49 1
auto[2013265920:2147483647] 104 1 T6 1 T62 1 T133 1
auto[2147483648:2281701375] 103 1 T5 1 T103 1 T57 2
auto[2281701376:2415919103] 101 1 T5 1 T52 2 T6 1
auto[2415919104:2550136831] 95 1 T52 1 T6 1 T45 1
auto[2550136832:2684354559] 125 1 T3 1 T5 1 T33 1
auto[2684354560:2818572287] 104 1 T88 1 T34 1 T118 1
auto[2818572288:2952790015] 125 1 T52 1 T49 1 T6 1
auto[2952790016:3087007743] 113 1 T34 1 T52 1 T136 1
auto[3087007744:3221225471] 101 1 T5 1 T52 1 T200 1
auto[3221225472:3355443199] 108 1 T23 1 T52 1 T198 1
auto[3355443200:3489660927] 91 1 T56 1 T6 1 T57 1
auto[3489660928:3623878655] 118 1 T5 1 T34 2 T6 1
auto[3623878656:3758096383] 104 1 T3 1 T33 1 T52 1
auto[3758096384:3892314111] 125 1 T5 1 T52 1 T6 1
auto[3892314112:4026531839] 110 1 T5 1 T199 1 T34 1
auto[4026531840:4160749567] 88 1 T12 1 T52 1 T6 1
auto[4160749568:4294967295] 102 1 T88 1 T118 1 T52 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 55 1 T6 1 T87 1 T7 2
auto[0:134217727] auto[1] 76 1 T199 1 T52 1 T69 1
auto[134217728:268435455] auto[0] 35 1 T278 1 T270 1 T210 2
auto[134217728:268435455] auto[1] 66 1 T5 1 T48 1 T52 1
auto[268435456:402653183] auto[0] 69 1 T103 1 T66 1 T20 1
auto[268435456:402653183] auto[1] 59 1 T199 1 T119 1 T53 1
auto[402653184:536870911] auto[0] 56 1 T133 2 T46 1 T142 1
auto[402653184:536870911] auto[1] 58 1 T57 1 T69 1 T53 1
auto[536870912:671088639] auto[0] 57 1 T33 1 T88 1 T52 2
auto[536870912:671088639] auto[1] 56 1 T16 1 T6 1 T198 1
auto[671088640:805306367] auto[0] 49 1 T23 1 T118 1 T6 1
auto[671088640:805306367] auto[1] 65 1 T14 1 T201 1 T49 1
auto[805306368:939524095] auto[0] 48 1 T14 1 T49 1 T245 1
auto[805306368:939524095] auto[1] 53 1 T5 1 T58 1 T154 1
auto[939524096:1073741823] auto[0] 43 1 T23 1 T119 1 T56 1
auto[939524096:1073741823] auto[1] 64 1 T23 1 T52 1 T201 1
auto[1073741824:1207959551] auto[0] 65 1 T14 1 T103 1 T45 2
auto[1073741824:1207959551] auto[1] 67 1 T201 1 T50 1 T57 1
auto[1207959552:1342177279] auto[0] 49 1 T199 1 T52 2 T119 1
auto[1207959552:1342177279] auto[1] 71 1 T52 2 T6 1 T198 1
auto[1342177280:1476395007] auto[0] 61 1 T52 1 T6 1 T103 1
auto[1342177280:1476395007] auto[1] 52 1 T5 1 T52 1 T6 2
auto[1476395008:1610612735] auto[0] 39 1 T56 1 T7 1 T94 1
auto[1476395008:1610612735] auto[1] 46 1 T5 2 T14 1 T118 1
auto[1610612736:1744830463] auto[0] 42 1 T5 1 T52 1 T6 1
auto[1610612736:1744830463] auto[1] 53 1 T118 1 T6 1 T57 1
auto[1744830464:1879048191] auto[0] 65 1 T103 1 T57 1 T331 1
auto[1744830464:1879048191] auto[1] 56 1 T5 1 T50 1 T29 1
auto[1879048192:2013265919] auto[0] 71 1 T201 1 T49 1 T6 1
auto[1879048192:2013265919] auto[1] 57 1 T5 2 T103 1 T57 1
auto[2013265920:2147483647] auto[0] 50 1 T6 1 T133 1 T190 1
auto[2013265920:2147483647] auto[1] 54 1 T62 1 T66 1 T19 2
auto[2147483648:2281701375] auto[0] 37 1 T5 1 T57 2 T245 1
auto[2147483648:2281701375] auto[1] 66 1 T103 1 T65 1 T130 2
auto[2281701376:2415919103] auto[0] 45 1 T6 1 T69 1 T245 1
auto[2281701376:2415919103] auto[1] 56 1 T5 1 T52 2 T50 1
auto[2415919104:2550136831] auto[0] 42 1 T245 1 T20 1 T64 1
auto[2415919104:2550136831] auto[1] 53 1 T52 1 T6 1 T45 1
auto[2550136832:2684354559] auto[0] 57 1 T3 1 T5 1 T33 1
auto[2550136832:2684354559] auto[1] 68 1 T6 1 T103 1 T50 1
auto[2684354560:2818572287] auto[0] 46 1 T34 1 T103 1 T69 1
auto[2684354560:2818572287] auto[1] 58 1 T88 1 T118 1 T6 1
auto[2818572288:2952790015] auto[0] 73 1 T52 1 T49 1 T6 1
auto[2818572288:2952790015] auto[1] 52 1 T57 1 T200 1 T28 1
auto[2952790016:3087007743] auto[0] 62 1 T34 1 T136 1 T65 1
auto[2952790016:3087007743] auto[1] 51 1 T52 1 T198 1 T45 1
auto[3087007744:3221225471] auto[0] 47 1 T52 1 T200 1 T19 1
auto[3087007744:3221225471] auto[1] 54 1 T5 1 T85 1 T47 1
auto[3221225472:3355443199] auto[0] 49 1 T52 1 T130 1 T202 1
auto[3221225472:3355443199] auto[1] 59 1 T23 1 T198 1 T57 1
auto[3355443200:3489660927] auto[0] 45 1 T56 1 T57 1 T81 1
auto[3355443200:3489660927] auto[1] 46 1 T6 1 T202 1 T66 1
auto[3489660928:3623878655] auto[0] 58 1 T34 2 T86 1 T24 1
auto[3489660928:3623878655] auto[1] 60 1 T5 1 T6 1 T57 1
auto[3623878656:3758096383] auto[0] 53 1 T3 1 T33 1 T6 1
auto[3623878656:3758096383] auto[1] 51 1 T52 1 T57 1 T272 1
auto[3758096384:3892314111] auto[0] 61 1 T52 1 T45 1 T57 1
auto[3758096384:3892314111] auto[1] 64 1 T5 1 T6 1 T69 1
auto[3892314112:4026531839] auto[0] 62 1 T34 1 T56 2 T62 1
auto[3892314112:4026531839] auto[1] 48 1 T5 1 T199 1 T119 1
auto[4026531840:4160749567] auto[0] 37 1 T6 1 T50 1 T57 1
auto[4026531840:4160749567] auto[1] 51 1 T12 1 T52 1 T57 1
auto[4160749568:4294967295] auto[0] 53 1 T118 1 T119 1 T103 1
auto[4160749568:4294967295] auto[1] 49 1 T88 1 T52 1 T37 1

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