Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7386

1

T3

4

T5

21

T12

2

auto[1]

309

1

T118

9

T119

3

T130

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3101	1			T3	2		T5	9		T12	1
auto[134217728:268435455]	179	1			T5	1		T14	1		T23	1
auto[268435456:402653183]	141	1			T13	1		T14	1		T34	1
auto[402653184:536870911]	162	1			T5	2		T199	1		T52	1
auto[536870912:671088639]	148	1			T5	1		T52	1		T56	1
auto[671088640:805306367]	156	1			T14	1		T23	1		T118	1
auto[805306368:939524095]	136	1			T5	1		T52	1		T49	1
auto[939524096:1073741823]	146	1			T5	2		T34	1		T118	1
auto[1073741824:1207959551]	153	1			T5	1		T14	1		T23	1
auto[1207959552:1342177279]	149	1			T5	1		T14	1		T118	1
auto[1342177280:1476395007]	153	1			T23	1		T34	1		T48	1
auto[1476395008:1610612735]	150	1			T199	1		T34	1		T118	1
auto[1610612736:1744830463]	164	1			T5	1		T12	1		T14	2
auto[1744830464:1879048191]	128	1			T88	1		T34	1		T118	1
auto[1879048192:2013265919]	139	1			T14	1		T118	1		T52	3
auto[2013265920:2147483647]	165	1			T33	1		T52	1		T103	1
auto[2147483648:2281701375]	164	1			T23	1		T118	2		T52	2
auto[2281701376:2415919103]	135	1			T52	1		T49	1		T56	1
auto[2415919104:2550136831]	119	1			T52	2		T119	1		T56	1
auto[2550136832:2684354559]	131	1			T3	1		T34	1		T52	1
auto[2684354560:2818572287]	143	1			T14	1		T33	1		T103	2
auto[2818572288:2952790015]	164	1			T52	1		T119	1		T57	4
auto[2952790016:3087007743]	144	1			T199	1		T52	1		T6	1
auto[3087007744:3221225471]	146	1			T14	2		T52	1		T49	1
auto[3221225472:3355443199]	150	1			T118	2		T6	1		T103	2
auto[3355443200:3489660927]	149	1			T5	1		T23	1		T88	1
auto[3489660928:3623878655]	142	1			T199	1		T34	1		T52	2
auto[3623878656:3758096383]	130	1			T5	1		T88	1		T34	1
auto[3758096384:3892314111]	145	1			T3	1		T23	1		T52	2
auto[3892314112:4026531839]	141	1			T52	2		T6	2		T103	1
auto[4026531840:4160749567]	147	1			T88	1		T52	1		T50	1
auto[4160749568:4294967295]	175	1			T118	1		T52	5		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3092	1			T3	2		T5	9		T12	1
auto[0:134217727]	auto[1]	9	1			T142	3		T282	1		T366	1
auto[134217728:268435455]	auto[0]	168	1			T5	1		T14	1		T23	1
auto[134217728:268435455]	auto[1]	11	1			T154	1		T144	1		T239	1
auto[268435456:402653183]	auto[0]	136	1			T13	1		T14	1		T34	1
auto[268435456:402653183]	auto[1]	5	1			T118	1		T144	1		T294	1
auto[402653184:536870911]	auto[0]	152	1			T5	2		T199	1		T52	1
auto[402653184:536870911]	auto[1]	10	1			T154	1		T278	1		T252	1
auto[536870912:671088639]	auto[0]	141	1			T5	1		T52	1		T56	1
auto[536870912:671088639]	auto[1]	7	1			T251	2		T277	1		T353	1
auto[671088640:805306367]	auto[0]	146	1			T14	1		T23	1		T52	2
auto[671088640:805306367]	auto[1]	10	1			T118	1		T130	1		T239	1
auto[805306368:939524095]	auto[0]	131	1			T5	1		T52	1		T49	1
auto[805306368:939524095]	auto[1]	5	1			T239	1		T300	1		T262	1
auto[939524096:1073741823]	auto[0]	137	1			T5	2		T34	1		T118	1
auto[939524096:1073741823]	auto[1]	9	1			T154	1		T278	1		T277	1
auto[1073741824:1207959551]	auto[0]	147	1			T5	1		T14	1		T23	1
auto[1073741824:1207959551]	auto[1]	6	1			T154	1		T328	1		T367	1
auto[1207959552:1342177279]	auto[0]	137	1			T5	1		T14	1		T52	2
auto[1207959552:1342177279]	auto[1]	12	1			T118	1		T154	1		T278	1
auto[1342177280:1476395007]	auto[0]	139	1			T23	1		T34	1		T48	1
auto[1342177280:1476395007]	auto[1]	14	1			T144	1		T328	1		T300	2
auto[1476395008:1610612735]	auto[0]	143	1			T199	1		T34	1		T118	1
auto[1476395008:1610612735]	auto[1]	7	1			T141	1		T278	1		T277	1
auto[1610612736:1744830463]	auto[0]	152	1			T5	1		T12	1		T14	2
auto[1610612736:1744830463]	auto[1]	12	1			T141	1		T347	1		T252	1
auto[1744830464:1879048191]	auto[0]	120	1			T88	1		T34	1		T52	1
auto[1744830464:1879048191]	auto[1]	8	1			T118	1		T278	1		T277	1
auto[1879048192:2013265919]	auto[0]	131	1			T14	1		T118	1		T52	3
auto[1879048192:2013265919]	auto[1]	8	1			T130	1		T141	1		T278	1
auto[2013265920:2147483647]	auto[0]	154	1			T33	1		T52	1		T103	1
auto[2013265920:2147483647]	auto[1]	11	1			T154	1		T142	1		T251	1
auto[2147483648:2281701375]	auto[0]	151	1			T23	1		T118	1		T52	2
auto[2147483648:2281701375]	auto[1]	13	1			T118	1		T154	1		T142	1
auto[2281701376:2415919103]	auto[0]	121	1			T52	1		T49	1		T56	1
auto[2281701376:2415919103]	auto[1]	14	1			T278	1		T144	1		T251	1
auto[2415919104:2550136831]	auto[0]	111	1			T52	2		T56	1		T6	1
auto[2415919104:2550136831]	auto[1]	8	1			T119	1		T141	1		T277	1
auto[2550136832:2684354559]	auto[0]	122	1			T3	1		T34	1		T52	1
auto[2550136832:2684354559]	auto[1]	9	1			T154	1		T239	1		T277	1
auto[2684354560:2818572287]	auto[0]	138	1			T14	1		T33	1		T103	2
auto[2684354560:2818572287]	auto[1]	5	1			T130	1		T278	1		T362	1
auto[2818572288:2952790015]	auto[0]	155	1			T52	1		T57	4		T200	2
auto[2818572288:2952790015]	auto[1]	9	1			T119	1		T141	1		T154	1
auto[2952790016:3087007743]	auto[0]	132	1			T199	1		T52	1		T6	1
auto[2952790016:3087007743]	auto[1]	12	1			T130	1		T278	1		T282	1
auto[3087007744:3221225471]	auto[0]	134	1			T14	2		T52	1		T49	1
auto[3087007744:3221225471]	auto[1]	12	1			T141	1		T154	1		T144	1
auto[3221225472:3355443199]	auto[0]	139	1			T6	1		T103	2		T69	1
auto[3221225472:3355443199]	auto[1]	11	1			T118	2		T239	1		T261	1
auto[3355443200:3489660927]	auto[0]	139	1			T5	1		T23	1		T88	1
auto[3355443200:3489660927]	auto[1]	10	1			T154	2		T353	1		T366	1
auto[3489660928:3623878655]	auto[0]	132	1			T199	1		T34	1		T52	2
auto[3489660928:3623878655]	auto[1]	10	1			T119	1		T262	1		T368	1
auto[3623878656:3758096383]	auto[0]	122	1			T5	1		T88	1		T34	1
auto[3623878656:3758096383]	auto[1]	8	1			T118	1		T300	1		T334	1
auto[3758096384:3892314111]	auto[0]	132	1			T3	1		T23	1		T52	2
auto[3758096384:3892314111]	auto[1]	13	1			T141	1		T142	1		T252	1
auto[3892314112:4026531839]	auto[0]	129	1			T52	2		T6	2		T103	1
auto[3892314112:4026531839]	auto[1]	12	1			T154	1		T144	1		T239	1
auto[4026531840:4160749567]	auto[0]	140	1			T88	1		T52	1		T50	1
auto[4026531840:4160749567]	auto[1]	7	1			T141	1		T252	1		T334	1
auto[4160749568:4294967295]	auto[0]	163	1			T52	5		T6	1		T57	2
auto[4160749568:4294967295]	auto[1]	12	1			T118	1		T130	1		T154	1