Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4732

1

T3

2

T5

22

T14

6

auto[1]

2308

1

T3

2

T5

10

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	200	1			T5	2		T23	2		T119	2
auto[134217728:268435455]	272	1			T23	2		T48	2		T52	2
auto[268435456:402653183]	234	1			T23	2		T199	2		T6	2
auto[402653184:536870911]	254	1			T118	2		T52	2		T53	2
auto[536870912:671088639]	226	1			T52	2		T136	2		T103	2
auto[671088640:805306367]	246	1			T34	2		T119	2		T6	4
auto[805306368:939524095]	210	1			T56	2		T50	2		T57	2
auto[939524096:1073741823]	222	1			T3	2		T12	2		T199	2
auto[1073741824:1207959551]	228	1			T52	2		T56	2		T6	2
auto[1207959552:1342177279]	194	1			T33	2		T52	2		T201	2
auto[1342177280:1476395007]	230	1			T5	2		T52	2		T6	2
auto[1476395008:1610612735]	236	1			T5	2		T119	2		T49	2
auto[1610612736:1744830463]	218	1			T118	2		T6	2		T62	2
auto[1744830464:1879048191]	226	1			T52	4		T6	4		T57	2
auto[1879048192:2013265919]	204	1			T5	2		T118	2		T57	6
auto[2013265920:2147483647]	200	1			T34	2		T56	2		T6	2
auto[2147483648:2281701375]	198	1			T34	2		T52	2		T6	2
auto[2281701376:2415919103]	218	1			T5	4		T33	4		T52	4
auto[2415919104:2550136831]	206	1			T199	2		T52	2		T6	4
auto[2550136832:2684354559]	232	1			T199	2		T52	2		T6	2
auto[2684354560:2818572287]	186	1			T52	2		T103	2		T139	2
auto[2818572288:2952790015]	208	1			T5	6		T88	2		T52	2
auto[2952790016:3087007743]	270	1			T5	4		T88	2		T34	2
auto[3087007744:3221225471]	198	1			T6	2		T331	2		T36	2
auto[3221225472:3355443199]	224	1			T52	2		T136	2		T198	2
auto[3355443200:3489660927]	230	1			T5	4		T14	2		T201	2
auto[3489660928:3623878655]	236	1			T23	2		T52	2		T136	2
auto[3623878656:3758096383]	210	1			T3	2		T5	2		T52	4
auto[3758096384:3892314111]	222	1			T5	2		T34	2		T52	2
auto[3892314112:4026531839]	198	1			T52	6		T49	2		T6	2
auto[4026531840:4160749567]	210	1			T5	2		T14	2		T34	2
auto[4160749568:4294967295]	194	1			T14	4		T88	2		T118	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	116	1			T23	2		T103	2		T57	2
auto[0:134217727]	auto[1]	84	1			T5	2		T119	2		T7	2
auto[134217728:268435455]	auto[0]	174	1			T23	2		T52	2		T56	2
auto[134217728:268435455]	auto[1]	98	1			T48	2		T6	2		T50	2
auto[268435456:402653183]	auto[0]	144	1			T23	2		T190	2		T94	2
auto[268435456:402653183]	auto[1]	90	1			T199	2		T6	2		T202	2
auto[402653184:536870911]	auto[0]	182	1			T118	2		T53	2		T87	2
auto[402653184:536870911]	auto[1]	72	1			T52	2		T86	2		T64	2
auto[536870912:671088639]	auto[0]	162	1			T103	2		T53	2		T66	2
auto[536870912:671088639]	auto[1]	64	1			T52	2		T136	2		T27	2
auto[671088640:805306367]	auto[0]	166	1			T34	2		T119	2		T6	2
auto[671088640:805306367]	auto[1]	80	1			T6	2		T58	2		T193	2
auto[805306368:939524095]	auto[0]	142	1			T56	2		T50	2		T57	2
auto[805306368:939524095]	auto[1]	68	1			T28	2		T73	2		T47	4
auto[939524096:1073741823]	auto[0]	128	1			T201	2		T103	2		T57	2
auto[939524096:1073741823]	auto[1]	94	1			T3	2		T12	2		T199	2
auto[1073741824:1207959551]	auto[0]	144	1			T52	2		T56	2		T6	2
auto[1073741824:1207959551]	auto[1]	84	1			T46	2		T278	2		T73	2
auto[1207959552:1342177279]	auto[0]	142	1			T33	2		T49	2		T56	2
auto[1207959552:1342177279]	auto[1]	52	1			T52	2		T201	2		T47	2
auto[1342177280:1476395007]	auto[0]	164	1			T52	2		T130	2		T245	2
auto[1342177280:1476395007]	auto[1]	66	1			T5	2		T6	2		T200	2
auto[1476395008:1610612735]	auto[0]	168	1			T5	2		T49	2		T6	2
auto[1476395008:1610612735]	auto[1]	68	1			T119	2		T27	2		T331	2
auto[1610612736:1744830463]	auto[0]	152	1			T118	2		T62	2		T92	2
auto[1610612736:1744830463]	auto[1]	66	1			T6	2		T7	2		T24	2
auto[1744830464:1879048191]	auto[0]	156	1			T52	2		T6	4		T57	2
auto[1744830464:1879048191]	auto[1]	70	1			T52	2		T7	2		T255	2
auto[1879048192:2013265919]	auto[0]	146	1			T5	2		T118	2		T57	4
auto[1879048192:2013265919]	auto[1]	58	1			T57	2		T65	2		T141	2
auto[2013265920:2147483647]	auto[0]	130	1			T34	2		T56	2		T6	2
auto[2013265920:2147483647]	auto[1]	70	1			T200	2		T116	2		T210	2
auto[2147483648:2281701375]	auto[0]	112	1			T34	2		T6	2		T141	2
auto[2147483648:2281701375]	auto[1]	86	1			T52	2		T69	2		T53	2
auto[2281701376:2415919103]	auto[0]	132	1			T5	4		T33	2		T201	2
auto[2281701376:2415919103]	auto[1]	86	1			T33	2		T52	4		T6	2
auto[2415919104:2550136831]	auto[0]	130	1			T52	2		T6	4		T57	2
auto[2415919104:2550136831]	auto[1]	76	1			T199	2		T69	2		T133	2
auto[2550136832:2684354559]	auto[0]	162	1			T6	2		T57	2		T200	2
auto[2550136832:2684354559]	auto[1]	70	1			T199	2		T52	2		T66	2
auto[2684354560:2818572287]	auto[0]	106	1			T139	2		T58	2		T272	2
auto[2684354560:2818572287]	auto[1]	80	1			T52	2		T103	2		T245	2
auto[2818572288:2952790015]	auto[0]	158	1			T5	4		T88	2		T52	2
auto[2818572288:2952790015]	auto[1]	50	1			T5	2		T119	2		T245	2
auto[2952790016:3087007743]	auto[0]	192	1			T5	2		T88	2		T34	2
auto[2952790016:3087007743]	auto[1]	78	1			T5	2		T103	2		T57	2
auto[3087007744:3221225471]	auto[0]	136	1			T6	2		T331	2		T36	2
auto[3087007744:3221225471]	auto[1]	62	1			T87	2		T144	2		T47	2
auto[3221225472:3355443199]	auto[0]	138	1			T103	2		T46	4		T7	2
auto[3221225472:3355443199]	auto[1]	86	1			T52	2		T136	2		T198	2
auto[3355443200:3489660927]	auto[0]	162	1			T5	4		T14	2		T201	2
auto[3355443200:3489660927]	auto[1]	68	1			T85	2		T7	4		T144	2
auto[3489660928:3623878655]	auto[0]	166	1			T23	2		T52	2		T103	2
auto[3489660928:3623878655]	auto[1]	70	1			T136	2		T198	2		T57	2
auto[3623878656:3758096383]	auto[0]	154	1			T3	2		T5	2		T52	2
auto[3623878656:3758096383]	auto[1]	56	1			T52	2		T116	2		T144	2
auto[3758096384:3892314111]	auto[0]	156	1			T34	2		T50	2		T57	2
auto[3758096384:3892314111]	auto[1]	66	1			T5	2		T52	2		T119	2
auto[3892314112:4026531839]	auto[0]	122	1			T52	4		T57	2		T245	2
auto[3892314112:4026531839]	auto[1]	76	1			T52	2		T49	2		T6	2
auto[4026531840:4160749567]	auto[0]	152	1			T5	2		T34	2		T119	2
auto[4026531840:4160749567]	auto[1]	58	1			T14	2		T82	2		T7	2
auto[4160749568:4294967295]	auto[0]	138	1			T14	4		T88	2		T118	2
auto[4160749568:4294967295]	auto[1]	56	1			T82	2		T7	6		T29	2