Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.37 99.00 98.11 98.33 97.67 98.93 98.41 91.14


Total test records in report: 1083
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1009 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2613554559 Jun 07 06:49:54 PM PDT 24 Jun 07 06:49:57 PM PDT 24 163586872 ps
T1010 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1758049653 Jun 07 06:48:35 PM PDT 24 Jun 07 06:48:39 PM PDT 24 289799233 ps
T1011 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2028580669 Jun 07 06:48:10 PM PDT 24 Jun 07 06:48:13 PM PDT 24 34563009 ps
T1012 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3650480529 Jun 07 06:48:37 PM PDT 24 Jun 07 06:48:38 PM PDT 24 105766546 ps
T1013 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2390152817 Jun 07 06:49:29 PM PDT 24 Jun 07 06:49:32 PM PDT 24 58443510 ps
T182 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.265576549 Jun 07 06:49:17 PM PDT 24 Jun 07 06:49:24 PM PDT 24 252212434 ps
T1014 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1858100140 Jun 07 06:48:50 PM PDT 24 Jun 07 06:49:01 PM PDT 24 2011210465 ps
T1015 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.381628298 Jun 07 06:50:13 PM PDT 24 Jun 07 06:50:15 PM PDT 24 76150496 ps
T1016 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.620220093 Jun 07 06:48:37 PM PDT 24 Jun 07 06:48:41 PM PDT 24 64816949 ps
T1017 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3029873933 Jun 07 06:50:09 PM PDT 24 Jun 07 06:50:11 PM PDT 24 90231918 ps
T1018 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2995006219 Jun 07 06:48:35 PM PDT 24 Jun 07 06:48:40 PM PDT 24 146094154 ps
T1019 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.245783736 Jun 07 06:49:30 PM PDT 24 Jun 07 06:49:32 PM PDT 24 58092089 ps
T1020 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1390682894 Jun 07 06:48:50 PM PDT 24 Jun 07 06:48:52 PM PDT 24 159515323 ps
T1021 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3690555559 Jun 07 06:49:37 PM PDT 24 Jun 07 06:49:39 PM PDT 24 20625359 ps
T1022 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1060755571 Jun 07 06:49:24 PM PDT 24 Jun 07 06:49:29 PM PDT 24 253848514 ps
T1023 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1931763215 Jun 07 06:49:38 PM PDT 24 Jun 07 06:49:41 PM PDT 24 109333647 ps
T1024 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.767225237 Jun 07 06:48:49 PM PDT 24 Jun 07 06:48:52 PM PDT 24 31793688 ps
T166 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3341041296 Jun 07 06:49:16 PM PDT 24 Jun 07 06:49:25 PM PDT 24 867675534 ps
T1025 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.11241083 Jun 07 06:48:42 PM PDT 24 Jun 07 06:48:46 PM PDT 24 171173848 ps
T1026 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.598129087 Jun 07 06:48:30 PM PDT 24 Jun 07 06:48:31 PM PDT 24 35252556 ps
T1027 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2262683410 Jun 07 06:48:11 PM PDT 24 Jun 07 06:48:12 PM PDT 24 93013973 ps
T1028 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3338544901 Jun 07 06:50:21 PM PDT 24 Jun 07 06:50:23 PM PDT 24 36812325 ps
T1029 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2772758991 Jun 07 06:48:43 PM PDT 24 Jun 07 06:48:54 PM PDT 24 792523011 ps
T1030 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2348188232 Jun 07 06:48:48 PM PDT 24 Jun 07 06:48:50 PM PDT 24 195168240 ps
T1031 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.51873796 Jun 07 06:49:25 PM PDT 24 Jun 07 06:49:34 PM PDT 24 1161966813 ps
T1032 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3961985655 Jun 07 06:49:09 PM PDT 24 Jun 07 06:49:11 PM PDT 24 109456294 ps
T1033 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2257131795 Jun 07 06:48:11 PM PDT 24 Jun 07 06:48:13 PM PDT 24 23967438 ps
T1034 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2673935849 Jun 07 06:47:59 PM PDT 24 Jun 07 06:48:07 PM PDT 24 294940450 ps
T1035 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.185820272 Jun 07 06:48:56 PM PDT 24 Jun 07 06:48:59 PM PDT 24 159151625 ps
T173 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1041299477 Jun 07 06:49:13 PM PDT 24 Jun 07 06:49:22 PM PDT 24 334118285 ps
T167 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2620806091 Jun 07 06:49:31 PM PDT 24 Jun 07 06:49:40 PM PDT 24 1115384062 ps
T1036 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1563363008 Jun 07 06:49:44 PM PDT 24 Jun 07 06:49:45 PM PDT 24 20950681 ps
T1037 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.417387773 Jun 07 06:48:58 PM PDT 24 Jun 07 06:49:01 PM PDT 24 81989577 ps
T1038 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2543196601 Jun 07 06:50:17 PM PDT 24 Jun 07 06:50:20 PM PDT 24 48872635 ps
T1039 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.124318985 Jun 07 06:49:14 PM PDT 24 Jun 07 06:49:16 PM PDT 24 16543745 ps
T1040 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.672458579 Jun 07 06:48:50 PM PDT 24 Jun 07 06:48:54 PM PDT 24 205456892 ps
T180 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.103652622 Jun 07 06:48:59 PM PDT 24 Jun 07 06:49:08 PM PDT 24 1078182911 ps
T1041 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2357239409 Jun 07 06:48:15 PM PDT 24 Jun 07 06:48:18 PM PDT 24 50836013 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3558328847 Jun 07 06:48:23 PM PDT 24 Jun 07 06:48:26 PM PDT 24 81171834 ps
T1043 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4227690307 Jun 07 06:48:49 PM PDT 24 Jun 07 06:48:52 PM PDT 24 46516421 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1215524045 Jun 07 06:48:36 PM PDT 24 Jun 07 06:48:37 PM PDT 24 11017051 ps
T1045 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1141727231 Jun 07 06:49:18 PM PDT 24 Jun 07 06:49:20 PM PDT 24 68277921 ps
T1046 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.18814899 Jun 07 06:48:57 PM PDT 24 Jun 07 06:48:59 PM PDT 24 28741079 ps
T1047 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.908415853 Jun 07 06:49:28 PM PDT 24 Jun 07 06:49:31 PM PDT 24 171278718 ps
T1048 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2252078538 Jun 07 06:49:24 PM PDT 24 Jun 07 06:49:28 PM PDT 24 341359092 ps
T1049 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4220885009 Jun 07 06:49:30 PM PDT 24 Jun 07 06:49:32 PM PDT 24 15975934 ps
T1050 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1189666575 Jun 07 06:49:48 PM PDT 24 Jun 07 06:49:50 PM PDT 24 20799488 ps
T1051 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.929447721 Jun 07 06:50:10 PM PDT 24 Jun 07 06:50:12 PM PDT 24 17817355 ps
T1052 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.594260232 Jun 07 06:48:04 PM PDT 24 Jun 07 06:48:07 PM PDT 24 337421966 ps
T1053 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4181594117 Jun 07 06:49:23 PM PDT 24 Jun 07 06:49:26 PM PDT 24 83343783 ps
T1054 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.200180158 Jun 07 06:49:54 PM PDT 24 Jun 07 06:50:00 PM PDT 24 623851077 ps
T1055 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2301750742 Jun 07 06:50:01 PM PDT 24 Jun 07 06:50:03 PM PDT 24 107483470 ps
T1056 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3117225875 Jun 07 06:49:53 PM PDT 24 Jun 07 06:49:57 PM PDT 24 212694910 ps
T1057 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3142173706 Jun 07 06:49:38 PM PDT 24 Jun 07 06:49:42 PM PDT 24 76195610 ps
T1058 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3092650730 Jun 07 06:48:56 PM PDT 24 Jun 07 06:49:03 PM PDT 24 111266773 ps
T171 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.791762407 Jun 07 06:49:03 PM PDT 24 Jun 07 06:49:13 PM PDT 24 840773418 ps
T1059 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2827990395 Jun 07 06:47:57 PM PDT 24 Jun 07 06:47:58 PM PDT 24 12419503 ps
T1060 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3570958138 Jun 07 06:47:58 PM PDT 24 Jun 07 06:47:59 PM PDT 24 16914358 ps
T1061 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3082973581 Jun 07 06:49:03 PM PDT 24 Jun 07 06:49:06 PM PDT 24 50363181 ps
T172 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.975693707 Jun 07 06:48:23 PM PDT 24 Jun 07 06:48:29 PM PDT 24 137554689 ps
T1062 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3821320661 Jun 07 06:49:12 PM PDT 24 Jun 07 06:49:13 PM PDT 24 14230825 ps
T1063 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1494515170 Jun 07 06:49:20 PM PDT 24 Jun 07 06:49:22 PM PDT 24 9497111 ps
T1064 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3032633636 Jun 07 06:47:56 PM PDT 24 Jun 07 06:47:58 PM PDT 24 32381309 ps
T175 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2869632684 Jun 07 06:49:22 PM PDT 24 Jun 07 06:49:28 PM PDT 24 567313277 ps
T1065 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3610472393 Jun 07 06:48:04 PM PDT 24 Jun 07 06:48:07 PM PDT 24 341185357 ps
T1066 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2128106290 Jun 07 06:49:03 PM PDT 24 Jun 07 06:49:10 PM PDT 24 444402344 ps
T1067 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.844474224 Jun 07 06:50:10 PM PDT 24 Jun 07 06:50:13 PM PDT 24 12149544 ps
T1068 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4042472111 Jun 07 06:49:54 PM PDT 24 Jun 07 06:49:58 PM PDT 24 197807746 ps
T1069 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2766029521 Jun 07 06:47:59 PM PDT 24 Jun 07 06:48:03 PM PDT 24 193511831 ps
T1070 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3600963630 Jun 07 06:49:12 PM PDT 24 Jun 07 06:49:14 PM PDT 24 27538063 ps
T1071 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3603010477 Jun 07 06:48:43 PM PDT 24 Jun 07 06:48:47 PM PDT 24 61348603 ps
T1072 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1250347721 Jun 07 06:49:39 PM PDT 24 Jun 07 06:49:43 PM PDT 24 138011783 ps
T1073 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2565950597 Jun 07 06:49:56 PM PDT 24 Jun 07 06:50:01 PM PDT 24 117475401 ps
T1074 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3428623042 Jun 07 06:49:23 PM PDT 24 Jun 07 06:49:35 PM PDT 24 2063877004 ps
T1075 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.588519309 Jun 07 06:50:01 PM PDT 24 Jun 07 06:50:02 PM PDT 24 10976783 ps
T1076 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2838929191 Jun 07 06:49:30 PM PDT 24 Jun 07 06:49:39 PM PDT 24 209067053 ps
T1077 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3705551210 Jun 07 06:48:31 PM PDT 24 Jun 07 06:48:39 PM PDT 24 588294284 ps
T1078 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1572986459 Jun 07 06:49:04 PM PDT 24 Jun 07 06:49:07 PM PDT 24 55388763 ps
T1079 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2092921331 Jun 07 06:49:28 PM PDT 24 Jun 07 06:49:30 PM PDT 24 19870126 ps
T1080 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.986911373 Jun 07 06:49:28 PM PDT 24 Jun 07 06:49:32 PM PDT 24 201303881 ps
T1081 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2390819687 Jun 07 06:49:56 PM PDT 24 Jun 07 06:49:58 PM PDT 24 21433549 ps
T1082 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2281608308 Jun 07 06:47:58 PM PDT 24 Jun 07 06:48:01 PM PDT 24 75319909 ps
T1083 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2397359434 Jun 07 06:49:54 PM PDT 24 Jun 07 06:49:59 PM PDT 24 75825153 ps

Test location /workspace/coverage/default/18.keymgr_stress_all.4258610166
Short name T5
Test name
Test status
Simulation time 44619118456 ps
CPU time 117.95 seconds
Started Jun 07 07:09:36 PM PDT 24
Finished Jun 07 07:11:36 PM PDT 24
Peak memory 216904 kb
Host smart-c39af01f-b9b2-4733-8260-b3d434d676b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258610166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.4258610166
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.4158449573
Short name T52
Test name
Test status
Simulation time 491537483 ps
CPU time 22.61 seconds
Started Jun 07 07:09:29 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 220876 kb
Host smart-f16077b0-cffc-4c7f-80cf-15e2ee46aaca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158449573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.4158449573
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3204307684
Short name T60
Test name
Test status
Simulation time 316391855 ps
CPU time 11.61 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:10:03 PM PDT 24
Peak memory 222564 kb
Host smart-a973418a-f371-4cb5-9e07-8e332a132807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204307684 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3204307684
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2991956460
Short name T8
Test name
Test status
Simulation time 742470768 ps
CPU time 6.83 seconds
Started Jun 07 07:08:25 PM PDT 24
Finished Jun 07 07:08:33 PM PDT 24
Peak memory 230664 kb
Host smart-919f4219-5496-4594-8895-df604ba9a3d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991956460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2991956460
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1672819925
Short name T57
Test name
Test status
Simulation time 3770773506 ps
CPU time 32.44 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:09:27 PM PDT 24
Peak memory 216160 kb
Host smart-9b35d5bb-9e17-4479-87d6-71ce6d454982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672819925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1672819925
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3461912392
Short name T12
Test name
Test status
Simulation time 125387226 ps
CPU time 1.41 seconds
Started Jun 07 07:10:41 PM PDT 24
Finished Jun 07 07:10:48 PM PDT 24
Peak memory 209988 kb
Host smart-217c17d7-4dac-44ae-8bed-1a4d29a3b754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461912392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3461912392
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.471036090
Short name T7
Test name
Test status
Simulation time 4929400738 ps
CPU time 57.68 seconds
Started Jun 07 07:10:18 PM PDT 24
Finished Jun 07 07:11:18 PM PDT 24
Peak memory 216888 kb
Host smart-69850f6b-9550-4fc0-8ba5-623578b96dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471036090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.471036090
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3614318540
Short name T118
Test name
Test status
Simulation time 278554653 ps
CPU time 7.85 seconds
Started Jun 07 07:10:01 PM PDT 24
Finished Jun 07 07:10:13 PM PDT 24
Peak memory 222576 kb
Host smart-8d8c2a17-eff8-4351-baf0-8d1912394e5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614318540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3614318540
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3632200089
Short name T245
Test name
Test status
Simulation time 430904322 ps
CPU time 3.85 seconds
Started Jun 07 07:08:48 PM PDT 24
Finished Jun 07 07:08:57 PM PDT 24
Peak memory 206216 kb
Host smart-1c6ee89c-9d2d-458f-894b-3e5bdde4d3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632200089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3632200089
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2545220894
Short name T113
Test name
Test status
Simulation time 866792575 ps
CPU time 8.25 seconds
Started Jun 07 06:48:47 PM PDT 24
Finished Jun 07 06:48:56 PM PDT 24
Peak memory 214272 kb
Host smart-91d33fca-3859-42df-bef1-a9a2e3e8dbcb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545220894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2545220894
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1733346526
Short name T47
Test name
Test status
Simulation time 3274863349 ps
CPU time 32.87 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:11:00 PM PDT 24
Peak memory 216860 kb
Host smart-9c0a72a8-7a07-4b6e-a837-286215716d25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733346526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1733346526
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3286896898
Short name T154
Test name
Test status
Simulation time 709777795 ps
CPU time 8.66 seconds
Started Jun 07 07:08:50 PM PDT 24
Finished Jun 07 07:09:04 PM PDT 24
Peak memory 214316 kb
Host smart-105f49fa-be30-4648-be4c-9eefd4510ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286896898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3286896898
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2001618286
Short name T116
Test name
Test status
Simulation time 586686662 ps
CPU time 27.69 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:10:19 PM PDT 24
Peak memory 222600 kb
Host smart-e15439b0-0274-476f-9066-7198a5c392e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001618286 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2001618286
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1433143348
Short name T19
Test name
Test status
Simulation time 180665024 ps
CPU time 4.27 seconds
Started Jun 07 07:09:46 PM PDT 24
Finished Jun 07 07:09:52 PM PDT 24
Peak memory 220884 kb
Host smart-867e96d8-b7fb-4d48-b629-05a51788d4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433143348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1433143348
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1003437811
Short name T252
Test name
Test status
Simulation time 310690964 ps
CPU time 14.89 seconds
Started Jun 07 07:10:53 PM PDT 24
Finished Jun 07 07:11:16 PM PDT 24
Peak memory 215732 kb
Host smart-9a9f9f2b-6aa1-4c5b-84f5-bd5b5a83d232
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003437811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1003437811
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2255250709
Short name T210
Test name
Test status
Simulation time 1167660421 ps
CPU time 45.5 seconds
Started Jun 07 07:08:33 PM PDT 24
Finished Jun 07 07:09:22 PM PDT 24
Peak memory 216028 kb
Host smart-2d5ef576-d915-43bb-84be-1fe7cc388687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255250709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2255250709
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3981801004
Short name T366
Test name
Test status
Simulation time 2293200657 ps
CPU time 129.75 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:13:30 PM PDT 24
Peak memory 222512 kb
Host smart-c107e9cf-8d27-42d6-aa74-50d9c69cf30b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981801004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3981801004
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.337417553
Short name T1
Test name
Test status
Simulation time 56281234 ps
CPU time 2.84 seconds
Started Jun 07 07:08:08 PM PDT 24
Finished Jun 07 07:08:12 PM PDT 24
Peak memory 210444 kb
Host smart-65723154-aa2a-4d28-9b6b-424670f4f00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337417553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.337417553
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1438343032
Short name T73
Test name
Test status
Simulation time 5797924984 ps
CPU time 27.67 seconds
Started Jun 07 07:08:00 PM PDT 24
Finished Jun 07 07:08:29 PM PDT 24
Peak memory 222708 kb
Host smart-71f61299-58e9-452d-827d-23f6cae8042b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438343032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1438343032
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.99778327
Short name T121
Test name
Test status
Simulation time 71398630 ps
CPU time 2.83 seconds
Started Jun 07 06:49:10 PM PDT 24
Finished Jun 07 06:49:14 PM PDT 24
Peak memory 214248 kb
Host smart-1576d404-f682-437d-8bed-78c021349a90
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99778327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_
reg_errors.99778327
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3673472684
Short name T300
Test name
Test status
Simulation time 676931469 ps
CPU time 12.68 seconds
Started Jun 07 07:11:01 PM PDT 24
Finished Jun 07 07:11:22 PM PDT 24
Peak memory 215860 kb
Host smart-ce62d74f-5790-469e-b5a4-e960fe706541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673472684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3673472684
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2020333681
Short name T223
Test name
Test status
Simulation time 1177557817 ps
CPU time 48.28 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:10:42 PM PDT 24
Peak memory 222404 kb
Host smart-4a9f0a89-bdcb-4fa0-bfe3-6879abf286ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020333681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2020333681
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.688928682
Short name T6
Test name
Test status
Simulation time 3404441777 ps
CPU time 24.91 seconds
Started Jun 07 07:09:54 PM PDT 24
Finished Jun 07 07:10:21 PM PDT 24
Peak memory 215144 kb
Host smart-27ecd68e-a1d6-414f-b0d4-8c0a8b9845c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688928682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.688928682
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.118331036
Short name T280
Test name
Test status
Simulation time 3772982985 ps
CPU time 37.26 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 216120 kb
Host smart-1b9dcb4b-c32e-4479-bc4c-74251b394feb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118331036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.118331036
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.39168448
Short name T36
Test name
Test status
Simulation time 679116919 ps
CPU time 7.36 seconds
Started Jun 07 07:10:32 PM PDT 24
Finished Jun 07 07:10:43 PM PDT 24
Peak memory 217848 kb
Host smart-48ae6f15-984f-4858-9b50-b63ddac5dabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39168448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.39168448
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3259946652
Short name T64
Test name
Test status
Simulation time 5276172591 ps
CPU time 46.99 seconds
Started Jun 07 07:10:01 PM PDT 24
Finished Jun 07 07:10:52 PM PDT 24
Peak memory 221276 kb
Host smart-98c2852a-a0e1-4912-a1be-d12f40046f6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259946652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3259946652
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.888319113
Short name T155
Test name
Test status
Simulation time 122007786 ps
CPU time 3.46 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:30 PM PDT 24
Peak memory 217988 kb
Host smart-a3baa811-8030-4d7d-a029-f3bfab107da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888319113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.888319113
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2642501599
Short name T315
Test name
Test status
Simulation time 3708370204 ps
CPU time 16.15 seconds
Started Jun 07 07:09:57 PM PDT 24
Finished Jun 07 07:10:16 PM PDT 24
Peak memory 215724 kb
Host smart-14d23f2f-248b-48d0-9bbc-f7e254d8f860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642501599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2642501599
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.529895011
Short name T25
Test name
Test status
Simulation time 181200067 ps
CPU time 4.26 seconds
Started Jun 07 07:08:02 PM PDT 24
Finished Jun 07 07:08:07 PM PDT 24
Peak memory 209796 kb
Host smart-18814a50-139a-4441-9b8a-c5fb6cc7ff2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529895011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.529895011
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3260970113
Short name T367
Test name
Test status
Simulation time 2471429808 ps
CPU time 63.82 seconds
Started Jun 07 07:08:15 PM PDT 24
Finished Jun 07 07:09:20 PM PDT 24
Peak memory 222496 kb
Host smart-d2996132-f74f-4e44-8a58-77c2540f2a4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260970113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3260970113
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2684083011
Short name T212
Test name
Test status
Simulation time 4576448980 ps
CPU time 75.01 seconds
Started Jun 07 07:09:05 PM PDT 24
Finished Jun 07 07:10:22 PM PDT 24
Peak memory 216628 kb
Host smart-24b0fa9f-ee1a-4679-9906-da64b9d16c61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684083011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2684083011
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2487356361
Short name T20
Test name
Test status
Simulation time 45744808 ps
CPU time 3.13 seconds
Started Jun 07 07:10:15 PM PDT 24
Finished Jun 07 07:10:20 PM PDT 24
Peak memory 222416 kb
Host smart-bfd3a62b-85c0-4d19-b489-8747b8b49bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487356361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2487356361
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3983589977
Short name T93
Test name
Test status
Simulation time 591080632 ps
CPU time 9.29 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:10 PM PDT 24
Peak memory 220956 kb
Host smart-7b6689c4-75a1-4db2-96d1-bd064f0bd2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983589977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3983589977
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3354280484
Short name T375
Test name
Test status
Simulation time 129195363 ps
CPU time 0.97 seconds
Started Jun 07 07:09:18 PM PDT 24
Finished Jun 07 07:09:20 PM PDT 24
Peak memory 206120 kb
Host smart-cb916a40-c4f3-4906-a9dc-8ace0139c638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354280484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3354280484
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.791762407
Short name T171
Test name
Test status
Simulation time 840773418 ps
CPU time 8.73 seconds
Started Jun 07 06:49:03 PM PDT 24
Finished Jun 07 06:49:13 PM PDT 24
Peak memory 213828 kb
Host smart-02a177f3-884b-49e8-a2c8-3581a21734d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791762407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
791762407
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3918728718
Short name T76
Test name
Test status
Simulation time 5180278037 ps
CPU time 51.36 seconds
Started Jun 07 07:10:05 PM PDT 24
Finished Jun 07 07:11:00 PM PDT 24
Peak memory 222652 kb
Host smart-e2c1e3b9-b766-4bc2-b9cb-8cd74ba64408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918728718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3918728718
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2757049133
Short name T364
Test name
Test status
Simulation time 1288317694 ps
CPU time 66.16 seconds
Started Jun 07 07:10:15 PM PDT 24
Finished Jun 07 07:11:24 PM PDT 24
Peak memory 214840 kb
Host smart-ddcb7573-bdea-4661-9a06-accfbf34879e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757049133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2757049133
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.493841882
Short name T111
Test name
Test status
Simulation time 129656089 ps
CPU time 6.05 seconds
Started Jun 07 07:10:55 PM PDT 24
Finished Jun 07 07:11:09 PM PDT 24
Peak memory 214320 kb
Host smart-d2fb79e6-5825-4925-b159-135c2a25d111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493841882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.493841882
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.526746434
Short name T165
Test name
Test status
Simulation time 407680496 ps
CPU time 8.73 seconds
Started Jun 07 06:48:36 PM PDT 24
Finished Jun 07 06:48:46 PM PDT 24
Peak memory 205544 kb
Host smart-56076849-77cf-4101-847b-6c90cd8ae0ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526746434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
526746434
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1241271601
Short name T68
Test name
Test status
Simulation time 121071462 ps
CPU time 4.38 seconds
Started Jun 07 07:09:08 PM PDT 24
Finished Jun 07 07:09:14 PM PDT 24
Peak memory 214580 kb
Host smart-c3412d6b-f266-47e1-ac85-790efba6303e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241271601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1241271601
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2959273481
Short name T92
Test name
Test status
Simulation time 455940241 ps
CPU time 5.23 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:42 PM PDT 24
Peak memory 214324 kb
Host smart-9f336b96-3d81-45b0-b9cd-70a3e1e9e41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959273481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2959273481
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2577926733
Short name T79
Test name
Test status
Simulation time 2313868268 ps
CPU time 30.56 seconds
Started Jun 07 07:08:18 PM PDT 24
Finished Jun 07 07:08:51 PM PDT 24
Peak memory 220872 kb
Host smart-6256fabb-6409-412d-8b39-dc36e7cf0521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577926733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2577926733
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.195149868
Short name T214
Test name
Test status
Simulation time 118220967961 ps
CPU time 544.05 seconds
Started Jun 07 07:10:35 PM PDT 24
Finished Jun 07 07:19:43 PM PDT 24
Peak memory 230572 kb
Host smart-e3618c44-f90c-48d9-b7b8-bb268f9ebbce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195149868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.195149868
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2421624307
Short name T32
Test name
Test status
Simulation time 257880706 ps
CPU time 3.46 seconds
Started Jun 07 07:09:34 PM PDT 24
Finished Jun 07 07:09:39 PM PDT 24
Peak memory 215368 kb
Host smart-68fddc27-07f3-48cc-97e1-10649df24f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421624307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2421624307
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2071660971
Short name T765
Test name
Test status
Simulation time 129733797 ps
CPU time 2.5 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:03 PM PDT 24
Peak memory 214240 kb
Host smart-c88ed0ef-0a79-42f4-a98c-73e32f4d57c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071660971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2071660971
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.753500592
Short name T49
Test name
Test status
Simulation time 105807525 ps
CPU time 4.74 seconds
Started Jun 07 07:09:11 PM PDT 24
Finished Jun 07 07:09:17 PM PDT 24
Peak memory 214300 kb
Host smart-dec95373-322a-46f4-8dcc-961d46b1fcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753500592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.753500592
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.4105193317
Short name T107
Test name
Test status
Simulation time 46030062 ps
CPU time 3.32 seconds
Started Jun 07 07:09:57 PM PDT 24
Finished Jun 07 07:10:03 PM PDT 24
Peak memory 214324 kb
Host smart-3439b68f-5aaa-47c7-97c6-329c9c5ffdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105193317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.4105193317
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.265576549
Short name T182
Test name
Test status
Simulation time 252212434 ps
CPU time 6.32 seconds
Started Jun 07 06:49:17 PM PDT 24
Finished Jun 07 06:49:24 PM PDT 24
Peak memory 213816 kb
Host smart-34381b2d-e052-4a10-806a-b25e545a4228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265576549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.265576549
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2779619567
Short name T39
Test name
Test status
Simulation time 117914619 ps
CPU time 3.79 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:50 PM PDT 24
Peak memory 210864 kb
Host smart-e43dacea-5955-4c8a-9918-808280d49bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779619567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2779619567
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.973208461
Short name T51
Test name
Test status
Simulation time 657816062 ps
CPU time 24.53 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:44 PM PDT 24
Peak memory 216296 kb
Host smart-2f9e1a50-1885-4529-a77e-f9e1752657e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973208461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.973208461
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3609717321
Short name T159
Test name
Test status
Simulation time 408130695 ps
CPU time 10.36 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:12 PM PDT 24
Peak memory 222636 kb
Host smart-5658f715-9446-4b03-9985-a579455be882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609717321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3609717321
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1767586586
Short name T209
Test name
Test status
Simulation time 4232782023 ps
CPU time 129.12 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:11:10 PM PDT 24
Peak memory 222468 kb
Host smart-d3fc3fcf-eae6-44ed-aa32-72d6dc3b40c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767586586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1767586586
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2661438736
Short name T363
Test name
Test status
Simulation time 782241137 ps
CPU time 10.9 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:10:03 PM PDT 24
Peak memory 214712 kb
Host smart-c5a2b413-3001-4b22-b8e2-70441885f8d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661438736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2661438736
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.909551032
Short name T231
Test name
Test status
Simulation time 449784544 ps
CPU time 4.8 seconds
Started Jun 07 07:08:47 PM PDT 24
Finished Jun 07 07:08:56 PM PDT 24
Peak memory 214388 kb
Host smart-f758e408-ee94-405f-9c45-e7666bac25dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909551032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.909551032
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2811218423
Short name T162
Test name
Test status
Simulation time 319210784 ps
CPU time 6.43 seconds
Started Jun 07 06:49:47 PM PDT 24
Finished Jun 07 06:49:55 PM PDT 24
Peak memory 205616 kb
Host smart-49c06abf-d493-42f3-bcce-6fd809c6c96a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811218423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2811218423
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.103652622
Short name T180
Test name
Test status
Simulation time 1078182911 ps
CPU time 7.87 seconds
Started Jun 07 06:48:59 PM PDT 24
Finished Jun 07 06:49:08 PM PDT 24
Peak memory 213716 kb
Host smart-9567e1cb-d8a6-484e-8058-f46f480c49bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103652622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
103652622
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3341041296
Short name T166
Test name
Test status
Simulation time 867675534 ps
CPU time 8.3 seconds
Started Jun 07 06:49:16 PM PDT 24
Finished Jun 07 06:49:25 PM PDT 24
Peak memory 215336 kb
Host smart-03a6c540-1df8-4448-ac13-a08507fa74fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341041296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3341041296
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1237972542
Short name T42
Test name
Test status
Simulation time 1624437311 ps
CPU time 30.03 seconds
Started Jun 07 07:07:54 PM PDT 24
Finished Jun 07 07:08:25 PM PDT 24
Peak memory 238232 kb
Host smart-f0cfe168-c655-418d-8145-0d166687a883
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237972542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1237972542
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2666134977
Short name T307
Test name
Test status
Simulation time 195361299 ps
CPU time 6.58 seconds
Started Jun 07 07:09:35 PM PDT 24
Finished Jun 07 07:09:43 PM PDT 24
Peak memory 222464 kb
Host smart-abbdb380-ca0e-45a0-9e7e-f44728692a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666134977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2666134977
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.14334432
Short name T327
Test name
Test status
Simulation time 351305423 ps
CPU time 17.94 seconds
Started Jun 07 07:08:08 PM PDT 24
Finished Jun 07 07:08:27 PM PDT 24
Peak memory 216552 kb
Host smart-5bf953a4-02aa-4ca0-b09e-2dadcc677aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14334432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.14334432
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2506755812
Short name T321
Test name
Test status
Simulation time 145039361 ps
CPU time 3.33 seconds
Started Jun 07 07:10:00 PM PDT 24
Finished Jun 07 07:10:08 PM PDT 24
Peak memory 214300 kb
Host smart-67ca433d-673b-4a80-96c3-637316552230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506755812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2506755812
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3122662801
Short name T191
Test name
Test status
Simulation time 647819181 ps
CPU time 17.4 seconds
Started Jun 07 07:10:10 PM PDT 24
Finished Jun 07 07:10:30 PM PDT 24
Peak memory 207956 kb
Host smart-743d70ec-a222-4ef2-bdb8-05b9faa24d66
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122662801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3122662801
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1210907088
Short name T278
Test name
Test status
Simulation time 623460050 ps
CPU time 32.6 seconds
Started Jun 07 07:10:18 PM PDT 24
Finished Jun 07 07:10:53 PM PDT 24
Peak memory 215156 kb
Host smart-cdc78122-fcc2-4987-a215-b57df1ee088d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1210907088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1210907088
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2673606290
Short name T233
Test name
Test status
Simulation time 238225808 ps
CPU time 4.78 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:25 PM PDT 24
Peak memory 214336 kb
Host smart-3b043bf4-925f-4553-b53f-6371fae756d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673606290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2673606290
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3579321203
Short name T117
Test name
Test status
Simulation time 2439760731 ps
CPU time 21.56 seconds
Started Jun 07 07:08:36 PM PDT 24
Finished Jun 07 07:08:59 PM PDT 24
Peak memory 221172 kb
Host smart-2a346111-10e5-455d-95f0-0e6d16270702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579321203 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3579321203
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.975693707
Short name T172
Test name
Test status
Simulation time 137554689 ps
CPU time 5.5 seconds
Started Jun 07 06:48:23 PM PDT 24
Finished Jun 07 06:48:29 PM PDT 24
Peak memory 213904 kb
Host smart-05dcd15a-b73d-4044-b411-8662e1c588a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975693707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
975693707
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2885811362
Short name T176
Test name
Test status
Simulation time 70574732 ps
CPU time 1.98 seconds
Started Jun 07 07:10:30 PM PDT 24
Finished Jun 07 07:10:36 PM PDT 24
Peak memory 210140 kb
Host smart-8dfbcc35-b4b1-4098-803d-a468da2d35fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885811362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2885811362
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2883074452
Short name T156
Test name
Test status
Simulation time 89965651 ps
CPU time 3.95 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 218468 kb
Host smart-09122512-506b-4a3d-9a1d-ed20a37ba4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883074452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2883074452
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3401473824
Short name T160
Test name
Test status
Simulation time 269438512 ps
CPU time 5.48 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:57 PM PDT 24
Peak memory 217304 kb
Host smart-9a8c7ee0-1d99-43dd-af06-d62983d7cea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401473824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3401473824
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3411748300
Short name T158
Test name
Test status
Simulation time 96833082 ps
CPU time 4.45 seconds
Started Jun 07 07:10:34 PM PDT 24
Finished Jun 07 07:10:42 PM PDT 24
Peak memory 217820 kb
Host smart-187c97d1-184e-4e06-9557-c3b250c99071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411748300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3411748300
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2992511845
Short name T144
Test name
Test status
Simulation time 168256027 ps
CPU time 8.97 seconds
Started Jun 07 07:07:58 PM PDT 24
Finished Jun 07 07:08:08 PM PDT 24
Peak memory 214632 kb
Host smart-e89727c4-b45a-4a2b-808a-6344d17f3c97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2992511845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2992511845
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4283175661
Short name T257
Test name
Test status
Simulation time 616584383 ps
CPU time 2.97 seconds
Started Jun 07 07:07:56 PM PDT 24
Finished Jun 07 07:08:00 PM PDT 24
Peak memory 215364 kb
Host smart-d1fba7a6-cde7-4db4-838e-7b42398df916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283175661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4283175661
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2720473016
Short name T334
Test name
Test status
Simulation time 108311197 ps
CPU time 6.21 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:07 PM PDT 24
Peak memory 222544 kb
Host smart-487eace7-8330-4364-bdbc-1979408659c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720473016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2720473016
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1692925822
Short name T46
Test name
Test status
Simulation time 75159990 ps
CPU time 4.33 seconds
Started Jun 07 07:09:28 PM PDT 24
Finished Jun 07 07:09:35 PM PDT 24
Peak memory 214364 kb
Host smart-8416f072-b629-4ea8-8ff7-9c5875bb9f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692925822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1692925822
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2807683701
Short name T260
Test name
Test status
Simulation time 303062448 ps
CPU time 2.76 seconds
Started Jun 07 07:09:58 PM PDT 24
Finished Jun 07 07:10:05 PM PDT 24
Peak memory 214264 kb
Host smart-5d5a6755-ded5-40f6-9fdf-8671b28d7da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807683701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2807683701
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3681448508
Short name T294
Test name
Test status
Simulation time 249222329 ps
CPU time 13.33 seconds
Started Jun 07 07:10:56 PM PDT 24
Finished Jun 07 07:11:17 PM PDT 24
Peak memory 215080 kb
Host smart-a501be8f-7b3b-4f8a-b6ed-8ddf162066c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681448508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3681448508
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.932924295
Short name T218
Test name
Test status
Simulation time 157192201 ps
CPU time 4.81 seconds
Started Jun 07 07:11:08 PM PDT 24
Finished Jun 07 07:11:23 PM PDT 24
Peak memory 210640 kb
Host smart-f5233b20-74f4-4807-8fca-b728721b83d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932924295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.932924295
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3119152638
Short name T41
Test name
Test status
Simulation time 1013860367 ps
CPU time 6.3 seconds
Started Jun 07 07:08:07 PM PDT 24
Finished Jun 07 07:08:15 PM PDT 24
Peak memory 230432 kb
Host smart-e9e84620-e429-4d28-92a6-0dbaddbca6d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119152638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3119152638
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1687809701
Short name T161
Test name
Test status
Simulation time 53610156 ps
CPU time 2.76 seconds
Started Jun 07 07:07:54 PM PDT 24
Finished Jun 07 07:07:57 PM PDT 24
Peak memory 218004 kb
Host smart-fc0dc359-72a6-4dda-bfd9-8c63791b7056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687809701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1687809701
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1991739664
Short name T96
Test name
Test status
Simulation time 929196588 ps
CPU time 13.33 seconds
Started Jun 07 07:08:01 PM PDT 24
Finished Jun 07 07:08:16 PM PDT 24
Peak memory 214368 kb
Host smart-f5a70065-5752-4eae-8782-6e7c5c0f7725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991739664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1991739664
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2038156848
Short name T292
Test name
Test status
Simulation time 142070185 ps
CPU time 5.45 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:07 PM PDT 24
Peak memory 208660 kb
Host smart-a2df648b-d675-4486-a6ec-7de70797ed58
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038156848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2038156848
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2277402778
Short name T241
Test name
Test status
Simulation time 125305118 ps
CPU time 3.35 seconds
Started Jun 07 07:08:56 PM PDT 24
Finished Jun 07 07:09:04 PM PDT 24
Peak memory 214280 kb
Host smart-a6f75132-85c3-4631-8eee-9b69520f7712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277402778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2277402778
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2789263129
Short name T206
Test name
Test status
Simulation time 1203721057 ps
CPU time 24.29 seconds
Started Jun 07 07:09:09 PM PDT 24
Finished Jun 07 07:09:35 PM PDT 24
Peak memory 208400 kb
Host smart-edfc3b19-3447-41f0-9f28-6a707884dc7d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789263129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2789263129
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2482083659
Short name T297
Test name
Test status
Simulation time 530582663 ps
CPU time 14.18 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:37 PM PDT 24
Peak memory 216368 kb
Host smart-0d7399f1-8bd8-4532-b8db-c7b29313d097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482083659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2482083659
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1967029929
Short name T228
Test name
Test status
Simulation time 158184982 ps
CPU time 9.38 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:31 PM PDT 24
Peak memory 222624 kb
Host smart-110d6c33-a361-4222-92d8-23ae55efdcb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967029929 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1967029929
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.257463456
Short name T234
Test name
Test status
Simulation time 237986604 ps
CPU time 3.38 seconds
Started Jun 07 07:08:08 PM PDT 24
Finished Jun 07 07:08:12 PM PDT 24
Peak memory 214344 kb
Host smart-81a2342e-e182-4927-a4a2-cba62a3485e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257463456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.257463456
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1792136423
Short name T119
Test name
Test status
Simulation time 242417690 ps
CPU time 4.46 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 214332 kb
Host smart-a92966ee-f386-40ce-8433-96195290a53e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792136423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1792136423
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3673767446
Short name T261
Test name
Test status
Simulation time 54823195 ps
CPU time 4.09 seconds
Started Jun 07 07:10:25 PM PDT 24
Finished Jun 07 07:10:33 PM PDT 24
Peak memory 214272 kb
Host smart-f1712bc9-855d-4522-a639-4153777ca0a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673767446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3673767446
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3818319973
Short name T319
Test name
Test status
Simulation time 1846146884 ps
CPU time 26.25 seconds
Started Jun 07 07:10:43 PM PDT 24
Finished Jun 07 07:11:17 PM PDT 24
Peak memory 215340 kb
Host smart-d1d5de69-bc23-4022-aec3-60af65c004ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818319973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3818319973
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1487038013
Short name T305
Test name
Test status
Simulation time 1066352639 ps
CPU time 37.8 seconds
Started Jun 07 07:11:04 PM PDT 24
Finished Jun 07 07:11:50 PM PDT 24
Peak memory 215992 kb
Host smart-e172e95a-5402-44e8-96a9-ef7b3385d681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487038013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1487038013
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2793192974
Short name T163
Test name
Test status
Simulation time 5105203284 ps
CPU time 11.29 seconds
Started Jun 07 06:48:05 PM PDT 24
Finished Jun 07 06:48:17 PM PDT 24
Peak memory 205752 kb
Host smart-983276fa-1985-436e-bb2d-5bb25eec79f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793192974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
793192974
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1254785078
Short name T944
Test name
Test status
Simulation time 1353661081 ps
CPU time 32.26 seconds
Started Jun 07 06:47:57 PM PDT 24
Finished Jun 07 06:48:29 PM PDT 24
Peak memory 205596 kb
Host smart-c625d357-48ed-4c22-b8f2-1cf6cafb3505
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254785078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
254785078
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3032633636
Short name T1064
Test name
Test status
Simulation time 32381309 ps
CPU time 1.06 seconds
Started Jun 07 06:47:56 PM PDT 24
Finished Jun 07 06:47:58 PM PDT 24
Peak memory 205524 kb
Host smart-3b8349aa-4882-4969-a8b4-de26beb06ddd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032633636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
032633636
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.594260232
Short name T1052
Test name
Test status
Simulation time 337421966 ps
CPU time 2.46 seconds
Started Jun 07 06:48:04 PM PDT 24
Finished Jun 07 06:48:07 PM PDT 24
Peak memory 213772 kb
Host smart-3e156271-fb91-46aa-876b-50f5f719e362
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594260232 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.594260232
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3570958138
Short name T1060
Test name
Test status
Simulation time 16914358 ps
CPU time 1.12 seconds
Started Jun 07 06:47:58 PM PDT 24
Finished Jun 07 06:47:59 PM PDT 24
Peak memory 205592 kb
Host smart-56da9e96-ead4-4c1c-b620-60fd992e724b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570958138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3570958138
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2827990395
Short name T1059
Test name
Test status
Simulation time 12419503 ps
CPU time 0.87 seconds
Started Jun 07 06:47:57 PM PDT 24
Finished Jun 07 06:47:58 PM PDT 24
Peak memory 205316 kb
Host smart-6dcc4076-60f8-478f-bf54-7d2f8bd86f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827990395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2827990395
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2244090046
Short name T935
Test name
Test status
Simulation time 270921034 ps
CPU time 2.15 seconds
Started Jun 07 06:48:06 PM PDT 24
Finished Jun 07 06:48:08 PM PDT 24
Peak memory 205580 kb
Host smart-5275f1e6-cdf4-4a10-83b0-bcf4197615d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244090046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2244090046
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2281608308
Short name T1082
Test name
Test status
Simulation time 75319909 ps
CPU time 2.82 seconds
Started Jun 07 06:47:58 PM PDT 24
Finished Jun 07 06:48:01 PM PDT 24
Peak memory 214160 kb
Host smart-86e04c80-1fd2-4122-9b77-663556963ad2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281608308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2281608308
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2673935849
Short name T1034
Test name
Test status
Simulation time 294940450 ps
CPU time 7.55 seconds
Started Jun 07 06:47:59 PM PDT 24
Finished Jun 07 06:48:07 PM PDT 24
Peak memory 214124 kb
Host smart-c8d14bb5-4457-4ec3-9ded-7f674417d85b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673935849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2673935849
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2766029521
Short name T1069
Test name
Test status
Simulation time 193511831 ps
CPU time 3.16 seconds
Started Jun 07 06:47:59 PM PDT 24
Finished Jun 07 06:48:03 PM PDT 24
Peak memory 216492 kb
Host smart-c150ee3d-efd1-4dd1-8650-257ba2ecf61e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766029521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2766029521
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.337227897
Short name T181
Test name
Test status
Simulation time 153291012 ps
CPU time 4.49 seconds
Started Jun 07 06:47:56 PM PDT 24
Finished Jun 07 06:48:01 PM PDT 24
Peak memory 213824 kb
Host smart-e280fc77-b3dd-433b-b287-e05ed6c8e891
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337227897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
337227897
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2959224576
Short name T997
Test name
Test status
Simulation time 143021132 ps
CPU time 4.82 seconds
Started Jun 07 06:48:13 PM PDT 24
Finished Jun 07 06:48:18 PM PDT 24
Peak memory 205688 kb
Host smart-5980f102-c2b8-46ab-a46c-b35ed598e843
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959224576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
959224576
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1792411991
Short name T1003
Test name
Test status
Simulation time 1290419837 ps
CPU time 17.87 seconds
Started Jun 07 06:48:11 PM PDT 24
Finished Jun 07 06:48:30 PM PDT 24
Peak memory 205624 kb
Host smart-55cb8385-37d2-4dfa-acd4-e27cbc00dc0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792411991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
792411991
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2257131795
Short name T1033
Test name
Test status
Simulation time 23967438 ps
CPU time 1.01 seconds
Started Jun 07 06:48:11 PM PDT 24
Finished Jun 07 06:48:13 PM PDT 24
Peak memory 205640 kb
Host smart-ab60c7fb-a174-4ec5-9d5a-6d024f8c2fcd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257131795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
257131795
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2541044459
Short name T352
Test name
Test status
Simulation time 158592043 ps
CPU time 2.08 seconds
Started Jun 07 06:48:18 PM PDT 24
Finished Jun 07 06:48:21 PM PDT 24
Peak memory 213948 kb
Host smart-7cc6381f-36c8-40ea-bca0-dcb324d026c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541044459 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2541044459
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2262683410
Short name T1027
Test name
Test status
Simulation time 93013973 ps
CPU time 1.21 seconds
Started Jun 07 06:48:11 PM PDT 24
Finished Jun 07 06:48:12 PM PDT 24
Peak memory 205576 kb
Host smart-ec18fe0e-55b9-42da-b533-fb7678efeef9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262683410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2262683410
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2655294271
Short name T963
Test name
Test status
Simulation time 53976358 ps
CPU time 0.75 seconds
Started Jun 07 06:48:11 PM PDT 24
Finished Jun 07 06:48:12 PM PDT 24
Peak memory 205260 kb
Host smart-f723b438-f1d6-4ed2-b862-a4f0b5d80c13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655294271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2655294271
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2357239409
Short name T1041
Test name
Test status
Simulation time 50836013 ps
CPU time 2.09 seconds
Started Jun 07 06:48:15 PM PDT 24
Finished Jun 07 06:48:18 PM PDT 24
Peak memory 205608 kb
Host smart-2d395f16-a0b2-473b-89ed-dcbada7288fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357239409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2357239409
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3610472393
Short name T1065
Test name
Test status
Simulation time 341185357 ps
CPU time 2.86 seconds
Started Jun 07 06:48:04 PM PDT 24
Finished Jun 07 06:48:07 PM PDT 24
Peak memory 214240 kb
Host smart-e09a088d-e772-456f-936c-8309306b7678
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610472393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3610472393
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2958396735
Short name T951
Test name
Test status
Simulation time 429103432 ps
CPU time 17.03 seconds
Started Jun 07 06:48:10 PM PDT 24
Finished Jun 07 06:48:28 PM PDT 24
Peak memory 214096 kb
Host smart-c7d24a41-10e4-48f7-840b-4ce3d9fff915
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958396735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2958396735
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2028580669
Short name T1011
Test name
Test status
Simulation time 34563009 ps
CPU time 2.14 seconds
Started Jun 07 06:48:10 PM PDT 24
Finished Jun 07 06:48:13 PM PDT 24
Peak memory 213744 kb
Host smart-fa8451be-82a8-4295-8529-a3f5d7a7480a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028580669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2028580669
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.86460102
Short name T177
Test name
Test status
Simulation time 182873987 ps
CPU time 2.66 seconds
Started Jun 07 06:48:12 PM PDT 24
Finished Jun 07 06:48:15 PM PDT 24
Peak memory 213728 kb
Host smart-43a1e65c-8e8c-40e5-adfc-579bf2c06cce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86460102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.86460102
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1644770503
Short name T930
Test name
Test status
Simulation time 20153253 ps
CPU time 1.14 seconds
Started Jun 07 06:49:28 PM PDT 24
Finished Jun 07 06:49:30 PM PDT 24
Peak memory 205428 kb
Host smart-7fd59d88-b666-4ad2-854b-88c79bfed430
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644770503 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1644770503
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.908415853
Short name T1047
Test name
Test status
Simulation time 171278718 ps
CPU time 1.27 seconds
Started Jun 07 06:49:28 PM PDT 24
Finished Jun 07 06:49:31 PM PDT 24
Peak memory 205484 kb
Host smart-a1a33cd0-b76c-4188-ad58-44be9bef79f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908415853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.908415853
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2092921331
Short name T1079
Test name
Test status
Simulation time 19870126 ps
CPU time 0.73 seconds
Started Jun 07 06:49:28 PM PDT 24
Finished Jun 07 06:49:30 PM PDT 24
Peak memory 204964 kb
Host smart-f953d1f4-fec3-41fd-9eb8-e8737ad029bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092921331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2092921331
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.986911373
Short name T1080
Test name
Test status
Simulation time 201303881 ps
CPU time 2.1 seconds
Started Jun 07 06:49:28 PM PDT 24
Finished Jun 07 06:49:32 PM PDT 24
Peak memory 205496 kb
Host smart-be8be5ac-072f-4ac6-85e2-a203aec35af4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986911373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.986911373
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2027421302
Short name T992
Test name
Test status
Simulation time 113376870 ps
CPU time 2.06 seconds
Started Jun 07 06:49:18 PM PDT 24
Finished Jun 07 06:49:21 PM PDT 24
Peak memory 214128 kb
Host smart-b8f14ac1-1b8f-412a-b421-eb0505de4870
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027421302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2027421302
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.562628401
Short name T122
Test name
Test status
Simulation time 1403153068 ps
CPU time 12.65 seconds
Started Jun 07 06:49:20 PM PDT 24
Finished Jun 07 06:49:33 PM PDT 24
Peak memory 214192 kb
Host smart-3600c278-ffc6-44cd-a63a-aeeffff95797
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562628401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.562628401
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1060755571
Short name T1022
Test name
Test status
Simulation time 253848514 ps
CPU time 4.35 seconds
Started Jun 07 06:49:24 PM PDT 24
Finished Jun 07 06:49:29 PM PDT 24
Peak memory 213728 kb
Host smart-1a7ee059-c2d0-42fe-9225-dfccde1f5a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060755571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1060755571
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.979655286
Short name T985
Test name
Test status
Simulation time 103842102 ps
CPU time 1.04 seconds
Started Jun 07 06:49:24 PM PDT 24
Finished Jun 07 06:49:26 PM PDT 24
Peak memory 205508 kb
Host smart-03171861-3b36-432f-8444-efe25bd42add
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979655286 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.979655286
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3919387061
Short name T153
Test name
Test status
Simulation time 20606803 ps
CPU time 0.98 seconds
Started Jun 07 06:49:25 PM PDT 24
Finished Jun 07 06:49:26 PM PDT 24
Peak memory 205536 kb
Host smart-77e0e223-8b2d-4104-bdc5-605e74d4defb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919387061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3919387061
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.729253555
Short name T984
Test name
Test status
Simulation time 69685975 ps
CPU time 0.7 seconds
Started Jun 07 06:49:23 PM PDT 24
Finished Jun 07 06:49:24 PM PDT 24
Peak memory 205288 kb
Host smart-c2f11811-87cc-4b32-a6a4-594336d3acf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729253555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.729253555
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2445037334
Short name T150
Test name
Test status
Simulation time 79782519 ps
CPU time 3.01 seconds
Started Jun 07 06:49:23 PM PDT 24
Finished Jun 07 06:49:26 PM PDT 24
Peak memory 205636 kb
Host smart-a7b236c0-14f7-45ec-9f26-aced52c29572
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445037334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2445037334
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.4047017752
Short name T978
Test name
Test status
Simulation time 154605517 ps
CPU time 3.1 seconds
Started Jun 07 06:49:22 PM PDT 24
Finished Jun 07 06:49:26 PM PDT 24
Peak memory 214236 kb
Host smart-03c7c2bf-1c21-4f1e-9d95-139b5825f3f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047017752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.4047017752
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.51873796
Short name T1031
Test name
Test status
Simulation time 1161966813 ps
CPU time 8.05 seconds
Started Jun 07 06:49:25 PM PDT 24
Finished Jun 07 06:49:34 PM PDT 24
Peak memory 214168 kb
Host smart-541b8b39-9060-40f1-bf9e-6d81d5706cc4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51873796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.k
eymgr_shadow_reg_errors_with_csr_rw.51873796
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2252078538
Short name T1048
Test name
Test status
Simulation time 341359092 ps
CPU time 2.65 seconds
Started Jun 07 06:49:24 PM PDT 24
Finished Jun 07 06:49:28 PM PDT 24
Peak memory 213832 kb
Host smart-0bde5084-d557-49e7-b8c9-180e976eee03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252078538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2252078538
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2869632684
Short name T175
Test name
Test status
Simulation time 567313277 ps
CPU time 4.58 seconds
Started Jun 07 06:49:22 PM PDT 24
Finished Jun 07 06:49:28 PM PDT 24
Peak memory 205620 kb
Host smart-04c8043c-b49d-4499-90e9-667dd26d1724
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869632684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2869632684
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.4241544001
Short name T994
Test name
Test status
Simulation time 23271082 ps
CPU time 1.55 seconds
Started Jun 07 06:49:30 PM PDT 24
Finished Jun 07 06:49:33 PM PDT 24
Peak memory 217848 kb
Host smart-0013aa6b-dc57-4e93-b469-4beb7164df0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241544001 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.4241544001
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2390152817
Short name T1013
Test name
Test status
Simulation time 58443510 ps
CPU time 1.28 seconds
Started Jun 07 06:49:29 PM PDT 24
Finished Jun 07 06:49:32 PM PDT 24
Peak memory 205628 kb
Host smart-5156b811-e8fc-450b-8083-dcacedd885a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390152817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2390152817
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2079002939
Short name T938
Test name
Test status
Simulation time 11685392 ps
CPU time 0.83 seconds
Started Jun 07 06:49:32 PM PDT 24
Finished Jun 07 06:49:34 PM PDT 24
Peak memory 205300 kb
Host smart-aad95723-2a94-4da9-9bb6-22c9e1dd8fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079002939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2079002939
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.469806018
Short name T149
Test name
Test status
Simulation time 40053184 ps
CPU time 1.42 seconds
Started Jun 07 06:49:31 PM PDT 24
Finished Jun 07 06:49:34 PM PDT 24
Peak memory 205656 kb
Host smart-fa42fdc5-f19a-45ef-9590-e174e5b13d4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469806018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.469806018
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4181594117
Short name T1053
Test name
Test status
Simulation time 83343783 ps
CPU time 2.08 seconds
Started Jun 07 06:49:23 PM PDT 24
Finished Jun 07 06:49:26 PM PDT 24
Peak memory 214188 kb
Host smart-208e4a00-5d9b-4458-a809-f558a055c647
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181594117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.4181594117
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3428623042
Short name T1074
Test name
Test status
Simulation time 2063877004 ps
CPU time 10.19 seconds
Started Jun 07 06:49:23 PM PDT 24
Finished Jun 07 06:49:35 PM PDT 24
Peak memory 214180 kb
Host smart-92be0793-ed58-4132-b69a-31fdf92cd094
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428623042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3428623042
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3120702045
Short name T941
Test name
Test status
Simulation time 90815094 ps
CPU time 1.64 seconds
Started Jun 07 06:49:21 PM PDT 24
Finished Jun 07 06:49:24 PM PDT 24
Peak memory 205572 kb
Host smart-5e89c987-e595-40d3-ae95-b064a757ebe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120702045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3120702045
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2620806091
Short name T167
Test name
Test status
Simulation time 1115384062 ps
CPU time 7.96 seconds
Started Jun 07 06:49:31 PM PDT 24
Finished Jun 07 06:49:40 PM PDT 24
Peak memory 213872 kb
Host smart-4fab6119-34cf-4762-991f-f42f0262e908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620806091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2620806091
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.368764151
Short name T964
Test name
Test status
Simulation time 30703103 ps
CPU time 1.8 seconds
Started Jun 07 06:49:39 PM PDT 24
Finished Jun 07 06:49:41 PM PDT 24
Peak memory 213896 kb
Host smart-d36adc6a-a363-456a-a01e-3ef5652fa750
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368764151 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.368764151
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4220885009
Short name T1049
Test name
Test status
Simulation time 15975934 ps
CPU time 1.02 seconds
Started Jun 07 06:49:30 PM PDT 24
Finished Jun 07 06:49:32 PM PDT 24
Peak memory 205296 kb
Host smart-9ab9a2e9-729b-4a4b-8a02-e18e701d3487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220885009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.4220885009
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.245783736
Short name T1019
Test name
Test status
Simulation time 58092089 ps
CPU time 0.77 seconds
Started Jun 07 06:49:30 PM PDT 24
Finished Jun 07 06:49:32 PM PDT 24
Peak memory 205164 kb
Host smart-9f41c11a-9df9-4e3c-b998-90408d40c493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245783736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.245783736
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4031014630
Short name T148
Test name
Test status
Simulation time 840865345 ps
CPU time 3.83 seconds
Started Jun 07 06:49:31 PM PDT 24
Finished Jun 07 06:49:36 PM PDT 24
Peak memory 205584 kb
Host smart-45098872-416d-4b52-a415-1ca696e17c33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031014630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4031014630
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1718751615
Short name T961
Test name
Test status
Simulation time 41188696 ps
CPU time 1.52 seconds
Started Jun 07 06:49:29 PM PDT 24
Finished Jun 07 06:49:32 PM PDT 24
Peak memory 214184 kb
Host smart-4f43d98b-1dcc-4621-a46b-b66a08f02e6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718751615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1718751615
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2838929191
Short name T1076
Test name
Test status
Simulation time 209067053 ps
CPU time 7.65 seconds
Started Jun 07 06:49:30 PM PDT 24
Finished Jun 07 06:49:39 PM PDT 24
Peak memory 220248 kb
Host smart-3852c8df-042f-44a5-bc12-752f907554e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838929191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2838929191
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3321254458
Short name T1001
Test name
Test status
Simulation time 537137168 ps
CPU time 5.76 seconds
Started Jun 07 06:49:31 PM PDT 24
Finished Jun 07 06:49:38 PM PDT 24
Peak memory 213964 kb
Host smart-7e8e9716-90fe-4c2b-99ac-d71c27e66ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321254458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3321254458
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.67396148
Short name T958
Test name
Test status
Simulation time 162099978 ps
CPU time 3.02 seconds
Started Jun 07 06:49:31 PM PDT 24
Finished Jun 07 06:49:35 PM PDT 24
Peak memory 215024 kb
Host smart-491670e0-db41-4b99-b3a9-f199dcbb3372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67396148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.67396148
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3690555559
Short name T1021
Test name
Test status
Simulation time 20625359 ps
CPU time 1.25 seconds
Started Jun 07 06:49:37 PM PDT 24
Finished Jun 07 06:49:39 PM PDT 24
Peak memory 213928 kb
Host smart-ab1ced28-11df-4d54-8880-5cb5c2e34b6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690555559 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3690555559
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3464283686
Short name T151
Test name
Test status
Simulation time 21895595 ps
CPU time 0.96 seconds
Started Jun 07 06:49:37 PM PDT 24
Finished Jun 07 06:49:39 PM PDT 24
Peak memory 205424 kb
Host smart-9b914877-0290-4cb7-ba35-2b062d00751b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464283686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3464283686
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1563363008
Short name T1036
Test name
Test status
Simulation time 20950681 ps
CPU time 0.7 seconds
Started Jun 07 06:49:44 PM PDT 24
Finished Jun 07 06:49:45 PM PDT 24
Peak memory 205288 kb
Host smart-3dc1613e-2077-4ebd-a471-7dd0d4bfce17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563363008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1563363008
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4150923334
Short name T932
Test name
Test status
Simulation time 206792484 ps
CPU time 3.87 seconds
Started Jun 07 06:49:37 PM PDT 24
Finished Jun 07 06:49:42 PM PDT 24
Peak memory 205632 kb
Host smart-3bc43cd3-c7cb-4cf2-b489-9276c60fe4a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150923334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4150923334
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1250347721
Short name T1072
Test name
Test status
Simulation time 138011783 ps
CPU time 2.63 seconds
Started Jun 07 06:49:39 PM PDT 24
Finished Jun 07 06:49:43 PM PDT 24
Peak memory 214200 kb
Host smart-c94bb82a-e181-4ae3-ba46-29a9325ca81f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250347721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1250347721
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.375878113
Short name T975
Test name
Test status
Simulation time 341622372 ps
CPU time 13.77 seconds
Started Jun 07 06:49:37 PM PDT 24
Finished Jun 07 06:49:52 PM PDT 24
Peak memory 214296 kb
Host smart-221b0938-92c9-492b-bd7d-ab5203821c1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375878113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.375878113
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1931763215
Short name T1023
Test name
Test status
Simulation time 109333647 ps
CPU time 2.44 seconds
Started Jun 07 06:49:38 PM PDT 24
Finished Jun 07 06:49:41 PM PDT 24
Peak memory 213804 kb
Host smart-6cc82fc4-8cce-48f6-8b32-af067cfb6529
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931763215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1931763215
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1750321583
Short name T170
Test name
Test status
Simulation time 138566505 ps
CPU time 5.43 seconds
Started Jun 07 06:49:39 PM PDT 24
Finished Jun 07 06:49:45 PM PDT 24
Peak memory 213732 kb
Host smart-73f69d58-ea1e-4f4b-bd4b-0da92cfc727a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750321583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1750321583
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2057586125
Short name T949
Test name
Test status
Simulation time 35805642 ps
CPU time 2.37 seconds
Started Jun 07 06:49:46 PM PDT 24
Finished Jun 07 06:49:49 PM PDT 24
Peak memory 213804 kb
Host smart-83b0ee00-6a74-4cb9-9ccc-58d5fb2c89a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057586125 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2057586125
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.88006412
Short name T982
Test name
Test status
Simulation time 20557784 ps
CPU time 1.22 seconds
Started Jun 07 06:49:47 PM PDT 24
Finished Jun 07 06:49:50 PM PDT 24
Peak memory 205476 kb
Host smart-7641202d-4cd0-4e84-82bb-106658d4a4e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88006412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.88006412
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.120786840
Short name T917
Test name
Test status
Simulation time 113522921 ps
CPU time 0.77 seconds
Started Jun 07 06:49:48 PM PDT 24
Finished Jun 07 06:49:49 PM PDT 24
Peak memory 205292 kb
Host smart-085ae27e-5045-4318-8674-c18715332496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120786840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.120786840
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2179293036
Short name T152
Test name
Test status
Simulation time 356647440 ps
CPU time 1.48 seconds
Started Jun 07 06:49:49 PM PDT 24
Finished Jun 07 06:49:51 PM PDT 24
Peak memory 205624 kb
Host smart-c96f371d-bd40-4b85-b05a-e760c45bde1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179293036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2179293036
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1740512358
Short name T115
Test name
Test status
Simulation time 48401466 ps
CPU time 2 seconds
Started Jun 07 06:49:42 PM PDT 24
Finished Jun 07 06:49:45 PM PDT 24
Peak memory 214148 kb
Host smart-5b93acbd-e7b6-424b-b77a-3826d184427d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740512358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1740512358
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3142173706
Short name T1057
Test name
Test status
Simulation time 76195610 ps
CPU time 3.69 seconds
Started Jun 07 06:49:38 PM PDT 24
Finished Jun 07 06:49:42 PM PDT 24
Peak memory 214252 kb
Host smart-ef4017d0-a597-426b-a5e8-f47517e74e48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142173706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3142173706
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2390165257
Short name T916
Test name
Test status
Simulation time 108886068 ps
CPU time 3.72 seconds
Started Jun 07 06:49:38 PM PDT 24
Finished Jun 07 06:49:42 PM PDT 24
Peak memory 213648 kb
Host smart-f1be9f4b-441f-4fa0-a8fd-26bc87f1b05c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390165257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2390165257
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.391380528
Short name T965
Test name
Test status
Simulation time 440582985 ps
CPU time 5.06 seconds
Started Jun 07 06:49:38 PM PDT 24
Finished Jun 07 06:49:44 PM PDT 24
Peak memory 213836 kb
Host smart-6463c14f-72b4-427b-9b61-d65b72aba9fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391380528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.391380528
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1373473769
Short name T1000
Test name
Test status
Simulation time 411998969 ps
CPU time 1.37 seconds
Started Jun 07 06:49:53 PM PDT 24
Finished Jun 07 06:49:55 PM PDT 24
Peak memory 213776 kb
Host smart-2f629b38-b5ac-4aba-a1e3-5a8f9d281a07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373473769 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1373473769
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2224629712
Short name T924
Test name
Test status
Simulation time 59597270 ps
CPU time 1.11 seconds
Started Jun 07 06:49:48 PM PDT 24
Finished Jun 07 06:49:50 PM PDT 24
Peak memory 205684 kb
Host smart-110f04fb-14ba-4b74-bba1-d620908d5b96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224629712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2224629712
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1729758665
Short name T969
Test name
Test status
Simulation time 17155416 ps
CPU time 0.72 seconds
Started Jun 07 06:49:45 PM PDT 24
Finished Jun 07 06:49:46 PM PDT 24
Peak memory 205316 kb
Host smart-ef262758-786f-47a8-9f87-db5ceb4c7bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729758665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1729758665
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2613554559
Short name T1009
Test name
Test status
Simulation time 163586872 ps
CPU time 1.69 seconds
Started Jun 07 06:49:54 PM PDT 24
Finished Jun 07 06:49:57 PM PDT 24
Peak memory 205644 kb
Host smart-96cc031a-76a4-4375-b405-86d10aedcb00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613554559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2613554559
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3046061024
Short name T120
Test name
Test status
Simulation time 508371388 ps
CPU time 2.94 seconds
Started Jun 07 06:49:50 PM PDT 24
Finished Jun 07 06:49:54 PM PDT 24
Peak memory 214164 kb
Host smart-b554e165-ef27-4d3f-bc7f-004355abd3e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046061024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3046061024
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.427668084
Short name T1005
Test name
Test status
Simulation time 972070498 ps
CPU time 8.39 seconds
Started Jun 07 06:49:47 PM PDT 24
Finished Jun 07 06:49:57 PM PDT 24
Peak memory 214160 kb
Host smart-3a6972bf-e054-4ff2-91ad-1d7eb71e5920
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427668084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.427668084
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1189666575
Short name T1050
Test name
Test status
Simulation time 20799488 ps
CPU time 1.46 seconds
Started Jun 07 06:49:48 PM PDT 24
Finished Jun 07 06:49:50 PM PDT 24
Peak memory 213740 kb
Host smart-58d79c53-c325-4d61-8da9-97a03c5f9996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189666575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1189666575
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1932926960
Short name T926
Test name
Test status
Simulation time 87412401 ps
CPU time 1.51 seconds
Started Jun 07 06:49:57 PM PDT 24
Finished Jun 07 06:50:00 PM PDT 24
Peak memory 213824 kb
Host smart-3e0ad95f-cfac-4844-9263-08f205dbca84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932926960 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1932926960
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1803879264
Short name T939
Test name
Test status
Simulation time 32575948 ps
CPU time 1.1 seconds
Started Jun 07 06:49:54 PM PDT 24
Finished Jun 07 06:49:56 PM PDT 24
Peak memory 205624 kb
Host smart-0461a2cf-398b-4034-8de4-8d995ba32daf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803879264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1803879264
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3251589802
Short name T977
Test name
Test status
Simulation time 36297284 ps
CPU time 0.91 seconds
Started Jun 07 06:49:54 PM PDT 24
Finished Jun 07 06:49:55 PM PDT 24
Peak memory 205284 kb
Host smart-26bf1d96-932c-4014-8382-aa37293a72c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251589802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3251589802
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2390819687
Short name T1081
Test name
Test status
Simulation time 21433549 ps
CPU time 1.43 seconds
Started Jun 07 06:49:56 PM PDT 24
Finished Jun 07 06:49:58 PM PDT 24
Peak memory 205636 kb
Host smart-9b6f3b30-8c69-4266-a29f-233b3e89e23d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390819687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2390819687
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.200180158
Short name T1054
Test name
Test status
Simulation time 623851077 ps
CPU time 4.39 seconds
Started Jun 07 06:49:54 PM PDT 24
Finished Jun 07 06:50:00 PM PDT 24
Peak memory 214108 kb
Host smart-1ec1aa59-88fe-428f-a5e4-99a577cfd1de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200180158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.200180158
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2616221621
Short name T114
Test name
Test status
Simulation time 414273953 ps
CPU time 13.42 seconds
Started Jun 07 06:49:57 PM PDT 24
Finished Jun 07 06:50:11 PM PDT 24
Peak memory 214128 kb
Host smart-25518b27-4164-48eb-bffb-e774404718d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616221621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2616221621
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3117225875
Short name T1056
Test name
Test status
Simulation time 212694910 ps
CPU time 2.36 seconds
Started Jun 07 06:49:53 PM PDT 24
Finished Jun 07 06:49:57 PM PDT 24
Peak memory 205620 kb
Host smart-cbcd59c6-ce86-4186-b2d2-068cad50c21e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117225875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3117225875
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4042472111
Short name T1068
Test name
Test status
Simulation time 197807746 ps
CPU time 2.63 seconds
Started Jun 07 06:49:54 PM PDT 24
Finished Jun 07 06:49:58 PM PDT 24
Peak memory 205604 kb
Host smart-65842139-5e7c-4dae-b3f7-b367f9dff815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042472111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.4042472111
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2763870113
Short name T980
Test name
Test status
Simulation time 604505844 ps
CPU time 1.81 seconds
Started Jun 07 06:49:53 PM PDT 24
Finished Jun 07 06:49:56 PM PDT 24
Peak memory 213900 kb
Host smart-3862661a-4ad8-4faa-9c51-64a7803aca7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763870113 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2763870113
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.810609403
Short name T950
Test name
Test status
Simulation time 30759318 ps
CPU time 0.88 seconds
Started Jun 07 06:49:56 PM PDT 24
Finished Jun 07 06:49:58 PM PDT 24
Peak memory 205364 kb
Host smart-0f573ece-1c33-413a-973a-e91748436586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810609403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.810609403
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.553059717
Short name T933
Test name
Test status
Simulation time 9493506 ps
CPU time 0.68 seconds
Started Jun 07 06:49:55 PM PDT 24
Finished Jun 07 06:49:57 PM PDT 24
Peak memory 205260 kb
Host smart-c270fdf8-537e-4960-9bdb-3998589d1105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553059717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.553059717
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2699078832
Short name T981
Test name
Test status
Simulation time 236318330 ps
CPU time 2.02 seconds
Started Jun 07 06:49:55 PM PDT 24
Finished Jun 07 06:49:59 PM PDT 24
Peak memory 205660 kb
Host smart-524827cd-a3bf-4cec-8d45-128b3dbb884d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699078832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2699078832
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2054342380
Short name T123
Test name
Test status
Simulation time 87741075 ps
CPU time 3.09 seconds
Started Jun 07 06:49:58 PM PDT 24
Finished Jun 07 06:50:02 PM PDT 24
Peak memory 214064 kb
Host smart-6795fe60-5fe6-4826-8288-db119fdd9a24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054342380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2054342380
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2254730103
Short name T1006
Test name
Test status
Simulation time 553181160 ps
CPU time 8.27 seconds
Started Jun 07 06:49:54 PM PDT 24
Finished Jun 07 06:50:03 PM PDT 24
Peak memory 214056 kb
Host smart-aeaea4b9-90e7-4d30-9de5-fe03ea918c5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254730103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2254730103
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.732426034
Short name T995
Test name
Test status
Simulation time 26080655 ps
CPU time 1.67 seconds
Started Jun 07 06:49:53 PM PDT 24
Finished Jun 07 06:49:56 PM PDT 24
Peak memory 213924 kb
Host smart-3f3f251f-51f7-448a-82fb-1f1af45adc01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732426034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.732426034
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.292461395
Short name T946
Test name
Test status
Simulation time 144470497 ps
CPU time 5.31 seconds
Started Jun 07 06:49:54 PM PDT 24
Finished Jun 07 06:50:00 PM PDT 24
Peak memory 213648 kb
Host smart-c25c5395-6fae-47a0-84b6-efcd11ad6d3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292461395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.292461395
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.592910070
Short name T974
Test name
Test status
Simulation time 17891853 ps
CPU time 1.19 seconds
Started Jun 07 06:50:01 PM PDT 24
Finished Jun 07 06:50:02 PM PDT 24
Peak memory 213904 kb
Host smart-9fd721d2-fccf-4b6d-b6b3-ac5701072ee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592910070 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.592910070
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2041434644
Short name T928
Test name
Test status
Simulation time 11629751 ps
CPU time 0.88 seconds
Started Jun 07 06:50:03 PM PDT 24
Finished Jun 07 06:50:05 PM PDT 24
Peak memory 205388 kb
Host smart-d4c1f552-eec5-4c19-a056-3b1bb9835ebf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041434644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2041434644
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.269605193
Short name T966
Test name
Test status
Simulation time 9881449 ps
CPU time 0.72 seconds
Started Jun 07 06:50:05 PM PDT 24
Finished Jun 07 06:50:06 PM PDT 24
Peak memory 205308 kb
Host smart-9c88b57a-5710-4dba-b34e-88f50c07f1fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269605193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.269605193
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4262135428
Short name T996
Test name
Test status
Simulation time 49722410 ps
CPU time 2.55 seconds
Started Jun 07 06:50:04 PM PDT 24
Finished Jun 07 06:50:07 PM PDT 24
Peak memory 205656 kb
Host smart-4a94529e-3c99-4bd0-a494-45c9abca59cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262135428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.4262135428
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2565950597
Short name T1073
Test name
Test status
Simulation time 117475401 ps
CPU time 3.07 seconds
Started Jun 07 06:49:56 PM PDT 24
Finished Jun 07 06:50:01 PM PDT 24
Peak memory 214140 kb
Host smart-a1c0d76a-102f-404e-b3ee-926fd32edd82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565950597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2565950597
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2397359434
Short name T1083
Test name
Test status
Simulation time 75825153 ps
CPU time 3.62 seconds
Started Jun 07 06:49:54 PM PDT 24
Finished Jun 07 06:49:59 PM PDT 24
Peak memory 214204 kb
Host smart-b3f5c90c-44c1-4c34-bd8b-a1bbbccfb6fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397359434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2397359434
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3019795904
Short name T936
Test name
Test status
Simulation time 1053314951 ps
CPU time 3.28 seconds
Started Jun 07 06:50:03 PM PDT 24
Finished Jun 07 06:50:07 PM PDT 24
Peak memory 213812 kb
Host smart-761d656b-892f-485a-9619-f0a502052fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019795904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3019795904
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2358733121
Short name T179
Test name
Test status
Simulation time 100972132 ps
CPU time 4.42 seconds
Started Jun 07 06:50:00 PM PDT 24
Finished Jun 07 06:50:06 PM PDT 24
Peak memory 213896 kb
Host smart-82617d59-c740-4995-a3a6-0ad6b336c290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358733121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2358733121
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.841282697
Short name T976
Test name
Test status
Simulation time 3012442001 ps
CPU time 9.4 seconds
Started Jun 07 06:48:30 PM PDT 24
Finished Jun 07 06:48:41 PM PDT 24
Peak memory 205636 kb
Host smart-1f50c51c-001c-4ae6-b534-b733a6f92f5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841282697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.841282697
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3705551210
Short name T1077
Test name
Test status
Simulation time 588294284 ps
CPU time 7.82 seconds
Started Jun 07 06:48:31 PM PDT 24
Finished Jun 07 06:48:39 PM PDT 24
Peak memory 205532 kb
Host smart-afb026ea-e4aa-44af-a782-adb1819ba5af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705551210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
705551210
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3286949142
Short name T986
Test name
Test status
Simulation time 25132364 ps
CPU time 0.99 seconds
Started Jun 07 06:48:31 PM PDT 24
Finished Jun 07 06:48:33 PM PDT 24
Peak memory 205444 kb
Host smart-bddcf618-e8cb-4211-ace4-0747e58377f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286949142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
286949142
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1787767027
Short name T972
Test name
Test status
Simulation time 170149114 ps
CPU time 1.87 seconds
Started Jun 07 06:48:30 PM PDT 24
Finished Jun 07 06:48:33 PM PDT 24
Peak memory 205512 kb
Host smart-b0ebba5a-1d22-40f1-b97d-02d7d0eb9cdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787767027 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1787767027
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.598129087
Short name T1026
Test name
Test status
Simulation time 35252556 ps
CPU time 0.94 seconds
Started Jun 07 06:48:30 PM PDT 24
Finished Jun 07 06:48:31 PM PDT 24
Peak memory 205360 kb
Host smart-f4ea4c6a-4c28-448d-8671-d4973c006be7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598129087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.598129087
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3382127780
Short name T954
Test name
Test status
Simulation time 19191487 ps
CPU time 0.72 seconds
Started Jun 07 06:48:23 PM PDT 24
Finished Jun 07 06:48:25 PM PDT 24
Peak memory 205248 kb
Host smart-fa9b6f02-c2c8-490d-a871-c1bbc673e1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382127780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3382127780
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3166002219
Short name T922
Test name
Test status
Simulation time 21647624 ps
CPU time 1.46 seconds
Started Jun 07 06:48:31 PM PDT 24
Finished Jun 07 06:48:33 PM PDT 24
Peak memory 205620 kb
Host smart-c1fc8925-900d-4d75-b5cb-6bb68ac43712
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166002219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3166002219
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3558328847
Short name T1042
Test name
Test status
Simulation time 81171834 ps
CPU time 2.51 seconds
Started Jun 07 06:48:23 PM PDT 24
Finished Jun 07 06:48:26 PM PDT 24
Peak memory 214196 kb
Host smart-d85b40fd-5fa4-4103-af5c-f97d0f51c670
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558328847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3558328847
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.154592342
Short name T948
Test name
Test status
Simulation time 344058695 ps
CPU time 6.97 seconds
Started Jun 07 06:48:23 PM PDT 24
Finished Jun 07 06:48:31 PM PDT 24
Peak memory 214296 kb
Host smart-d068d130-c602-4596-9ebe-e09a9ac5f3c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154592342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.154592342
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.91120681
Short name T918
Test name
Test status
Simulation time 93817639 ps
CPU time 3.18 seconds
Started Jun 07 06:48:24 PM PDT 24
Finished Jun 07 06:48:28 PM PDT 24
Peak memory 213700 kb
Host smart-5a88abbd-10eb-4450-be8e-2cefab6252b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91120681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.91120681
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2758613255
Short name T953
Test name
Test status
Simulation time 36586705 ps
CPU time 0.73 seconds
Started Jun 07 06:50:05 PM PDT 24
Finished Jun 07 06:50:06 PM PDT 24
Peak memory 205228 kb
Host smart-b640caea-ebda-4192-8f27-f9bcaebea657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758613255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2758613255
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2301750742
Short name T1055
Test name
Test status
Simulation time 107483470 ps
CPU time 0.8 seconds
Started Jun 07 06:50:01 PM PDT 24
Finished Jun 07 06:50:03 PM PDT 24
Peak memory 205304 kb
Host smart-2ab11963-1c89-4536-b012-b254ad73d76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301750742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2301750742
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2518261516
Short name T957
Test name
Test status
Simulation time 12042329 ps
CPU time 0.85 seconds
Started Jun 07 06:50:03 PM PDT 24
Finished Jun 07 06:50:04 PM PDT 24
Peak memory 205312 kb
Host smart-529ffb3b-942e-46b4-9cb1-9b40f55949bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518261516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2518261516
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.588519309
Short name T1075
Test name
Test status
Simulation time 10976783 ps
CPU time 0.71 seconds
Started Jun 07 06:50:01 PM PDT 24
Finished Jun 07 06:50:02 PM PDT 24
Peak memory 205280 kb
Host smart-b6f8858e-1693-43d6-887e-56ea2d0e6bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588519309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.588519309
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2696788747
Short name T952
Test name
Test status
Simulation time 8969803 ps
CPU time 0.81 seconds
Started Jun 07 06:50:03 PM PDT 24
Finished Jun 07 06:50:05 PM PDT 24
Peak memory 205308 kb
Host smart-209246a8-b3f6-432d-9871-9d1582d3fe94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696788747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2696788747
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.844474224
Short name T1067
Test name
Test status
Simulation time 12149544 ps
CPU time 0.8 seconds
Started Jun 07 06:50:10 PM PDT 24
Finished Jun 07 06:50:13 PM PDT 24
Peak memory 205328 kb
Host smart-57cd502d-e41d-4d26-b545-d025e7e20bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844474224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.844474224
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.984458062
Short name T962
Test name
Test status
Simulation time 26296590 ps
CPU time 0.8 seconds
Started Jun 07 06:50:14 PM PDT 24
Finished Jun 07 06:50:16 PM PDT 24
Peak memory 205192 kb
Host smart-8d77a8a5-51ce-439b-9750-6dd5059263e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984458062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.984458062
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3316122083
Short name T1008
Test name
Test status
Simulation time 41115468 ps
CPU time 0.74 seconds
Started Jun 07 06:50:09 PM PDT 24
Finished Jun 07 06:50:11 PM PDT 24
Peak memory 205312 kb
Host smart-6bdc7c80-e043-4d1a-aedf-201d79fa6cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316122083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3316122083
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3483990047
Short name T983
Test name
Test status
Simulation time 54131771 ps
CPU time 0.76 seconds
Started Jun 07 06:50:08 PM PDT 24
Finished Jun 07 06:50:10 PM PDT 24
Peak memory 205224 kb
Host smart-4dabae1b-8f80-4a54-932e-5d21a499384b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483990047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3483990047
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3112780491
Short name T914
Test name
Test status
Simulation time 37545692 ps
CPU time 0.82 seconds
Started Jun 07 06:50:09 PM PDT 24
Finished Jun 07 06:50:12 PM PDT 24
Peak memory 205204 kb
Host smart-cfd9c6d5-e852-44b9-8418-cbeafc5d8a36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112780491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3112780491
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.620220093
Short name T1016
Test name
Test status
Simulation time 64816949 ps
CPU time 3.63 seconds
Started Jun 07 06:48:37 PM PDT 24
Finished Jun 07 06:48:41 PM PDT 24
Peak memory 205660 kb
Host smart-90243d6c-de73-4c57-876d-af556c79284b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620220093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.620220093
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.303989479
Short name T947
Test name
Test status
Simulation time 1801765607 ps
CPU time 7.47 seconds
Started Jun 07 06:48:35 PM PDT 24
Finished Jun 07 06:48:43 PM PDT 24
Peak memory 205440 kb
Host smart-3767bd33-5f98-4833-9ef3-a437cbd16913
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303989479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.303989479
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3650480529
Short name T1012
Test name
Test status
Simulation time 105766546 ps
CPU time 0.99 seconds
Started Jun 07 06:48:37 PM PDT 24
Finished Jun 07 06:48:38 PM PDT 24
Peak memory 205456 kb
Host smart-95a937cc-dbc5-4fb3-9317-44eb1dd5d81a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650480529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
650480529
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.541994037
Short name T921
Test name
Test status
Simulation time 311447930 ps
CPU time 1.69 seconds
Started Jun 07 06:48:44 PM PDT 24
Finished Jun 07 06:48:47 PM PDT 24
Peak memory 213940 kb
Host smart-b0dfce0f-7ee9-4d96-aae2-f3f22157bedf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541994037 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.541994037
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2164789832
Short name T973
Test name
Test status
Simulation time 31122423 ps
CPU time 1.11 seconds
Started Jun 07 06:48:36 PM PDT 24
Finished Jun 07 06:48:38 PM PDT 24
Peak memory 205672 kb
Host smart-abd02341-ae9f-4ed6-8de8-125c455e2c78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164789832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2164789832
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1215524045
Short name T1044
Test name
Test status
Simulation time 11017051 ps
CPU time 0.7 seconds
Started Jun 07 06:48:36 PM PDT 24
Finished Jun 07 06:48:37 PM PDT 24
Peak memory 205316 kb
Host smart-b92bea5d-65f9-47e5-a9b8-f54e5ca153ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215524045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1215524045
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3256797191
Short name T927
Test name
Test status
Simulation time 375887705 ps
CPU time 2.79 seconds
Started Jun 07 06:48:36 PM PDT 24
Finished Jun 07 06:48:40 PM PDT 24
Peak memory 205636 kb
Host smart-b9da1b42-c6ae-4f91-ab45-c08c42a52934
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256797191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3256797191
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2995006219
Short name T1018
Test name
Test status
Simulation time 146094154 ps
CPU time 4.36 seconds
Started Jun 07 06:48:35 PM PDT 24
Finished Jun 07 06:48:40 PM PDT 24
Peak memory 214184 kb
Host smart-4d158f8b-c528-4d0a-868e-a877e479951b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995006219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2995006219
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2591678013
Short name T979
Test name
Test status
Simulation time 149773099 ps
CPU time 6.56 seconds
Started Jun 07 06:48:35 PM PDT 24
Finished Jun 07 06:48:42 PM PDT 24
Peak memory 214204 kb
Host smart-19bfc3e1-fdc6-4d09-949b-0a9f13f290ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591678013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2591678013
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1758049653
Short name T1010
Test name
Test status
Simulation time 289799233 ps
CPU time 3.31 seconds
Started Jun 07 06:48:35 PM PDT 24
Finished Jun 07 06:48:39 PM PDT 24
Peak memory 221940 kb
Host smart-98aaed02-07d6-4dc0-b195-6ea4505988f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758049653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1758049653
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2942698573
Short name T915
Test name
Test status
Simulation time 37723379 ps
CPU time 0.8 seconds
Started Jun 07 06:50:09 PM PDT 24
Finished Jun 07 06:50:11 PM PDT 24
Peak memory 205288 kb
Host smart-d98c475c-6d7a-4eac-9c89-11f62f68facb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942698573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2942698573
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3029873933
Short name T1017
Test name
Test status
Simulation time 90231918 ps
CPU time 0.84 seconds
Started Jun 07 06:50:09 PM PDT 24
Finished Jun 07 06:50:11 PM PDT 24
Peak memory 205292 kb
Host smart-c5ab6866-0524-473e-857a-f90cadceecb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029873933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3029873933
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.769302026
Short name T987
Test name
Test status
Simulation time 11973965 ps
CPU time 0.87 seconds
Started Jun 07 06:50:14 PM PDT 24
Finished Jun 07 06:50:16 PM PDT 24
Peak memory 205340 kb
Host smart-0eefd10c-4517-4772-ac0b-c3a4ff42ea53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769302026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.769302026
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3798925660
Short name T942
Test name
Test status
Simulation time 10354559 ps
CPU time 0.72 seconds
Started Jun 07 06:50:09 PM PDT 24
Finished Jun 07 06:50:11 PM PDT 24
Peak memory 205312 kb
Host smart-6a098685-2aa3-4d87-af3b-28e89514941a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798925660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3798925660
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3514043908
Short name T925
Test name
Test status
Simulation time 14556536 ps
CPU time 0.9 seconds
Started Jun 07 06:50:09 PM PDT 24
Finished Jun 07 06:50:12 PM PDT 24
Peak memory 205376 kb
Host smart-3fac86a5-2951-454e-821b-3c529be7d688
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514043908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3514043908
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2750612489
Short name T920
Test name
Test status
Simulation time 33852310 ps
CPU time 0.77 seconds
Started Jun 07 06:50:08 PM PDT 24
Finished Jun 07 06:50:10 PM PDT 24
Peak memory 205268 kb
Host smart-8941ee83-32ae-4bf9-b707-d1a16c95d3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750612489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2750612489
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1857438127
Short name T913
Test name
Test status
Simulation time 11769786 ps
CPU time 0.83 seconds
Started Jun 07 06:50:10 PM PDT 24
Finished Jun 07 06:50:13 PM PDT 24
Peak memory 205284 kb
Host smart-bc5fee6c-af16-4f88-8f60-7874bed2a9ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857438127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1857438127
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1469067980
Short name T989
Test name
Test status
Simulation time 16863386 ps
CPU time 0.72 seconds
Started Jun 07 06:50:13 PM PDT 24
Finished Jun 07 06:50:15 PM PDT 24
Peak memory 205112 kb
Host smart-ae941464-0fd9-4393-b36f-03aad10aaf49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469067980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1469067980
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4230947216
Short name T929
Test name
Test status
Simulation time 11205247 ps
CPU time 0.82 seconds
Started Jun 07 06:50:13 PM PDT 24
Finished Jun 07 06:50:15 PM PDT 24
Peak memory 205416 kb
Host smart-b2a46be3-df74-4e44-8f8f-5b0bd4df1fde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230947216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4230947216
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.381628298
Short name T1015
Test name
Test status
Simulation time 76150496 ps
CPU time 0.77 seconds
Started Jun 07 06:50:13 PM PDT 24
Finished Jun 07 06:50:15 PM PDT 24
Peak memory 205336 kb
Host smart-fd4acd76-d7cb-404d-887e-c49b817a77d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381628298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.381628298
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1858100140
Short name T1014
Test name
Test status
Simulation time 2011210465 ps
CPU time 10.4 seconds
Started Jun 07 06:48:50 PM PDT 24
Finished Jun 07 06:49:01 PM PDT 24
Peak memory 205616 kb
Host smart-cf71a427-4775-4ea6-8e17-52359cd548ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858100140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
858100140
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2967999226
Short name T991
Test name
Test status
Simulation time 136377891 ps
CPU time 6.28 seconds
Started Jun 07 06:48:49 PM PDT 24
Finished Jun 07 06:48:57 PM PDT 24
Peak memory 205668 kb
Host smart-9f6970d1-9880-473c-8e13-186cfc152deb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967999226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
967999226
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1390682894
Short name T1020
Test name
Test status
Simulation time 159515323 ps
CPU time 1.37 seconds
Started Jun 07 06:48:50 PM PDT 24
Finished Jun 07 06:48:52 PM PDT 24
Peak memory 205520 kb
Host smart-b2e67fc7-03f0-4474-81e4-cdb4e677fec8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390682894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
390682894
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4227690307
Short name T1043
Test name
Test status
Simulation time 46516421 ps
CPU time 1.82 seconds
Started Jun 07 06:48:49 PM PDT 24
Finished Jun 07 06:48:52 PM PDT 24
Peak memory 213836 kb
Host smart-a57fae94-dc24-45ff-b43a-2f5a934ec1f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227690307 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4227690307
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.767225237
Short name T1024
Test name
Test status
Simulation time 31793688 ps
CPU time 1.67 seconds
Started Jun 07 06:48:49 PM PDT 24
Finished Jun 07 06:48:52 PM PDT 24
Peak memory 205544 kb
Host smart-67a4a5dc-33c7-439d-993a-d3cfcbc4470a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767225237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.767225237
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2709089185
Short name T990
Test name
Test status
Simulation time 15525901 ps
CPU time 0.79 seconds
Started Jun 07 06:48:44 PM PDT 24
Finished Jun 07 06:48:46 PM PDT 24
Peak memory 205288 kb
Host smart-a828a7b7-6be2-4c9b-a6bb-7d69b32fcd94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709089185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2709089185
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2348188232
Short name T1030
Test name
Test status
Simulation time 195168240 ps
CPU time 1.65 seconds
Started Jun 07 06:48:48 PM PDT 24
Finished Jun 07 06:48:50 PM PDT 24
Peak memory 205640 kb
Host smart-ba9be8aa-a392-40bc-bbe7-541c6a3a7ff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348188232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2348188232
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3603010477
Short name T1071
Test name
Test status
Simulation time 61348603 ps
CPU time 2.46 seconds
Started Jun 07 06:48:43 PM PDT 24
Finished Jun 07 06:48:47 PM PDT 24
Peak memory 214108 kb
Host smart-fbfef7d4-84bf-4b7b-9b39-837512b4a68c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603010477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3603010477
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2772758991
Short name T1029
Test name
Test status
Simulation time 792523011 ps
CPU time 9.32 seconds
Started Jun 07 06:48:43 PM PDT 24
Finished Jun 07 06:48:54 PM PDT 24
Peak memory 214084 kb
Host smart-885ea4c0-5960-43be-91d5-fd42926fb949
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772758991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2772758991
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.11241083
Short name T1025
Test name
Test status
Simulation time 171173848 ps
CPU time 2.76 seconds
Started Jun 07 06:48:42 PM PDT 24
Finished Jun 07 06:48:46 PM PDT 24
Peak memory 213852 kb
Host smart-3dac591a-adbe-4d64-a4ee-4a16007f2864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11241083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.11241083
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2910817519
Short name T350
Test name
Test status
Simulation time 221782996 ps
CPU time 3.43 seconds
Started Jun 07 06:48:45 PM PDT 24
Finished Jun 07 06:48:49 PM PDT 24
Peak memory 205620 kb
Host smart-69b29636-dc05-4b13-ae20-097d5b2535d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910817519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2910817519
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3517143352
Short name T959
Test name
Test status
Simulation time 21387193 ps
CPU time 0.72 seconds
Started Jun 07 06:50:08 PM PDT 24
Finished Jun 07 06:50:10 PM PDT 24
Peak memory 205300 kb
Host smart-147aafab-6f88-48cf-8f90-40640afeb7bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517143352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3517143352
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1015622482
Short name T931
Test name
Test status
Simulation time 39362781 ps
CPU time 0.71 seconds
Started Jun 07 06:50:10 PM PDT 24
Finished Jun 07 06:50:13 PM PDT 24
Peak memory 205284 kb
Host smart-5254db81-eaa3-4297-bea8-fd78007b2b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015622482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1015622482
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1963658015
Short name T968
Test name
Test status
Simulation time 42377709 ps
CPU time 0.83 seconds
Started Jun 07 06:50:09 PM PDT 24
Finished Jun 07 06:50:11 PM PDT 24
Peak memory 205300 kb
Host smart-60e9d0e4-bf05-473c-a205-94a5f238512c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963658015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1963658015
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2243877015
Short name T999
Test name
Test status
Simulation time 38211459 ps
CPU time 0.84 seconds
Started Jun 07 06:50:08 PM PDT 24
Finished Jun 07 06:50:11 PM PDT 24
Peak memory 205148 kb
Host smart-bfc960f0-9efd-4a6a-86fc-2d86e9b5bd30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243877015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2243877015
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.524744035
Short name T993
Test name
Test status
Simulation time 11632437 ps
CPU time 0.73 seconds
Started Jun 07 06:50:14 PM PDT 24
Finished Jun 07 06:50:16 PM PDT 24
Peak memory 205192 kb
Host smart-26463806-a84a-40ef-8d30-33f7058dce3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524744035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.524744035
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3458197598
Short name T940
Test name
Test status
Simulation time 18237080 ps
CPU time 0.8 seconds
Started Jun 07 06:50:10 PM PDT 24
Finished Jun 07 06:50:12 PM PDT 24
Peak memory 205312 kb
Host smart-5c759be3-81bf-4080-91b9-97a8bfa71eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458197598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3458197598
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.929447721
Short name T1051
Test name
Test status
Simulation time 17817355 ps
CPU time 0.72 seconds
Started Jun 07 06:50:10 PM PDT 24
Finished Jun 07 06:50:12 PM PDT 24
Peak memory 205240 kb
Host smart-d3e9ea5a-791b-409f-ba4f-54e60f0e172f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929447721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.929447721
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3338544901
Short name T1028
Test name
Test status
Simulation time 36812325 ps
CPU time 0.84 seconds
Started Jun 07 06:50:21 PM PDT 24
Finished Jun 07 06:50:23 PM PDT 24
Peak memory 205288 kb
Host smart-cf5c89ff-087e-43fb-8a6b-26c1021d8364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338544901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3338544901
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3867258410
Short name T956
Test name
Test status
Simulation time 46670138 ps
CPU time 0.88 seconds
Started Jun 07 06:50:20 PM PDT 24
Finished Jun 07 06:50:21 PM PDT 24
Peak memory 205208 kb
Host smart-862d22a1-a851-48b6-803c-6035631962ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867258410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3867258410
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2543196601
Short name T1038
Test name
Test status
Simulation time 48872635 ps
CPU time 0.79 seconds
Started Jun 07 06:50:17 PM PDT 24
Finished Jun 07 06:50:20 PM PDT 24
Peak memory 205148 kb
Host smart-04ece3c4-8f7f-4144-81c9-1b3fde1b07aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543196601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2543196601
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2124355140
Short name T971
Test name
Test status
Simulation time 88237127 ps
CPU time 1.6 seconds
Started Jun 07 06:48:57 PM PDT 24
Finished Jun 07 06:49:00 PM PDT 24
Peak memory 213916 kb
Host smart-c99c3f94-9e1b-44d8-bc8e-9491085972ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124355140 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2124355140
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3221857583
Short name T147
Test name
Test status
Simulation time 30365994 ps
CPU time 1.21 seconds
Started Jun 07 06:48:49 PM PDT 24
Finished Jun 07 06:48:51 PM PDT 24
Peak memory 205600 kb
Host smart-d900e901-e32b-4c48-b298-7544d521e576
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221857583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3221857583
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2052637191
Short name T945
Test name
Test status
Simulation time 43555550 ps
CPU time 0.78 seconds
Started Jun 07 06:48:48 PM PDT 24
Finished Jun 07 06:48:49 PM PDT 24
Peak memory 205220 kb
Host smart-c2b7ff7d-c4ef-4eab-ba64-0369419c7a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052637191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2052637191
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.417387773
Short name T1037
Test name
Test status
Simulation time 81989577 ps
CPU time 1.74 seconds
Started Jun 07 06:48:58 PM PDT 24
Finished Jun 07 06:49:01 PM PDT 24
Peak memory 205684 kb
Host smart-cef007f3-7fa9-4ecf-a956-000e3ebc8639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417387773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.417387773
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.672458579
Short name T1040
Test name
Test status
Simulation time 205456892 ps
CPU time 2.36 seconds
Started Jun 07 06:48:50 PM PDT 24
Finished Jun 07 06:48:54 PM PDT 24
Peak memory 214208 kb
Host smart-af02e61e-5b14-47cc-8e5f-6aa1bed85d4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672458579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.672458579
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.795193955
Short name T955
Test name
Test status
Simulation time 60814641 ps
CPU time 1.88 seconds
Started Jun 07 06:48:49 PM PDT 24
Finished Jun 07 06:48:52 PM PDT 24
Peak memory 213788 kb
Host smart-065833a9-51ae-4b15-b2d3-4fdb76c7e454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795193955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.795193955
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3697092802
Short name T351
Test name
Test status
Simulation time 116506860 ps
CPU time 2.58 seconds
Started Jun 07 06:48:49 PM PDT 24
Finished Jun 07 06:48:52 PM PDT 24
Peak memory 214900 kb
Host smart-c8288f72-ed41-49bf-8048-76853fb97479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697092802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3697092802
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1572986459
Short name T1078
Test name
Test status
Simulation time 55388763 ps
CPU time 1.17 seconds
Started Jun 07 06:49:04 PM PDT 24
Finished Jun 07 06:49:07 PM PDT 24
Peak memory 205604 kb
Host smart-50e0ce8a-cfdf-488b-ad8b-d2d20c848d3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572986459 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1572986459
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3082973581
Short name T1061
Test name
Test status
Simulation time 50363181 ps
CPU time 1.12 seconds
Started Jun 07 06:49:03 PM PDT 24
Finished Jun 07 06:49:06 PM PDT 24
Peak memory 205624 kb
Host smart-67810ba3-e27c-4274-b0b8-2fd85819def6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082973581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3082973581
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.18814899
Short name T1046
Test name
Test status
Simulation time 28741079 ps
CPU time 0.8 seconds
Started Jun 07 06:48:57 PM PDT 24
Finished Jun 07 06:48:59 PM PDT 24
Peak memory 205284 kb
Host smart-576ade24-a556-4e6a-a31a-66b5cc7c743b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18814899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.18814899
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2470869338
Short name T1007
Test name
Test status
Simulation time 1599203783 ps
CPU time 2.63 seconds
Started Jun 07 06:49:02 PM PDT 24
Finished Jun 07 06:49:06 PM PDT 24
Peak memory 205580 kb
Host smart-a45856ac-752e-457c-b17f-1e30fa2191a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470869338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2470869338
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.185820272
Short name T1035
Test name
Test status
Simulation time 159151625 ps
CPU time 2.31 seconds
Started Jun 07 06:48:56 PM PDT 24
Finished Jun 07 06:48:59 PM PDT 24
Peak memory 214196 kb
Host smart-636e8353-c410-426a-af3f-e0b2aedad152
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185820272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.185820272
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3092650730
Short name T1058
Test name
Test status
Simulation time 111266773 ps
CPU time 5.03 seconds
Started Jun 07 06:48:56 PM PDT 24
Finished Jun 07 06:49:03 PM PDT 24
Peak memory 214172 kb
Host smart-551a145c-8148-4fde-9246-38014ff4c41e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092650730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3092650730
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1600180258
Short name T988
Test name
Test status
Simulation time 37831832 ps
CPU time 2.25 seconds
Started Jun 07 06:48:57 PM PDT 24
Finished Jun 07 06:49:00 PM PDT 24
Peak memory 213796 kb
Host smart-ec6b6e56-f6bf-4de4-9386-3ae9a307d179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600180258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1600180258
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3600963630
Short name T1070
Test name
Test status
Simulation time 27538063 ps
CPU time 1.19 seconds
Started Jun 07 06:49:12 PM PDT 24
Finished Jun 07 06:49:14 PM PDT 24
Peak memory 213828 kb
Host smart-8cf1b3a6-c40e-4029-9359-5e792235e883
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600963630 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3600963630
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1585000020
Short name T923
Test name
Test status
Simulation time 87233257 ps
CPU time 1.04 seconds
Started Jun 07 06:49:13 PM PDT 24
Finished Jun 07 06:49:15 PM PDT 24
Peak memory 205544 kb
Host smart-c0b77ce6-5679-4e13-8e43-7d69828c6493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585000020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1585000020
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1557058307
Short name T912
Test name
Test status
Simulation time 63377659 ps
CPU time 0.82 seconds
Started Jun 07 06:49:03 PM PDT 24
Finished Jun 07 06:49:05 PM PDT 24
Peak memory 205244 kb
Host smart-3c75d28f-71bc-4b1b-89f5-5570e258019b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557058307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1557058307
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3108162969
Short name T1004
Test name
Test status
Simulation time 99894905 ps
CPU time 3.8 seconds
Started Jun 07 06:49:14 PM PDT 24
Finished Jun 07 06:49:19 PM PDT 24
Peak memory 205760 kb
Host smart-81105f91-eca4-46d6-be70-b1361bae3ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108162969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3108162969
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3217984590
Short name T967
Test name
Test status
Simulation time 52846455 ps
CPU time 1.68 seconds
Started Jun 07 06:49:05 PM PDT 24
Finished Jun 07 06:49:09 PM PDT 24
Peak memory 214188 kb
Host smart-372537c6-34a2-4645-ab4a-f0ec52c68bf6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217984590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3217984590
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2128106290
Short name T1066
Test name
Test status
Simulation time 444402344 ps
CPU time 5.63 seconds
Started Jun 07 06:49:03 PM PDT 24
Finished Jun 07 06:49:10 PM PDT 24
Peak memory 214260 kb
Host smart-40ada2be-b98a-4a1a-8d93-d93d1f9f0d29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128106290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2128106290
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2558891763
Short name T919
Test name
Test status
Simulation time 77619470 ps
CPU time 2.24 seconds
Started Jun 07 06:49:03 PM PDT 24
Finished Jun 07 06:49:06 PM PDT 24
Peak memory 217052 kb
Host smart-19049605-42d1-4711-af2d-5bc248cdbb1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558891763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2558891763
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3961985655
Short name T1032
Test name
Test status
Simulation time 109456294 ps
CPU time 1.22 seconds
Started Jun 07 06:49:09 PM PDT 24
Finished Jun 07 06:49:11 PM PDT 24
Peak memory 205524 kb
Host smart-cc85aa16-7170-411f-8201-d52a24c6d64c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961985655 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3961985655
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.124318985
Short name T1039
Test name
Test status
Simulation time 16543745 ps
CPU time 0.88 seconds
Started Jun 07 06:49:14 PM PDT 24
Finished Jun 07 06:49:16 PM PDT 24
Peak memory 205472 kb
Host smart-89526db3-9d73-4a11-9ac4-23dcb3362ff8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124318985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.124318985
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3821320661
Short name T1062
Test name
Test status
Simulation time 14230825 ps
CPU time 0.77 seconds
Started Jun 07 06:49:12 PM PDT 24
Finished Jun 07 06:49:13 PM PDT 24
Peak memory 205272 kb
Host smart-ccd803a7-40cc-44dd-ac87-7fc0536ca82f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821320661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3821320661
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1644009356
Short name T146
Test name
Test status
Simulation time 206293772 ps
CPU time 1.39 seconds
Started Jun 07 06:49:13 PM PDT 24
Finished Jun 07 06:49:16 PM PDT 24
Peak memory 205644 kb
Host smart-ee86201b-d210-4c7c-8c10-45a63a8676fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644009356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1644009356
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1345185584
Short name T1002
Test name
Test status
Simulation time 346091521 ps
CPU time 2.95 seconds
Started Jun 07 06:49:10 PM PDT 24
Finished Jun 07 06:49:13 PM PDT 24
Peak memory 214156 kb
Host smart-4f76dd05-d9d1-4975-aba9-dc70f0bc93c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345185584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1345185584
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3440972164
Short name T970
Test name
Test status
Simulation time 562055105 ps
CPU time 4.73 seconds
Started Jun 07 06:49:12 PM PDT 24
Finished Jun 07 06:49:17 PM PDT 24
Peak memory 214196 kb
Host smart-a3574546-c811-4c38-95db-359331b41d7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440972164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3440972164
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2680668377
Short name T934
Test name
Test status
Simulation time 421061054 ps
CPU time 4.24 seconds
Started Jun 07 06:49:14 PM PDT 24
Finished Jun 07 06:49:19 PM PDT 24
Peak memory 213872 kb
Host smart-5d3431e6-ea42-43a4-89e4-77f4af8d0dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680668377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2680668377
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1041299477
Short name T173
Test name
Test status
Simulation time 334118285 ps
CPU time 7.43 seconds
Started Jun 07 06:49:13 PM PDT 24
Finished Jun 07 06:49:22 PM PDT 24
Peak memory 213828 kb
Host smart-5a5de669-2e99-4dcc-8dff-c42e83ef5ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041299477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1041299477
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2960958156
Short name T943
Test name
Test status
Simulation time 718078433 ps
CPU time 1.63 seconds
Started Jun 07 06:49:17 PM PDT 24
Finished Jun 07 06:49:19 PM PDT 24
Peak memory 213872 kb
Host smart-9ed3f1fe-ecb0-4a7d-b6cc-4f2bb4a17d87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960958156 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2960958156
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1865122772
Short name T960
Test name
Test status
Simulation time 57985884 ps
CPU time 1.06 seconds
Started Jun 07 06:49:22 PM PDT 24
Finished Jun 07 06:49:24 PM PDT 24
Peak memory 205504 kb
Host smart-8b0bebe2-cdde-4a49-9c6f-4dcc7f0eb022
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865122772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1865122772
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1494515170
Short name T1063
Test name
Test status
Simulation time 9497111 ps
CPU time 0.77 seconds
Started Jun 07 06:49:20 PM PDT 24
Finished Jun 07 06:49:22 PM PDT 24
Peak memory 205312 kb
Host smart-bc3ee0e5-784d-4bed-a961-34515d6f9b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494515170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1494515170
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.406963064
Short name T937
Test name
Test status
Simulation time 413483977 ps
CPU time 1.51 seconds
Started Jun 07 06:49:20 PM PDT 24
Finished Jun 07 06:49:22 PM PDT 24
Peak memory 205580 kb
Host smart-c1a4780b-13f0-4fcc-950e-2ffc4c68e744
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406963064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.406963064
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3941249673
Short name T998
Test name
Test status
Simulation time 831367349 ps
CPU time 10.28 seconds
Started Jun 07 06:49:19 PM PDT 24
Finished Jun 07 06:49:30 PM PDT 24
Peak memory 214008 kb
Host smart-55b4b6cc-c0ae-4142-88f0-74d9920b0816
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941249673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3941249673
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1141727231
Short name T1045
Test name
Test status
Simulation time 68277921 ps
CPU time 1.98 seconds
Started Jun 07 06:49:18 PM PDT 24
Finished Jun 07 06:49:20 PM PDT 24
Peak memory 213880 kb
Host smart-30861b72-f30e-4d2f-9832-39ddaf774d12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141727231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1141727231
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.102003103
Short name T413
Test name
Test status
Simulation time 55429060 ps
CPU time 0.72 seconds
Started Jun 07 07:07:55 PM PDT 24
Finished Jun 07 07:07:57 PM PDT 24
Peak memory 205928 kb
Host smart-c6b0c947-4c46-45c7-adc5-ed88c13efd50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102003103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.102003103
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.945048750
Short name T828
Test name
Test status
Simulation time 141115168 ps
CPU time 2.04 seconds
Started Jun 07 07:07:54 PM PDT 24
Finished Jun 07 07:07:57 PM PDT 24
Peak memory 209368 kb
Host smart-5ef12a9e-cacd-4d51-b8c2-b1d0e3d1b4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945048750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.945048750
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3034587311
Short name T243
Test name
Test status
Simulation time 733726229 ps
CPU time 4.74 seconds
Started Jun 07 07:07:55 PM PDT 24
Finished Jun 07 07:08:01 PM PDT 24
Peak memory 214272 kb
Host smart-7cd5548d-870a-4443-bc0d-806937bf53e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034587311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3034587311
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1800835894
Short name T883
Test name
Test status
Simulation time 134727920 ps
CPU time 3.05 seconds
Started Jun 07 07:07:55 PM PDT 24
Finished Jun 07 07:08:00 PM PDT 24
Peak memory 222380 kb
Host smart-1e6f8637-9d14-4fbb-ba28-97365a95a91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800835894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1800835894
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1650233269
Short name T136
Test name
Test status
Simulation time 379798883 ps
CPU time 6.28 seconds
Started Jun 07 07:07:54 PM PDT 24
Finished Jun 07 07:08:01 PM PDT 24
Peak memory 209556 kb
Host smart-15d756fc-c698-4fd6-ac6d-7a666497ad0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650233269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1650233269
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.105072285
Short name T726
Test name
Test status
Simulation time 542099715 ps
CPU time 5.84 seconds
Started Jun 07 07:07:47 PM PDT 24
Finished Jun 07 07:07:54 PM PDT 24
Peak memory 208016 kb
Host smart-6b1045f7-1531-4ddf-9715-47e4cf556d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105072285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.105072285
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2604887225
Short name T689
Test name
Test status
Simulation time 109963443 ps
CPU time 1.8 seconds
Started Jun 07 07:07:49 PM PDT 24
Finished Jun 07 07:07:51 PM PDT 24
Peak memory 206960 kb
Host smart-7a2f5582-0d7c-41e2-910a-70730c717240
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604887225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2604887225
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.734392460
Short name T662
Test name
Test status
Simulation time 35885673 ps
CPU time 2.2 seconds
Started Jun 07 07:07:47 PM PDT 24
Finished Jun 07 07:07:50 PM PDT 24
Peak memory 206920 kb
Host smart-d1047552-a884-4b6e-a768-9df075813b56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734392460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.734392460
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3825364609
Short name T137
Test name
Test status
Simulation time 434682760 ps
CPU time 3.9 seconds
Started Jun 07 07:07:54 PM PDT 24
Finished Jun 07 07:07:59 PM PDT 24
Peak memory 207280 kb
Host smart-158dbee7-2202-447b-83ea-30040e0279e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825364609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3825364609
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2096799201
Short name T462
Test name
Test status
Simulation time 66334664 ps
CPU time 2.82 seconds
Started Jun 07 07:07:54 PM PDT 24
Finished Jun 07 07:07:58 PM PDT 24
Peak memory 209936 kb
Host smart-eee62792-a9c4-43e2-a0f1-4cd05e8afe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096799201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2096799201
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1200398298
Short name T678
Test name
Test status
Simulation time 353335130 ps
CPU time 3.08 seconds
Started Jun 07 07:07:47 PM PDT 24
Finished Jun 07 07:07:51 PM PDT 24
Peak memory 208300 kb
Host smart-58743ea1-d066-4b7d-9cd8-41a39dbc1bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200398298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1200398298
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.979895660
Short name T200
Test name
Test status
Simulation time 639872657 ps
CPU time 7.26 seconds
Started Jun 07 07:07:54 PM PDT 24
Finished Jun 07 07:08:02 PM PDT 24
Peak memory 209492 kb
Host smart-c997530a-e75c-4fd9-aa1d-b36645e7661d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979895660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.979895660
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2977958735
Short name T541
Test name
Test status
Simulation time 124144649 ps
CPU time 4.65 seconds
Started Jun 07 07:07:56 PM PDT 24
Finished Jun 07 07:08:02 PM PDT 24
Peak memory 207616 kb
Host smart-a82beaa7-cb95-45ee-ae3a-da5490d1046d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977958735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2977958735
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.103529474
Short name T806
Test name
Test status
Simulation time 488309174 ps
CPU time 2.25 seconds
Started Jun 07 07:07:55 PM PDT 24
Finished Jun 07 07:07:59 PM PDT 24
Peak memory 210196 kb
Host smart-60c01461-c4d1-4f08-bea2-3efcbc2b130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103529474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.103529474
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2339465324
Short name T666
Test name
Test status
Simulation time 122241594 ps
CPU time 0.85 seconds
Started Jun 07 07:08:02 PM PDT 24
Finished Jun 07 07:08:04 PM PDT 24
Peak memory 205960 kb
Host smart-7e79e515-9bf8-406f-bc2f-2a84202ccf72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339465324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2339465324
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.129792621
Short name T237
Test name
Test status
Simulation time 33184302 ps
CPU time 2.16 seconds
Started Jun 07 07:08:05 PM PDT 24
Finished Jun 07 07:08:08 PM PDT 24
Peak memory 214276 kb
Host smart-1ab3a68b-202e-4861-9a09-e7d464fe1f75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129792621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.129792621
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3346236061
Short name T65
Test name
Test status
Simulation time 95129249 ps
CPU time 3.56 seconds
Started Jun 07 07:08:01 PM PDT 24
Finished Jun 07 07:08:06 PM PDT 24
Peak memory 218320 kb
Host smart-86af2a92-6ab6-48c7-a652-9e145e69c332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346236061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3346236061
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.153984310
Short name T615
Test name
Test status
Simulation time 448896021 ps
CPU time 3.82 seconds
Started Jun 07 07:08:04 PM PDT 24
Finished Jun 07 07:08:09 PM PDT 24
Peak memory 206084 kb
Host smart-7132fcb7-bef2-4712-99d9-c05d55a41905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153984310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.153984310
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.89673910
Short name T225
Test name
Test status
Simulation time 2872623055 ps
CPU time 20.2 seconds
Started Jun 07 07:08:05 PM PDT 24
Finished Jun 07 07:08:26 PM PDT 24
Peak memory 214384 kb
Host smart-8b16fdec-0f2b-4a01-9b94-52458ff92545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89673910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.89673910
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3175787666
Short name T844
Test name
Test status
Simulation time 150814830 ps
CPU time 5.79 seconds
Started Jun 07 07:07:54 PM PDT 24
Finished Jun 07 07:08:01 PM PDT 24
Peak memory 208036 kb
Host smart-780f7da9-0977-43a4-a319-e31548c8f2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175787666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3175787666
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2117489335
Short name T10
Test name
Test status
Simulation time 300128930 ps
CPU time 9.22 seconds
Started Jun 07 07:08:05 PM PDT 24
Finished Jun 07 07:08:15 PM PDT 24
Peak memory 230544 kb
Host smart-9463eddf-cdc4-4e84-8326-564224d97b5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117489335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2117489335
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1189416925
Short name T781
Test name
Test status
Simulation time 40099802 ps
CPU time 1.91 seconds
Started Jun 07 07:07:53 PM PDT 24
Finished Jun 07 07:07:56 PM PDT 24
Peak memory 208376 kb
Host smart-17725cf4-e6d6-4148-9a06-52a178b441f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189416925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1189416925
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2346991409
Short name T496
Test name
Test status
Simulation time 2339884461 ps
CPU time 14.86 seconds
Started Jun 07 07:07:59 PM PDT 24
Finished Jun 07 07:08:15 PM PDT 24
Peak memory 208740 kb
Host smart-0481ed72-0953-4d38-87d1-07b37ee6041a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346991409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2346991409
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1782295332
Short name T822
Test name
Test status
Simulation time 178631979 ps
CPU time 7.71 seconds
Started Jun 07 07:07:56 PM PDT 24
Finished Jun 07 07:08:05 PM PDT 24
Peak memory 208036 kb
Host smart-e7451006-6485-4783-8c38-6e5b89434fcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782295332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1782295332
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.4027340532
Short name T208
Test name
Test status
Simulation time 145588141 ps
CPU time 2.63 seconds
Started Jun 07 07:07:58 PM PDT 24
Finished Jun 07 07:08:02 PM PDT 24
Peak memory 208628 kb
Host smart-798c26cf-1794-47c3-8ac9-359f9cbde960
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027340532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.4027340532
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2470780921
Short name T401
Test name
Test status
Simulation time 139632876 ps
CPU time 2.76 seconds
Started Jun 07 07:08:02 PM PDT 24
Finished Jun 07 07:08:06 PM PDT 24
Peak memory 208168 kb
Host smart-7c226e3c-a856-441c-a7c1-699fe66a307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470780921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2470780921
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.4189172530
Short name T399
Test name
Test status
Simulation time 100355119 ps
CPU time 3.66 seconds
Started Jun 07 07:07:55 PM PDT 24
Finished Jun 07 07:08:00 PM PDT 24
Peak memory 206744 kb
Host smart-63d5c0e6-7977-413c-ac77-9cbbe6410680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189172530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.4189172530
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3471976427
Short name T803
Test name
Test status
Simulation time 1148761628 ps
CPU time 7.12 seconds
Started Jun 07 07:08:02 PM PDT 24
Finished Jun 07 07:08:10 PM PDT 24
Peak memory 220604 kb
Host smart-2faa78b1-08c5-4aa0-b2f5-079c4cae8b94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471976427 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3471976427
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2362948212
Short name T589
Test name
Test status
Simulation time 225541496 ps
CPU time 5.37 seconds
Started Jun 07 07:08:05 PM PDT 24
Finished Jun 07 07:08:11 PM PDT 24
Peak memory 214256 kb
Host smart-4c53899e-0444-457a-af3f-b2cf88959618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362948212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2362948212
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2733644060
Short name T550
Test name
Test status
Simulation time 684370688 ps
CPU time 4.14 seconds
Started Jun 07 07:08:02 PM PDT 24
Finished Jun 07 07:08:07 PM PDT 24
Peak memory 210280 kb
Host smart-6b4f967b-d4ea-431b-8daa-f24474e240a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733644060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2733644060
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.291101684
Short name T428
Test name
Test status
Simulation time 37394455 ps
CPU time 0.84 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:02 PM PDT 24
Peak memory 205960 kb
Host smart-7851382b-3a86-4897-94f8-e6cb9bddd52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291101684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.291101684
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1582877368
Short name T353
Test name
Test status
Simulation time 693789427 ps
CPU time 4.63 seconds
Started Jun 07 07:09:04 PM PDT 24
Finished Jun 07 07:09:11 PM PDT 24
Peak memory 215256 kb
Host smart-5fa538b4-bcd8-415b-bb56-2accd28d65e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582877368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1582877368
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2263466598
Short name T820
Test name
Test status
Simulation time 664016939 ps
CPU time 4.45 seconds
Started Jun 07 07:08:59 PM PDT 24
Finished Jun 07 07:09:06 PM PDT 24
Peak memory 209796 kb
Host smart-d72b4b0c-1a1a-4607-98af-9f24cbc2080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263466598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2263466598
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3412824207
Short name T856
Test name
Test status
Simulation time 110082129 ps
CPU time 3.2 seconds
Started Jun 07 07:09:03 PM PDT 24
Finished Jun 07 07:09:08 PM PDT 24
Peak memory 218240 kb
Host smart-e297022f-bf2a-408c-bf7d-5311885c334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412824207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3412824207
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1188024728
Short name T614
Test name
Test status
Simulation time 2793347995 ps
CPU time 8.05 seconds
Started Jun 07 07:08:56 PM PDT 24
Finished Jun 07 07:09:08 PM PDT 24
Peak memory 214508 kb
Host smart-8de5e0d5-fba5-4393-9e0c-2a474bc3c405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188024728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1188024728
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2198921152
Short name T469
Test name
Test status
Simulation time 21868238 ps
CPU time 1.86 seconds
Started Jun 07 07:08:51 PM PDT 24
Finished Jun 07 07:08:57 PM PDT 24
Peak memory 206916 kb
Host smart-c70dd538-27e8-41b8-8629-51bff3815bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198921152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2198921152
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1264338243
Short name T572
Test name
Test status
Simulation time 156984632 ps
CPU time 2.29 seconds
Started Jun 07 07:08:56 PM PDT 24
Finished Jun 07 07:09:03 PM PDT 24
Peak memory 206948 kb
Host smart-adf41b66-7269-4af6-966b-7a54e2c4ab90
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264338243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1264338243
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1408482164
Short name T461
Test name
Test status
Simulation time 243104557 ps
CPU time 3.14 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:04 PM PDT 24
Peak memory 206844 kb
Host smart-336a399a-07d2-4d72-83b6-68c55b1a7efb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408482164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1408482164
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3157546375
Short name T248
Test name
Test status
Simulation time 216572314 ps
CPU time 3.26 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:04 PM PDT 24
Peak memory 218384 kb
Host smart-03ddc700-59cc-4581-8db7-02932e35c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157546375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3157546375
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.172294176
Short name T832
Test name
Test status
Simulation time 272355752 ps
CPU time 3.08 seconds
Started Jun 07 07:08:47 PM PDT 24
Finished Jun 07 07:08:55 PM PDT 24
Peak memory 208552 kb
Host smart-98156cc6-e8ec-4104-a2b0-51c08c6051a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172294176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.172294176
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3117988201
Short name T184
Test name
Test status
Simulation time 1981115651 ps
CPU time 31.88 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:33 PM PDT 24
Peak memory 222540 kb
Host smart-5049dc04-a546-43de-a3f6-b82a112bf5f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117988201 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3117988201
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2878712912
Short name T418
Test name
Test status
Simulation time 99641894 ps
CPU time 5.09 seconds
Started Jun 07 07:08:59 PM PDT 24
Finished Jun 07 07:09:07 PM PDT 24
Peak memory 210024 kb
Host smart-dece5682-a0b8-4003-986b-f41f444ba3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878712912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2878712912
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2674876818
Short name T493
Test name
Test status
Simulation time 144708987 ps
CPU time 2.99 seconds
Started Jun 07 07:09:03 PM PDT 24
Finished Jun 07 07:09:08 PM PDT 24
Peak memory 210580 kb
Host smart-52b49aa0-a201-442c-a5c6-ad950f38bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674876818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2674876818
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2769530246
Short name T800
Test name
Test status
Simulation time 48759118 ps
CPU time 0.76 seconds
Started Jun 07 07:09:07 PM PDT 24
Finished Jun 07 07:09:09 PM PDT 24
Peak memory 205896 kb
Host smart-90e8a1d0-5162-494a-a33c-659442f62086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769530246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2769530246
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3690974587
Short name T38
Test name
Test status
Simulation time 85393591 ps
CPU time 3.77 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:05 PM PDT 24
Peak memory 214360 kb
Host smart-2030d23a-08b7-448f-93e3-2760e541b5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690974587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3690974587
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2787848418
Short name T751
Test name
Test status
Simulation time 22657301 ps
CPU time 1.81 seconds
Started Jun 07 07:08:56 PM PDT 24
Finished Jun 07 07:09:02 PM PDT 24
Peak memory 214312 kb
Host smart-aacad682-7066-4364-b168-0ef4b0055d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787848418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2787848418
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1722086465
Short name T91
Test name
Test status
Simulation time 161069643 ps
CPU time 1.93 seconds
Started Jun 07 07:09:00 PM PDT 24
Finished Jun 07 07:09:05 PM PDT 24
Peak memory 214268 kb
Host smart-66198e97-feba-4f89-a762-df3853c699ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722086465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1722086465
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3793603204
Short name T634
Test name
Test status
Simulation time 123601565 ps
CPU time 3.29 seconds
Started Jun 07 07:08:56 PM PDT 24
Finished Jun 07 07:09:04 PM PDT 24
Peak memory 218092 kb
Host smart-2c95b337-5e52-4404-9b0b-9bf7d26550fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793603204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3793603204
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1249578378
Short name T198
Test name
Test status
Simulation time 116148215 ps
CPU time 5.95 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:07 PM PDT 24
Peak memory 209692 kb
Host smart-98405910-91ad-4833-a6a8-801db99512d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249578378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1249578378
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2694621527
Short name T534
Test name
Test status
Simulation time 185398837 ps
CPU time 5.04 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:06 PM PDT 24
Peak memory 208608 kb
Host smart-2138f801-8c80-4458-9bd7-6bd98220ee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694621527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2694621527
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3844482309
Short name T455
Test name
Test status
Simulation time 35741491 ps
CPU time 2.46 seconds
Started Jun 07 07:09:00 PM PDT 24
Finished Jun 07 07:09:05 PM PDT 24
Peak memory 208840 kb
Host smart-0b70d339-8183-40a6-b615-4d78507c2021
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844482309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3844482309
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1563278579
Short name T622
Test name
Test status
Simulation time 359688752 ps
CPU time 2.28 seconds
Started Jun 07 07:08:58 PM PDT 24
Finished Jun 07 07:09:04 PM PDT 24
Peak memory 208840 kb
Host smart-5e7c0702-ab2d-494f-843f-2cfd32f3ce17
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563278579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1563278579
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1417974150
Short name T458
Test name
Test status
Simulation time 160827924 ps
CPU time 3.17 seconds
Started Jun 07 07:08:56 PM PDT 24
Finished Jun 07 07:09:03 PM PDT 24
Peak memory 206980 kb
Host smart-46d81194-c8f9-49c9-8d25-c8ce2c3f7aa5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417974150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1417974150
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2372269787
Short name T582
Test name
Test status
Simulation time 117663535 ps
CPU time 2.3 seconds
Started Jun 07 07:08:59 PM PDT 24
Finished Jun 07 07:09:04 PM PDT 24
Peak memory 214296 kb
Host smart-0f08cb66-b4c0-40e2-ab2c-baffd5180f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372269787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2372269787
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.442389981
Short name T756
Test name
Test status
Simulation time 104697140 ps
CPU time 2.68 seconds
Started Jun 07 07:08:56 PM PDT 24
Finished Jun 07 07:09:03 PM PDT 24
Peak memory 206972 kb
Host smart-53758071-e89a-4888-bff8-a36b2b5d8bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442389981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.442389981
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1651445784
Short name T842
Test name
Test status
Simulation time 3371555350 ps
CPU time 22.27 seconds
Started Jun 07 07:08:58 PM PDT 24
Finished Jun 07 07:09:24 PM PDT 24
Peak memory 217008 kb
Host smart-b0902cea-73f9-4262-b0df-6a2f4b2046e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651445784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1651445784
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.679530663
Short name T112
Test name
Test status
Simulation time 1068342203 ps
CPU time 10.45 seconds
Started Jun 07 07:08:57 PM PDT 24
Finished Jun 07 07:09:11 PM PDT 24
Peak memory 219520 kb
Host smart-ff353609-4856-49ba-865b-8f6d45f75d95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679530663 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.679530663
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3993853662
Short name T133
Test name
Test status
Simulation time 858980462 ps
CPU time 6.4 seconds
Started Jun 07 07:08:55 PM PDT 24
Finished Jun 07 07:09:06 PM PDT 24
Peak memory 218524 kb
Host smart-a7ace1b3-99f4-4ad2-8ef9-45a652432e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993853662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3993853662
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2978523295
Short name T661
Test name
Test status
Simulation time 153717405 ps
CPU time 2.21 seconds
Started Jun 07 07:08:59 PM PDT 24
Finished Jun 07 07:09:04 PM PDT 24
Peak memory 209976 kb
Host smart-d4433424-52bb-4c83-b538-d8f7816d3609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978523295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2978523295
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1250139182
Short name T755
Test name
Test status
Simulation time 33385460 ps
CPU time 0.81 seconds
Started Jun 07 07:09:03 PM PDT 24
Finished Jun 07 07:09:06 PM PDT 24
Peak memory 205920 kb
Host smart-4a900f64-cb6d-4ed1-936d-b681c41bfd3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250139182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1250139182
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3280560918
Short name T362
Test name
Test status
Simulation time 50881703 ps
CPU time 3.66 seconds
Started Jun 07 07:09:09 PM PDT 24
Finished Jun 07 07:09:14 PM PDT 24
Peak memory 215536 kb
Host smart-6bbeaf56-48c9-4e0d-bfb8-9163e706ba7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280560918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3280560918
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3161794786
Short name T889
Test name
Test status
Simulation time 170533106 ps
CPU time 3.04 seconds
Started Jun 07 07:09:04 PM PDT 24
Finished Jun 07 07:09:08 PM PDT 24
Peak memory 214408 kb
Host smart-ec29c3b9-d4d9-4b56-9846-b3b0dda048a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161794786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3161794786
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1864962048
Short name T98
Test name
Test status
Simulation time 75772224 ps
CPU time 2.57 seconds
Started Jun 07 07:09:04 PM PDT 24
Finished Jun 07 07:09:08 PM PDT 24
Peak memory 214888 kb
Host smart-c05c0418-064b-48a1-bd21-42c57d24e624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864962048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1864962048
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1650177887
Short name T332
Test name
Test status
Simulation time 52909084 ps
CPU time 2.33 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:24 PM PDT 24
Peak memory 214268 kb
Host smart-16ecb6dc-a096-4232-8efb-13c01293c96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650177887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1650177887
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.185795993
Short name T226
Test name
Test status
Simulation time 50996116 ps
CPU time 3.68 seconds
Started Jun 07 07:09:07 PM PDT 24
Finished Jun 07 07:09:12 PM PDT 24
Peak memory 214324 kb
Host smart-0c3bbd85-2d0a-41a6-b994-7b1daf49611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185795993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.185795993
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1161838086
Short name T695
Test name
Test status
Simulation time 772377732 ps
CPU time 5.49 seconds
Started Jun 07 07:09:04 PM PDT 24
Finished Jun 07 07:09:11 PM PDT 24
Peak memory 208980 kb
Host smart-552d2eea-2b61-43ed-83af-e42d3bcc0ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161838086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1161838086
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1787040951
Short name T859
Test name
Test status
Simulation time 76466308 ps
CPU time 1.92 seconds
Started Jun 07 07:09:05 PM PDT 24
Finished Jun 07 07:09:09 PM PDT 24
Peak memory 206080 kb
Host smart-3cc12aec-2f00-449a-ae05-d23b2d096e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787040951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1787040951
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1091238951
Short name T705
Test name
Test status
Simulation time 28251489 ps
CPU time 2.35 seconds
Started Jun 07 07:09:04 PM PDT 24
Finished Jun 07 07:09:08 PM PDT 24
Peak memory 208956 kb
Host smart-f75b0e16-0737-4c2c-9190-abf91bff5ca7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091238951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1091238951
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3059918847
Short name T506
Test name
Test status
Simulation time 444585327 ps
CPU time 3.9 seconds
Started Jun 07 07:09:05 PM PDT 24
Finished Jun 07 07:09:11 PM PDT 24
Peak memory 208552 kb
Host smart-d7b23eb6-cc85-45f3-9332-b8b27b20d703
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059918847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3059918847
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.828601640
Short name T712
Test name
Test status
Simulation time 468266311 ps
CPU time 3.86 seconds
Started Jun 07 07:09:05 PM PDT 24
Finished Jun 07 07:09:11 PM PDT 24
Peak memory 208776 kb
Host smart-b85e2a8b-2146-4227-b666-25e983527b56
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828601640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.828601640
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1291990629
Short name T438
Test name
Test status
Simulation time 241869438 ps
CPU time 1.89 seconds
Started Jun 07 07:09:07 PM PDT 24
Finished Jun 07 07:09:10 PM PDT 24
Peak memory 207688 kb
Host smart-0cdf58e9-b1af-4d2f-888d-6f2df6d33887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291990629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1291990629
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.417443978
Short name T790
Test name
Test status
Simulation time 2288322223 ps
CPU time 10.96 seconds
Started Jun 07 07:09:03 PM PDT 24
Finished Jun 07 07:09:15 PM PDT 24
Peak memory 207952 kb
Host smart-2fb8e2cd-b08c-41d8-9f4b-af6eb04fe19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417443978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.417443978
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3001219114
Short name T852
Test name
Test status
Simulation time 226344265 ps
CPU time 4.47 seconds
Started Jun 07 07:09:04 PM PDT 24
Finished Jun 07 07:09:10 PM PDT 24
Peak memory 207720 kb
Host smart-031ebd7f-874a-498f-95f8-9054b40e5ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001219114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3001219114
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2979049331
Short name T40
Test name
Test status
Simulation time 378583667 ps
CPU time 2.54 seconds
Started Jun 07 07:09:06 PM PDT 24
Finished Jun 07 07:09:09 PM PDT 24
Peak memory 210308 kb
Host smart-d6259127-79c6-4ca1-8694-e3eaeec4528a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979049331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2979049331
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.10110017
Short name T142
Test name
Test status
Simulation time 220903189 ps
CPU time 11.68 seconds
Started Jun 07 07:09:16 PM PDT 24
Finished Jun 07 07:09:28 PM PDT 24
Peak memory 214308 kb
Host smart-6317173e-431c-4fef-b44d-deaf072d6abb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10110017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.10110017
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1037734781
Short name T369
Test name
Test status
Simulation time 943357609 ps
CPU time 2.82 seconds
Started Jun 07 07:09:11 PM PDT 24
Finished Jun 07 07:09:15 PM PDT 24
Peak memory 209564 kb
Host smart-e4933f9f-6ca8-4f43-9fc0-709c1465090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037734781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1037734781
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4005099824
Short name T720
Test name
Test status
Simulation time 2205938678 ps
CPU time 6.36 seconds
Started Jun 07 07:09:10 PM PDT 24
Finished Jun 07 07:09:18 PM PDT 24
Peak memory 208456 kb
Host smart-6afe0ddd-6fbf-4735-a4dc-be4f10e510b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005099824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4005099824
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.4191494453
Short name T242
Test name
Test status
Simulation time 91578038 ps
CPU time 1.83 seconds
Started Jun 07 07:09:18 PM PDT 24
Finished Jun 07 07:09:21 PM PDT 24
Peak memory 214328 kb
Host smart-6ae1c21a-6619-4ea8-ac51-e5c878358008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191494453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4191494453
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2285308855
Short name T517
Test name
Test status
Simulation time 32937176 ps
CPU time 2.36 seconds
Started Jun 07 07:09:11 PM PDT 24
Finished Jun 07 07:09:15 PM PDT 24
Peak memory 214320 kb
Host smart-8e383c63-66e3-4c95-bbc9-d67b0d376c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285308855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2285308855
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2541048052
Short name T763
Test name
Test status
Simulation time 1112440444 ps
CPU time 4.06 seconds
Started Jun 07 07:09:06 PM PDT 24
Finished Jun 07 07:09:11 PM PDT 24
Peak memory 207324 kb
Host smart-29f43ed4-a849-479c-af89-4c211c452580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541048052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2541048052
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3864268042
Short name T472
Test name
Test status
Simulation time 857527212 ps
CPU time 23.34 seconds
Started Jun 07 07:09:04 PM PDT 24
Finished Jun 07 07:09:29 PM PDT 24
Peak memory 208200 kb
Host smart-70638b87-2706-40bf-9156-2e9b3ae8d2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864268042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3864268042
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3227059256
Short name T616
Test name
Test status
Simulation time 1551015878 ps
CPU time 35.22 seconds
Started Jun 07 07:09:08 PM PDT 24
Finished Jun 07 07:09:45 PM PDT 24
Peak memory 208288 kb
Host smart-4f5cbd8a-55f3-4e0a-bd31-71170b62712f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227059256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3227059256
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.473295560
Short name T600
Test name
Test status
Simulation time 1274599877 ps
CPU time 5.27 seconds
Started Jun 07 07:09:09 PM PDT 24
Finished Jun 07 07:09:16 PM PDT 24
Peak memory 207852 kb
Host smart-2500865b-ac05-44fb-939a-3aa4cdca11d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473295560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.473295560
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3016922525
Short name T902
Test name
Test status
Simulation time 70038459 ps
CPU time 2.14 seconds
Started Jun 07 07:09:11 PM PDT 24
Finished Jun 07 07:09:14 PM PDT 24
Peak memory 208536 kb
Host smart-0fd752c4-8532-4e94-b984-1b03a79ff916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016922525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3016922525
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3036228709
Short name T895
Test name
Test status
Simulation time 88024728 ps
CPU time 2.36 seconds
Started Jun 07 07:09:03 PM PDT 24
Finished Jun 07 07:09:07 PM PDT 24
Peak memory 208612 kb
Host smart-4334b9e1-15d8-4548-acfd-089e5ea5e155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036228709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3036228709
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1400428852
Short name T103
Test name
Test status
Simulation time 328963569 ps
CPU time 14.41 seconds
Started Jun 07 07:09:13 PM PDT 24
Finished Jun 07 07:09:29 PM PDT 24
Peak memory 215068 kb
Host smart-f23186b5-0a93-474f-b6fc-f236c295a03e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400428852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1400428852
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.492219417
Short name T127
Test name
Test status
Simulation time 1392926348 ps
CPU time 10.19 seconds
Started Jun 07 07:09:14 PM PDT 24
Finished Jun 07 07:09:25 PM PDT 24
Peak memory 219800 kb
Host smart-38e00074-3769-449f-bcac-e64399ae86cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492219417 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.492219417
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3312598090
Short name T23
Test name
Test status
Simulation time 371576750 ps
CPU time 7.75 seconds
Started Jun 07 07:09:12 PM PDT 24
Finished Jun 07 07:09:21 PM PDT 24
Peak memory 214412 kb
Host smart-0288fcec-3a6c-40cd-8d28-65f7b25a64bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312598090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3312598090
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2408265384
Short name T520
Test name
Test status
Simulation time 222726881 ps
CPU time 2.86 seconds
Started Jun 07 07:09:14 PM PDT 24
Finished Jun 07 07:09:18 PM PDT 24
Peak memory 210528 kb
Host smart-9788df93-2f3b-40e3-a08f-59ee839a25f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408265384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2408265384
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1747173553
Short name T378
Test name
Test status
Simulation time 16110289 ps
CPU time 0.81 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:22 PM PDT 24
Peak memory 205948 kb
Host smart-50c9ae33-ad02-4254-8a8b-cebb5df0e935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747173553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1747173553
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1732907755
Short name T301
Test name
Test status
Simulation time 86654079 ps
CPU time 3.49 seconds
Started Jun 07 07:09:11 PM PDT 24
Finished Jun 07 07:09:15 PM PDT 24
Peak memory 214308 kb
Host smart-8c626908-249b-42d8-8947-d7a071c22556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732907755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1732907755
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3874967091
Short name T899
Test name
Test status
Simulation time 34891981 ps
CPU time 1.74 seconds
Started Jun 07 07:09:14 PM PDT 24
Finished Jun 07 07:09:16 PM PDT 24
Peak memory 214252 kb
Host smart-4239eb45-ca84-4d2f-a872-3f0ffb9e8732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874967091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3874967091
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.4214263616
Short name T642
Test name
Test status
Simulation time 75080096 ps
CPU time 2.23 seconds
Started Jun 07 07:09:19 PM PDT 24
Finished Jun 07 07:09:22 PM PDT 24
Peak memory 209888 kb
Host smart-f48b9bd7-03b0-443a-967e-b494c0e4e864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214263616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.4214263616
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3375948132
Short name T95
Test name
Test status
Simulation time 508611808 ps
CPU time 5.17 seconds
Started Jun 07 07:09:13 PM PDT 24
Finished Jun 07 07:09:19 PM PDT 24
Peak memory 220936 kb
Host smart-9ab11f90-c16e-4811-b20c-47d5fd23c015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375948132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3375948132
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2325778107
Short name T878
Test name
Test status
Simulation time 1696715345 ps
CPU time 7.66 seconds
Started Jun 07 07:09:13 PM PDT 24
Finished Jun 07 07:09:21 PM PDT 24
Peak memory 222428 kb
Host smart-1cc9995a-ca52-4088-ac14-94ed2b16e74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325778107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2325778107
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3244221481
Short name T470
Test name
Test status
Simulation time 118662292 ps
CPU time 3.41 seconds
Started Jun 07 07:09:12 PM PDT 24
Finished Jun 07 07:09:16 PM PDT 24
Peak memory 217984 kb
Host smart-732b280c-3699-487b-9009-00c69d0e8779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244221481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3244221481
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1849987
Short name T460
Test name
Test status
Simulation time 5307343786 ps
CPU time 55.12 seconds
Started Jun 07 07:09:12 PM PDT 24
Finished Jun 07 07:10:08 PM PDT 24
Peak memory 208988 kb
Host smart-9954ad7d-3b61-4ef2-b774-7aacfc286687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1849987
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2518686408
Short name T275
Test name
Test status
Simulation time 1282493508 ps
CPU time 24.03 seconds
Started Jun 07 07:09:16 PM PDT 24
Finished Jun 07 07:09:41 PM PDT 24
Peak memory 208952 kb
Host smart-d8115cf3-936e-4a1b-87bf-ddbe7117cf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518686408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2518686408
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3511833268
Short name T415
Test name
Test status
Simulation time 1715012064 ps
CPU time 23.21 seconds
Started Jun 07 07:09:10 PM PDT 24
Finished Jun 07 07:09:34 PM PDT 24
Peak memory 208984 kb
Host smart-cef85161-f117-4fee-8f09-e18b0264375e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511833268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3511833268
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.886090068
Short name T708
Test name
Test status
Simulation time 420755653 ps
CPU time 4.71 seconds
Started Jun 07 07:09:13 PM PDT 24
Finished Jun 07 07:09:19 PM PDT 24
Peak memory 208008 kb
Host smart-2abf3daf-2791-4f12-8618-2f2b517e83e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886090068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.886090068
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.224746485
Short name T487
Test name
Test status
Simulation time 49469278 ps
CPU time 1.87 seconds
Started Jun 07 07:09:10 PM PDT 24
Finished Jun 07 07:09:13 PM PDT 24
Peak memory 208536 kb
Host smart-f7de8e2e-75a3-47fe-9e00-2529e945697d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224746485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.224746485
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.4266705982
Short name T644
Test name
Test status
Simulation time 61850952 ps
CPU time 1.6 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:23 PM PDT 24
Peak memory 216288 kb
Host smart-3ba0bb49-69dd-4a27-846b-5b6e8979f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266705982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4266705982
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.417168914
Short name T192
Test name
Test status
Simulation time 908190234 ps
CPU time 6.24 seconds
Started Jun 07 07:09:14 PM PDT 24
Finished Jun 07 07:09:21 PM PDT 24
Peak memory 208452 kb
Host smart-3a0e4a67-7ac5-4c22-91dc-434c013ff72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417168914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.417168914
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1357132919
Short name T773
Test name
Test status
Simulation time 101023209 ps
CPU time 4.19 seconds
Started Jun 07 07:09:13 PM PDT 24
Finished Jun 07 07:09:18 PM PDT 24
Peak memory 209152 kb
Host smart-195fa15d-0142-431c-849d-91ae2425deb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357132919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1357132919
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.658757959
Short name T876
Test name
Test status
Simulation time 264004726 ps
CPU time 1.51 seconds
Started Jun 07 07:09:22 PM PDT 24
Finished Jun 07 07:09:26 PM PDT 24
Peak memory 209932 kb
Host smart-752436e7-2853-45d7-89e5-a6b423068613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658757959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.658757959
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1526255288
Short name T437
Test name
Test status
Simulation time 42902621 ps
CPU time 0.91 seconds
Started Jun 07 07:09:19 PM PDT 24
Finished Jun 07 07:09:21 PM PDT 24
Peak memory 205924 kb
Host smart-6cc5ee5c-f2b9-43b1-bc42-3b976fa8b477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526255288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1526255288
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3949848384
Short name T277
Test name
Test status
Simulation time 112703880 ps
CPU time 6.39 seconds
Started Jun 07 07:09:19 PM PDT 24
Finished Jun 07 07:09:26 PM PDT 24
Peak memory 215272 kb
Host smart-4b50d7d1-8ed3-45da-9736-8f2fda9080ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949848384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3949848384
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.783414877
Short name T853
Test name
Test status
Simulation time 183430563 ps
CPU time 3.43 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:25 PM PDT 24
Peak memory 221804 kb
Host smart-c686bade-1daa-4a13-93a8-ae41dab1bbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783414877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.783414877
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1432012893
Short name T71
Test name
Test status
Simulation time 380387620 ps
CPU time 3.34 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:26 PM PDT 24
Peak memory 207072 kb
Host smart-2e9210d0-d9ec-4e6e-baa8-3b22f4270f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432012893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1432012893
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3899924132
Short name T870
Test name
Test status
Simulation time 462510634 ps
CPU time 7.31 seconds
Started Jun 07 07:09:21 PM PDT 24
Finished Jun 07 07:09:31 PM PDT 24
Peak memory 209784 kb
Host smart-c370c0b2-c6f7-451f-8fd7-a0fc9e8f8918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899924132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3899924132
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2846838015
Short name T276
Test name
Test status
Simulation time 54465729 ps
CPU time 3.4 seconds
Started Jun 07 07:09:21 PM PDT 24
Finished Jun 07 07:09:27 PM PDT 24
Peak memory 214696 kb
Host smart-6ecc989e-8c94-464a-b2a3-be324846d650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846838015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2846838015
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3221486253
Short name T563
Test name
Test status
Simulation time 63764912 ps
CPU time 2.31 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:25 PM PDT 24
Peak memory 207956 kb
Host smart-582f8ee4-ce36-4f4b-a8a8-0dd88a04b3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221486253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3221486253
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.241033817
Short name T583
Test name
Test status
Simulation time 234539843 ps
CPU time 7.02 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:29 PM PDT 24
Peak memory 209812 kb
Host smart-8f920e44-b6f7-4165-8646-45609f730b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241033817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.241033817
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2875624002
Short name T593
Test name
Test status
Simulation time 68232202 ps
CPU time 2.39 seconds
Started Jun 07 07:09:21 PM PDT 24
Finished Jun 07 07:09:26 PM PDT 24
Peak memory 206976 kb
Host smart-bd603db1-1746-4035-8902-965fa86b3854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875624002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2875624002
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2664151557
Short name T882
Test name
Test status
Simulation time 44816556 ps
CPU time 2.41 seconds
Started Jun 07 07:09:23 PM PDT 24
Finished Jun 07 07:09:27 PM PDT 24
Peak memory 207032 kb
Host smart-87be1c99-9860-4cf4-a500-804c46ee07ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664151557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2664151557
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2600307017
Short name T310
Test name
Test status
Simulation time 35035101 ps
CPU time 2.3 seconds
Started Jun 07 07:09:21 PM PDT 24
Finished Jun 07 07:09:26 PM PDT 24
Peak memory 208392 kb
Host smart-9ec0d0e3-7d36-4de6-b8e8-d9d0d0e16626
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600307017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2600307017
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.954600157
Short name T704
Test name
Test status
Simulation time 50800100 ps
CPU time 2.8 seconds
Started Jun 07 07:09:24 PM PDT 24
Finished Jun 07 07:09:28 PM PDT 24
Peak memory 206876 kb
Host smart-643c6b65-0a3f-4402-9112-0d48ce27f6c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954600157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.954600157
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3266219072
Short name T747
Test name
Test status
Simulation time 184917339 ps
CPU time 4.63 seconds
Started Jun 07 07:09:21 PM PDT 24
Finished Jun 07 07:09:28 PM PDT 24
Peak memory 208120 kb
Host smart-fceb542e-a086-423a-9c7b-a8698b4b0c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266219072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3266219072
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2355965681
Short name T778
Test name
Test status
Simulation time 669201739 ps
CPU time 2.51 seconds
Started Jun 07 07:09:18 PM PDT 24
Finished Jun 07 07:09:22 PM PDT 24
Peak memory 206992 kb
Host smart-f8b700ba-66d8-413c-9507-c2c2a93523a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355965681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2355965681
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.4202014683
Short name T457
Test name
Test status
Simulation time 34154973 ps
CPU time 2.5 seconds
Started Jun 07 07:09:21 PM PDT 24
Finished Jun 07 07:09:26 PM PDT 24
Peak memory 218288 kb
Host smart-2b13bf12-98b5-449e-bf53-f19341ac4a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202014683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.4202014683
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.464167420
Short name T659
Test name
Test status
Simulation time 35595643 ps
CPU time 1.86 seconds
Started Jun 07 07:09:32 PM PDT 24
Finished Jun 07 07:09:35 PM PDT 24
Peak memory 209988 kb
Host smart-e58fb660-d1c5-4345-abd2-06696c335301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464167420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.464167420
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2736170169
Short name T681
Test name
Test status
Simulation time 13001555 ps
CPU time 0.77 seconds
Started Jun 07 07:09:29 PM PDT 24
Finished Jun 07 07:09:31 PM PDT 24
Peak memory 205940 kb
Host smart-60ee0e75-52eb-4117-a306-fc415e93260b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736170169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2736170169
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3648096708
Short name T141
Test name
Test status
Simulation time 351105488 ps
CPU time 3.03 seconds
Started Jun 07 07:09:31 PM PDT 24
Finished Jun 07 07:09:35 PM PDT 24
Peak memory 214320 kb
Host smart-c24f3992-4ebc-4e3d-9860-772802ea2cd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648096708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3648096708
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1015259874
Short name T540
Test name
Test status
Simulation time 300836768 ps
CPU time 3.51 seconds
Started Jun 07 07:09:29 PM PDT 24
Finished Jun 07 07:09:34 PM PDT 24
Peak memory 214592 kb
Host smart-b388071d-3b27-4f6b-ada6-a59c8610bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015259874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1015259874
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2403191814
Short name T491
Test name
Test status
Simulation time 473859762 ps
CPU time 11.65 seconds
Started Jun 07 07:09:28 PM PDT 24
Finished Jun 07 07:09:41 PM PDT 24
Peak memory 209304 kb
Host smart-61209a53-e352-4b74-a81f-0216f23eb9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403191814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2403191814
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1723436360
Short name T308
Test name
Test status
Simulation time 272601384 ps
CPU time 2.86 seconds
Started Jun 07 07:09:33 PM PDT 24
Finished Jun 07 07:09:38 PM PDT 24
Peak memory 214328 kb
Host smart-87e03cf1-6ad6-434f-a3d8-669fe55b7caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723436360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1723436360
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2763511414
Short name T258
Test name
Test status
Simulation time 270604589 ps
CPU time 3.73 seconds
Started Jun 07 07:09:28 PM PDT 24
Finished Jun 07 07:09:34 PM PDT 24
Peak memory 214388 kb
Host smart-0697ba8a-8da7-4aed-83d8-463d8ecb61dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763511414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2763511414
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_random.3255792251
Short name T390
Test name
Test status
Simulation time 124437392 ps
CPU time 4.62 seconds
Started Jun 07 07:09:30 PM PDT 24
Finished Jun 07 07:09:36 PM PDT 24
Peak memory 214348 kb
Host smart-dae7642d-d0ea-41e6-8b4b-4ba1a988b6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255792251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3255792251
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3771701011
Short name T475
Test name
Test status
Simulation time 94296299 ps
CPU time 4.12 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:25 PM PDT 24
Peak memory 208952 kb
Host smart-fc2e8a6b-b309-44ce-9a47-dfaf02110302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771701011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3771701011
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1012518009
Short name T528
Test name
Test status
Simulation time 202264514 ps
CPU time 3.05 seconds
Started Jun 07 07:09:28 PM PDT 24
Finished Jun 07 07:09:32 PM PDT 24
Peak memory 206976 kb
Host smart-224ffd0b-fb5a-41fb-9a2d-6906805e05dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012518009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1012518009
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1325957608
Short name T416
Test name
Test status
Simulation time 64586342 ps
CPU time 3.27 seconds
Started Jun 07 07:09:20 PM PDT 24
Finished Jun 07 07:09:24 PM PDT 24
Peak memory 207040 kb
Host smart-5d71f930-5680-4e43-9919-c593a5f14c13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325957608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1325957608
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.264821802
Short name T714
Test name
Test status
Simulation time 3200758036 ps
CPU time 20.12 seconds
Started Jun 07 07:09:33 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 208176 kb
Host smart-c1be65a9-ef3f-4836-9edf-00af12488fb6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264821802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.264821802
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2176632267
Short name T737
Test name
Test status
Simulation time 1156409248 ps
CPU time 4.46 seconds
Started Jun 07 07:09:29 PM PDT 24
Finished Jun 07 07:09:35 PM PDT 24
Peak memory 209332 kb
Host smart-7bb7b2b1-5d97-4ac0-a985-70572b9c5dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176632267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2176632267
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2904141420
Short name T736
Test name
Test status
Simulation time 538031040 ps
CPU time 3.77 seconds
Started Jun 07 07:09:19 PM PDT 24
Finished Jun 07 07:09:24 PM PDT 24
Peak memory 206740 kb
Host smart-6a673c51-100e-49d6-b1fa-6f58dd1af9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904141420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2904141420
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.408282432
Short name T492
Test name
Test status
Simulation time 8411905337 ps
CPU time 59.94 seconds
Started Jun 07 07:09:29 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 222608 kb
Host smart-ccecb7cc-8ced-42b5-8c3d-b76e3406eae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408282432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.408282432
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2730779332
Short name T302
Test name
Test status
Simulation time 159782773 ps
CPU time 5.95 seconds
Started Jun 07 07:09:27 PM PDT 24
Finished Jun 07 07:09:34 PM PDT 24
Peak memory 209800 kb
Host smart-aeaf0ff4-3c52-4a68-9cdd-3cb374b9b0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730779332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2730779332
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3191145032
Short name T459
Test name
Test status
Simulation time 1006802104 ps
CPU time 5.05 seconds
Started Jun 07 07:09:29 PM PDT 24
Finished Jun 07 07:09:36 PM PDT 24
Peak memory 211088 kb
Host smart-b5771a59-833a-461b-b1e4-879d8bdcc9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191145032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3191145032
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.152289000
Short name T396
Test name
Test status
Simulation time 79729551 ps
CPU time 0.77 seconds
Started Jun 07 07:09:32 PM PDT 24
Finished Jun 07 07:09:34 PM PDT 24
Peak memory 205960 kb
Host smart-d2c39383-e88f-4e6f-bcd1-d9344d6896d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152289000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.152289000
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3916761164
Short name T251
Test name
Test status
Simulation time 2490218796 ps
CPU time 132.66 seconds
Started Jun 07 07:09:33 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 219772 kb
Host smart-90e885e7-bcf0-44ce-af72-fc0cef26275d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916761164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3916761164
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2515293359
Short name T211
Test name
Test status
Simulation time 114823970 ps
CPU time 3.92 seconds
Started Jun 07 07:09:29 PM PDT 24
Finished Jun 07 07:09:35 PM PDT 24
Peak memory 208164 kb
Host smart-d9b82ac4-e0ed-46c7-80d5-e8f6ae5d76d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515293359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2515293359
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.495760185
Short name T56
Test name
Test status
Simulation time 259019113 ps
CPU time 2.62 seconds
Started Jun 07 07:09:28 PM PDT 24
Finished Jun 07 07:09:33 PM PDT 24
Peak memory 210364 kb
Host smart-15b63a20-9976-4561-b7df-4e6857ae30ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495760185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.495760185
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.737810732
Short name T259
Test name
Test status
Simulation time 45978674 ps
CPU time 1.89 seconds
Started Jun 07 07:09:33 PM PDT 24
Finished Jun 07 07:09:36 PM PDT 24
Peak memory 214448 kb
Host smart-fe63f592-8ba1-407f-9240-8866b777cb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737810732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.737810732
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3435651198
Short name T783
Test name
Test status
Simulation time 634081713 ps
CPU time 4.01 seconds
Started Jun 07 07:09:31 PM PDT 24
Finished Jun 07 07:09:37 PM PDT 24
Peak memory 209072 kb
Host smart-293fefa2-9b2f-4a47-91a7-6a1b6414c8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435651198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3435651198
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.797290821
Short name T860
Test name
Test status
Simulation time 418771810 ps
CPU time 6.06 seconds
Started Jun 07 07:09:26 PM PDT 24
Finished Jun 07 07:09:33 PM PDT 24
Peak memory 207396 kb
Host smart-e63a318f-f323-45a9-966e-7c80d8464c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797290821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.797290821
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.382766045
Short name T627
Test name
Test status
Simulation time 107978334 ps
CPU time 3.99 seconds
Started Jun 07 07:09:28 PM PDT 24
Finished Jun 07 07:09:34 PM PDT 24
Peak memory 208832 kb
Host smart-f11c7875-9d7e-4d6c-a88b-8cb8f50512cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382766045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.382766045
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3959569123
Short name T420
Test name
Test status
Simulation time 402312444 ps
CPU time 4.91 seconds
Started Jun 07 07:09:26 PM PDT 24
Finished Jun 07 07:09:32 PM PDT 24
Peak memory 207376 kb
Host smart-8b98bf70-745b-4471-aa15-1bdc8e4b844a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959569123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3959569123
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2111533449
Short name T694
Test name
Test status
Simulation time 50648593 ps
CPU time 2.6 seconds
Started Jun 07 07:09:31 PM PDT 24
Finished Jun 07 07:09:35 PM PDT 24
Peak memory 208796 kb
Host smart-fd764eda-4aa4-428a-8902-44214c045a29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111533449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2111533449
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.261483573
Short name T335
Test name
Test status
Simulation time 80264423 ps
CPU time 3.91 seconds
Started Jun 07 07:09:27 PM PDT 24
Finished Jun 07 07:09:33 PM PDT 24
Peak memory 208864 kb
Host smart-4e71c07a-0f98-4711-a7e1-4e2625b13b16
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261483573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.261483573
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2761740581
Short name T199
Test name
Test status
Simulation time 79493746 ps
CPU time 3.46 seconds
Started Jun 07 07:09:28 PM PDT 24
Finished Jun 07 07:09:34 PM PDT 24
Peak memory 218408 kb
Host smart-1dd150ee-2da8-4b3a-b899-d2d297b7c4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761740581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2761740581
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3017066308
Short name T740
Test name
Test status
Simulation time 844329372 ps
CPU time 7.97 seconds
Started Jun 07 07:09:32 PM PDT 24
Finished Jun 07 07:09:41 PM PDT 24
Peak memory 214332 kb
Host smart-d4938cf4-6cf7-4563-9e96-a45b02929226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017066308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3017066308
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1695044917
Short name T632
Test name
Test status
Simulation time 46469842 ps
CPU time 2.62 seconds
Started Jun 07 07:09:28 PM PDT 24
Finished Jun 07 07:09:32 PM PDT 24
Peak memory 210044 kb
Host smart-a9306ab0-d725-44cc-8755-ca402e1f04eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695044917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1695044917
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1840998867
Short name T408
Test name
Test status
Simulation time 18470055 ps
CPU time 0.83 seconds
Started Jun 07 07:09:35 PM PDT 24
Finished Jun 07 07:09:37 PM PDT 24
Peak memory 205948 kb
Host smart-b546d53c-6d45-4eed-8c1c-cc8f11bfc934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840998867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1840998867
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1605094184
Short name T194
Test name
Test status
Simulation time 58519647 ps
CPU time 3.39 seconds
Started Jun 07 07:09:36 PM PDT 24
Finished Jun 07 07:09:41 PM PDT 24
Peak memory 214636 kb
Host smart-791bd1db-d1bb-4e48-9cd0-60937670815d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605094184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1605094184
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1209576887
Short name T74
Test name
Test status
Simulation time 62303376 ps
CPU time 3.15 seconds
Started Jun 07 07:09:34 PM PDT 24
Finished Jun 07 07:09:39 PM PDT 24
Peak memory 218144 kb
Host smart-8c61beb0-9e5d-4f0b-ad6d-ef19cb60dfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209576887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1209576887
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.94486207
Short name T833
Test name
Test status
Simulation time 96065299 ps
CPU time 3.3 seconds
Started Jun 07 07:09:36 PM PDT 24
Finished Jun 07 07:09:41 PM PDT 24
Peak memory 214240 kb
Host smart-ee20f4ec-cf30-40ed-b7f8-3241e500305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94486207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.94486207
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2234493141
Short name T365
Test name
Test status
Simulation time 62636714 ps
CPU time 1.8 seconds
Started Jun 07 07:09:38 PM PDT 24
Finished Jun 07 07:09:42 PM PDT 24
Peak memory 218980 kb
Host smart-287d2c42-25d9-40a3-bb3e-ff42cfac7b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234493141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2234493141
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1297934464
Short name T215
Test name
Test status
Simulation time 1304420424 ps
CPU time 3.12 seconds
Started Jun 07 07:09:35 PM PDT 24
Finished Jun 07 07:09:40 PM PDT 24
Peak memory 222484 kb
Host smart-fa56d0bb-c1ed-4082-a8c9-fd47efd3dff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297934464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1297934464
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3822842212
Short name T617
Test name
Test status
Simulation time 234506458 ps
CPU time 3.91 seconds
Started Jun 07 07:09:34 PM PDT 24
Finished Jun 07 07:09:39 PM PDT 24
Peak memory 209012 kb
Host smart-eab2480e-8938-4302-80cb-96e4e7847e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822842212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3822842212
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.4217955929
Short name T436
Test name
Test status
Simulation time 182369444 ps
CPU time 6.07 seconds
Started Jun 07 07:09:27 PM PDT 24
Finished Jun 07 07:09:35 PM PDT 24
Peak memory 208492 kb
Host smart-e968a050-03a9-432b-913b-d84bd25e6b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217955929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.4217955929
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3377109901
Short name T839
Test name
Test status
Simulation time 726002581 ps
CPU time 7.73 seconds
Started Jun 07 07:09:39 PM PDT 24
Finished Jun 07 07:09:49 PM PDT 24
Peak memory 208464 kb
Host smart-7ca04e26-d7a1-4f43-a29f-fb86a25dfc04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377109901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3377109901
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.931384391
Short name T766
Test name
Test status
Simulation time 593461254 ps
CPU time 14.06 seconds
Started Jun 07 07:09:39 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 208680 kb
Host smart-336bf26a-a6c1-401d-9661-771b22e925cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931384391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.931384391
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.939310096
Short name T631
Test name
Test status
Simulation time 291181592 ps
CPU time 2.67 seconds
Started Jun 07 07:09:38 PM PDT 24
Finished Jun 07 07:09:42 PM PDT 24
Peak memory 206968 kb
Host smart-b2db8182-8c90-45df-a3fc-ebaa10cb1cb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939310096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.939310096
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2370429476
Short name T358
Test name
Test status
Simulation time 59533278 ps
CPU time 2.91 seconds
Started Jun 07 07:09:37 PM PDT 24
Finished Jun 07 07:09:42 PM PDT 24
Peak memory 214328 kb
Host smart-9af2fa1a-c8fc-42d7-9420-d002cff99c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370429476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2370429476
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2289189451
Short name T663
Test name
Test status
Simulation time 612132552 ps
CPU time 6.66 seconds
Started Jun 07 07:09:30 PM PDT 24
Finished Jun 07 07:09:38 PM PDT 24
Peak memory 208136 kb
Host smart-d845ea3f-c439-4b19-9b18-c84735621dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289189451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2289189451
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.414423160
Short name T283
Test name
Test status
Simulation time 55107029 ps
CPU time 3.29 seconds
Started Jun 07 07:09:33 PM PDT 24
Finished Jun 07 07:09:38 PM PDT 24
Peak memory 207408 kb
Host smart-af8caab9-96b0-4f39-a1b3-15febf83867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414423160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.414423160
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2794742023
Short name T684
Test name
Test status
Simulation time 106983224 ps
CPU time 1.81 seconds
Started Jun 07 07:09:34 PM PDT 24
Finished Jun 07 07:09:37 PM PDT 24
Peak memory 210204 kb
Host smart-2b521bed-0e91-446f-80ac-01ea69dfbd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794742023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2794742023
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.945259667
Short name T477
Test name
Test status
Simulation time 36730348 ps
CPU time 0.88 seconds
Started Jun 07 07:09:34 PM PDT 24
Finished Jun 07 07:09:36 PM PDT 24
Peak memory 205972 kb
Host smart-0727c701-2a30-4925-8686-149614920eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945259667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.945259667
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3679386179
Short name T82
Test name
Test status
Simulation time 929790091 ps
CPU time 4 seconds
Started Jun 07 07:09:34 PM PDT 24
Finished Jun 07 07:09:40 PM PDT 24
Peak memory 215524 kb
Host smart-5c213d7f-cf26-4c72-a056-3e53a7ff0295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679386179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3679386179
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1841150302
Short name T67
Test name
Test status
Simulation time 471677349 ps
CPU time 5.19 seconds
Started Jun 07 07:09:36 PM PDT 24
Finished Jun 07 07:09:43 PM PDT 24
Peak memory 214568 kb
Host smart-2ee2bf40-4d93-4943-86b3-c414c2fa65f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841150302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1841150302
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.696919647
Short name T542
Test name
Test status
Simulation time 1494532412 ps
CPU time 8.74 seconds
Started Jun 07 07:09:35 PM PDT 24
Finished Jun 07 07:09:45 PM PDT 24
Peak memory 214316 kb
Host smart-029ea4ab-4a49-428d-9f83-253197f41311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696919647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.696919647
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.855920024
Short name T621
Test name
Test status
Simulation time 297382778 ps
CPU time 3.63 seconds
Started Jun 07 07:09:37 PM PDT 24
Finished Jun 07 07:09:42 PM PDT 24
Peak memory 214348 kb
Host smart-176e0c7d-cb9b-4378-a452-ab1816311812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855920024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.855920024
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1795430467
Short name T894
Test name
Test status
Simulation time 169248018 ps
CPU time 3.07 seconds
Started Jun 07 07:09:34 PM PDT 24
Finished Jun 07 07:09:39 PM PDT 24
Peak memory 214448 kb
Host smart-22cb6f14-b6e9-4e6c-ac17-4af538846f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795430467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1795430467
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2699337494
Short name T343
Test name
Test status
Simulation time 117981766 ps
CPU time 3.41 seconds
Started Jun 07 07:09:34 PM PDT 24
Finished Jun 07 07:09:39 PM PDT 24
Peak memory 207656 kb
Host smart-a51e2c9d-6053-4e11-b8d7-be523b3db9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699337494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2699337494
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2096734792
Short name T339
Test name
Test status
Simulation time 772199145 ps
CPU time 6.4 seconds
Started Jun 07 07:09:39 PM PDT 24
Finished Jun 07 07:09:47 PM PDT 24
Peak memory 208752 kb
Host smart-d5e7f02f-4ca7-4bb2-9a5c-e0f1e21f2d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096734792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2096734792
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3508670608
Short name T735
Test name
Test status
Simulation time 35104394 ps
CPU time 2.37 seconds
Started Jun 07 07:09:39 PM PDT 24
Finished Jun 07 07:09:43 PM PDT 24
Peak memory 206852 kb
Host smart-3b468628-9cd9-4179-b406-9b32afea8ba2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508670608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3508670608
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1620173990
Short name T900
Test name
Test status
Simulation time 191056527 ps
CPU time 2.74 seconds
Started Jun 07 07:09:33 PM PDT 24
Finished Jun 07 07:09:37 PM PDT 24
Peak memory 207008 kb
Host smart-64e0149a-95ce-4cdf-8b1a-d025cb8802c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620173990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1620173990
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1615082084
Short name T896
Test name
Test status
Simulation time 115623608 ps
CPU time 3.08 seconds
Started Jun 07 07:09:36 PM PDT 24
Finished Jun 07 07:09:41 PM PDT 24
Peak memory 208752 kb
Host smart-c76ba413-5c27-410d-b4ef-c45aeb6f3a18
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615082084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1615082084
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1333683773
Short name T630
Test name
Test status
Simulation time 289962679 ps
CPU time 3.58 seconds
Started Jun 07 07:09:36 PM PDT 24
Finished Jun 07 07:09:42 PM PDT 24
Peak memory 208008 kb
Host smart-0096d09d-6cfc-475c-8afc-6936ee4cabdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333683773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1333683773
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1105717069
Short name T379
Test name
Test status
Simulation time 35492980 ps
CPU time 2.07 seconds
Started Jun 07 07:09:36 PM PDT 24
Finished Jun 07 07:09:40 PM PDT 24
Peak memory 207004 kb
Host smart-76c564fb-827c-477d-a842-cfdc35ca95a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105717069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1105717069
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2830174775
Short name T253
Test name
Test status
Simulation time 193402128 ps
CPU time 7.41 seconds
Started Jun 07 07:09:37 PM PDT 24
Finished Jun 07 07:09:46 PM PDT 24
Peak memory 216512 kb
Host smart-ece4f27b-24f1-41c7-886c-0c011421c44d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830174775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2830174775
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3199716780
Short name T128
Test name
Test status
Simulation time 734951790 ps
CPU time 13.88 seconds
Started Jun 07 07:09:39 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 222672 kb
Host smart-106992f2-6391-4869-88ea-9e60b4c83760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199716780 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3199716780
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.694978010
Short name T272
Test name
Test status
Simulation time 636887414 ps
CPU time 13.61 seconds
Started Jun 07 07:09:36 PM PDT 24
Finished Jun 07 07:09:51 PM PDT 24
Peak memory 208656 kb
Host smart-9fcbadce-1c12-4887-a487-52c6c1f81d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694978010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.694978010
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3422706391
Short name T489
Test name
Test status
Simulation time 259913286 ps
CPU time 2.34 seconds
Started Jun 07 07:09:39 PM PDT 24
Finished Jun 07 07:09:43 PM PDT 24
Peak memory 209896 kb
Host smart-ff7d82c6-991d-4e3e-8a74-89161dbb2adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422706391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3422706391
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.67478141
Short name T819
Test name
Test status
Simulation time 20342254 ps
CPU time 0.73 seconds
Started Jun 07 07:08:10 PM PDT 24
Finished Jun 07 07:08:12 PM PDT 24
Peak memory 205960 kb
Host smart-2ad0e666-168b-4c09-a028-9bc368f19f54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67478141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.67478141
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.778120601
Short name T58
Test name
Test status
Simulation time 1326570120 ps
CPU time 3.1 seconds
Started Jun 07 07:08:06 PM PDT 24
Finished Jun 07 07:08:10 PM PDT 24
Peak memory 214640 kb
Host smart-bdff5c39-dd46-46a6-ba37-9c7b3a6f2b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778120601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.778120601
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3532575770
Short name T611
Test name
Test status
Simulation time 180826045 ps
CPU time 3.28 seconds
Started Jun 07 07:08:08 PM PDT 24
Finished Jun 07 07:08:12 PM PDT 24
Peak memory 209756 kb
Host smart-e5319344-b497-4189-a1ae-3f057ea29b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532575770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3532575770
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1308962085
Short name T232
Test name
Test status
Simulation time 536228887 ps
CPU time 5.34 seconds
Started Jun 07 07:08:10 PM PDT 24
Finished Jun 07 07:08:16 PM PDT 24
Peak memory 220708 kb
Host smart-bd7c915b-b72e-450b-b1f4-42d4e0bfbba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308962085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1308962085
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3213499626
Short name T906
Test name
Test status
Simulation time 91519309 ps
CPU time 4.43 seconds
Started Jun 07 07:08:07 PM PDT 24
Finished Jun 07 07:08:13 PM PDT 24
Peak memory 222568 kb
Host smart-24dfd431-ac72-4062-b4f5-dddafc6bf639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213499626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3213499626
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2650918637
Short name T55
Test name
Test status
Simulation time 44836110 ps
CPU time 2.2 seconds
Started Jun 07 07:08:06 PM PDT 24
Finished Jun 07 07:08:10 PM PDT 24
Peak memory 220200 kb
Host smart-0431fcc1-cff3-4f2b-a037-c0dd4bdac83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650918637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2650918637
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.702818018
Short name T687
Test name
Test status
Simulation time 100056390 ps
CPU time 4.01 seconds
Started Jun 07 07:08:07 PM PDT 24
Finished Jun 07 07:08:12 PM PDT 24
Peak memory 207616 kb
Host smart-4497187d-2f95-4285-8a89-1ab69bff4453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702818018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.702818018
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2226543051
Short name T612
Test name
Test status
Simulation time 48230137 ps
CPU time 2.63 seconds
Started Jun 07 07:08:02 PM PDT 24
Finished Jun 07 07:08:06 PM PDT 24
Peak memory 206984 kb
Host smart-29c45c8f-d7ed-43b9-8cb0-5bf486139368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226543051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2226543051
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3700613063
Short name T386
Test name
Test status
Simulation time 175983939 ps
CPU time 2.8 seconds
Started Jun 07 07:08:08 PM PDT 24
Finished Jun 07 07:08:12 PM PDT 24
Peak memory 208924 kb
Host smart-63bcb66f-dd93-4266-91c0-aa2b9e58939e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700613063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3700613063
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.594878272
Short name T422
Test name
Test status
Simulation time 114122024 ps
CPU time 3.9 seconds
Started Jun 07 07:08:05 PM PDT 24
Finished Jun 07 07:08:10 PM PDT 24
Peak memory 208608 kb
Host smart-bf674c09-e606-4fd8-a766-1024a5361933
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594878272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.594878272
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3437973738
Short name T393
Test name
Test status
Simulation time 99500458 ps
CPU time 4.42 seconds
Started Jun 07 07:08:08 PM PDT 24
Finished Jun 07 07:08:13 PM PDT 24
Peak memory 208992 kb
Host smart-1a46ac7d-7156-4607-9515-77313ed2d8a2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437973738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3437973738
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1399960605
Short name T403
Test name
Test status
Simulation time 249472839 ps
CPU time 4.82 seconds
Started Jun 07 07:08:08 PM PDT 24
Finished Jun 07 07:08:14 PM PDT 24
Peak memory 208768 kb
Host smart-725a8cf9-936d-4170-adb7-bbec40c11206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399960605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1399960605
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1774401683
Short name T857
Test name
Test status
Simulation time 869430240 ps
CPU time 3.32 seconds
Started Jun 07 07:07:59 PM PDT 24
Finished Jun 07 07:08:04 PM PDT 24
Peak memory 206720 kb
Host smart-71072720-4107-40f7-bc27-bd814476a86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774401683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1774401683
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.299304562
Short name T432
Test name
Test status
Simulation time 913163220 ps
CPU time 9.81 seconds
Started Jun 07 07:08:08 PM PDT 24
Finished Jun 07 07:08:19 PM PDT 24
Peak memory 222428 kb
Host smart-cce1846a-00e5-405d-aced-b21aeac26533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299304562 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.299304562
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.32564764
Short name T88
Test name
Test status
Simulation time 54766921 ps
CPU time 2.26 seconds
Started Jun 07 07:08:10 PM PDT 24
Finished Jun 07 07:08:14 PM PDT 24
Peak memory 207360 kb
Host smart-78dbaeda-9659-47f1-ba43-2797cbc75b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32564764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.32564764
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2717073961
Short name T380
Test name
Test status
Simulation time 15089949 ps
CPU time 0.72 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:49 PM PDT 24
Peak memory 205952 kb
Host smart-3102a8cb-f309-430f-83a7-f7ba82c892ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717073961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2717073961
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1545019305
Short name T538
Test name
Test status
Simulation time 462309066 ps
CPU time 3.75 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:51 PM PDT 24
Peak memory 210064 kb
Host smart-ae40e7ac-6c95-4287-b6ff-3b9b55ffa49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545019305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1545019305
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3695414305
Short name T544
Test name
Test status
Simulation time 657493941 ps
CPU time 17.19 seconds
Started Jun 07 07:09:45 PM PDT 24
Finished Jun 07 07:10:04 PM PDT 24
Peak memory 214308 kb
Host smart-549ef9bc-3e0d-4b8a-98ab-8624141ae2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695414305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3695414305
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3163333226
Short name T880
Test name
Test status
Simulation time 452228847 ps
CPU time 5.05 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 222504 kb
Host smart-e372980e-d853-4be0-b457-e0717cb4bdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163333226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3163333226
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3290821049
Short name T533
Test name
Test status
Simulation time 117029707 ps
CPU time 4.45 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:56 PM PDT 24
Peak memory 214252 kb
Host smart-58fa0bc2-97ec-404b-9035-0eae143d233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290821049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3290821049
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1897344341
Short name T143
Test name
Test status
Simulation time 106581141 ps
CPU time 5.24 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 219408 kb
Host smart-ce81005a-90c9-41f2-aed2-731b8df18833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897344341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1897344341
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3750641040
Short name T510
Test name
Test status
Simulation time 160946104 ps
CPU time 4.09 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:09:56 PM PDT 24
Peak memory 218244 kb
Host smart-030b148e-4264-4217-9969-69d50a412c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750641040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3750641040
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1247590430
Short name T267
Test name
Test status
Simulation time 433080145 ps
CPU time 3.87 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 208660 kb
Host smart-9c23a132-361c-4db8-8f6d-d607c5238d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247590430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1247590430
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3759584622
Short name T205
Test name
Test status
Simulation time 899517216 ps
CPU time 6.74 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 207884 kb
Host smart-b4b39670-124a-42a7-b72e-199e4688d0eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759584622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3759584622
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.133562695
Short name T287
Test name
Test status
Simulation time 32391146 ps
CPU time 2.39 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:53 PM PDT 24
Peak memory 209096 kb
Host smart-3064ed7f-0229-4e48-a61d-b6dc62d893e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133562695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.133562695
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3557337152
Short name T476
Test name
Test status
Simulation time 519098340 ps
CPU time 4.64 seconds
Started Jun 07 07:09:46 PM PDT 24
Finished Jun 07 07:09:52 PM PDT 24
Peak memory 208844 kb
Host smart-c66100cb-dfc7-46f9-8a31-8b6daa0adeec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557337152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3557337152
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3036040993
Short name T447
Test name
Test status
Simulation time 17136629 ps
CPU time 1.56 seconds
Started Jun 07 07:09:46 PM PDT 24
Finished Jun 07 07:09:49 PM PDT 24
Peak memory 206916 kb
Host smart-2a4420de-df95-4f26-9141-e61c8912bd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036040993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3036040993
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3275372370
Short name T456
Test name
Test status
Simulation time 1450115684 ps
CPU time 12.77 seconds
Started Jun 07 07:09:46 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 207920 kb
Host smart-887353b0-9322-45a7-a7c7-b91e100d4539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275372370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3275372370
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.991033346
Short name T784
Test name
Test status
Simulation time 183849434 ps
CPU time 3.25 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 206892 kb
Host smart-1fde3db8-1bff-42c2-bcb9-0e6bcb04860c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991033346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.991033346
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3812189679
Short name T888
Test name
Test status
Simulation time 813788946 ps
CPU time 17.04 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:10:07 PM PDT 24
Peak memory 222448 kb
Host smart-dc92b751-5863-44ce-89ec-df6d79b18d62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812189679 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3812189679
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1163782096
Short name T86
Test name
Test status
Simulation time 111237854 ps
CPU time 3.4 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:53 PM PDT 24
Peak memory 214340 kb
Host smart-85320733-668f-44fc-a75f-078631bf312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163782096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1163782096
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3419648187
Short name T623
Test name
Test status
Simulation time 143398008 ps
CPU time 2 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:53 PM PDT 24
Peak memory 210112 kb
Host smart-245d1023-3438-4e0d-8861-60bd2a1dbe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419648187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3419648187
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.648020686
Short name T884
Test name
Test status
Simulation time 22027559 ps
CPU time 0.74 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:49 PM PDT 24
Peak memory 205964 kb
Host smart-99497708-c98f-4725-97fc-5c86e3fdf6ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648020686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.648020686
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1958959018
Short name T361
Test name
Test status
Simulation time 312901010 ps
CPU time 2.54 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:09:52 PM PDT 24
Peak memory 214292 kb
Host smart-b23e2967-4421-4dfc-a5fe-f98fd1870983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958959018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1958959018
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.520563283
Short name T77
Test name
Test status
Simulation time 270667869 ps
CPU time 1.51 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 208020 kb
Host smart-a9d08ee7-8c50-46dd-9ddd-7eb4dbad1e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520563283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.520563283
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3343763468
Short name T729
Test name
Test status
Simulation time 162988494 ps
CPU time 3.57 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:09:53 PM PDT 24
Peak memory 206300 kb
Host smart-95ab0e5f-af8a-4783-8844-213134610e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343763468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3343763468
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2281828678
Short name T284
Test name
Test status
Simulation time 36998112 ps
CPU time 2.3 seconds
Started Jun 07 07:09:54 PM PDT 24
Finished Jun 07 07:09:59 PM PDT 24
Peak memory 221600 kb
Host smart-3860f0c5-b7a7-41ee-a5d1-41623550107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281828678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2281828678
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3456904649
Short name T629
Test name
Test status
Simulation time 1117408021 ps
CPU time 4.71 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:09:57 PM PDT 24
Peak memory 222464 kb
Host smart-cebc35ec-02ae-4b7a-a22b-581cc9b7aa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456904649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3456904649
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.356399811
Short name T236
Test name
Test status
Simulation time 389541421 ps
CPU time 3.93 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:52 PM PDT 24
Peak memory 219104 kb
Host smart-3116645a-0ba6-453a-b8ff-14374e0ca680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356399811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.356399811
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3560692641
Short name T561
Test name
Test status
Simulation time 33306520 ps
CPU time 2.29 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:51 PM PDT 24
Peak memory 208608 kb
Host smart-9dc3de7b-c593-4d36-90d3-e6b3626df6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560692641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3560692641
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2892044942
Short name T805
Test name
Test status
Simulation time 125795008 ps
CPU time 3.25 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:51 PM PDT 24
Peak memory 208068 kb
Host smart-11615cd0-9008-43a9-a1cd-241090ea9c15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892044942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2892044942
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.4131574477
Short name T336
Test name
Test status
Simulation time 219023986 ps
CPU time 3.34 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 208780 kb
Host smart-e5facbe7-5a42-4e8c-81d5-5f190bbb6f9d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131574477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.4131574477
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3613420108
Short name T313
Test name
Test status
Simulation time 193795235 ps
CPU time 5.93 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:57 PM PDT 24
Peak memory 208404 kb
Host smart-c6b807a7-1be6-4022-9af7-a5e4b227e4e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613420108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3613420108
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.179393340
Short name T391
Test name
Test status
Simulation time 75849788 ps
CPU time 1.88 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:09:51 PM PDT 24
Peak memory 207488 kb
Host smart-3cae9fdb-80a8-4fe9-b778-b3d60064aab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179393340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.179393340
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2739752722
Short name T579
Test name
Test status
Simulation time 889361190 ps
CPU time 3.56 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:52 PM PDT 24
Peak memory 206904 kb
Host smart-4a99b417-a368-4f01-800f-8d313271c8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739752722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2739752722
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2609837278
Short name T281
Test name
Test status
Simulation time 900464450 ps
CPU time 15.36 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:10:08 PM PDT 24
Peak memory 216472 kb
Host smart-83d07825-12ca-49e3-bd69-531f08084c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609837278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2609837278
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3063445764
Short name T675
Test name
Test status
Simulation time 145534068 ps
CPU time 3.74 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:52 PM PDT 24
Peak memory 207632 kb
Host smart-1d920f51-5dde-48a6-9845-74ca091184a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063445764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3063445764
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1859482004
Short name T788
Test name
Test status
Simulation time 133120477 ps
CPU time 2.11 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:09:52 PM PDT 24
Peak memory 210288 kb
Host smart-43da2a08-387d-4671-8d06-25331c3fb52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859482004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1859482004
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.736980385
Short name T658
Test name
Test status
Simulation time 20148925 ps
CPU time 0.75 seconds
Started Jun 07 07:09:53 PM PDT 24
Finished Jun 07 07:09:57 PM PDT 24
Peak memory 205928 kb
Host smart-fd5b72a7-3afc-4ea5-8ab0-d548fdfdbd5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736980385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.736980385
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2651922393
Short name T347
Test name
Test status
Simulation time 54842116 ps
CPU time 2.25 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 214320 kb
Host smart-537b4dc0-137b-44f2-9fad-dbce1a0c7029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651922393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2651922393
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3361301756
Short name T596
Test name
Test status
Simulation time 61015049 ps
CPU time 2.76 seconds
Started Jun 07 07:09:53 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 209392 kb
Host smart-c58fa850-4fc4-4ef9-8f63-f64e0d3d1369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361301756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3361301756
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3050239499
Short name T836
Test name
Test status
Simulation time 720837337 ps
CPU time 10.96 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:10:02 PM PDT 24
Peak memory 208324 kb
Host smart-4ae505dc-a0f0-411b-b2ca-a7965d5e381d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050239499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3050239499
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2022134939
Short name T553
Test name
Test status
Simulation time 211843038 ps
CPU time 4.18 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 214172 kb
Host smart-b08c28a0-7bea-471f-ab16-c8b463b9c9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022134939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2022134939
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2897882394
Short name T651
Test name
Test status
Simulation time 342528562 ps
CPU time 3.12 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:51 PM PDT 24
Peak memory 214236 kb
Host smart-95cf9f39-1a69-4b91-9a5f-5c8be6c41651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897882394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2897882394
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1341459575
Short name T535
Test name
Test status
Simulation time 1462218484 ps
CPU time 9.54 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 207780 kb
Host smart-f97292ed-09c6-4289-a3be-c3a59f954bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341459575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1341459575
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3876784760
Short name T547
Test name
Test status
Simulation time 1130565502 ps
CPU time 30.71 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:10:19 PM PDT 24
Peak memory 208660 kb
Host smart-7b9a109e-86da-4175-a133-07a84b39f4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876784760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3876784760
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1906433524
Short name T901
Test name
Test status
Simulation time 218017947 ps
CPU time 5.82 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:09:56 PM PDT 24
Peak memory 208392 kb
Host smart-315049ad-ede4-4e11-a300-e6db88acbc5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906433524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1906433524
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3716628754
Short name T481
Test name
Test status
Simulation time 161094333 ps
CPU time 6.3 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 208060 kb
Host smart-d422a416-1d5b-4c8d-af73-1d61402c34cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716628754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3716628754
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3017601251
Short name T566
Test name
Test status
Simulation time 36813255 ps
CPU time 2.65 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 208760 kb
Host smart-c37e9549-cea9-4c4d-bb56-b8524bb0457c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017601251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3017601251
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3504345278
Short name T795
Test name
Test status
Simulation time 301346659 ps
CPU time 3.39 seconds
Started Jun 07 07:09:54 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 209044 kb
Host smart-d430fa34-1ea7-4813-b1d7-a661e0e1d2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504345278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3504345278
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1526550514
Short name T382
Test name
Test status
Simulation time 31209321 ps
CPU time 2.16 seconds
Started Jun 07 07:09:47 PM PDT 24
Finished Jun 07 07:09:50 PM PDT 24
Peak memory 206896 kb
Host smart-a7ec0fdd-9411-4006-8702-b47150a07f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526550514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1526550514
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2986257361
Short name T271
Test name
Test status
Simulation time 578324979 ps
CPU time 17.98 seconds
Started Jun 07 07:09:46 PM PDT 24
Finished Jun 07 07:10:05 PM PDT 24
Peak memory 208308 kb
Host smart-087900c0-066a-45ea-a23a-00a8d26a13b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986257361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2986257361
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.414759067
Short name T59
Test name
Test status
Simulation time 83684284 ps
CPU time 2.17 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 210144 kb
Host smart-37252678-c476-4bc4-9df8-230601c5e8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414759067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.414759067
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2339700215
Short name T564
Test name
Test status
Simulation time 55022215 ps
CPU time 0.78 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 205932 kb
Host smart-64f44227-4538-46d2-8298-c5b30ffedb3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339700215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2339700215
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.408459504
Short name T671
Test name
Test status
Simulation time 225442016 ps
CPU time 4.04 seconds
Started Jun 07 07:09:52 PM PDT 24
Finished Jun 07 07:09:59 PM PDT 24
Peak memory 214520 kb
Host smart-be39a9f9-aee4-457a-9ae0-e0826a5e593a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408459504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.408459504
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2112884425
Short name T480
Test name
Test status
Simulation time 89110173 ps
CPU time 1.88 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:09:56 PM PDT 24
Peak memory 208100 kb
Host smart-6fcfa264-4152-4302-b5f1-8bf88411608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112884425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2112884425
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3381169650
Short name T482
Test name
Test status
Simulation time 59072797 ps
CPU time 1.99 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 214400 kb
Host smart-a4d6ebfb-c2d0-43e9-b8f6-7159fc5f248c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381169650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3381169650
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.290819079
Short name T467
Test name
Test status
Simulation time 667589021 ps
CPU time 2.5 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:09:56 PM PDT 24
Peak memory 214240 kb
Host smart-9e829fc0-3b14-4180-afc7-c239c017898a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290819079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.290819079
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2099393974
Short name T398
Test name
Test status
Simulation time 206841717 ps
CPU time 5.32 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 218964 kb
Host smart-9fe7628d-ac25-4046-98a9-190122bf9ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099393974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2099393974
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.4150303852
Short name T891
Test name
Test status
Simulation time 4466237902 ps
CPU time 81.8 seconds
Started Jun 07 07:09:53 PM PDT 24
Finished Jun 07 07:11:18 PM PDT 24
Peak memory 214412 kb
Host smart-de7e2a31-f5c0-438b-9b3d-a319909ac775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150303852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4150303852
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2812943659
Short name T286
Test name
Test status
Simulation time 134683532 ps
CPU time 2.62 seconds
Started Jun 07 07:09:52 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 208680 kb
Host smart-28a3832e-099b-48f2-8928-a52b8e4cd47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812943659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2812943659
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1704220885
Short name T619
Test name
Test status
Simulation time 405432535 ps
CPU time 5.7 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 208008 kb
Host smart-e1e2d5e1-fa62-4e75-a6a0-5ae7dfbc1611
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704220885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1704220885
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3082885886
Short name T789
Test name
Test status
Simulation time 150496396 ps
CPU time 2.45 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 206840 kb
Host smart-211856b4-b4c7-49bf-b55a-69fdc710f209
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082885886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3082885886
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1454236841
Short name T838
Test name
Test status
Simulation time 77261275 ps
CPU time 3.69 seconds
Started Jun 07 07:09:48 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 208484 kb
Host smart-126c2b16-e79d-4984-8dfd-0565d0563f1d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454236841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1454236841
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.927446170
Short name T450
Test name
Test status
Simulation time 117074112 ps
CPU time 2.54 seconds
Started Jun 07 07:09:55 PM PDT 24
Finished Jun 07 07:09:59 PM PDT 24
Peak memory 209380 kb
Host smart-97b9bf33-934f-4410-9bb2-9a080ea66b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927446170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.927446170
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.4101850603
Short name T490
Test name
Test status
Simulation time 352269524 ps
CPU time 3.11 seconds
Started Jun 07 07:09:49 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 208132 kb
Host smart-9e163a3b-89ce-4d6c-8a61-2d88dd69c8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101850603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.4101850603
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1770356930
Short name T329
Test name
Test status
Simulation time 3703746132 ps
CPU time 11.44 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:10:05 PM PDT 24
Peak memory 218472 kb
Host smart-28c96531-b1cd-46c0-a7b5-279566665c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770356930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1770356930
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.221409310
Short name T757
Test name
Test status
Simulation time 435302391 ps
CPU time 3.44 seconds
Started Jun 07 07:09:54 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 210048 kb
Host smart-8aa63111-8753-4bdd-b453-d2a4e77a9339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221409310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.221409310
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3474144143
Short name T412
Test name
Test status
Simulation time 23629156 ps
CPU time 0.78 seconds
Started Jun 07 07:09:57 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 205968 kb
Host smart-3ffd3318-939c-483d-9884-8460e9a5b0a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474144143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3474144143
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4169939241
Short name T885
Test name
Test status
Simulation time 67927507 ps
CPU time 3.04 seconds
Started Jun 07 07:09:55 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 208448 kb
Host smart-927e748c-b2b3-4809-999d-7faba94f94ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169939241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4169939241
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2206790557
Short name T875
Test name
Test status
Simulation time 424907967 ps
CPU time 7.87 seconds
Started Jun 07 07:09:55 PM PDT 24
Finished Jun 07 07:10:05 PM PDT 24
Peak memory 208992 kb
Host smart-e184c006-e480-4082-9e11-ad678b1d2bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206790557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2206790557
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2811550700
Short name T635
Test name
Test status
Simulation time 142967284 ps
CPU time 2.34 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:09:56 PM PDT 24
Peak memory 214300 kb
Host smart-2b2a2238-ff98-4782-940a-5b7ed4931f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811550700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2811550700
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4263666709
Short name T595
Test name
Test status
Simulation time 908007121 ps
CPU time 5.83 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:09:59 PM PDT 24
Peak memory 214284 kb
Host smart-debbbabd-92ff-4df0-85b8-b77d4b46d5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263666709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4263666709
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.1445633020
Short name T772
Test name
Test status
Simulation time 784310325 ps
CPU time 6.1 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 209048 kb
Host smart-07416cf0-7882-4604-a5a5-1e93663443e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445633020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1445633020
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.40289750
Short name T578
Test name
Test status
Simulation time 877314821 ps
CPU time 4.36 seconds
Started Jun 07 07:09:53 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 207120 kb
Host smart-01b2b392-f59a-4da5-9012-43ab943d82c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40289750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.40289750
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1104407855
Short name T723
Test name
Test status
Simulation time 103042631 ps
CPU time 4.11 seconds
Started Jun 07 07:09:57 PM PDT 24
Finished Jun 07 07:10:04 PM PDT 24
Peak memory 208120 kb
Host smart-5e9e7da4-a76a-4a43-98ca-8c85c03b4766
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104407855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1104407855
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1395204559
Short name T417
Test name
Test status
Simulation time 167804543 ps
CPU time 6.2 seconds
Started Jun 07 07:09:57 PM PDT 24
Finished Jun 07 07:10:05 PM PDT 24
Peak memory 208888 kb
Host smart-837a8283-9a95-494d-a3db-569d2827140f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395204559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1395204559
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.411051277
Short name T554
Test name
Test status
Simulation time 1045583997 ps
CPU time 28.28 seconds
Started Jun 07 07:09:51 PM PDT 24
Finished Jun 07 07:10:22 PM PDT 24
Peak memory 209060 kb
Host smart-3542f77a-c7fd-4f99-a3f5-8c2df08429c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411051277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.411051277
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.508580349
Short name T850
Test name
Test status
Simulation time 278784521 ps
CPU time 3.39 seconds
Started Jun 07 07:09:56 PM PDT 24
Finished Jun 07 07:10:02 PM PDT 24
Peak memory 218244 kb
Host smart-61da1128-b166-494c-ba25-22a72a26339c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508580349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.508580349
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2306330179
Short name T109
Test name
Test status
Simulation time 137860196 ps
CPU time 3.84 seconds
Started Jun 07 07:09:50 PM PDT 24
Finished Jun 07 07:09:57 PM PDT 24
Peak memory 208220 kb
Host smart-4e57739b-184c-4353-9ee2-83a1c9bb8264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306330179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2306330179
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3283475818
Short name T78
Test name
Test status
Simulation time 13464409143 ps
CPU time 86.53 seconds
Started Jun 07 07:09:55 PM PDT 24
Finished Jun 07 07:11:23 PM PDT 24
Peak memory 216928 kb
Host smart-b0658f21-4ac9-4ec1-b717-a9185042b244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283475818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3283475818
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2919095412
Short name T760
Test name
Test status
Simulation time 403835661 ps
CPU time 15.49 seconds
Started Jun 07 07:09:54 PM PDT 24
Finished Jun 07 07:10:12 PM PDT 24
Peak memory 222652 kb
Host smart-40feab8e-2373-4bdc-a2e2-37fea29fdc5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919095412 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2919095412
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2196882308
Short name T87
Test name
Test status
Simulation time 238379297 ps
CPU time 4.15 seconds
Started Jun 07 07:09:54 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 214304 kb
Host smart-2061a3a9-0f1c-4f8f-a904-d5ef614a417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196882308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2196882308
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.993601637
Short name T749
Test name
Test status
Simulation time 615792740 ps
CPU time 1.54 seconds
Started Jun 07 07:09:57 PM PDT 24
Finished Jun 07 07:10:02 PM PDT 24
Peak memory 209544 kb
Host smart-d541e63b-062c-4921-a9fe-4a3cd4ed9d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993601637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.993601637
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1353992215
Short name T692
Test name
Test status
Simulation time 24897812 ps
CPU time 0.77 seconds
Started Jun 07 07:10:01 PM PDT 24
Finished Jun 07 07:10:06 PM PDT 24
Peak memory 205940 kb
Host smart-1112a94f-8c28-4e1b-ae1d-9b5e70f77405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353992215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1353992215
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2628288862
Short name T16
Test name
Test status
Simulation time 116649335 ps
CPU time 3.4 seconds
Started Jun 07 07:09:59 PM PDT 24
Finished Jun 07 07:10:07 PM PDT 24
Peak memory 210120 kb
Host smart-58b29292-c72e-46c6-9d73-99ab89640cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628288862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2628288862
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.4003855106
Short name T818
Test name
Test status
Simulation time 40244981 ps
CPU time 2.28 seconds
Started Jun 07 07:09:55 PM PDT 24
Finished Jun 07 07:10:00 PM PDT 24
Peak memory 207480 kb
Host smart-acc6491e-8678-49e0-9bcd-1a5da043e8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003855106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.4003855106
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3535025664
Short name T849
Test name
Test status
Simulation time 51705876 ps
CPU time 3.38 seconds
Started Jun 07 07:09:58 PM PDT 24
Finished Jun 07 07:10:06 PM PDT 24
Peak memory 206764 kb
Host smart-25e02f73-21fe-4316-adfe-6a5ed5447d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535025664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3535025664
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.642993818
Short name T145
Test name
Test status
Simulation time 467550295 ps
CPU time 3.28 seconds
Started Jun 07 07:09:58 PM PDT 24
Finished Jun 07 07:10:05 PM PDT 24
Peak memory 210780 kb
Host smart-1ecaed1f-f0d0-41f8-8ec0-0f68569e7b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642993818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.642993818
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1306371758
Short name T910
Test name
Test status
Simulation time 127004192 ps
CPU time 2.54 seconds
Started Jun 07 07:09:54 PM PDT 24
Finished Jun 07 07:09:59 PM PDT 24
Peak memory 208208 kb
Host smart-624c8b9b-9c46-4a13-86a2-5e0db365037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306371758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1306371758
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1281168284
Short name T359
Test name
Test status
Simulation time 168953213 ps
CPU time 3.39 seconds
Started Jun 07 07:09:56 PM PDT 24
Finished Jun 07 07:10:02 PM PDT 24
Peak memory 208324 kb
Host smart-45850919-db22-4a87-b321-0edf0912fbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281168284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1281168284
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3796758519
Short name T660
Test name
Test status
Simulation time 260879164 ps
CPU time 3.2 seconds
Started Jun 07 07:09:53 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 206960 kb
Host smart-a1420981-fc32-4671-a361-82025694a05d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796758519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3796758519
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2344865636
Short name T140
Test name
Test status
Simulation time 153409652 ps
CPU time 2.37 seconds
Started Jun 07 07:09:53 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 207152 kb
Host smart-b9e21db0-5b61-4746-9114-33e529095cc3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344865636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2344865636
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1046108608
Short name T11
Test name
Test status
Simulation time 23111088 ps
CPU time 1.7 seconds
Started Jun 07 07:09:53 PM PDT 24
Finished Jun 07 07:09:57 PM PDT 24
Peak memory 206908 kb
Host smart-4b776401-ff5f-4eae-a1c9-80de69246be0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046108608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1046108608
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2041830644
Short name T522
Test name
Test status
Simulation time 46609276 ps
CPU time 1.84 seconds
Started Jun 07 07:09:59 PM PDT 24
Finished Jun 07 07:10:06 PM PDT 24
Peak memory 209816 kb
Host smart-b25f897b-847b-4715-b735-c87a4a84b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041830644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2041830644
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3083675834
Short name T645
Test name
Test status
Simulation time 96914614 ps
CPU time 3.13 seconds
Started Jun 07 07:09:55 PM PDT 24
Finished Jun 07 07:10:01 PM PDT 24
Peak memory 208484 kb
Host smart-b1e25521-7b22-47e8-a40c-8dd90904a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083675834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3083675834
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.94410911
Short name T890
Test name
Test status
Simulation time 138448813 ps
CPU time 5.64 seconds
Started Jun 07 07:09:58 PM PDT 24
Finished Jun 07 07:10:07 PM PDT 24
Peak memory 210460 kb
Host smart-2af1db31-2f3a-445b-8252-27fe83cbea83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94410911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.94410911
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2510792827
Short name T348
Test name
Test status
Simulation time 111975779 ps
CPU time 2.15 seconds
Started Jun 07 07:09:58 PM PDT 24
Finished Jun 07 07:10:03 PM PDT 24
Peak memory 210112 kb
Host smart-9cea2573-b1d1-49b8-922c-a81035874822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510792827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2510792827
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3188818995
Short name T854
Test name
Test status
Simulation time 22117304 ps
CPU time 0.84 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:11 PM PDT 24
Peak memory 205940 kb
Host smart-1119d886-aa55-4b38-95a4-b59138cb2b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188818995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3188818995
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3111199020
Short name T753
Test name
Test status
Simulation time 142831474 ps
CPU time 3.17 seconds
Started Jun 07 07:10:01 PM PDT 24
Finished Jun 07 07:10:09 PM PDT 24
Peak memory 214576 kb
Host smart-f338f330-1711-431d-882f-f7b1025adda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111199020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3111199020
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.252511687
Short name T72
Test name
Test status
Simulation time 27718902 ps
CPU time 1.69 seconds
Started Jun 07 07:09:58 PM PDT 24
Finished Jun 07 07:10:03 PM PDT 24
Peak memory 207192 kb
Host smart-275419fa-33f6-4965-addf-c8bb850faf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252511687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.252511687
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.793858571
Short name T217
Test name
Test status
Simulation time 525827575 ps
CPU time 2.99 seconds
Started Jun 07 07:10:00 PM PDT 24
Finished Jun 07 07:10:08 PM PDT 24
Peak memory 209512 kb
Host smart-ecf902b8-6e1a-4cbc-ad9d-f6b440381c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793858571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.793858571
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3129619768
Short name T250
Test name
Test status
Simulation time 3544404855 ps
CPU time 29.12 seconds
Started Jun 07 07:10:00 PM PDT 24
Finished Jun 07 07:10:34 PM PDT 24
Peak memory 218384 kb
Host smart-1a18b93a-f2cd-4c60-8ee2-e0d698b4d5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129619768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3129619768
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.231199594
Short name T104
Test name
Test status
Simulation time 930271576 ps
CPU time 13.58 seconds
Started Jun 07 07:09:59 PM PDT 24
Finished Jun 07 07:10:17 PM PDT 24
Peak memory 207988 kb
Host smart-88227e81-7210-4664-99b9-a1e9ec87f532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231199594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.231199594
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.132190387
Short name T812
Test name
Test status
Simulation time 559936385 ps
CPU time 4.74 seconds
Started Jun 07 07:10:00 PM PDT 24
Finished Jun 07 07:10:09 PM PDT 24
Peak memory 207844 kb
Host smart-ecae3f78-c600-420e-8f3a-275de79e0931
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132190387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.132190387
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2616163904
Short name T395
Test name
Test status
Simulation time 102121364 ps
CPU time 1.88 seconds
Started Jun 07 07:10:00 PM PDT 24
Finished Jun 07 07:10:07 PM PDT 24
Peak memory 206900 kb
Host smart-01e72b3f-0304-4840-91e3-d9d2da923edc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616163904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2616163904
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2240132373
Short name T189
Test name
Test status
Simulation time 413772175 ps
CPU time 5.03 seconds
Started Jun 07 07:10:01 PM PDT 24
Finished Jun 07 07:10:10 PM PDT 24
Peak memory 208092 kb
Host smart-b1f85f91-e81e-4ba4-9e95-e3b2fb4473d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240132373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2240132373
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.152042596
Short name T443
Test name
Test status
Simulation time 1406753214 ps
CPU time 3.17 seconds
Started Jun 07 07:09:59 PM PDT 24
Finished Jun 07 07:10:07 PM PDT 24
Peak memory 214400 kb
Host smart-54123e07-3207-48a1-b8b0-0cdd75072c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152042596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.152042596
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2782756328
Short name T841
Test name
Test status
Simulation time 97617717 ps
CPU time 3.57 seconds
Started Jun 07 07:10:01 PM PDT 24
Finished Jun 07 07:10:09 PM PDT 24
Peak memory 208412 kb
Host smart-909ba20b-1e52-4a91-b2b9-8a8ca821eedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782756328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2782756328
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4214577206
Short name T523
Test name
Test status
Simulation time 2292959620 ps
CPU time 40.34 seconds
Started Jun 07 07:10:02 PM PDT 24
Finished Jun 07 07:10:46 PM PDT 24
Peak memory 222240 kb
Host smart-661e1f61-bf40-474b-ba26-03970cd2a130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214577206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4214577206
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.508775748
Short name T14
Test name
Test status
Simulation time 1015747451 ps
CPU time 4.48 seconds
Started Jun 07 07:10:01 PM PDT 24
Finished Jun 07 07:10:10 PM PDT 24
Peak memory 207472 kb
Host smart-6c91799d-6125-47cd-b4ae-ef1e135ead13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508775748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.508775748
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1431559185
Short name T597
Test name
Test status
Simulation time 103646537 ps
CPU time 2.97 seconds
Started Jun 07 07:09:58 PM PDT 24
Finished Jun 07 07:10:04 PM PDT 24
Peak memory 210620 kb
Host smart-9a673a4a-026e-4ccb-b999-3394fae95754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431559185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1431559185
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1151173068
Short name T439
Test name
Test status
Simulation time 14133823 ps
CPU time 0.91 seconds
Started Jun 07 07:10:09 PM PDT 24
Finished Jun 07 07:10:14 PM PDT 24
Peak memory 206084 kb
Host smart-31b92b77-2e4b-40fe-b52c-57f7b2d1a05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151173068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1151173068
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3747300540
Short name T909
Test name
Test status
Simulation time 273145288 ps
CPU time 14.98 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:25 PM PDT 24
Peak memory 214376 kb
Host smart-36e5ace8-70b8-42f7-bb74-2e22a640f4a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747300540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3747300540
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.753987077
Short name T604
Test name
Test status
Simulation time 991367181 ps
CPU time 4.49 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:16 PM PDT 24
Peak memory 221728 kb
Host smart-150d4ad5-fd02-427a-a4d8-d1c2423fe5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753987077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.753987077
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1420483005
Short name T587
Test name
Test status
Simulation time 77630600 ps
CPU time 2.91 seconds
Started Jun 07 07:10:09 PM PDT 24
Finished Jun 07 07:10:16 PM PDT 24
Peak memory 214400 kb
Host smart-ce93443a-a2f7-4e77-83c1-a4ef87dba6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420483005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1420483005
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3520648670
Short name T99
Test name
Test status
Simulation time 713035611 ps
CPU time 10.32 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:20 PM PDT 24
Peak memory 220828 kb
Host smart-53cff759-fc24-4f2a-8e39-c650d5963d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520648670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3520648670
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2857232919
Short name T809
Test name
Test status
Simulation time 66168060 ps
CPU time 3.04 seconds
Started Jun 07 07:10:08 PM PDT 24
Finished Jun 07 07:10:15 PM PDT 24
Peak memory 222328 kb
Host smart-33d20966-640b-421e-82d5-e2480532588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857232919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2857232919
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2889272873
Short name T825
Test name
Test status
Simulation time 73110875 ps
CPU time 3.23 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:15 PM PDT 24
Peak memory 220280 kb
Host smart-ab44f658-92f1-4ee0-8ba9-572a3c74cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889272873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2889272873
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1156108249
Short name T530
Test name
Test status
Simulation time 230271925 ps
CPU time 3.07 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:13 PM PDT 24
Peak memory 209120 kb
Host smart-a800e5c6-6a95-4baa-b7a7-d5329846f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156108249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1156108249
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.367941709
Short name T405
Test name
Test status
Simulation time 259462857 ps
CPU time 6.21 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:15 PM PDT 24
Peak memory 208268 kb
Host smart-502ae041-3d2d-483f-a1f4-1b9f15ee37ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367941709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.367941709
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3327449152
Short name T733
Test name
Test status
Simulation time 206842557 ps
CPU time 3.09 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:12 PM PDT 24
Peak memory 209008 kb
Host smart-81664d52-81ed-4fef-8415-64121dfcd7a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327449152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3327449152
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2023875626
Short name T314
Test name
Test status
Simulation time 60122096 ps
CPU time 2.74 seconds
Started Jun 07 07:10:05 PM PDT 24
Finished Jun 07 07:10:12 PM PDT 24
Peak memory 208580 kb
Host smart-d5015628-3d41-4420-8845-b6dde10c0d7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023875626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2023875626
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4268962737
Short name T767
Test name
Test status
Simulation time 115673096 ps
CPU time 2.4 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:14 PM PDT 24
Peak memory 206976 kb
Host smart-40aaf91d-2d5e-428d-b45d-8f4bad762621
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268962737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4268962737
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2845843730
Short name T898
Test name
Test status
Simulation time 63392227 ps
CPU time 2.76 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:13 PM PDT 24
Peak memory 210384 kb
Host smart-20b1f6b0-70cd-40d5-badc-303d53e7c73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845843730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2845843730
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.403593917
Short name T606
Test name
Test status
Simulation time 508479468 ps
CPU time 3.84 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:15 PM PDT 24
Peak memory 207228 kb
Host smart-7bff8a6a-bc8f-49b4-8633-50e28e522483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403593917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.403593917
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1843453454
Short name T787
Test name
Test status
Simulation time 201098458 ps
CPU time 9.36 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:20 PM PDT 24
Peak memory 222460 kb
Host smart-f26e8132-bc03-4259-bd4c-f7e01a0883e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843453454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1843453454
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1328160686
Short name T701
Test name
Test status
Simulation time 304294396 ps
CPU time 20.09 seconds
Started Jun 07 07:10:09 PM PDT 24
Finished Jun 07 07:10:33 PM PDT 24
Peak memory 222632 kb
Host smart-4580d17f-b2c7-4bb8-922e-74fae791a66c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328160686 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1328160686
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3629760683
Short name T479
Test name
Test status
Simulation time 310729706 ps
CPU time 9.09 seconds
Started Jun 07 07:10:08 PM PDT 24
Finished Jun 07 07:10:21 PM PDT 24
Peak memory 218504 kb
Host smart-854508d8-b4db-428e-bb58-32d9ebda8590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629760683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3629760683
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1102602300
Short name T174
Test name
Test status
Simulation time 51235619 ps
CPU time 1.78 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:13 PM PDT 24
Peak memory 209848 kb
Host smart-7ab2dac5-5595-4316-99d0-21149c4df2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102602300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1102602300
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.48370173
Short name T715
Test name
Test status
Simulation time 12546304 ps
CPU time 0.88 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:12 PM PDT 24
Peak memory 205972 kb
Host smart-5ea0c816-9bd8-4df0-a9ee-8054c756ac03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48370173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.48370173
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.926606007
Short name T130
Test name
Test status
Simulation time 506524099 ps
CPU time 3.99 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:15 PM PDT 24
Peak memory 215360 kb
Host smart-22263057-3e6e-4093-8a8a-06127c0e35e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=926606007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.926606007
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1069619102
Short name T157
Test name
Test status
Simulation time 113310636 ps
CPU time 3.52 seconds
Started Jun 07 07:10:08 PM PDT 24
Finished Jun 07 07:10:16 PM PDT 24
Peak memory 222680 kb
Host smart-c711d7a5-74cc-4c5c-bd7a-655abcfd961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069619102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1069619102
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2984017051
Short name T560
Test name
Test status
Simulation time 209573036 ps
CPU time 5.92 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:17 PM PDT 24
Peak memory 208076 kb
Host smart-c4882776-eb40-4f93-91bf-eb5b99d82e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984017051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2984017051
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3070365432
Short name T100
Test name
Test status
Simulation time 452296828 ps
CPU time 3.28 seconds
Started Jun 07 07:10:05 PM PDT 24
Finished Jun 07 07:10:12 PM PDT 24
Peak memory 208704 kb
Host smart-7cee2187-84f5-4068-b1ea-51c48ab5f40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070365432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3070365432
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2690361504
Short name T591
Test name
Test status
Simulation time 165168836 ps
CPU time 2.04 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:12 PM PDT 24
Peak memory 214260 kb
Host smart-d90891a2-1576-46bb-9797-0e199235fb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690361504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2690361504
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2504269979
Short name T325
Test name
Test status
Simulation time 59310579 ps
CPU time 3.93 seconds
Started Jun 07 07:10:08 PM PDT 24
Finished Jun 07 07:10:15 PM PDT 24
Peak memory 222560 kb
Host smart-da6c8de8-e4c9-4310-bb13-c09834d15849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504269979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2504269979
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1297673612
Short name T774
Test name
Test status
Simulation time 5070352347 ps
CPU time 25.52 seconds
Started Jun 07 07:10:10 PM PDT 24
Finished Jun 07 07:10:39 PM PDT 24
Peak memory 214420 kb
Host smart-a0514907-cf63-48da-8b29-68fc75b1b6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297673612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1297673612
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.600319962
Short name T569
Test name
Test status
Simulation time 638211303 ps
CPU time 3.83 seconds
Started Jun 07 07:10:08 PM PDT 24
Finished Jun 07 07:10:16 PM PDT 24
Peak memory 208800 kb
Host smart-f366062d-b040-4d8f-b340-c41896693e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600319962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.600319962
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.401742582
Short name T777
Test name
Test status
Simulation time 278570253 ps
CPU time 3.63 seconds
Started Jun 07 07:10:08 PM PDT 24
Finished Jun 07 07:10:16 PM PDT 24
Peak memory 208844 kb
Host smart-a1c50b62-ad7b-4d27-9683-6d483b9dfec8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401742582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.401742582
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1947943068
Short name T679
Test name
Test status
Simulation time 35040550 ps
CPU time 2.4 seconds
Started Jun 07 07:10:08 PM PDT 24
Finished Jun 07 07:10:14 PM PDT 24
Peak memory 206948 kb
Host smart-272a0994-a8a3-4b29-aa52-aba22aaed3c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947943068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1947943068
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1878129267
Short name T483
Test name
Test status
Simulation time 174615941 ps
CPU time 2.79 seconds
Started Jun 07 07:10:05 PM PDT 24
Finished Jun 07 07:10:12 PM PDT 24
Peak memory 206856 kb
Host smart-88e65405-cdec-46f6-8a11-5c0aa170fa99
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878129267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1878129267
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2510916226
Short name T513
Test name
Test status
Simulation time 92534097 ps
CPU time 2.8 seconds
Started Jun 07 07:10:09 PM PDT 24
Finished Jun 07 07:10:15 PM PDT 24
Peak memory 215808 kb
Host smart-a9818c50-277c-4923-b70e-7e9b771e64d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510916226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2510916226
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2723936382
Short name T613
Test name
Test status
Simulation time 172896197 ps
CPU time 4.44 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:14 PM PDT 24
Peak memory 208144 kb
Host smart-02455646-2e02-4832-897f-5afad642060c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723936382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2723936382
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.359978460
Short name T588
Test name
Test status
Simulation time 1551466412 ps
CPU time 18.74 seconds
Started Jun 07 07:10:09 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 222660 kb
Host smart-ba667e9f-ca23-4f14-964a-0efc088ee8d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359978460 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.359978460
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3841373749
Short name T108
Test name
Test status
Simulation time 1004723960 ps
CPU time 5.32 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:16 PM PDT 24
Peak memory 214336 kb
Host smart-ca7495df-11ac-4ea4-aa15-8a1521953a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841373749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3841373749
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2470604930
Short name T407
Test name
Test status
Simulation time 195525103 ps
CPU time 2.16 seconds
Started Jun 07 07:10:07 PM PDT 24
Finished Jun 07 07:10:13 PM PDT 24
Peak memory 209840 kb
Host smart-c4f40b48-ac1f-4986-95c9-3c774518ebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470604930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2470604930
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1368630171
Short name T693
Test name
Test status
Simulation time 37614950 ps
CPU time 0.96 seconds
Started Jun 07 07:10:17 PM PDT 24
Finished Jun 07 07:10:20 PM PDT 24
Peak memory 206212 kb
Host smart-604971fc-1ad2-4f02-a52f-3b60c2ff07e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368630171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1368630171
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2185661131
Short name T328
Test name
Test status
Simulation time 543049661 ps
CPU time 4.5 seconds
Started Jun 07 07:10:21 PM PDT 24
Finished Jun 07 07:10:29 PM PDT 24
Peak memory 214272 kb
Host smart-103ad560-ed77-4e63-90ae-24a3964c8bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185661131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2185661131
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3988743913
Short name T31
Test name
Test status
Simulation time 66528124 ps
CPU time 2.39 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:18 PM PDT 24
Peak memory 208652 kb
Host smart-1d1c1029-7d84-4072-a494-e84b7ef6773b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988743913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3988743913
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1523398283
Short name T807
Test name
Test status
Simulation time 353349763 ps
CPU time 5.86 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:21 PM PDT 24
Peak memory 214392 kb
Host smart-3066857e-2cfe-4ffe-b477-5dbb82740349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523398283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1523398283
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1350880087
Short name T707
Test name
Test status
Simulation time 508891799 ps
CPU time 4.05 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:20 PM PDT 24
Peak memory 222508 kb
Host smart-859af3e2-1e54-43d1-8fa7-0d5ee55efcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350880087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1350880087
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2550913567
Short name T652
Test name
Test status
Simulation time 238152449 ps
CPU time 2.47 seconds
Started Jun 07 07:10:15 PM PDT 24
Finished Jun 07 07:10:20 PM PDT 24
Peak memory 222436 kb
Host smart-d31b9868-8b67-4b66-9f14-fe47bf2c550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550913567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2550913567
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3594072122
Short name T264
Test name
Test status
Simulation time 246266412 ps
CPU time 7.2 seconds
Started Jun 07 07:10:15 PM PDT 24
Finished Jun 07 07:10:24 PM PDT 24
Peak memory 214392 kb
Host smart-1299c825-a843-44d1-8ad3-de6db8564d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594072122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3594072122
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2988022735
Short name T646
Test name
Test status
Simulation time 503384799 ps
CPU time 8.15 seconds
Started Jun 07 07:10:05 PM PDT 24
Finished Jun 07 07:10:17 PM PDT 24
Peak memory 218280 kb
Host smart-f9edd284-45c3-4805-81d2-02e76a6c4847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988022735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2988022735
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2448407505
Short name T697
Test name
Test status
Simulation time 142248875 ps
CPU time 5.15 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:15 PM PDT 24
Peak memory 208036 kb
Host smart-29797322-b522-489a-8d30-f7c992b75f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448407505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2448407505
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1786254886
Short name T536
Test name
Test status
Simulation time 693094607 ps
CPU time 6.4 seconds
Started Jun 07 07:10:08 PM PDT 24
Finished Jun 07 07:10:18 PM PDT 24
Peak memory 208588 kb
Host smart-d1fc4110-8c2b-401c-b12d-8ff777461ef7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786254886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1786254886
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3897089106
Short name T727
Test name
Test status
Simulation time 8261201412 ps
CPU time 33.25 seconds
Started Jun 07 07:10:08 PM PDT 24
Finished Jun 07 07:10:45 PM PDT 24
Peak memory 208856 kb
Host smart-bb1f9618-aeea-42cc-863f-de1641cbc07e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897089106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3897089106
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3784029995
Short name T444
Test name
Test status
Simulation time 44780736 ps
CPU time 2.44 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:18 PM PDT 24
Peak memory 214420 kb
Host smart-4552f067-744f-4168-b650-f64c5eabd6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784029995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3784029995
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3864039817
Short name T603
Test name
Test status
Simulation time 163959474 ps
CPU time 2.43 seconds
Started Jun 07 07:10:06 PM PDT 24
Finished Jun 07 07:10:12 PM PDT 24
Peak memory 208756 kb
Host smart-0a6ed5d5-e602-453b-9c0e-67f6af80cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864039817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3864039817
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3866594895
Short name T304
Test name
Test status
Simulation time 4330597376 ps
CPU time 74.01 seconds
Started Jun 07 07:10:18 PM PDT 24
Finished Jun 07 07:11:34 PM PDT 24
Peak memory 222548 kb
Host smart-fe5ffceb-8511-4d13-8fa1-fe0536a141f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866594895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3866594895
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1839657677
Short name T186
Test name
Test status
Simulation time 277749069 ps
CPU time 10.55 seconds
Started Jun 07 07:10:18 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 219828 kb
Host smart-b9bf74d3-2a89-4022-9906-1a39ca2192ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839657677 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1839657677
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3631183122
Short name T654
Test name
Test status
Simulation time 171513272 ps
CPU time 4.99 seconds
Started Jun 07 07:10:12 PM PDT 24
Finished Jun 07 07:10:19 PM PDT 24
Peak memory 210516 kb
Host smart-a8d16c43-775e-404e-97bc-ee49b23a82fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631183122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3631183122
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.700343653
Short name T426
Test name
Test status
Simulation time 268339900 ps
CPU time 2.71 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:19 PM PDT 24
Peak memory 209716 kb
Host smart-94819763-6995-491d-8f1d-470afd8e45c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700343653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.700343653
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1369083460
Short name T410
Test name
Test status
Simulation time 11949458 ps
CPU time 0.75 seconds
Started Jun 07 07:08:27 PM PDT 24
Finished Jun 07 07:08:31 PM PDT 24
Peak memory 205924 kb
Host smart-c251af3f-7fe9-4202-ab15-576b51c6ae38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369083460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1369083460
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1862485259
Short name T759
Test name
Test status
Simulation time 198366600 ps
CPU time 3.1 seconds
Started Jun 07 07:08:15 PM PDT 24
Finished Jun 07 07:08:20 PM PDT 24
Peak memory 214588 kb
Host smart-1798738b-0e9f-4f62-948b-5bef99f8233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862485259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1862485259
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.959436680
Short name T70
Test name
Test status
Simulation time 1420037568 ps
CPU time 3.46 seconds
Started Jun 07 07:08:15 PM PDT 24
Finished Jun 07 07:08:21 PM PDT 24
Peak memory 208956 kb
Host smart-b57255df-20ea-41d9-815d-c6f39d037a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959436680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.959436680
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.620872004
Short name T605
Test name
Test status
Simulation time 210662669 ps
CPU time 3.17 seconds
Started Jun 07 07:08:15 PM PDT 24
Finished Jun 07 07:08:21 PM PDT 24
Peak memory 222504 kb
Host smart-7001dc33-24c0-4b4d-a261-66c247a99923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620872004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.620872004
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1551051130
Short name T716
Test name
Test status
Simulation time 97336730 ps
CPU time 2.22 seconds
Started Jun 07 07:08:15 PM PDT 24
Finished Jun 07 07:08:19 PM PDT 24
Peak memory 214288 kb
Host smart-f9229e82-4a23-4fb6-8532-ed942f74d011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551051130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1551051130
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1196703442
Short name T45
Test name
Test status
Simulation time 74269427 ps
CPU time 3.15 seconds
Started Jun 07 07:08:14 PM PDT 24
Finished Jun 07 07:08:19 PM PDT 24
Peak memory 214360 kb
Host smart-389f8663-3222-4b6c-8048-fc2707b88e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196703442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1196703442
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.4013367605
Short name T602
Test name
Test status
Simulation time 280639489 ps
CPU time 7.1 seconds
Started Jun 07 07:08:18 PM PDT 24
Finished Jun 07 07:08:28 PM PDT 24
Peak memory 208000 kb
Host smart-52a0acfb-fa1a-4c12-abdd-c00766355149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013367605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.4013367605
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1387354067
Short name T507
Test name
Test status
Simulation time 3217353948 ps
CPU time 32.47 seconds
Started Jun 07 07:08:18 PM PDT 24
Finished Jun 07 07:08:53 PM PDT 24
Peak memory 208192 kb
Host smart-a5bb7d66-719b-461d-a17a-557ff6fe111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387354067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1387354067
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.4161105196
Short name T44
Test name
Test status
Simulation time 97947958 ps
CPU time 2.79 seconds
Started Jun 07 07:08:15 PM PDT 24
Finished Jun 07 07:08:19 PM PDT 24
Peak memory 207336 kb
Host smart-78784a5d-42d5-4a61-b429-28e8d453c174
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161105196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.4161105196
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1991885888
Short name T647
Test name
Test status
Simulation time 2107021621 ps
CPU time 29.52 seconds
Started Jun 07 07:08:14 PM PDT 24
Finished Jun 07 07:08:45 PM PDT 24
Peak memory 208132 kb
Host smart-f3ebc46e-ebaf-49c0-afaa-f07876b3318d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991885888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1991885888
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3192336197
Short name T577
Test name
Test status
Simulation time 153720228 ps
CPU time 1.91 seconds
Started Jun 07 07:08:15 PM PDT 24
Finished Jun 07 07:08:19 PM PDT 24
Peak memory 208832 kb
Host smart-db810ec7-d737-4f03-9168-cff1c37a99ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192336197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3192336197
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.393717634
Short name T296
Test name
Test status
Simulation time 414829387 ps
CPU time 7.84 seconds
Started Jun 07 07:08:18 PM PDT 24
Finished Jun 07 07:08:28 PM PDT 24
Peak memory 208984 kb
Host smart-117539b1-2af0-495e-aebd-c8c6c0890d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393717634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.393717634
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.334578405
Short name T555
Test name
Test status
Simulation time 22124885 ps
CPU time 1.74 seconds
Started Jun 07 07:08:07 PM PDT 24
Finished Jun 07 07:08:10 PM PDT 24
Peak memory 206892 kb
Host smart-e4986b51-59c2-4b22-936f-66dbebf9e4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334578405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.334578405
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.99672870
Short name T124
Test name
Test status
Simulation time 2803709749 ps
CPU time 24.05 seconds
Started Jun 07 07:08:24 PM PDT 24
Finished Jun 07 07:08:50 PM PDT 24
Peak memory 220676 kb
Host smart-b2daa01e-0d7a-4295-a04c-00596fbbd331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99672870 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.99672870
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2036487321
Short name T337
Test name
Test status
Simulation time 332774226 ps
CPU time 2.19 seconds
Started Jun 07 07:08:14 PM PDT 24
Finished Jun 07 07:08:17 PM PDT 24
Peak memory 207100 kb
Host smart-bc0c4956-9281-4ec1-8b28-888398996901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036487321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2036487321
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2822373831
Short name T764
Test name
Test status
Simulation time 1198970053 ps
CPU time 7.88 seconds
Started Jun 07 07:08:15 PM PDT 24
Finished Jun 07 07:08:24 PM PDT 24
Peak memory 210396 kb
Host smart-07ea1220-3e2d-41ee-ad72-6116ab5b3a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822373831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2822373831
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1024918475
Short name T411
Test name
Test status
Simulation time 42800973 ps
CPU time 0.94 seconds
Started Jun 07 07:10:13 PM PDT 24
Finished Jun 07 07:10:16 PM PDT 24
Peak memory 205888 kb
Host smart-5884bca9-13b9-4a8a-ad61-73e9ea8e380c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024918475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1024918475
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1887384650
Short name T445
Test name
Test status
Simulation time 223757743 ps
CPU time 3.29 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:19 PM PDT 24
Peak memory 214272 kb
Host smart-68b920b1-675a-42f2-ba22-9ac8dd8c7925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887384650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1887384650
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1388363652
Short name T499
Test name
Test status
Simulation time 289389973 ps
CPU time 3.29 seconds
Started Jun 07 07:10:20 PM PDT 24
Finished Jun 07 07:10:25 PM PDT 24
Peak memory 210164 kb
Host smart-9bfbfa39-7d9d-46f4-bf0f-3b43f82dbd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388363652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1388363652
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1847621726
Short name T873
Test name
Test status
Simulation time 102471396 ps
CPU time 4.67 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 209068 kb
Host smart-18221702-1e5c-464a-a924-e109dabfd141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847621726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1847621726
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1297825613
Short name T268
Test name
Test status
Simulation time 10594672268 ps
CPU time 17.96 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:34 PM PDT 24
Peak memory 214400 kb
Host smart-26e8d4c4-3508-4fb1-b09d-19a49f7d9c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297825613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1297825613
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_random.3157632073
Short name T867
Test name
Test status
Simulation time 157582057 ps
CPU time 4.09 seconds
Started Jun 07 07:10:16 PM PDT 24
Finished Jun 07 07:10:22 PM PDT 24
Peak memory 214320 kb
Host smart-ffced10b-abbd-4d05-9548-8a6ebe3913d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157632073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3157632073
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3740546363
Short name T441
Test name
Test status
Simulation time 530211328 ps
CPU time 18.57 seconds
Started Jun 07 07:10:20 PM PDT 24
Finished Jun 07 07:10:41 PM PDT 24
Peak memory 208352 kb
Host smart-870b2399-2a6c-432e-8a4b-4a1725d12fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740546363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3740546363
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2959582148
Short name T674
Test name
Test status
Simulation time 110197247 ps
CPU time 2.32 seconds
Started Jun 07 07:10:17 PM PDT 24
Finished Jun 07 07:10:21 PM PDT 24
Peak memory 206816 kb
Host smart-8cae1fa5-1de4-4ebe-b412-97f24373d14e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959582148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2959582148
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1074569478
Short name T423
Test name
Test status
Simulation time 105781956 ps
CPU time 4.41 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:21 PM PDT 24
Peak memory 207032 kb
Host smart-5613f1d5-389d-49e6-9dfb-5ea6ee970400
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074569478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1074569478
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2164193530
Short name T801
Test name
Test status
Simulation time 6579991094 ps
CPU time 41.3 seconds
Started Jun 07 07:10:21 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 208316 kb
Host smart-dbb662ee-1d38-4fcf-a6e9-06681595f81a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164193530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2164193530
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2047656599
Short name T406
Test name
Test status
Simulation time 141379038 ps
CPU time 2.36 seconds
Started Jun 07 07:10:21 PM PDT 24
Finished Jun 07 07:10:27 PM PDT 24
Peak memory 215712 kb
Host smart-3f7c7844-c00f-4dce-8da9-b39d1f485b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047656599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2047656599
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.321372810
Short name T505
Test name
Test status
Simulation time 145776745 ps
CPU time 3.18 seconds
Started Jun 07 07:10:17 PM PDT 24
Finished Jun 07 07:10:22 PM PDT 24
Peak memory 208672 kb
Host smart-80f03e01-b619-4c9e-927f-a02f1110d40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321372810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.321372810
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1061834491
Short name T709
Test name
Test status
Simulation time 2029818671 ps
CPU time 21.84 seconds
Started Jun 07 07:10:13 PM PDT 24
Finished Jun 07 07:10:37 PM PDT 24
Peak memory 222612 kb
Host smart-c52b2343-243f-4979-a412-f88027eda6f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061834491 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1061834491
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1254893457
Short name T868
Test name
Test status
Simulation time 112095164 ps
CPU time 4.93 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:21 PM PDT 24
Peak memory 208780 kb
Host smart-869db295-8798-436f-b21c-06933e8d6b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254893457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1254893457
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3442496320
Short name T168
Test name
Test status
Simulation time 392667977 ps
CPU time 1.82 seconds
Started Jun 07 07:10:12 PM PDT 24
Finished Jun 07 07:10:16 PM PDT 24
Peak memory 210500 kb
Host smart-e43b4bca-872c-4792-bbdf-05ec1e107427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442496320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3442496320
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.4149935357
Short name T388
Test name
Test status
Simulation time 30361158 ps
CPU time 0.92 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:27 PM PDT 24
Peak memory 206076 kb
Host smart-d976fe1b-676d-4dd8-9578-af31df0f1dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149935357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.4149935357
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2328660725
Short name T13
Test name
Test status
Simulation time 283034696 ps
CPU time 4.19 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:32 PM PDT 24
Peak memory 221120 kb
Host smart-94029fcb-14af-43ec-b1e0-57d2cffa6f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328660725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2328660725
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1717327998
Short name T525
Test name
Test status
Simulation time 38394425 ps
CPU time 1.44 seconds
Started Jun 07 07:10:12 PM PDT 24
Finished Jun 07 07:10:16 PM PDT 24
Peak memory 208484 kb
Host smart-4187b1c9-565e-4f2c-9a3d-243bde1cf9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717327998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1717327998
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2723548725
Short name T741
Test name
Test status
Simulation time 140933131 ps
CPU time 2.69 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:19 PM PDT 24
Peak memory 220084 kb
Host smart-4ec67b61-8829-422e-8a91-6200d08e954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723548725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2723548725
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3599450170
Short name T845
Test name
Test status
Simulation time 96093195 ps
CPU time 3.5 seconds
Started Jun 07 07:10:15 PM PDT 24
Finished Jun 07 07:10:20 PM PDT 24
Peak memory 208320 kb
Host smart-60c57aa9-c812-473b-8b2c-24f79d46e4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599450170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3599450170
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3511016997
Short name T190
Test name
Test status
Simulation time 3181133243 ps
CPU time 34.91 seconds
Started Jun 07 07:10:13 PM PDT 24
Finished Jun 07 07:10:50 PM PDT 24
Peak memory 214444 kb
Host smart-7808b45f-9301-4d44-bb4d-087e00d329ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511016997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3511016997
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2752481619
Short name T638
Test name
Test status
Simulation time 178315653 ps
CPU time 4.81 seconds
Started Jun 07 07:10:15 PM PDT 24
Finished Jun 07 07:10:22 PM PDT 24
Peak memory 208044 kb
Host smart-59e7f9ad-bd67-4812-83a2-c7e4f3494001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752481619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2752481619
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2300576715
Short name T791
Test name
Test status
Simulation time 48525253 ps
CPU time 2.86 seconds
Started Jun 07 07:10:21 PM PDT 24
Finished Jun 07 07:10:26 PM PDT 24
Peak memory 209084 kb
Host smart-b9dbdcf8-f885-47f2-b21e-a9e113f190f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300576715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2300576715
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3732403175
Short name T132
Test name
Test status
Simulation time 130414249 ps
CPU time 4.2 seconds
Started Jun 07 07:10:16 PM PDT 24
Finished Jun 07 07:10:22 PM PDT 24
Peak memory 207980 kb
Host smart-28e0cfb6-fdd4-40c8-a1b4-7269ed0f3762
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732403175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3732403175
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4232377932
Short name T573
Test name
Test status
Simulation time 80575278 ps
CPU time 2.36 seconds
Started Jun 07 07:10:15 PM PDT 24
Finished Jun 07 07:10:19 PM PDT 24
Peak memory 207036 kb
Host smart-097a5e08-2cd1-499c-a55f-aa3ff7e48810
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232377932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4232377932
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2510439105
Short name T584
Test name
Test status
Simulation time 209152458 ps
CPU time 4.47 seconds
Started Jun 07 07:10:24 PM PDT 24
Finished Jun 07 07:10:32 PM PDT 24
Peak memory 208852 kb
Host smart-d07189b1-aa21-459c-8cc5-f567d24c1aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510439105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2510439105
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1833033471
Short name T680
Test name
Test status
Simulation time 1704171190 ps
CPU time 23.75 seconds
Started Jun 07 07:10:14 PM PDT 24
Finished Jun 07 07:10:40 PM PDT 24
Peak memory 208012 kb
Host smart-7fed6cbb-3b8a-4a6b-a7ea-4a8bfb58292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833033471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1833033471
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.355100009
Short name T340
Test name
Test status
Simulation time 3218087458 ps
CPU time 37.87 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:11:03 PM PDT 24
Peak memory 222092 kb
Host smart-29200738-30b7-4b2b-9495-40ec87c63613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355100009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.355100009
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.467240798
Short name T69
Test name
Test status
Simulation time 158614342 ps
CPU time 10.71 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:36 PM PDT 24
Peak memory 220596 kb
Host smart-d0936e5e-fe6f-4e31-9df3-ae0b2b11ab9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467240798 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.467240798
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3475136922
Short name T324
Test name
Test status
Simulation time 124740017 ps
CPU time 5.57 seconds
Started Jun 07 07:10:21 PM PDT 24
Finished Jun 07 07:10:29 PM PDT 24
Peak memory 214280 kb
Host smart-533a685f-08c3-48ce-9665-017532933f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475136922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3475136922
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.156503562
Short name T452
Test name
Test status
Simulation time 68515188 ps
CPU time 2.84 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:29 PM PDT 24
Peak memory 209944 kb
Host smart-6f683ced-2a26-40ec-ae3b-7d9315250791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156503562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.156503562
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1956453801
Short name T521
Test name
Test status
Simulation time 184646067 ps
CPU time 0.72 seconds
Started Jun 07 07:10:24 PM PDT 24
Finished Jun 07 07:10:29 PM PDT 24
Peak memory 205972 kb
Host smart-dcd5859c-8632-4d45-96b0-acfb17a9535a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956453801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1956453801
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3683949269
Short name T289
Test name
Test status
Simulation time 549767914 ps
CPU time 14.33 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:42 PM PDT 24
Peak memory 214844 kb
Host smart-68226717-e29d-4e13-88d4-af4b0cf323c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3683949269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3683949269
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3072408063
Short name T26
Test name
Test status
Simulation time 240832887 ps
CPU time 5.19 seconds
Started Jun 07 07:10:19 PM PDT 24
Finished Jun 07 07:10:26 PM PDT 24
Peak memory 209860 kb
Host smart-aa7ca974-e582-4b94-82eb-e525bff147f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072408063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3072408063
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3626669814
Short name T193
Test name
Test status
Simulation time 86615241 ps
CPU time 2.52 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:28 PM PDT 24
Peak memory 208988 kb
Host smart-e76b5256-82bc-4045-8ec8-59d8a53bd1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626669814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3626669814
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2312122893
Short name T94
Test name
Test status
Simulation time 154963273 ps
CPU time 2.8 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:30 PM PDT 24
Peak memory 214348 kb
Host smart-43fc0a46-3ae2-46c3-9fac-722607218d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312122893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2312122893
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.836426697
Short name T323
Test name
Test status
Simulation time 139042584 ps
CPU time 3.68 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:30 PM PDT 24
Peak memory 214216 kb
Host smart-516ed493-b629-4c4e-9f75-b85dd966b568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836426697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.836426697
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.528126497
Short name T843
Test name
Test status
Simulation time 84343268 ps
CPU time 4.07 seconds
Started Jun 07 07:10:21 PM PDT 24
Finished Jun 07 07:10:28 PM PDT 24
Peak memory 209696 kb
Host smart-eda0882d-d255-4012-8222-1e178d94815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528126497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.528126497
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1041660118
Short name T295
Test name
Test status
Simulation time 562015180 ps
CPU time 2.71 seconds
Started Jun 07 07:10:24 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 218448 kb
Host smart-fb5f874a-c774-4636-bcb0-9493b719981a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041660118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1041660118
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.467499192
Short name T761
Test name
Test status
Simulation time 56960181 ps
CPU time 2.71 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:28 PM PDT 24
Peak memory 206880 kb
Host smart-ca279b20-c1f4-4662-ac54-57b676afc37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467499192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.467499192
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1014438144
Short name T610
Test name
Test status
Simulation time 2174209442 ps
CPU time 36.98 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:11:02 PM PDT 24
Peak memory 208420 kb
Host smart-4c40e9df-4ba3-411b-b7c3-b25e55675520
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014438144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1014438144
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2513598450
Short name T532
Test name
Test status
Simulation time 567874114 ps
CPU time 3.38 seconds
Started Jun 07 07:10:21 PM PDT 24
Finished Jun 07 07:10:28 PM PDT 24
Peak memory 208736 kb
Host smart-6d12d54d-56ac-49f8-be8f-a94723384e9d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513598450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2513598450
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.417769652
Short name T356
Test name
Test status
Simulation time 67398805 ps
CPU time 3.55 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:29 PM PDT 24
Peak memory 208856 kb
Host smart-45f518f6-cc63-45b0-9924-afadeea181f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417769652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.417769652
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1074725796
Short name T557
Test name
Test status
Simulation time 58681622 ps
CPU time 2.62 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:29 PM PDT 24
Peak memory 215632 kb
Host smart-d675c685-1487-40dc-9aa4-986a3b579a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074725796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1074725796
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3074479791
Short name T531
Test name
Test status
Simulation time 2678298478 ps
CPU time 16.19 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:43 PM PDT 24
Peak memory 208604 kb
Host smart-3daab2a4-7f09-49f5-9e1f-6e3d01c8747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074479791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3074479791
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1760558902
Short name T586
Test name
Test status
Simulation time 302987807 ps
CPU time 2.76 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:28 PM PDT 24
Peak memory 208136 kb
Host smart-de023c5e-6139-42dc-958c-0651f59bcd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760558902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1760558902
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1311474039
Short name T527
Test name
Test status
Simulation time 114709594 ps
CPU time 2.32 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:29 PM PDT 24
Peak memory 210020 kb
Host smart-a8d23900-7185-4e82-916e-70eb00ccf80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311474039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1311474039
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2725189146
Short name T385
Test name
Test status
Simulation time 133879063 ps
CPU time 0.77 seconds
Started Jun 07 07:10:21 PM PDT 24
Finished Jun 07 07:10:24 PM PDT 24
Peak memory 206040 kb
Host smart-a85700aa-eda6-4312-8054-bb444fa0e79b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725189146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2725189146
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.573647612
Short name T290
Test name
Test status
Simulation time 131629161 ps
CPU time 3.43 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 214372 kb
Host smart-3732b1fa-dd5e-40b4-a559-dd2c4408ddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573647612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.573647612
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1464662608
Short name T90
Test name
Test status
Simulation time 65735371 ps
CPU time 2.93 seconds
Started Jun 07 07:10:25 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 207932 kb
Host smart-b17530dd-cc5d-4d1f-8239-7950e7a8f540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464662608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1464662608
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.4045588699
Short name T907
Test name
Test status
Simulation time 39114161 ps
CPU time 2.04 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:29 PM PDT 24
Peak memory 214452 kb
Host smart-7aaa1083-f5d0-434e-99f3-5808a65d7053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045588699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4045588699
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.555774967
Short name T224
Test name
Test status
Simulation time 45642225 ps
CPU time 3.32 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:30 PM PDT 24
Peak memory 209572 kb
Host smart-efbe5596-7f81-4e82-a86a-88aaab012906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555774967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.555774967
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3774450319
Short name T556
Test name
Test status
Simulation time 988072720 ps
CPU time 7.81 seconds
Started Jun 07 07:10:24 PM PDT 24
Finished Jun 07 07:10:36 PM PDT 24
Peak memory 209012 kb
Host smart-61434c82-0578-48c7-b32a-f0ed0684073f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774450319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3774450319
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.652027634
Short name T269
Test name
Test status
Simulation time 199821255 ps
CPU time 4.49 seconds
Started Jun 07 07:10:24 PM PDT 24
Finished Jun 07 07:10:32 PM PDT 24
Peak memory 208644 kb
Host smart-c77d9440-17a3-41fe-a51c-e4bcfc5db5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652027634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.652027634
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1883157593
Short name T543
Test name
Test status
Simulation time 1157976933 ps
CPU time 3.04 seconds
Started Jun 07 07:10:25 PM PDT 24
Finished Jun 07 07:10:32 PM PDT 24
Peak memory 207028 kb
Host smart-443b2405-8190-4393-bf53-addd4c4ea286
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883157593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1883157593
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4213270485
Short name T110
Test name
Test status
Simulation time 30518636 ps
CPU time 2.19 seconds
Started Jun 07 07:10:20 PM PDT 24
Finished Jun 07 07:10:25 PM PDT 24
Peak memory 208688 kb
Host smart-0ca8e642-e9e6-4a53-8d69-6b69793c116b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213270485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4213270485
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.704950154
Short name T486
Test name
Test status
Simulation time 3435855607 ps
CPU time 30.74 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:58 PM PDT 24
Peak memory 208584 kb
Host smart-941bef99-054a-40d8-b086-36828719d04f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704950154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.704950154
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2424804329
Short name T139
Test name
Test status
Simulation time 29715906 ps
CPU time 1.41 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:27 PM PDT 24
Peak memory 208112 kb
Host smart-207ac3e8-c43c-4e99-9402-e01612b736e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424804329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2424804329
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.574324920
Short name T397
Test name
Test status
Simulation time 239205977 ps
CPU time 3.54 seconds
Started Jun 07 07:10:21 PM PDT 24
Finished Jun 07 07:10:27 PM PDT 24
Peak memory 208476 kb
Host smart-559fbe97-1f32-4b0e-a822-5dfa2ed27c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574324920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.574324920
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2418691496
Short name T509
Test name
Test status
Simulation time 886394252 ps
CPU time 21.08 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:47 PM PDT 24
Peak memory 218376 kb
Host smart-40e7af59-ea6f-415d-90dc-d05f47a9a387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418691496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2418691496
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.639144257
Short name T824
Test name
Test status
Simulation time 153169189 ps
CPU time 1.6 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:29 PM PDT 24
Peak memory 210568 kb
Host smart-24812b46-f8db-4ca9-ac95-d71f8f294ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639144257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.639144257
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2010722302
Short name T676
Test name
Test status
Simulation time 39262704 ps
CPU time 0.75 seconds
Started Jun 07 07:10:32 PM PDT 24
Finished Jun 07 07:10:37 PM PDT 24
Peak memory 205900 kb
Host smart-5a6632d7-3d74-4875-bd76-c14f320d0f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010722302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2010722302
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1196985279
Short name T255
Test name
Test status
Simulation time 87685821 ps
CPU time 2.28 seconds
Started Jun 07 07:10:32 PM PDT 24
Finished Jun 07 07:10:38 PM PDT 24
Peak memory 209348 kb
Host smart-50763b48-c30e-4801-98b2-f367e03658ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196985279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1196985279
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1186215763
Short name T874
Test name
Test status
Simulation time 358227381 ps
CPU time 5.04 seconds
Started Jun 07 07:10:30 PM PDT 24
Finished Jun 07 07:10:39 PM PDT 24
Peak memory 209688 kb
Host smart-773d8f3f-5f9e-4527-96c3-e0c830591b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186215763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1186215763
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1413091740
Short name T653
Test name
Test status
Simulation time 197752116 ps
CPU time 2.47 seconds
Started Jun 07 07:10:33 PM PDT 24
Finished Jun 07 07:10:39 PM PDT 24
Peak memory 214280 kb
Host smart-855c42b7-402b-4a82-8543-c96a585a5992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413091740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1413091740
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3403291274
Short name T743
Test name
Test status
Simulation time 763371227 ps
CPU time 3.38 seconds
Started Jun 07 07:10:36 PM PDT 24
Finished Jun 07 07:10:44 PM PDT 24
Peak memory 208176 kb
Host smart-31c595a7-90c2-4472-81ff-eb6962a6cbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403291274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3403291274
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1946122901
Short name T529
Test name
Test status
Simulation time 381409776 ps
CPU time 4.54 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 210036 kb
Host smart-258043b4-fab9-4291-9a61-3c3453148545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946122901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1946122901
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1597861076
Short name T703
Test name
Test status
Simulation time 86104787 ps
CPU time 3.53 seconds
Started Jun 07 07:10:22 PM PDT 24
Finished Jun 07 07:10:29 PM PDT 24
Peak memory 208052 kb
Host smart-2798daec-f05c-401c-9cd7-f99171cc5043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597861076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1597861076
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3027729002
Short name T238
Test name
Test status
Simulation time 51679199 ps
CPU time 3 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:30 PM PDT 24
Peak memory 206992 kb
Host smart-be96c756-a42a-4247-963a-8ac54bb29088
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027729002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3027729002
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1917978949
Short name T581
Test name
Test status
Simulation time 211444595 ps
CPU time 4.89 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 208860 kb
Host smart-867d2b23-b848-4e2a-8b16-b1ab678c14a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917978949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1917978949
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1375916231
Short name T813
Test name
Test status
Simulation time 40450638 ps
CPU time 2.66 seconds
Started Jun 07 07:10:25 PM PDT 24
Finished Jun 07 07:10:31 PM PDT 24
Peak memory 209060 kb
Host smart-b2b494d4-9cca-4f6d-a09a-c490a8d2cc7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375916231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1375916231
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3019324014
Short name T383
Test name
Test status
Simulation time 137445768 ps
CPU time 4.44 seconds
Started Jun 07 07:10:30 PM PDT 24
Finished Jun 07 07:10:38 PM PDT 24
Peak memory 218504 kb
Host smart-02ac8fcf-836c-4e68-b21a-3d0766f04853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019324014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3019324014
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3885883760
Short name T628
Test name
Test status
Simulation time 2064434891 ps
CPU time 5.46 seconds
Started Jun 07 07:10:23 PM PDT 24
Finished Jun 07 07:10:33 PM PDT 24
Peak memory 208588 kb
Host smart-3c23f528-eaf8-4276-9720-abb75ce9d157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885883760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3885883760
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2436965377
Short name T430
Test name
Test status
Simulation time 161437452 ps
CPU time 3.44 seconds
Started Jun 07 07:10:29 PM PDT 24
Finished Jun 07 07:10:37 PM PDT 24
Peak memory 207620 kb
Host smart-f3e31991-0b4a-471f-99a5-c07a3bbdb146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436965377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2436965377
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2918051512
Short name T471
Test name
Test status
Simulation time 10429465 ps
CPU time 0.82 seconds
Started Jun 07 07:10:38 PM PDT 24
Finished Jun 07 07:10:45 PM PDT 24
Peak memory 205908 kb
Host smart-92334798-3801-4b95-bbed-5ed148cde0a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918051512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2918051512
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3925032529
Short name T360
Test name
Test status
Simulation time 147613015 ps
CPU time 8.03 seconds
Started Jun 07 07:10:31 PM PDT 24
Finished Jun 07 07:10:43 PM PDT 24
Peak memory 214528 kb
Host smart-cbe56a08-7559-416d-bcc0-48b067bb3738
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925032529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3925032529
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1609134748
Short name T468
Test name
Test status
Simulation time 567022618 ps
CPU time 3.66 seconds
Started Jun 07 07:10:33 PM PDT 24
Finished Jun 07 07:10:40 PM PDT 24
Peak memory 218332 kb
Host smart-c2ffc34c-1120-4b32-8d53-ed36024f14cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609134748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1609134748
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.554601886
Short name T17
Test name
Test status
Simulation time 286186505 ps
CPU time 2.67 seconds
Started Jun 07 07:10:33 PM PDT 24
Finished Jun 07 07:10:39 PM PDT 24
Peak memory 214372 kb
Host smart-400e1323-a9b8-4a8c-a60c-adda40480689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554601886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.554601886
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.515867550
Short name T607
Test name
Test status
Simulation time 72475424 ps
CPU time 2.36 seconds
Started Jun 07 07:10:31 PM PDT 24
Finished Jun 07 07:10:37 PM PDT 24
Peak memory 222300 kb
Host smart-6d184630-9069-405b-bf6c-723378306dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515867550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.515867550
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2543777684
Short name T338
Test name
Test status
Simulation time 64739889 ps
CPU time 3.19 seconds
Started Jun 07 07:10:31 PM PDT 24
Finished Jun 07 07:10:38 PM PDT 24
Peak memory 214304 kb
Host smart-d6cb850a-c37c-4876-ad21-51d660dddad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543777684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2543777684
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2902561533
Short name T752
Test name
Test status
Simulation time 249200648 ps
CPU time 3.53 seconds
Started Jun 07 07:10:29 PM PDT 24
Finished Jun 07 07:10:37 PM PDT 24
Peak memory 207128 kb
Host smart-4b0b67d5-b8cf-4f87-99a7-0e08a1c1349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902561533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2902561533
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.4025115380
Short name T598
Test name
Test status
Simulation time 209008528 ps
CPU time 6.02 seconds
Started Jun 07 07:10:29 PM PDT 24
Finished Jun 07 07:10:39 PM PDT 24
Peak memory 208684 kb
Host smart-ffcea1e6-64ed-46f7-8c36-b41881b61d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025115380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.4025115380
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1870187237
Short name T501
Test name
Test status
Simulation time 3916604092 ps
CPU time 48.34 seconds
Started Jun 07 07:10:32 PM PDT 24
Finished Jun 07 07:11:24 PM PDT 24
Peak memory 209084 kb
Host smart-09263875-2e2e-4372-be71-8bcb3831bbb4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870187237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1870187237
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.118920171
Short name T43
Test name
Test status
Simulation time 53382620 ps
CPU time 2.81 seconds
Started Jun 07 07:10:35 PM PDT 24
Finished Jun 07 07:10:42 PM PDT 24
Peak memory 208612 kb
Host smart-f9ff63a2-d47e-4131-a0f9-c2d18f0f7bb0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118920171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.118920171
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.829527727
Short name T504
Test name
Test status
Simulation time 292150681 ps
CPU time 2.81 seconds
Started Jun 07 07:10:31 PM PDT 24
Finished Jun 07 07:10:37 PM PDT 24
Peak memory 208896 kb
Host smart-842596ad-6454-46ae-9f07-2347d3c8c2f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829527727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.829527727
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2794373627
Short name T354
Test name
Test status
Simulation time 103357615 ps
CPU time 4.08 seconds
Started Jun 07 07:10:33 PM PDT 24
Finished Jun 07 07:10:41 PM PDT 24
Peak memory 217780 kb
Host smart-d303d209-eceb-4b93-be44-c83c9a9bcef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794373627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2794373627
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3111191149
Short name T758
Test name
Test status
Simulation time 346994762 ps
CPU time 4.42 seconds
Started Jun 07 07:10:34 PM PDT 24
Finished Jun 07 07:10:42 PM PDT 24
Peak memory 206724 kb
Host smart-99c4287b-00dd-44db-9aef-9f99a495f117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111191149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3111191149
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3288844156
Short name T643
Test name
Test status
Simulation time 1399544292 ps
CPU time 20.22 seconds
Started Jun 07 07:10:41 PM PDT 24
Finished Jun 07 07:11:08 PM PDT 24
Peak memory 215232 kb
Host smart-8c963b65-1d56-4df5-b8e6-19a83883a00d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288844156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3288844156
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2229067808
Short name T185
Test name
Test status
Simulation time 419825495 ps
CPU time 13.5 seconds
Started Jun 07 07:10:41 PM PDT 24
Finished Jun 07 07:11:01 PM PDT 24
Peak memory 222604 kb
Host smart-0161c97b-1801-4a69-88c4-d716e931376e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229067808 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2229067808
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2152272874
Short name T908
Test name
Test status
Simulation time 203433477 ps
CPU time 5 seconds
Started Jun 07 07:10:34 PM PDT 24
Finished Jun 07 07:10:43 PM PDT 24
Peak memory 214348 kb
Host smart-026da5e9-7be1-48ab-bc19-41df6bddcdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152272874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2152272874
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.518591573
Short name T164
Test name
Test status
Simulation time 206829617 ps
CPU time 1.56 seconds
Started Jun 07 07:10:38 PM PDT 24
Finished Jun 07 07:10:45 PM PDT 24
Peak memory 210180 kb
Host smart-420d913a-16b5-422d-b210-5509981968b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518591573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.518591573
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2031694211
Short name T815
Test name
Test status
Simulation time 8831265 ps
CPU time 0.81 seconds
Started Jun 07 07:10:38 PM PDT 24
Finished Jun 07 07:10:45 PM PDT 24
Peak memory 205908 kb
Host smart-f00ea413-d047-4878-920c-0e34bc4c0031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031694211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2031694211
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3075524039
Short name T371
Test name
Test status
Simulation time 800868327 ps
CPU time 10.63 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:55 PM PDT 24
Peak memory 214336 kb
Host smart-6485cc17-afbb-4b64-85d9-e7151f494846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075524039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3075524039
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2890430893
Short name T27
Test name
Test status
Simulation time 98910737 ps
CPU time 3.61 seconds
Started Jun 07 07:10:37 PM PDT 24
Finished Jun 07 07:10:46 PM PDT 24
Peak memory 209264 kb
Host smart-31beb798-7395-4751-9860-64bdc6c09178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890430893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2890430893
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.817738556
Short name T463
Test name
Test status
Simulation time 33283805 ps
CPU time 2.3 seconds
Started Jun 07 07:10:43 PM PDT 24
Finished Jun 07 07:10:53 PM PDT 24
Peak memory 208340 kb
Host smart-3822ba0f-d5f2-445b-b189-bef9ffa69805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817738556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.817738556
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2459793054
Short name T274
Test name
Test status
Simulation time 27011681 ps
CPU time 1.86 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:46 PM PDT 24
Peak memory 214364 kb
Host smart-4e8c7afe-42ff-431b-9c48-27d5ddcf1d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459793054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2459793054
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3800441422
Short name T34
Test name
Test status
Simulation time 175331646 ps
CPU time 3.82 seconds
Started Jun 07 07:10:37 PM PDT 24
Finished Jun 07 07:10:46 PM PDT 24
Peak memory 214340 kb
Host smart-fc3781ea-39fb-42f9-bafe-4e23f362327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800441422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3800441422
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2193224188
Short name T220
Test name
Test status
Simulation time 136280735 ps
CPU time 3.22 seconds
Started Jun 07 07:10:36 PM PDT 24
Finished Jun 07 07:10:44 PM PDT 24
Peak memory 209880 kb
Host smart-2369027c-8aae-4000-932e-9486e67192bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193224188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2193224188
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2825949423
Short name T797
Test name
Test status
Simulation time 585630359 ps
CPU time 7.44 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:53 PM PDT 24
Peak memory 214316 kb
Host smart-e08ceaf8-9750-475b-8629-b59bd9d105c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825949423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2825949423
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2484615416
Short name T427
Test name
Test status
Simulation time 36936285 ps
CPU time 2.12 seconds
Started Jun 07 07:10:37 PM PDT 24
Finished Jun 07 07:10:44 PM PDT 24
Peak memory 206092 kb
Host smart-2b3a97da-9387-4ee1-b970-9c849b30eda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484615416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2484615416
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.779382615
Short name T204
Test name
Test status
Simulation time 843693079 ps
CPU time 4.64 seconds
Started Jun 07 07:10:37 PM PDT 24
Finished Jun 07 07:10:47 PM PDT 24
Peak memory 206960 kb
Host smart-732335b0-4288-4fce-a810-f33214fdd0a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779382615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.779382615
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.4066944214
Short name T207
Test name
Test status
Simulation time 46035718 ps
CPU time 2.48 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:49 PM PDT 24
Peak memory 208832 kb
Host smart-28d9d8ed-aac7-4908-bfb6-3f28bf5936c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066944214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4066944214
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.553445671
Short name T446
Test name
Test status
Simulation time 136809408 ps
CPU time 2.29 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:48 PM PDT 24
Peak memory 208620 kb
Host smart-0a0c61b4-d40f-4354-8651-e17de1224ff3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553445671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.553445671
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.4094161345
Short name T33
Test name
Test status
Simulation time 389176237 ps
CPU time 4.34 seconds
Started Jun 07 07:10:37 PM PDT 24
Finished Jun 07 07:10:46 PM PDT 24
Peak memory 209444 kb
Host smart-f7218773-2e6f-498a-b770-39c15ab3f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094161345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.4094161345
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1814241662
Short name T431
Test name
Test status
Simulation time 166914707 ps
CPU time 2.57 seconds
Started Jun 07 07:10:43 PM PDT 24
Finished Jun 07 07:10:53 PM PDT 24
Peak memory 206788 kb
Host smart-573e1f19-29fd-4467-acf9-36146a089cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814241662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1814241662
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3665886737
Short name T197
Test name
Test status
Simulation time 48756328607 ps
CPU time 55.6 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:11:40 PM PDT 24
Peak memory 219680 kb
Host smart-c03b24f7-3bb4-432c-88d7-0796d970765f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665886737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3665886737
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2876458000
Short name T745
Test name
Test status
Simulation time 114594432 ps
CPU time 5.4 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:50 PM PDT 24
Peak memory 222628 kb
Host smart-d437c6e8-5f8e-47dd-a43a-713ea7c66b6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876458000 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2876458000
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2522262748
Short name T106
Test name
Test status
Simulation time 740273704 ps
CPU time 18.83 seconds
Started Jun 07 07:10:36 PM PDT 24
Finished Jun 07 07:10:59 PM PDT 24
Peak memory 209276 kb
Host smart-f8f87fd9-1ec0-44b9-b041-d0a3463db6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522262748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2522262748
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2849930190
Short name T519
Test name
Test status
Simulation time 366582108 ps
CPU time 1.41 seconds
Started Jun 07 07:10:38 PM PDT 24
Finished Jun 07 07:10:45 PM PDT 24
Peak memory 208736 kb
Host smart-f82c83e2-c7e6-40c0-9df1-95e5e10cf8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849930190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2849930190
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1166855029
Short name T892
Test name
Test status
Simulation time 64843982 ps
CPU time 0.81 seconds
Started Jun 07 07:10:35 PM PDT 24
Finished Jun 07 07:10:40 PM PDT 24
Peak memory 205968 kb
Host smart-52cef656-d7bd-421f-9092-62f24c33656d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166855029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1166855029
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3614001201
Short name T240
Test name
Test status
Simulation time 58308370 ps
CPU time 3.96 seconds
Started Jun 07 07:10:37 PM PDT 24
Finished Jun 07 07:10:45 PM PDT 24
Peak memory 214344 kb
Host smart-18861a6d-0171-48cf-a0f0-fffb0e98caf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614001201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3614001201
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3586523530
Short name T816
Test name
Test status
Simulation time 325136283 ps
CPU time 4.09 seconds
Started Jun 07 07:10:41 PM PDT 24
Finished Jun 07 07:10:51 PM PDT 24
Peak memory 221584 kb
Host smart-a91a8e5c-d800-461e-956f-a50b65ff8c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586523530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3586523530
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.58046617
Short name T293
Test name
Test status
Simulation time 157053156 ps
CPU time 6.53 seconds
Started Jun 07 07:10:36 PM PDT 24
Finished Jun 07 07:10:47 PM PDT 24
Peak memory 214364 kb
Host smart-9644e596-4c5d-41cc-b3f9-9b552b15739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58046617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.58046617
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2792034820
Short name T601
Test name
Test status
Simulation time 54132415 ps
CPU time 2.3 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:47 PM PDT 24
Peak memory 214440 kb
Host smart-828057ea-c0bd-48ff-aa1d-fcfe0c3ff77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792034820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2792034820
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3337657276
Short name T273
Test name
Test status
Simulation time 560599024 ps
CPU time 3.83 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:50 PM PDT 24
Peak memory 222456 kb
Host smart-b9f01900-3a67-4ca5-8b62-7a589d9ca39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337657276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3337657276
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3300846845
Short name T299
Test name
Test status
Simulation time 1681846838 ps
CPU time 4.12 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:51 PM PDT 24
Peak memory 214344 kb
Host smart-b1c591d2-ef3d-43c1-ba23-9901c7d2a4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300846845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3300846845
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2886077342
Short name T626
Test name
Test status
Simulation time 4815597110 ps
CPU time 47.65 seconds
Started Jun 07 07:10:42 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 210520 kb
Host smart-a3a004ff-e6cd-4049-ae4e-c64bcc99b151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886077342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2886077342
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1197421503
Short name T858
Test name
Test status
Simulation time 114476438 ps
CPU time 2.9 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:49 PM PDT 24
Peak memory 206892 kb
Host smart-627d0ce9-3109-4380-959b-748254efb402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197421503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1197421503
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2288939926
Short name T771
Test name
Test status
Simulation time 18475547 ps
CPU time 1.73 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:47 PM PDT 24
Peak memory 207036 kb
Host smart-31e73237-f7e3-421a-b34b-f6f42928170f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288939926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2288939926
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3153158883
Short name T381
Test name
Test status
Simulation time 77564671 ps
CPU time 1.82 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:48 PM PDT 24
Peak memory 206940 kb
Host smart-732c47e6-cc65-4767-afca-6434759e49dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153158883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3153158883
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3166738084
Short name T770
Test name
Test status
Simulation time 245470146 ps
CPU time 3.01 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:49 PM PDT 24
Peak memory 207124 kb
Host smart-33806801-b06a-4aee-b0fb-b5ce0133a7a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166738084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3166738084
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2393819288
Short name T861
Test name
Test status
Simulation time 132339041 ps
CPU time 2.08 seconds
Started Jun 07 07:10:38 PM PDT 24
Finished Jun 07 07:10:45 PM PDT 24
Peak memory 208628 kb
Host smart-a926b693-f79c-4098-8ed3-2929be7571ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393819288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2393819288
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.823185180
Short name T826
Test name
Test status
Simulation time 190533136 ps
CPU time 3.16 seconds
Started Jun 07 07:10:38 PM PDT 24
Finished Jun 07 07:10:47 PM PDT 24
Peak memory 208560 kb
Host smart-dff73dd6-1e92-4833-998a-bfcdd4b69f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823185180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.823185180
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2849922055
Short name T187
Test name
Test status
Simulation time 649098804 ps
CPU time 8.74 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:53 PM PDT 24
Peak memory 222556 kb
Host smart-d8a69d81-02d8-493d-a19f-8447d916979c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849922055 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2849922055
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2616395879
Short name T734
Test name
Test status
Simulation time 93645447 ps
CPU time 4.35 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:50 PM PDT 24
Peak memory 218248 kb
Host smart-c550911f-b535-4b25-b552-63801bb30607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616395879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2616395879
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1325899852
Short name T15
Test name
Test status
Simulation time 18085713 ps
CPU time 0.81 seconds
Started Jun 07 07:10:37 PM PDT 24
Finished Jun 07 07:10:43 PM PDT 24
Peak memory 205948 kb
Host smart-05eeed55-11f9-4e84-b22b-355ca3d40db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325899852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1325899852
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2281420751
Short name T785
Test name
Test status
Simulation time 1071982297 ps
CPU time 10.5 seconds
Started Jun 07 07:10:48 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 214780 kb
Host smart-b9f942ea-b10b-4d1a-8a2c-adca86656e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281420751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2281420751
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3565063387
Short name T37
Test name
Test status
Simulation time 71299700 ps
CPU time 2.66 seconds
Started Jun 07 07:10:38 PM PDT 24
Finished Jun 07 07:10:45 PM PDT 24
Peak memory 209276 kb
Host smart-c9bf849c-4585-498d-a636-51e688cdd7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565063387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3565063387
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3842979613
Short name T3
Test name
Test status
Simulation time 76768165 ps
CPU time 1.76 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:47 PM PDT 24
Peak memory 218352 kb
Host smart-6697e159-8305-43df-a1f0-c82d4c7a9c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842979613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3842979613
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.4168207728
Short name T256
Test name
Test status
Simulation time 51769591 ps
CPU time 2.04 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:10:57 PM PDT 24
Peak memory 213884 kb
Host smart-c54b9536-d722-45c8-b0d1-baf89f948b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168207728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4168207728
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.898104544
Short name T442
Test name
Test status
Simulation time 516850724 ps
CPU time 3.17 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:48 PM PDT 24
Peak memory 214288 kb
Host smart-b1b5dd25-2090-4dcd-852d-5dd6425ef596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898104544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.898104544
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3167754754
Short name T331
Test name
Test status
Simulation time 200143439 ps
CPU time 3.46 seconds
Started Jun 07 07:10:38 PM PDT 24
Finished Jun 07 07:10:47 PM PDT 24
Peak memory 208044 kb
Host smart-a2264940-50d6-4742-8c91-c3b362007d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167754754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3167754754
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1401493747
Short name T512
Test name
Test status
Simulation time 135903120 ps
CPU time 5.32 seconds
Started Jun 07 07:10:44 PM PDT 24
Finished Jun 07 07:10:56 PM PDT 24
Peak memory 214308 kb
Host smart-fbcda127-e0d6-45bb-b17f-f6b6259f2b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401493747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1401493747
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.65190676
Short name T402
Test name
Test status
Simulation time 38579038 ps
CPU time 1.77 seconds
Started Jun 07 07:10:44 PM PDT 24
Finished Jun 07 07:10:53 PM PDT 24
Peak memory 206092 kb
Host smart-63f438a5-b442-486f-a113-318574f6c3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65190676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.65190676
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2535028031
Short name T565
Test name
Test status
Simulation time 56483837 ps
CPU time 2.42 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:49 PM PDT 24
Peak memory 207468 kb
Host smart-20be870a-b36f-469c-adc0-4294f51cf226
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535028031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2535028031
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1482205923
Short name T732
Test name
Test status
Simulation time 183125557 ps
CPU time 4.13 seconds
Started Jun 07 07:10:38 PM PDT 24
Finished Jun 07 07:10:47 PM PDT 24
Peak memory 207024 kb
Host smart-49f683ea-f5bf-4919-8204-b8571fca99fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482205923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1482205923
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.517689252
Short name T394
Test name
Test status
Simulation time 1285217409 ps
CPU time 8.3 seconds
Started Jun 07 07:10:44 PM PDT 24
Finished Jun 07 07:10:59 PM PDT 24
Peak memory 208440 kb
Host smart-4c786d41-6b62-407e-94fe-2776cd313029
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517689252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.517689252
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.4080854523
Short name T648
Test name
Test status
Simulation time 188194996 ps
CPU time 3.44 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:50 PM PDT 24
Peak memory 208572 kb
Host smart-d5cc4e38-c2af-4fae-a648-27bed9d3ead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080854523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4080854523
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.936238683
Short name T454
Test name
Test status
Simulation time 180662249 ps
CPU time 2.42 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:49 PM PDT 24
Peak memory 208256 kb
Host smart-5f2b96e7-f4a4-4bd0-8739-975cfde4c3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936238683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.936238683
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3582183847
Short name T196
Test name
Test status
Simulation time 989316193 ps
CPU time 35.92 seconds
Started Jun 07 07:10:38 PM PDT 24
Finished Jun 07 07:11:19 PM PDT 24
Peak memory 222436 kb
Host smart-92e0d9cc-2f58-4b2d-bf0d-72a93bde03e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582183847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3582183847
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3749538738
Short name T798
Test name
Test status
Simulation time 79913410 ps
CPU time 3.81 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:49 PM PDT 24
Peak memory 207444 kb
Host smart-0f0f0b6d-06d8-4f97-af1d-a6cee7369403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749538738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3749538738
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.612020609
Short name T656
Test name
Test status
Simulation time 149753204 ps
CPU time 1.68 seconds
Started Jun 07 07:10:37 PM PDT 24
Finished Jun 07 07:10:44 PM PDT 24
Peak memory 209940 kb
Host smart-0fdc6760-a5ec-4abe-a17e-150ed69b9bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612020609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.612020609
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.148468099
Short name T518
Test name
Test status
Simulation time 19274650 ps
CPU time 0.81 seconds
Started Jun 07 07:10:46 PM PDT 24
Finished Jun 07 07:10:55 PM PDT 24
Peak memory 205844 kb
Host smart-2d4aad60-0786-431a-ab27-1d69f48ef593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148468099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.148468099
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1257219858
Short name T750
Test name
Test status
Simulation time 3386954676 ps
CPU time 89.79 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:12:16 PM PDT 24
Peak memory 215352 kb
Host smart-d30d1555-ee83-4877-b1b8-58718b07c6cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257219858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1257219858
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.905809087
Short name T690
Test name
Test status
Simulation time 197697427 ps
CPU time 2.84 seconds
Started Jun 07 07:10:42 PM PDT 24
Finished Jun 07 07:10:51 PM PDT 24
Peak memory 206928 kb
Host smart-7f2d3a78-f79c-46ed-a21b-3b677a7af75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905809087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.905809087
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1294621079
Short name T85
Test name
Test status
Simulation time 62262467 ps
CPU time 2.48 seconds
Started Jun 07 07:10:41 PM PDT 24
Finished Jun 07 07:10:50 PM PDT 24
Peak memory 214376 kb
Host smart-d18cf992-e1df-42e7-85b5-63e439c749d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294621079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1294621079
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.947807319
Short name T724
Test name
Test status
Simulation time 87585615 ps
CPU time 1.96 seconds
Started Jun 07 07:10:42 PM PDT 24
Finished Jun 07 07:10:51 PM PDT 24
Peak memory 214280 kb
Host smart-ed9b405d-bb66-46b6-80d4-a890da64af12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947807319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.947807319
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.840429858
Short name T451
Test name
Test status
Simulation time 62279038 ps
CPU time 2.63 seconds
Started Jun 07 07:10:42 PM PDT 24
Finished Jun 07 07:10:51 PM PDT 24
Peak memory 209876 kb
Host smart-76b139c5-8745-4741-a494-fc103ec25fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840429858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.840429858
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3622121179
Short name T698
Test name
Test status
Simulation time 573862236 ps
CPU time 5.88 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:51 PM PDT 24
Peak memory 208744 kb
Host smart-42843acb-f88f-47cf-9cc6-3de3eda90a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622121179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3622121179
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2352035242
Short name T537
Test name
Test status
Simulation time 1809084670 ps
CPU time 18.04 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:11:04 PM PDT 24
Peak memory 207788 kb
Host smart-dc7b7b9b-6490-4828-9459-0484589e0135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352035242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2352035242
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.377392301
Short name T392
Test name
Test status
Simulation time 3212287062 ps
CPU time 29.34 seconds
Started Jun 07 07:10:44 PM PDT 24
Finished Jun 07 07:11:21 PM PDT 24
Peak memory 208476 kb
Host smart-5a7a6b41-cab7-477f-93c1-46f994c3a05d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377392301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.377392301
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3357536214
Short name T670
Test name
Test status
Simulation time 215959817 ps
CPU time 4.57 seconds
Started Jun 07 07:10:41 PM PDT 24
Finished Jun 07 07:10:52 PM PDT 24
Peak memory 208872 kb
Host smart-9aaac079-d7dc-4d87-b149-5f1a4e4b2f68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357536214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3357536214
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3565975003
Short name T592
Test name
Test status
Simulation time 114903285 ps
CPU time 4.87 seconds
Started Jun 07 07:10:42 PM PDT 24
Finished Jun 07 07:10:54 PM PDT 24
Peak memory 208076 kb
Host smart-9704a6b4-a8ef-4b19-b34d-85442ba8439a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565975003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3565975003
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1993607627
Short name T552
Test name
Test status
Simulation time 39336336 ps
CPU time 2.25 seconds
Started Jun 07 07:10:42 PM PDT 24
Finished Jun 07 07:10:51 PM PDT 24
Peak memory 218256 kb
Host smart-d8383796-2c74-49bd-8644-2ccfec33b6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993607627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1993607627
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2490838525
Short name T429
Test name
Test status
Simulation time 1666332664 ps
CPU time 4.66 seconds
Started Jun 07 07:10:39 PM PDT 24
Finished Jun 07 07:10:50 PM PDT 24
Peak memory 208216 kb
Host smart-7f1c8260-6ca0-4729-8215-129b232bebaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490838525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2490838525
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2173012519
Short name T810
Test name
Test status
Simulation time 1053545171 ps
CPU time 35.31 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:11:31 PM PDT 24
Peak memory 214812 kb
Host smart-3131cd27-cc76-4237-a8d4-8159be299399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173012519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2173012519
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3920962992
Short name T125
Test name
Test status
Simulation time 1851430333 ps
CPU time 10.79 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 222256 kb
Host smart-79966ec1-fec4-4896-b2c7-e74e6f6a1284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920962992 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3920962992
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.4068558189
Short name T728
Test name
Test status
Simulation time 1477119743 ps
CPU time 5.02 seconds
Started Jun 07 07:10:42 PM PDT 24
Finished Jun 07 07:10:53 PM PDT 24
Peak memory 222416 kb
Host smart-c4ef5a72-dc2d-4fe2-a14d-4811eabe0272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068558189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.4068558189
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2489936450
Short name T834
Test name
Test status
Simulation time 1508379027 ps
CPU time 7.44 seconds
Started Jun 07 07:10:44 PM PDT 24
Finished Jun 07 07:10:58 PM PDT 24
Peak memory 210588 kb
Host smart-189a4a4d-d167-4fbb-8eeb-3f2cff33e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489936450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2489936450
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.269933882
Short name T508
Test name
Test status
Simulation time 17730927 ps
CPU time 0.86 seconds
Started Jun 07 07:08:36 PM PDT 24
Finished Jun 07 07:08:39 PM PDT 24
Peak memory 205924 kb
Host smart-fbda5d05-415b-4287-b62c-de8331854cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269933882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.269933882
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.4126582502
Short name T840
Test name
Test status
Simulation time 87654580 ps
CPU time 2.17 seconds
Started Jun 07 07:08:25 PM PDT 24
Finished Jun 07 07:08:29 PM PDT 24
Peak memory 214340 kb
Host smart-2c92067e-1ce4-45f9-89dc-79a8480cfb34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126582502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.4126582502
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3014323357
Short name T686
Test name
Test status
Simulation time 278741483 ps
CPU time 2.72 seconds
Started Jun 07 07:08:26 PM PDT 24
Finished Jun 07 07:08:31 PM PDT 24
Peak memory 214336 kb
Host smart-a58cab6a-facd-489e-88ac-1495678384fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014323357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3014323357
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1070939156
Short name T869
Test name
Test status
Simulation time 101102029 ps
CPU time 3.81 seconds
Started Jun 07 07:08:25 PM PDT 24
Finished Jun 07 07:08:30 PM PDT 24
Peak memory 208180 kb
Host smart-85f4a0ea-da6e-465d-b980-71e5e838d127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070939156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1070939156
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.406831290
Short name T230
Test name
Test status
Simulation time 117492589 ps
CPU time 5.21 seconds
Started Jun 07 07:08:25 PM PDT 24
Finished Jun 07 07:08:32 PM PDT 24
Peak memory 214340 kb
Host smart-26a91b58-28e2-4f0a-90d2-83a9353bbc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406831290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.406831290
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1704555751
Short name T814
Test name
Test status
Simulation time 36759977 ps
CPU time 2.93 seconds
Started Jun 07 07:08:26 PM PDT 24
Finished Jun 07 07:08:31 PM PDT 24
Peak memory 222360 kb
Host smart-f9178cf3-a668-456d-bf8a-b637ffe8118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704555751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1704555751
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3638676683
Short name T54
Test name
Test status
Simulation time 78229328 ps
CPU time 3.89 seconds
Started Jun 07 07:08:26 PM PDT 24
Finished Jun 07 07:08:32 PM PDT 24
Peak memory 218540 kb
Host smart-72ac7229-adde-40fc-a597-539ca167dec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638676683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3638676683
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3049142827
Short name T285
Test name
Test status
Simulation time 1260398908 ps
CPU time 5.88 seconds
Started Jun 07 07:08:25 PM PDT 24
Finished Jun 07 07:08:33 PM PDT 24
Peak memory 214344 kb
Host smart-53f983a1-fbe0-4b00-bfb3-45e9d4b9f5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049142827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3049142827
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3731044528
Short name T9
Test name
Test status
Simulation time 760009435 ps
CPU time 6.58 seconds
Started Jun 07 07:08:32 PM PDT 24
Finished Jun 07 07:08:42 PM PDT 24
Peak memory 230576 kb
Host smart-128940c0-37a9-43c1-9d9f-7959b49ff0d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731044528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3731044528
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2514901245
Short name T817
Test name
Test status
Simulation time 70355680 ps
CPU time 2.03 seconds
Started Jun 07 07:08:24 PM PDT 24
Finished Jun 07 07:08:28 PM PDT 24
Peak memory 206808 kb
Host smart-8f175e04-555a-4f18-b750-441a4a861cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514901245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2514901245
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.949952384
Short name T667
Test name
Test status
Simulation time 241767687 ps
CPU time 2.71 seconds
Started Jun 07 07:08:27 PM PDT 24
Finished Jun 07 07:08:33 PM PDT 24
Peak memory 208116 kb
Host smart-cb7c00df-9627-40a0-a540-ebb9f71be6fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949952384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.949952384
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4248682070
Short name T650
Test name
Test status
Simulation time 1321905818 ps
CPU time 15.51 seconds
Started Jun 07 07:08:26 PM PDT 24
Finished Jun 07 07:08:44 PM PDT 24
Peak memory 208168 kb
Host smart-b51c4ebe-f7ce-4c19-8f88-46afbe8ae53d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248682070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4248682070
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2904213771
Short name T526
Test name
Test status
Simulation time 385458035 ps
CPU time 6.03 seconds
Started Jun 07 07:08:26 PM PDT 24
Finished Jun 07 07:08:34 PM PDT 24
Peak memory 208136 kb
Host smart-1a7a9b10-48f4-46d2-8393-dadd62dd5880
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904213771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2904213771
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3882935304
Short name T473
Test name
Test status
Simulation time 509862814 ps
CPU time 1.92 seconds
Started Jun 07 07:08:25 PM PDT 24
Finished Jun 07 07:08:29 PM PDT 24
Peak memory 207788 kb
Host smart-e897e92d-98f7-453d-b5dd-da0620359896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882935304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3882935304
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.58840770
Short name T377
Test name
Test status
Simulation time 544868535 ps
CPU time 7.54 seconds
Started Jun 07 07:08:24 PM PDT 24
Finished Jun 07 07:08:33 PM PDT 24
Peak memory 206700 kb
Host smart-564a5ce1-e889-480c-a9f8-8de3ffecae97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58840770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.58840770
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1749123884
Short name T270
Test name
Test status
Simulation time 559363635 ps
CPU time 4.31 seconds
Started Jun 07 07:08:27 PM PDT 24
Finished Jun 07 07:08:35 PM PDT 24
Peak memory 208024 kb
Host smart-3c7d0a68-8fcb-4984-9450-211d24b9d218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749123884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1749123884
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.4183689692
Short name T551
Test name
Test status
Simulation time 88398613 ps
CPU time 1.57 seconds
Started Jun 07 07:08:25 PM PDT 24
Finished Jun 07 07:08:28 PM PDT 24
Peak memory 210156 kb
Host smart-8cef1b06-338c-460d-b15c-27464bd4f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183689692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.4183689692
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.946686552
Short name T414
Test name
Test status
Simulation time 14754985 ps
CPU time 0.79 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:10:55 PM PDT 24
Peak memory 205948 kb
Host smart-1d70c21a-7cb9-45e8-a230-d23ae2cb20ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946686552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.946686552
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3777401107
Short name T370
Test name
Test status
Simulation time 650320596 ps
CPU time 6.67 seconds
Started Jun 07 07:10:51 PM PDT 24
Finished Jun 07 07:11:05 PM PDT 24
Peak memory 214400 kb
Host smart-53820457-b1aa-4a5d-90e3-695a1ecdfb86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777401107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3777401107
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1593514566
Short name T780
Test name
Test status
Simulation time 237082556 ps
CPU time 5.29 seconds
Started Jun 07 07:10:52 PM PDT 24
Finished Jun 07 07:11:05 PM PDT 24
Peak memory 222676 kb
Host smart-f7a437e2-24f8-459d-b72a-626148c5418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593514566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1593514566
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.110779808
Short name T905
Test name
Test status
Simulation time 180168478 ps
CPU time 5.36 seconds
Started Jun 07 07:10:52 PM PDT 24
Finished Jun 07 07:11:05 PM PDT 24
Peak memory 218540 kb
Host smart-9d445019-251e-4d16-af76-f44e000bb095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110779808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.110779808
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1409249063
Short name T97
Test name
Test status
Simulation time 491257677 ps
CPU time 4.91 seconds
Started Jun 07 07:10:52 PM PDT 24
Finished Jun 07 07:11:04 PM PDT 24
Peak memory 222420 kb
Host smart-038772bc-855b-4d42-abc0-ffe8facba5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409249063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1409249063
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3725066699
Short name T725
Test name
Test status
Simulation time 272762486 ps
CPU time 3.14 seconds
Started Jun 07 07:10:46 PM PDT 24
Finished Jun 07 07:10:57 PM PDT 24
Peak memory 214364 kb
Host smart-03f9598f-793c-4f65-b19f-3abb267ce679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725066699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3725066699
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2662012542
Short name T318
Test name
Test status
Simulation time 80544761 ps
CPU time 4.28 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:10:59 PM PDT 24
Peak memory 209052 kb
Host smart-07597f52-43b8-4149-98aa-387e1bf0657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662012542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2662012542
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2220024717
Short name T837
Test name
Test status
Simulation time 270226466 ps
CPU time 7.45 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:09 PM PDT 24
Peak memory 214168 kb
Host smart-9aa63e97-476d-4516-9034-664dd78f5442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220024717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2220024717
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3793361666
Short name T702
Test name
Test status
Simulation time 131265745 ps
CPU time 4.1 seconds
Started Jun 07 07:10:41 PM PDT 24
Finished Jun 07 07:10:52 PM PDT 24
Peak memory 208648 kb
Host smart-1db9472a-e000-4294-a741-278c6f7ff88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793361666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3793361666
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1617445128
Short name T731
Test name
Test status
Simulation time 101660399 ps
CPU time 3 seconds
Started Jun 07 07:10:41 PM PDT 24
Finished Jun 07 07:10:51 PM PDT 24
Peak memory 208872 kb
Host smart-dc7648a9-84b2-41ad-9060-00786d2cc743
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617445128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1617445128
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.393917194
Short name T546
Test name
Test status
Simulation time 207543547 ps
CPU time 3.33 seconds
Started Jun 07 07:10:43 PM PDT 24
Finished Jun 07 07:10:54 PM PDT 24
Peak memory 208748 kb
Host smart-a842a358-d8a2-4816-8589-9af83770a075
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393917194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.393917194
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3902387270
Short name T811
Test name
Test status
Simulation time 100689554 ps
CPU time 2.17 seconds
Started Jun 07 07:10:53 PM PDT 24
Finished Jun 07 07:11:03 PM PDT 24
Peak memory 207028 kb
Host smart-e157d15f-796d-44db-8e2e-9790d056a19f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902387270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3902387270
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.4003447965
Short name T435
Test name
Test status
Simulation time 161590057 ps
CPU time 3.71 seconds
Started Jun 07 07:10:51 PM PDT 24
Finished Jun 07 07:11:03 PM PDT 24
Peak memory 207440 kb
Host smart-7496920e-0adb-4b92-92fa-634790811168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003447965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4003447965
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2356900282
Short name T400
Test name
Test status
Simulation time 205236141 ps
CPU time 4.6 seconds
Started Jun 07 07:10:40 PM PDT 24
Finished Jun 07 07:10:51 PM PDT 24
Peak memory 207888 kb
Host smart-7d00ed91-839b-4def-acd7-baac9cea1ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356900282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2356900282
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.528163870
Short name T696
Test name
Test status
Simulation time 1630598541 ps
CPU time 5.82 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:11:01 PM PDT 24
Peak memory 215872 kb
Host smart-687d87a5-8ec8-4f34-af83-e23a43a1088f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528163870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.528163870
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.945823840
Short name T511
Test name
Test status
Simulation time 1309273827 ps
CPU time 9.12 seconds
Started Jun 07 07:10:49 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 218268 kb
Host smart-15ca6384-cc8f-4332-beb8-d56fd52ba7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945823840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.945823840
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2082706163
Short name T700
Test name
Test status
Simulation time 35652138 ps
CPU time 2.09 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:04 PM PDT 24
Peak memory 209924 kb
Host smart-4f49b80b-939e-425b-b003-0a93d92742b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082706163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2082706163
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3847899996
Short name T831
Test name
Test status
Simulation time 31959800 ps
CPU time 1.03 seconds
Started Jun 07 07:10:52 PM PDT 24
Finished Jun 07 07:11:01 PM PDT 24
Peak memory 206128 kb
Host smart-e98d4a03-e7ad-4f93-b27d-8325bbd7011b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847899996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3847899996
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.782295388
Short name T372
Test name
Test status
Simulation time 303660753 ps
CPU time 4.39 seconds
Started Jun 07 07:10:52 PM PDT 24
Finished Jun 07 07:11:04 PM PDT 24
Peak memory 214312 kb
Host smart-a8142148-6ed1-4ea7-be09-c118cc0e1546
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=782295388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.782295388
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1433788618
Short name T503
Test name
Test status
Simulation time 726932289 ps
CPU time 3.12 seconds
Started Jun 07 07:10:51 PM PDT 24
Finished Jun 07 07:11:02 PM PDT 24
Peak memory 222756 kb
Host smart-1fa9f8fe-86da-4360-b2ab-8e091784694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433788618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1433788618
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.136395829
Short name T75
Test name
Test status
Simulation time 21293410 ps
CPU time 1.84 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:04 PM PDT 24
Peak memory 214408 kb
Host smart-93c6e566-7b37-46eb-acb4-13fd826191d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136395829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.136395829
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.91378926
Short name T21
Test name
Test status
Simulation time 128921878 ps
CPU time 4.57 seconds
Started Jun 07 07:10:46 PM PDT 24
Finished Jun 07 07:10:59 PM PDT 24
Peak memory 220816 kb
Host smart-127c33d1-1295-4e9c-8ceb-cfd6fe2b7758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91378926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.91378926
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3479323475
Short name T664
Test name
Test status
Simulation time 1857568408 ps
CPU time 3.96 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:10:58 PM PDT 24
Peak memory 214280 kb
Host smart-f9751b91-b37a-403d-a87a-364a331a9dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479323475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3479323475
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1592803750
Short name T848
Test name
Test status
Simulation time 40931669 ps
CPU time 2.44 seconds
Started Jun 07 07:10:48 PM PDT 24
Finished Jun 07 07:10:58 PM PDT 24
Peak memory 210076 kb
Host smart-b935aeb4-4d20-437d-a20b-e2f73c470240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592803750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1592803750
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2938573177
Short name T81
Test name
Test status
Simulation time 494716097 ps
CPU time 4.96 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:10:59 PM PDT 24
Peak memory 208620 kb
Host smart-c9cff150-af78-4d80-9521-12411c265787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938573177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2938573177
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3812624591
Short name T449
Test name
Test status
Simulation time 60745006 ps
CPU time 2.35 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:10:57 PM PDT 24
Peak memory 207276 kb
Host smart-a0fd7d01-c133-44e2-b676-c4d440469c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812624591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3812624591
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1369507799
Short name T440
Test name
Test status
Simulation time 54769407 ps
CPU time 2.71 seconds
Started Jun 07 07:10:49 PM PDT 24
Finished Jun 07 07:11:00 PM PDT 24
Peak memory 208756 kb
Host smart-5189e993-a377-4a87-9c17-4324174eb04e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369507799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1369507799
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2399958659
Short name T599
Test name
Test status
Simulation time 1823993458 ps
CPU time 38.29 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:11:33 PM PDT 24
Peak memory 208440 kb
Host smart-1f0d06dd-0a81-4b7a-8cc7-b24356991e34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399958659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2399958659
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2265181673
Short name T746
Test name
Test status
Simulation time 32624541 ps
CPU time 2.26 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:10:58 PM PDT 24
Peak memory 206992 kb
Host smart-8a6514cf-8f8a-43a9-9203-bad2f6ec3f89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265181673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2265181673
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2169442227
Short name T748
Test name
Test status
Simulation time 373983330 ps
CPU time 2.88 seconds
Started Jun 07 07:10:44 PM PDT 24
Finished Jun 07 07:10:54 PM PDT 24
Peak memory 214340 kb
Host smart-bc49230e-18de-4e4d-a3eb-766585253b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169442227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2169442227
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1715556457
Short name T497
Test name
Test status
Simulation time 58260686 ps
CPU time 2.41 seconds
Started Jun 07 07:10:53 PM PDT 24
Finished Jun 07 07:11:03 PM PDT 24
Peak memory 207416 kb
Host smart-5f3f5b32-9d4c-4243-a5fd-73ce1a4ef6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715556457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1715556457
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1033584726
Short name T222
Test name
Test status
Simulation time 1253608902 ps
CPU time 32.59 seconds
Started Jun 07 07:10:49 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 215820 kb
Host smart-99df2836-b875-4a76-a644-87476efa7a87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033584726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1033584726
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2214720829
Short name T216
Test name
Test status
Simulation time 349974918 ps
CPU time 7.65 seconds
Started Jun 07 07:10:49 PM PDT 24
Finished Jun 07 07:11:04 PM PDT 24
Peak memory 222580 kb
Host smart-d281e892-a47f-4482-b6b7-ff9d841303d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214720829 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2214720829
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3547180633
Short name T298
Test name
Test status
Simulation time 65337201 ps
CPU time 3.6 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:10:59 PM PDT 24
Peak memory 208752 kb
Host smart-b77e1a5f-4046-4b51-85d1-50681449067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547180633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3547180633
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1196886375
Short name T609
Test name
Test status
Simulation time 94615043 ps
CPU time 2.39 seconds
Started Jun 07 07:10:48 PM PDT 24
Finished Jun 07 07:10:59 PM PDT 24
Peak memory 210360 kb
Host smart-c15e61e1-daf4-4114-850e-8f9284b3f903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196886375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1196886375
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1290321029
Short name T474
Test name
Test status
Simulation time 16378979 ps
CPU time 0.78 seconds
Started Jun 07 07:10:53 PM PDT 24
Finished Jun 07 07:11:02 PM PDT 24
Peak memory 205968 kb
Host smart-184db22d-be38-45ba-b709-e8fc08ab9448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290321029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1290321029
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3946481680
Short name T494
Test name
Test status
Simulation time 68986848 ps
CPU time 2.08 seconds
Started Jun 07 07:10:57 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 216068 kb
Host smart-2c651a83-7edf-4407-b0aa-b264332ae27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946481680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3946481680
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1194491607
Short name T640
Test name
Test status
Simulation time 404760416 ps
CPU time 8.54 seconds
Started Jun 07 07:10:52 PM PDT 24
Finished Jun 07 07:11:08 PM PDT 24
Peak memory 208000 kb
Host smart-677b1093-0bb8-4c31-ac9f-2c8e16367c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194491607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1194491607
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1209096021
Short name T322
Test name
Test status
Simulation time 29087292 ps
CPU time 1.87 seconds
Started Jun 07 07:10:48 PM PDT 24
Finished Jun 07 07:10:58 PM PDT 24
Peak memory 214268 kb
Host smart-e15fb5d8-c3c5-4b6a-9c7e-e5799af6fb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209096021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1209096021
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2252221395
Short name T219
Test name
Test status
Simulation time 74616908 ps
CPU time 3.32 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:10:59 PM PDT 24
Peak memory 209012 kb
Host smart-45c43d18-0344-4007-b729-0ab14a14db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252221395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2252221395
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2366933744
Short name T576
Test name
Test status
Simulation time 482071937 ps
CPU time 7.24 seconds
Started Jun 07 07:10:50 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 214348 kb
Host smart-02a56d01-8a47-4c77-8ea9-4a9e59f3f525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366933744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2366933744
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3145915848
Short name T266
Test name
Test status
Simulation time 169806183 ps
CPU time 3.61 seconds
Started Jun 07 07:10:48 PM PDT 24
Finished Jun 07 07:11:00 PM PDT 24
Peak memory 208584 kb
Host smart-8e890080-4a20-4e2d-a6a5-04e4799c297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145915848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3145915848
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3339729270
Short name T620
Test name
Test status
Simulation time 264363341 ps
CPU time 3.17 seconds
Started Jun 07 07:10:50 PM PDT 24
Finished Jun 07 07:11:01 PM PDT 24
Peak memory 206956 kb
Host smart-c10c31be-9e43-4c4b-a8d4-35d6c6499a4e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339729270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3339729270
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2774495963
Short name T303
Test name
Test status
Simulation time 266420819 ps
CPU time 3.14 seconds
Started Jun 07 07:10:50 PM PDT 24
Finished Jun 07 07:11:01 PM PDT 24
Peak memory 206944 kb
Host smart-d3a62bd7-ebe7-4032-8c6d-3776ac3ffede
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774495963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2774495963
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3849864088
Short name T488
Test name
Test status
Simulation time 52616691 ps
CPU time 2.21 seconds
Started Jun 07 07:10:47 PM PDT 24
Finished Jun 07 07:10:57 PM PDT 24
Peak memory 208588 kb
Host smart-fce2a9e4-f386-4354-a6fc-a0ea168b8b00
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849864088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3849864088
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.933256939
Short name T846
Test name
Test status
Simulation time 41354376 ps
CPU time 1.83 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:04 PM PDT 24
Peak memory 207076 kb
Host smart-5224901f-de7f-4a53-bf65-281cc26aff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933256939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.933256939
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3720728773
Short name T376
Test name
Test status
Simulation time 463052837 ps
CPU time 3.04 seconds
Started Jun 07 07:10:46 PM PDT 24
Finished Jun 07 07:10:57 PM PDT 24
Peak memory 206816 kb
Host smart-7d67280f-6226-4686-87d5-8d3ff9b73011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720728773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3720728773
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1012866866
Short name T792
Test name
Test status
Simulation time 9309720826 ps
CPU time 63.28 seconds
Started Jun 07 07:10:53 PM PDT 24
Finished Jun 07 07:12:05 PM PDT 24
Peak memory 216396 kb
Host smart-0dc9f24d-f4c0-4524-b12d-52f802e0fd16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012866866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1012866866
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3053067536
Short name T904
Test name
Test status
Simulation time 78629167 ps
CPU time 4.28 seconds
Started Jun 07 07:10:46 PM PDT 24
Finished Jun 07 07:10:57 PM PDT 24
Peak memory 207556 kb
Host smart-2f7357f5-75ae-4dec-940f-066b3f1aa7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053067536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3053067536
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2389118966
Short name T183
Test name
Test status
Simulation time 341373614 ps
CPU time 1.42 seconds
Started Jun 07 07:10:55 PM PDT 24
Finished Jun 07 07:11:04 PM PDT 24
Peak memory 209948 kb
Host smart-3804bca7-87d6-4a80-993a-05bf700c824f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389118966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2389118966
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1758886959
Short name T558
Test name
Test status
Simulation time 29640847 ps
CPU time 0.79 seconds
Started Jun 07 07:10:58 PM PDT 24
Finished Jun 07 07:11:07 PM PDT 24
Peak memory 205912 kb
Host smart-140b4bf8-f246-4421-a934-7579a89b7c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758886959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1758886959
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3369214262
Short name T28
Test name
Test status
Simulation time 268975635 ps
CPU time 3.98 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 208756 kb
Host smart-a4573d1d-04d5-4299-b599-cf82c4949199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369214262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3369214262
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1982519089
Short name T830
Test name
Test status
Simulation time 59024926 ps
CPU time 1.48 seconds
Started Jun 07 07:10:56 PM PDT 24
Finished Jun 07 07:11:05 PM PDT 24
Peak memory 207012 kb
Host smart-48e7fe4a-4044-4c38-8b1c-a0aca9973c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982519089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1982519089
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3415513681
Short name T524
Test name
Test status
Simulation time 27763567 ps
CPU time 1.84 seconds
Started Jun 07 07:10:59 PM PDT 24
Finished Jun 07 07:11:08 PM PDT 24
Peak memory 214340 kb
Host smart-1b83155a-cbbc-4b4e-b134-ec29961ee2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415513681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3415513681
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3872905769
Short name T590
Test name
Test status
Simulation time 70833343 ps
CPU time 2.91 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:05 PM PDT 24
Peak memory 214280 kb
Host smart-8e6b5a2b-6460-47c1-acf7-020a01d7f583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872905769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3872905769
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3676207635
Short name T62
Test name
Test status
Simulation time 73654902 ps
CPU time 3.6 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:15 PM PDT 24
Peak memory 210104 kb
Host smart-db5e1058-deb9-4994-a2cc-a5326052839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676207635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3676207635
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.897522561
Short name T311
Test name
Test status
Simulation time 41773288 ps
CPU time 3.1 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:05 PM PDT 24
Peak memory 222488 kb
Host smart-a1865b36-bc45-4874-9cc5-9b91461a51af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897522561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.897522561
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2476517428
Short name T691
Test name
Test status
Simulation time 412055074 ps
CPU time 2.74 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:13 PM PDT 24
Peak memory 206880 kb
Host smart-349c684b-7d7a-4e07-bc16-a36d99dadeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476517428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2476517428
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2922863275
Short name T320
Test name
Test status
Simulation time 53829711 ps
CPU time 2.96 seconds
Started Jun 07 07:10:55 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 206980 kb
Host smart-65733efc-41df-4ddd-83c3-c90914f85c9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922863275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2922863275
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2148876960
Short name T83
Test name
Test status
Simulation time 6039306421 ps
CPU time 58.15 seconds
Started Jun 07 07:10:56 PM PDT 24
Finished Jun 07 07:12:02 PM PDT 24
Peak memory 208928 kb
Host smart-93bbeead-3d07-4d9d-83d2-04f38d9d81d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148876960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2148876960
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2693573065
Short name T539
Test name
Test status
Simulation time 41913296 ps
CPU time 2.25 seconds
Started Jun 07 07:10:56 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 207044 kb
Host smart-a18608d5-2363-49a5-8070-e3ead1d7709f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693573065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2693573065
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3376014615
Short name T333
Test name
Test status
Simulation time 3545508885 ps
CPU time 12.18 seconds
Started Jun 07 07:10:59 PM PDT 24
Finished Jun 07 07:11:19 PM PDT 24
Peak memory 221004 kb
Host smart-8a8947d1-e29a-4cf2-912c-e0ee4c4fc9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376014615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3376014615
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2912004867
Short name T404
Test name
Test status
Simulation time 61502710 ps
CPU time 2.59 seconds
Started Jun 07 07:10:55 PM PDT 24
Finished Jun 07 07:11:05 PM PDT 24
Peak memory 208200 kb
Host smart-1811ef08-6eee-4f98-b378-2cf379953aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912004867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2912004867
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2083822871
Short name T893
Test name
Test status
Simulation time 1396340385 ps
CPU time 15.56 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:17 PM PDT 24
Peak memory 222444 kb
Host smart-2728523a-7876-4881-9836-a429729a5f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083822871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2083822871
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3396870000
Short name T722
Test name
Test status
Simulation time 429681712 ps
CPU time 8.27 seconds
Started Jun 07 07:10:53 PM PDT 24
Finished Jun 07 07:11:09 PM PDT 24
Peak memory 222584 kb
Host smart-55a64fb8-4d4a-495d-90d2-ce0a27224a4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396870000 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3396870000
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3263607226
Short name T567
Test name
Test status
Simulation time 1959524465 ps
CPU time 5.2 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:07 PM PDT 24
Peak memory 218388 kb
Host smart-99b92488-88c4-42fd-8528-3cb7ccdadd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263607226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3263607226
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.4070503071
Short name T672
Test name
Test status
Simulation time 84394870 ps
CPU time 2.45 seconds
Started Jun 07 07:11:00 PM PDT 24
Finished Jun 07 07:11:10 PM PDT 24
Peak memory 210904 kb
Host smart-4eac1e09-cadc-40c5-a830-f714bdda3600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070503071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.4070503071
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.748735911
Short name T897
Test name
Test status
Simulation time 16847450 ps
CPU time 0.87 seconds
Started Jun 07 07:10:59 PM PDT 24
Finished Jun 07 07:11:07 PM PDT 24
Peak memory 206132 kb
Host smart-2c23a8b8-dd90-41de-9d5d-6899988d5ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748735911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.748735911
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.501908177
Short name T368
Test name
Test status
Simulation time 256486091 ps
CPU time 4.93 seconds
Started Jun 07 07:10:56 PM PDT 24
Finished Jun 07 07:11:09 PM PDT 24
Peak memory 215728 kb
Host smart-abc47ad3-a2c8-4f31-ae78-e734ac3d90f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501908177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.501908177
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.4251173971
Short name T213
Test name
Test status
Simulation time 1457981433 ps
CPU time 46.64 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:58 PM PDT 24
Peak memory 214652 kb
Host smart-b4e30fb1-7a53-419e-9c09-a0f01e8f02da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251173971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.4251173971
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3316671401
Short name T571
Test name
Test status
Simulation time 29225001 ps
CPU time 1.63 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:11 PM PDT 24
Peak memory 206988 kb
Host smart-612cac4d-138a-4f81-8331-1ef3b44c676c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316671401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3316671401
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1632504476
Short name T50
Test name
Test status
Simulation time 38347425 ps
CPU time 2.31 seconds
Started Jun 07 07:11:01 PM PDT 24
Finished Jun 07 07:11:12 PM PDT 24
Peak memory 214360 kb
Host smart-b1d5b300-47dc-4320-a8a2-8e6261516ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632504476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1632504476
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3804159007
Short name T665
Test name
Test status
Simulation time 69185300 ps
CPU time 2.93 seconds
Started Jun 07 07:10:55 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 220584 kb
Host smart-10905368-d4ff-414e-a870-4d97a3d36166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804159007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3804159007
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3018611872
Short name T227
Test name
Test status
Simulation time 385916617 ps
CPU time 5.06 seconds
Started Jun 07 07:10:55 PM PDT 24
Finished Jun 07 07:11:07 PM PDT 24
Peak memory 210312 kb
Host smart-30bb8618-7d89-4209-8b3e-ab4cac85e73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018611872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3018611872
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2138970588
Short name T683
Test name
Test status
Simulation time 191720683 ps
CPU time 3.5 seconds
Started Jun 07 07:10:56 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 208288 kb
Host smart-5f69469e-cc00-42ab-9342-9f4c0e0e69a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138970588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2138970588
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.462940681
Short name T515
Test name
Test status
Simulation time 67157885 ps
CPU time 3.5 seconds
Started Jun 07 07:10:56 PM PDT 24
Finished Jun 07 07:11:06 PM PDT 24
Peak memory 208300 kb
Host smart-18a122e7-cf41-45cf-a64f-b2ef04d2b595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462940681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.462940681
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.780805710
Short name T637
Test name
Test status
Simulation time 308879799 ps
CPU time 3.07 seconds
Started Jun 07 07:10:57 PM PDT 24
Finished Jun 07 07:11:08 PM PDT 24
Peak memory 208476 kb
Host smart-cef14d5d-f839-4189-a5b6-24e9ad8d1238
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780805710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.780805710
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2135502783
Short name T570
Test name
Test status
Simulation time 22681166 ps
CPU time 1.82 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:13 PM PDT 24
Peak memory 207064 kb
Host smart-11f075c8-b3fe-41fa-a153-2b9b6bf9f77d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135502783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2135502783
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3922036870
Short name T389
Test name
Test status
Simulation time 9426883904 ps
CPU time 16.36 seconds
Started Jun 07 07:11:01 PM PDT 24
Finished Jun 07 07:11:25 PM PDT 24
Peak memory 208372 kb
Host smart-e6d7016e-c413-4aed-a720-1cf3eb549f0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922036870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3922036870
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3057486024
Short name T249
Test name
Test status
Simulation time 499726461 ps
CPU time 14.97 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:17 PM PDT 24
Peak memory 220452 kb
Host smart-82fcf659-7d82-4c1e-ab0b-2c8e2504caf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057486024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3057486024
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.577523379
Short name T829
Test name
Test status
Simulation time 607018418 ps
CPU time 2.72 seconds
Started Jun 07 07:10:53 PM PDT 24
Finished Jun 07 07:11:03 PM PDT 24
Peak memory 206952 kb
Host smart-7bb29a92-d01a-4194-8248-4fec539366c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577523379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.577523379
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.4246785317
Short name T291
Test name
Test status
Simulation time 800604728 ps
CPU time 9.73 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:12 PM PDT 24
Peak memory 219708 kb
Host smart-4610d549-3633-4e17-8ca7-fd0b51dbc0f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246785317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4246785317
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1181260040
Short name T316
Test name
Test status
Simulation time 49363894 ps
CPU time 3.27 seconds
Started Jun 07 07:10:54 PM PDT 24
Finished Jun 07 07:11:05 PM PDT 24
Peak memory 214352 kb
Host smart-30332930-d50c-44e3-bef8-4483f5af671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181260040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1181260040
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3860256128
Short name T871
Test name
Test status
Simulation time 82673223 ps
CPU time 2.35 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:12 PM PDT 24
Peak memory 209836 kb
Host smart-6d8a5ff7-bca8-4209-9104-a9d67e7bf600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860256128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3860256128
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2313472074
Short name T562
Test name
Test status
Simulation time 47485445 ps
CPU time 0.81 seconds
Started Jun 07 07:11:04 PM PDT 24
Finished Jun 07 07:11:14 PM PDT 24
Peak memory 205956 kb
Host smart-b024aa10-8ce0-4aac-b242-17a6fd6c9e79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313472074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2313472074
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.842172258
Short name T282
Test name
Test status
Simulation time 190544137 ps
CPU time 3.61 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:14 PM PDT 24
Peak memory 215556 kb
Host smart-9af94679-7984-43ea-9c83-66400ff39f17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842172258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.842172258
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1558739056
Short name T465
Test name
Test status
Simulation time 372911181 ps
CPU time 3.96 seconds
Started Jun 07 07:11:05 PM PDT 24
Finished Jun 07 07:11:18 PM PDT 24
Peak memory 214564 kb
Host smart-41ec195f-c7d6-4db2-b867-9e07620cf758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558739056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1558739056
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2530574365
Short name T673
Test name
Test status
Simulation time 63627545 ps
CPU time 2.5 seconds
Started Jun 07 07:11:05 PM PDT 24
Finished Jun 07 07:11:16 PM PDT 24
Peak memory 208700 kb
Host smart-3c7b0ae5-5fee-410d-a4d3-5181bea3a97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530574365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2530574365
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1909078615
Short name T244
Test name
Test status
Simulation time 66793434 ps
CPU time 2.48 seconds
Started Jun 07 07:11:06 PM PDT 24
Finished Jun 07 07:11:17 PM PDT 24
Peak memory 214328 kb
Host smart-9860897b-059b-49db-b54d-59160256e9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909078615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1909078615
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3488155396
Short name T782
Test name
Test status
Simulation time 45883513 ps
CPU time 2.49 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:14 PM PDT 24
Peak memory 214468 kb
Host smart-e60b4d23-281f-494a-bb48-8f05f0e6977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488155396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3488155396
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_random.3882745799
Short name T677
Test name
Test status
Simulation time 216173919 ps
CPU time 3.35 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:14 PM PDT 24
Peak memory 207644 kb
Host smart-2e09087f-b137-4a2e-8aef-ca913b410973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882745799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3882745799
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1770739531
Short name T821
Test name
Test status
Simulation time 160317796 ps
CPU time 2.54 seconds
Started Jun 07 07:10:55 PM PDT 24
Finished Jun 07 07:11:05 PM PDT 24
Peak memory 206972 kb
Host smart-a2898030-0b72-4bb6-801c-2557c617dcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770739531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1770739531
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.4216280266
Short name T203
Test name
Test status
Simulation time 675886030 ps
CPU time 5.92 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:18 PM PDT 24
Peak memory 208900 kb
Host smart-bcc036f1-12ba-40a2-8042-b67e91b46150
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216280266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.4216280266
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2874545705
Short name T448
Test name
Test status
Simulation time 35129272 ps
CPU time 2.57 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:12 PM PDT 24
Peak memory 208680 kb
Host smart-46dd4c65-1ef9-4d20-99a6-e3ff2d248b9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874545705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2874545705
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1985649479
Short name T682
Test name
Test status
Simulation time 252795601 ps
CPU time 4.78 seconds
Started Jun 07 07:11:06 PM PDT 24
Finished Jun 07 07:11:20 PM PDT 24
Peak memory 208152 kb
Host smart-327dedfb-379f-4e56-ac09-ef89f8fbee35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985649479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1985649479
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.95471900
Short name T639
Test name
Test status
Simulation time 245069941 ps
CPU time 3.54 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:15 PM PDT 24
Peak memory 209852 kb
Host smart-40806b89-1001-4c86-a719-e22605dade1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95471900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.95471900
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.4134692279
Short name T847
Test name
Test status
Simulation time 23936026 ps
CPU time 1.59 seconds
Started Jun 07 07:10:58 PM PDT 24
Finished Jun 07 07:11:07 PM PDT 24
Peak memory 206920 kb
Host smart-ffc4f1ab-9224-4376-a15e-71484825e6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134692279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.4134692279
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2858972915
Short name T80
Test name
Test status
Simulation time 200698425 ps
CPU time 14.26 seconds
Started Jun 07 07:11:08 PM PDT 24
Finished Jun 07 07:11:32 PM PDT 24
Peak memory 222596 kb
Host smart-d5545d69-7d1c-45ef-a3ee-e8767a055929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858972915 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2858972915
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.141855927
Short name T246
Test name
Test status
Simulation time 229675827 ps
CPU time 7.61 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:17 PM PDT 24
Peak memory 214360 kb
Host smart-66a39988-b5cf-4f59-9bc6-96fd1227fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141855927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.141855927
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2757423398
Short name T762
Test name
Test status
Simulation time 669604810 ps
CPU time 4.17 seconds
Started Jun 07 07:11:05 PM PDT 24
Finished Jun 07 07:11:18 PM PDT 24
Peak memory 210956 kb
Host smart-d8546988-df74-4093-ad3d-abba88a23f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757423398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2757423398
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.965678516
Short name T102
Test name
Test status
Simulation time 56018148 ps
CPU time 0.8 seconds
Started Jun 07 07:11:06 PM PDT 24
Finished Jun 07 07:11:16 PM PDT 24
Peak memory 205832 kb
Host smart-7368e913-0508-48b0-b9f9-5cdecc6d7ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965678516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.965678516
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.49945677
Short name T22
Test name
Test status
Simulation time 43368243 ps
CPU time 2.25 seconds
Started Jun 07 07:11:08 PM PDT 24
Finished Jun 07 07:11:20 PM PDT 24
Peak memory 214568 kb
Host smart-94a3bd47-d53f-4bad-8679-e6058752ad7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49945677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.49945677
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2507757533
Short name T713
Test name
Test status
Simulation time 631010679 ps
CPU time 3.92 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:16 PM PDT 24
Peak memory 208280 kb
Host smart-78597d4e-36f3-455f-8237-a63a17f25c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507757533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2507757533
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2035284106
Short name T641
Test name
Test status
Simulation time 93239826 ps
CPU time 2.76 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:15 PM PDT 24
Peak memory 214336 kb
Host smart-7e4c21f3-d241-495c-a369-087c81d0bcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035284106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2035284106
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.183442813
Short name T721
Test name
Test status
Simulation time 71184478 ps
CPU time 2.45 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:14 PM PDT 24
Peak memory 214324 kb
Host smart-9155f604-086f-49da-8d23-1cbdbb1427d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183442813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.183442813
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3984385060
Short name T719
Test name
Test status
Simulation time 391864215 ps
CPU time 2.65 seconds
Started Jun 07 07:11:01 PM PDT 24
Finished Jun 07 07:11:12 PM PDT 24
Peak memory 214352 kb
Host smart-220fe386-255d-4aa4-80a6-e7605c2d4146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984385060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3984385060
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1128721583
Short name T341
Test name
Test status
Simulation time 117422433 ps
CPU time 3.66 seconds
Started Jun 07 07:11:06 PM PDT 24
Finished Jun 07 07:11:19 PM PDT 24
Peak memory 207320 kb
Host smart-ff5516bb-9d2e-4b1d-ac1e-9dddeaabf259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128721583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1128721583
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1383706821
Short name T387
Test name
Test status
Simulation time 180264600 ps
CPU time 2.64 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:15 PM PDT 24
Peak memory 206132 kb
Host smart-47dbed87-afaf-4477-bc35-48ab0269047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383706821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1383706821
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1242421968
Short name T608
Test name
Test status
Simulation time 110863734 ps
CPU time 3.13 seconds
Started Jun 07 07:11:04 PM PDT 24
Finished Jun 07 07:11:15 PM PDT 24
Peak memory 208956 kb
Host smart-6de0cfaf-0c81-485c-aa56-d2f87b0ed2e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242421968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1242421968
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3573145480
Short name T808
Test name
Test status
Simulation time 186037508 ps
CPU time 2.94 seconds
Started Jun 07 07:11:04 PM PDT 24
Finished Jun 07 07:11:16 PM PDT 24
Peak memory 207448 kb
Host smart-9ed271cc-7cdd-4cce-bdd6-57a63973027f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573145480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3573145480
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.382792548
Short name T580
Test name
Test status
Simulation time 104882727 ps
CPU time 2.74 seconds
Started Jun 07 07:11:07 PM PDT 24
Finished Jun 07 07:11:19 PM PDT 24
Peak memory 207476 kb
Host smart-dd5b2951-f003-400d-aef7-e720743eae6e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382792548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.382792548
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1948336534
Short name T699
Test name
Test status
Simulation time 106838145 ps
CPU time 2.29 seconds
Started Jun 07 07:11:08 PM PDT 24
Finished Jun 07 07:11:20 PM PDT 24
Peak memory 208932 kb
Host smart-cebb30de-932e-4abe-a342-529d02ce571a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948336534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1948336534
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2871890293
Short name T799
Test name
Test status
Simulation time 83795264 ps
CPU time 3.22 seconds
Started Jun 07 07:11:01 PM PDT 24
Finished Jun 07 07:11:13 PM PDT 24
Peak memory 208788 kb
Host smart-3915a5fe-77ff-4eca-a97d-9ecc203ac189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871890293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2871890293
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3570972165
Short name T794
Test name
Test status
Simulation time 2200054201 ps
CPU time 52.39 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:12:03 PM PDT 24
Peak memory 215348 kb
Host smart-c901b6d9-9f82-444c-a4f3-1bca38f0d55c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570972165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3570972165
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3714968100
Short name T229
Test name
Test status
Simulation time 505294309 ps
CPU time 21.47 seconds
Started Jun 07 07:11:04 PM PDT 24
Finished Jun 07 07:11:33 PM PDT 24
Peak memory 222600 kb
Host smart-cb0193f9-df0a-45e9-a898-797b81bde407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714968100 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3714968100
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.755911780
Short name T516
Test name
Test status
Simulation time 675921912 ps
CPU time 7.38 seconds
Started Jun 07 07:11:04 PM PDT 24
Finished Jun 07 07:11:20 PM PDT 24
Peak memory 209164 kb
Host smart-2dd1c432-ce3b-4442-9b45-0a07f0f620f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755911780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.755911780
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3333391092
Short name T169
Test name
Test status
Simulation time 635498106 ps
CPU time 3.59 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:14 PM PDT 24
Peak memory 210468 kb
Host smart-a4fca67c-d89e-490d-802d-d2a4f32d8f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333391092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3333391092
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.684355049
Short name T585
Test name
Test status
Simulation time 12951395 ps
CPU time 0.75 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:21 PM PDT 24
Peak memory 205964 kb
Host smart-2fbc3846-b12c-46c3-a163-020aae733d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684355049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.684355049
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2862611595
Short name T373
Test name
Test status
Simulation time 72079912 ps
CPU time 4.24 seconds
Started Jun 07 07:11:07 PM PDT 24
Finished Jun 07 07:11:21 PM PDT 24
Peak memory 215536 kb
Host smart-694d2485-5afc-455b-928a-f95d86adbf52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862611595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2862611595
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1525519659
Short name T594
Test name
Test status
Simulation time 135146236 ps
CPU time 4.95 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:24 PM PDT 24
Peak memory 222716 kb
Host smart-00934709-1d90-47d6-9a7f-0caa2848da89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525519659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1525519659
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3642771535
Short name T796
Test name
Test status
Simulation time 141166896 ps
CPU time 3.36 seconds
Started Jun 07 07:11:01 PM PDT 24
Finished Jun 07 07:11:13 PM PDT 24
Peak memory 214336 kb
Host smart-f765c9fa-0895-4c9b-9383-41fac487898f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642771535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3642771535
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.4097147116
Short name T306
Test name
Test status
Simulation time 158275093 ps
CPU time 3.86 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:16 PM PDT 24
Peak memory 214744 kb
Host smart-34e890e8-0d6a-4e40-94f6-65e78cf15858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097147116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.4097147116
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1448469077
Short name T89
Test name
Test status
Simulation time 46455644 ps
CPU time 3.36 seconds
Started Jun 07 07:11:05 PM PDT 24
Finished Jun 07 07:11:18 PM PDT 24
Peak memory 222296 kb
Host smart-03040203-70b2-4d12-aced-19fe5574aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448469077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1448469077
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2128026489
Short name T717
Test name
Test status
Simulation time 493687088 ps
CPU time 2.02 seconds
Started Jun 07 07:11:06 PM PDT 24
Finished Jun 07 07:11:16 PM PDT 24
Peak memory 214368 kb
Host smart-866c644b-4e74-426c-aaba-d7479c3d1692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128026489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2128026489
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1357956768
Short name T574
Test name
Test status
Simulation time 94868904 ps
CPU time 3.68 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:16 PM PDT 24
Peak memory 208116 kb
Host smart-a9478631-8413-490b-a71f-3a33a54d6e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357956768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1357956768
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3775523467
Short name T864
Test name
Test status
Simulation time 40574760 ps
CPU time 2.26 seconds
Started Jun 07 07:11:06 PM PDT 24
Finished Jun 07 07:11:17 PM PDT 24
Peak memory 207008 kb
Host smart-9f94ed9a-94b3-473a-90be-1c05bb05d572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775523467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3775523467
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1709213896
Short name T718
Test name
Test status
Simulation time 519176052 ps
CPU time 3.46 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:14 PM PDT 24
Peak memory 206920 kb
Host smart-0d1fd6c1-ece2-49ef-be01-e352e444b635
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709213896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1709213896
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3279105664
Short name T669
Test name
Test status
Simulation time 28150167 ps
CPU time 2.06 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:14 PM PDT 24
Peak memory 208736 kb
Host smart-a99669d7-981e-4634-9e47-05064a82abaa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279105664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3279105664
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.851819630
Short name T357
Test name
Test status
Simulation time 253389441 ps
CPU time 5.52 seconds
Started Jun 07 07:11:03 PM PDT 24
Finished Jun 07 07:11:17 PM PDT 24
Peak memory 208624 kb
Host smart-c65ca2f5-8acf-41af-ac15-c3d0873e932f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851819630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.851819630
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.393080227
Short name T312
Test name
Test status
Simulation time 242185844 ps
CPU time 3.08 seconds
Started Jun 07 07:11:12 PM PDT 24
Finished Jun 07 07:11:26 PM PDT 24
Peak memory 209868 kb
Host smart-e0d4228f-a239-4df9-9ba4-5c2f39b14964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393080227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.393080227
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3820788543
Short name T545
Test name
Test status
Simulation time 1561043714 ps
CPU time 5.2 seconds
Started Jun 07 07:11:02 PM PDT 24
Finished Jun 07 07:11:15 PM PDT 24
Peak memory 208596 kb
Host smart-ecedb875-838e-4f2b-a8d3-dc4bfa96739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820788543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3820788543
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.153663989
Short name T326
Test name
Test status
Simulation time 343406309 ps
CPU time 14.56 seconds
Started Jun 07 07:11:14 PM PDT 24
Finished Jun 07 07:11:39 PM PDT 24
Peak memory 222676 kb
Host smart-bbb29a8e-a848-4a59-8ec1-6d5a574ed851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153663989 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.153663989
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.380842549
Short name T202
Test name
Test status
Simulation time 551396075 ps
CPU time 11.2 seconds
Started Jun 07 07:11:04 PM PDT 24
Finished Jun 07 07:11:24 PM PDT 24
Peak memory 222412 kb
Host smart-d683f0a0-1228-49e3-871b-ade241bc1836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380842549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.380842549
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.935459874
Short name T178
Test name
Test status
Simulation time 915227911 ps
CPU time 13.84 seconds
Started Jun 07 07:11:11 PM PDT 24
Finished Jun 07 07:11:35 PM PDT 24
Peak memory 210588 kb
Host smart-129901a2-a4d6-4b87-a151-f50a82ff0b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935459874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.935459874
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.826496197
Short name T549
Test name
Test status
Simulation time 51896920 ps
CPU time 0.78 seconds
Started Jun 07 07:11:12 PM PDT 24
Finished Jun 07 07:11:24 PM PDT 24
Peak memory 205980 kb
Host smart-1179722c-1467-4f03-9ccb-f0c5e1662a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826496197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.826496197
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2556984328
Short name T802
Test name
Test status
Simulation time 162363374 ps
CPU time 3.5 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:23 PM PDT 24
Peak memory 214352 kb
Host smart-333c7886-fbbd-4533-bbb9-d0d2f65d8150
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2556984328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2556984328
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3643213163
Short name T24
Test name
Test status
Simulation time 86481899 ps
CPU time 3.22 seconds
Started Jun 07 07:11:14 PM PDT 24
Finished Jun 07 07:11:27 PM PDT 24
Peak memory 208924 kb
Host smart-67dca0c3-0411-40ce-8880-54fedd6d998d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643213163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3643213163
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3430790605
Short name T779
Test name
Test status
Simulation time 136406432 ps
CPU time 4.92 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:25 PM PDT 24
Peak memory 209296 kb
Host smart-c546e7b0-79f7-4633-9bc9-14eb3713d85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430790605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3430790605
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2925960975
Short name T346
Test name
Test status
Simulation time 272326462 ps
CPU time 4.39 seconds
Started Jun 07 07:11:12 PM PDT 24
Finished Jun 07 07:11:27 PM PDT 24
Peak memory 220520 kb
Host smart-555ed452-1bfe-41a4-99c4-dcd853021bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925960975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2925960975
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.102922668
Short name T342
Test name
Test status
Simulation time 117027704 ps
CPU time 3.5 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:23 PM PDT 24
Peak memory 208384 kb
Host smart-14024763-36e3-4410-8bb6-a7af3cb1dc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102922668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.102922668
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3277455582
Short name T879
Test name
Test status
Simulation time 1811357871 ps
CPU time 4.58 seconds
Started Jun 07 07:11:08 PM PDT 24
Finished Jun 07 07:11:22 PM PDT 24
Peak memory 207024 kb
Host smart-d888c3cd-ee55-43c0-901b-efe2bd7bfd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277455582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3277455582
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4201326310
Short name T649
Test name
Test status
Simulation time 48800857 ps
CPU time 1.96 seconds
Started Jun 07 07:11:11 PM PDT 24
Finished Jun 07 07:11:23 PM PDT 24
Peak memory 208352 kb
Host smart-899cc8d3-552f-471f-8e10-f3ef381cf537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201326310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4201326310
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1217925675
Short name T195
Test name
Test status
Simulation time 3985683024 ps
CPU time 41.75 seconds
Started Jun 07 07:11:12 PM PDT 24
Finished Jun 07 07:12:04 PM PDT 24
Peak memory 208144 kb
Host smart-5e595def-7714-427a-a8c8-847b5221fe0d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217925675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1217925675
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.294763294
Short name T575
Test name
Test status
Simulation time 21579794 ps
CPU time 1.85 seconds
Started Jun 07 07:11:11 PM PDT 24
Finished Jun 07 07:11:23 PM PDT 24
Peak memory 206772 kb
Host smart-df8cfda6-f12a-4c2e-af33-99da4e9a51b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294763294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.294763294
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1040663737
Short name T288
Test name
Test status
Simulation time 887711234 ps
CPU time 32.66 seconds
Started Jun 07 07:11:09 PM PDT 24
Finished Jun 07 07:11:51 PM PDT 24
Peak memory 208900 kb
Host smart-1e339bd1-4b54-4812-bf77-6ae6d9b33a3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040663737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1040663737
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.453659863
Short name T877
Test name
Test status
Simulation time 85055410 ps
CPU time 3.44 seconds
Started Jun 07 07:11:12 PM PDT 24
Finished Jun 07 07:11:25 PM PDT 24
Peak memory 222412 kb
Host smart-4585952b-2716-4624-a5a0-5da397df6479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453659863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.453659863
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3096584662
Short name T384
Test name
Test status
Simulation time 235091704 ps
CPU time 2.71 seconds
Started Jun 07 07:11:11 PM PDT 24
Finished Jun 07 07:11:24 PM PDT 24
Peak memory 206880 kb
Host smart-72a22d48-461e-4536-b47e-7b6f7e73ec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096584662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3096584662
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2719591488
Short name T668
Test name
Test status
Simulation time 1140763884 ps
CPU time 11.13 seconds
Started Jun 07 07:11:15 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 218884 kb
Host smart-d1775c9d-9128-4b2c-817e-13933e54c5f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719591488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2719591488
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2592272485
Short name T265
Test name
Test status
Simulation time 914511516 ps
CPU time 15.32 seconds
Started Jun 07 07:11:13 PM PDT 24
Finished Jun 07 07:11:39 PM PDT 24
Peak memory 222652 kb
Host smart-734ce968-ebb1-4df0-a578-9c9b4519fde6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592272485 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2592272485
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.816773458
Short name T485
Test name
Test status
Simulation time 175187840 ps
CPU time 3.02 seconds
Started Jun 07 07:11:13 PM PDT 24
Finished Jun 07 07:11:27 PM PDT 24
Peak memory 207456 kb
Host smart-60a6e35b-ecd5-465e-9eb7-40903a2c23ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816773458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.816773458
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1639911695
Short name T349
Test name
Test status
Simulation time 40044297 ps
CPU time 1.82 seconds
Started Jun 07 07:11:12 PM PDT 24
Finished Jun 07 07:11:25 PM PDT 24
Peak memory 209880 kb
Host smart-b7a20a7e-62ab-4ed6-a748-6c10815cdcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639911695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1639911695
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.536321646
Short name T424
Test name
Test status
Simulation time 9577381 ps
CPU time 0.87 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:21 PM PDT 24
Peak memory 205948 kb
Host smart-a83f45d2-8ef2-4cfc-8d4c-ef45f3e23778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536321646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.536321646
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3429221982
Short name T823
Test name
Test status
Simulation time 46110194 ps
CPU time 2.07 seconds
Started Jun 07 07:11:11 PM PDT 24
Finished Jun 07 07:11:23 PM PDT 24
Peak memory 214280 kb
Host smart-74ccae3a-a888-46f3-9638-81496b0bb87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429221982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3429221982
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.646156021
Short name T484
Test name
Test status
Simulation time 60633938 ps
CPU time 2.78 seconds
Started Jun 07 07:11:14 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 219664 kb
Host smart-5e5b79d0-aa7e-43fc-9846-c45ae4c1ec5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646156021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.646156021
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.4082356308
Short name T881
Test name
Test status
Simulation time 66070630 ps
CPU time 2.27 seconds
Started Jun 07 07:11:15 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 214316 kb
Host smart-8f41ab7b-0b6a-4646-9b4a-43d8696eef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082356308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4082356308
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.232697732
Short name T53
Test name
Test status
Simulation time 585095153 ps
CPU time 4.85 seconds
Started Jun 07 07:11:12 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 222356 kb
Host smart-3621ebb0-dfcc-4463-af1e-36ad2cfe062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232697732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.232697732
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.622040379
Short name T433
Test name
Test status
Simulation time 99028582 ps
CPU time 3.17 seconds
Started Jun 07 07:11:09 PM PDT 24
Finished Jun 07 07:11:21 PM PDT 24
Peak memory 209332 kb
Host smart-3c981203-f98f-485f-8b7e-943192b9072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622040379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.622040379
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.784323873
Short name T498
Test name
Test status
Simulation time 797083412 ps
CPU time 8.48 seconds
Started Jun 07 07:11:11 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 208428 kb
Host smart-62804ef1-5f75-4871-925e-1e4cf501c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784323873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.784323873
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.567683653
Short name T409
Test name
Test status
Simulation time 1296641967 ps
CPU time 6.27 seconds
Started Jun 07 07:11:15 PM PDT 24
Finished Jun 07 07:11:32 PM PDT 24
Peak memory 208956 kb
Host smart-2d699462-3965-4728-8392-97b116a61077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567683653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.567683653
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1761322495
Short name T500
Test name
Test status
Simulation time 259721725 ps
CPU time 3 seconds
Started Jun 07 07:11:13 PM PDT 24
Finished Jun 07 07:11:27 PM PDT 24
Peak memory 206984 kb
Host smart-4a56d01a-579f-4e8a-a938-9b75aa7e0f62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761322495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1761322495
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.4265087484
Short name T775
Test name
Test status
Simulation time 1293411158 ps
CPU time 5.65 seconds
Started Jun 07 07:11:09 PM PDT 24
Finished Jun 07 07:11:24 PM PDT 24
Peak memory 208812 kb
Host smart-5c014dad-0dde-44e4-ba03-ad262bfe3c23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265087484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.4265087484
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.770843784
Short name T730
Test name
Test status
Simulation time 394336441 ps
CPU time 7 seconds
Started Jun 07 07:11:12 PM PDT 24
Finished Jun 07 07:11:30 PM PDT 24
Peak memory 208240 kb
Host smart-81a0c635-63b5-4c6b-b327-783fef185e54
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770843784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.770843784
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2942336636
Short name T655
Test name
Test status
Simulation time 180278050 ps
CPU time 1.76 seconds
Started Jun 07 07:11:11 PM PDT 24
Finished Jun 07 07:11:23 PM PDT 24
Peak memory 207600 kb
Host smart-380bf301-2197-449c-b7a1-11532ecbafc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942336636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2942336636
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.175496321
Short name T129
Test name
Test status
Simulation time 438159026 ps
CPU time 4.59 seconds
Started Jun 07 07:11:12 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 208004 kb
Host smart-d522baec-f6fd-4a00-846d-c7c28b99bdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175496321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.175496321
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3103103176
Short name T419
Test name
Test status
Simulation time 1695012093 ps
CPU time 21.75 seconds
Started Jun 07 07:11:08 PM PDT 24
Finished Jun 07 07:11:40 PM PDT 24
Peak memory 215480 kb
Host smart-cb6ee392-d126-4cd7-ae2f-f3f09509f8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103103176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3103103176
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3841674045
Short name T466
Test name
Test status
Simulation time 136982062 ps
CPU time 5.39 seconds
Started Jun 07 07:11:11 PM PDT 24
Finished Jun 07 07:11:26 PM PDT 24
Peak memory 208784 kb
Host smart-55007333-3baa-44e1-90e4-30983d90215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841674045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3841674045
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1275378764
Short name T63
Test name
Test status
Simulation time 59871884 ps
CPU time 2.68 seconds
Started Jun 07 07:11:11 PM PDT 24
Finished Jun 07 07:11:24 PM PDT 24
Peak memory 209860 kb
Host smart-7e0492f6-0ddb-4a16-bd06-98f78a4b30aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275378764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1275378764
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3842493191
Short name T101
Test name
Test status
Simulation time 50201512 ps
CPU time 0.89 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:37 PM PDT 24
Peak memory 205960 kb
Host smart-670fc9c6-3d7e-4ee1-a71d-5b1d28765209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842493191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3842493191
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2334844921
Short name T374
Test name
Test status
Simulation time 65183944 ps
CPU time 4.33 seconds
Started Jun 07 07:08:35 PM PDT 24
Finished Jun 07 07:08:41 PM PDT 24
Peak memory 214396 kb
Host smart-d920b5fe-fddb-4aa5-9f45-306d9009dada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334844921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2334844921
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3606958649
Short name T29
Test name
Test status
Simulation time 120325470 ps
CPU time 2.84 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:39 PM PDT 24
Peak memory 222672 kb
Host smart-44c058d3-6b0b-428a-946a-4d32f1dd8ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606958649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3606958649
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2969584698
Short name T48
Test name
Test status
Simulation time 22679577 ps
CPU time 1.79 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:38 PM PDT 24
Peak memory 207116 kb
Host smart-db316392-7978-416c-8328-9e9caa69c097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969584698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2969584698
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2503628359
Short name T345
Test name
Test status
Simulation time 341035396 ps
CPU time 5.22 seconds
Started Jun 07 07:08:35 PM PDT 24
Finished Jun 07 07:08:43 PM PDT 24
Peak memory 222428 kb
Host smart-17fff6ab-23c8-4845-9f29-52d4468ed05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503628359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2503628359
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2984049893
Short name T279
Test name
Test status
Simulation time 43182271 ps
CPU time 1.95 seconds
Started Jun 07 07:08:35 PM PDT 24
Finished Jun 07 07:08:39 PM PDT 24
Peak memory 216216 kb
Host smart-78c15cd3-ad40-4545-8542-daece1c99b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984049893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2984049893
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3336183974
Short name T478
Test name
Test status
Simulation time 296937592 ps
CPU time 9.75 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:46 PM PDT 24
Peak memory 209864 kb
Host smart-f6ea235d-5a31-4e8d-bcc6-2b900f234b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336183974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3336183974
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3913122009
Short name T754
Test name
Test status
Simulation time 129453435 ps
CPU time 4.12 seconds
Started Jun 07 07:08:37 PM PDT 24
Finished Jun 07 07:08:42 PM PDT 24
Peak memory 208048 kb
Host smart-ee7f9eec-b521-4d83-b085-67f81eeff926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913122009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3913122009
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2865191188
Short name T742
Test name
Test status
Simulation time 1499128367 ps
CPU time 36.43 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:09:13 PM PDT 24
Peak memory 208504 kb
Host smart-9f28d369-98a8-48e6-a9d5-08ab09606254
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865191188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2865191188
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2739028962
Short name T131
Test name
Test status
Simulation time 42859197 ps
CPU time 2.67 seconds
Started Jun 07 07:08:35 PM PDT 24
Finished Jun 07 07:08:40 PM PDT 24
Peak memory 208712 kb
Host smart-eff35e17-7857-4039-8747-ef4bac043f2f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739028962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2739028962
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3358178954
Short name T495
Test name
Test status
Simulation time 1290046073 ps
CPU time 30.84 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:09:08 PM PDT 24
Peak memory 208704 kb
Host smart-e7d46c7a-009e-4c15-9991-3a43a0e62683
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358178954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3358178954
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.871384045
Short name T688
Test name
Test status
Simulation time 135287349 ps
CPU time 4.24 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:41 PM PDT 24
Peak memory 209628 kb
Host smart-2b1c3808-a388-4512-a925-fcf493ae38b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871384045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.871384045
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2394508997
Short name T786
Test name
Test status
Simulation time 31432891 ps
CPU time 2.19 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:39 PM PDT 24
Peak memory 206848 kb
Host smart-a61d9f33-70ff-4695-922d-1aac223517fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394508997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2394508997
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3049320295
Short name T769
Test name
Test status
Simulation time 7683054855 ps
CPU time 44.54 seconds
Started Jun 07 07:08:35 PM PDT 24
Finished Jun 07 07:09:22 PM PDT 24
Peak memory 222640 kb
Host smart-21100603-4d6f-449e-a3cc-7c3a028ab7c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049320295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3049320295
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2387674894
Short name T247
Test name
Test status
Simulation time 86816200 ps
CPU time 4.38 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:41 PM PDT 24
Peak memory 214312 kb
Host smart-ef8eb8d2-0f51-4f4b-8fba-f2d2f71eb0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387674894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2387674894
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2984605393
Short name T866
Test name
Test status
Simulation time 33564080 ps
CPU time 2.03 seconds
Started Jun 07 07:08:35 PM PDT 24
Finished Jun 07 07:08:39 PM PDT 24
Peak memory 210184 kb
Host smart-1a72ac4d-65ab-43c8-ad11-e5eb0b42e2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984605393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2984605393
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2981037940
Short name T739
Test name
Test status
Simulation time 50558555 ps
CPU time 0.74 seconds
Started Jun 07 07:08:40 PM PDT 24
Finished Jun 07 07:08:43 PM PDT 24
Peak memory 205928 kb
Host smart-0191a408-8f23-4c3f-9a03-f3e28c28f284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981037940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2981037940
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2118118854
Short name T239
Test name
Test status
Simulation time 812524496 ps
CPU time 12.5 seconds
Started Jun 07 07:08:41 PM PDT 24
Finished Jun 07 07:08:56 PM PDT 24
Peak memory 215624 kb
Host smart-20c0d58c-9f15-4b16-b9f9-5fb99b3d5015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2118118854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2118118854
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.4076771870
Short name T18
Test name
Test status
Simulation time 172501979 ps
CPU time 2.14 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:46 PM PDT 24
Peak memory 217184 kb
Host smart-cf2a775c-26e2-4678-9faf-eea6e73a5e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076771870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.4076771870
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2768714762
Short name T636
Test name
Test status
Simulation time 80281093 ps
CPU time 2.04 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:08:47 PM PDT 24
Peak memory 206976 kb
Host smart-f6f3b74f-190e-459f-8b12-4adb3c2339b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768714762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2768714762
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1784127614
Short name T706
Test name
Test status
Simulation time 105389245 ps
CPU time 2.01 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:46 PM PDT 24
Peak memory 214348 kb
Host smart-38f8a25b-68df-495d-9a8a-2a478ed02c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784127614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1784127614
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2676882988
Short name T66
Test name
Test status
Simulation time 61150999 ps
CPU time 3.82 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:49 PM PDT 24
Peak memory 220088 kb
Host smart-42427aa8-f9c7-440f-9781-bd95b3469434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676882988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2676882988
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2950870785
Short name T862
Test name
Test status
Simulation time 101103843 ps
CPU time 4.51 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:08:51 PM PDT 24
Peak memory 209376 kb
Host smart-87764b56-b869-4c48-bbeb-eea732ec33d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950870785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2950870785
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.821860935
Short name T134
Test name
Test status
Simulation time 437274204 ps
CPU time 13.23 seconds
Started Jun 07 07:08:35 PM PDT 24
Finished Jun 07 07:08:51 PM PDT 24
Peak memory 208596 kb
Host smart-66efc205-393a-4a9a-bfad-6ec24696e79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821860935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.821860935
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3212681328
Short name T903
Test name
Test status
Simulation time 153246981 ps
CPU time 2.36 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:39 PM PDT 24
Peak memory 206916 kb
Host smart-d914b452-3af6-48fc-95c0-4f6b8d0a5b7a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212681328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3212681328
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3667424986
Short name T835
Test name
Test status
Simulation time 59832950 ps
CPU time 3.1 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:40 PM PDT 24
Peak memory 206860 kb
Host smart-1e365f12-7bbd-49d1-88b4-1168c0e5fe4b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667424986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3667424986
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.50804097
Short name T768
Test name
Test status
Simulation time 65187200 ps
CPU time 3.35 seconds
Started Jun 07 07:08:34 PM PDT 24
Finished Jun 07 07:08:40 PM PDT 24
Peak memory 208804 kb
Host smart-007512ac-fe11-4761-b5dc-bb31b2864756
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50804097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.50804097
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3667971265
Short name T872
Test name
Test status
Simulation time 275130996 ps
CPU time 3.49 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:08:49 PM PDT 24
Peak memory 209612 kb
Host smart-13674a46-973f-47e2-8718-b52175eaabde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667971265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3667971265
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.874051050
Short name T434
Test name
Test status
Simulation time 638956229 ps
CPU time 11.29 seconds
Started Jun 07 07:08:33 PM PDT 24
Finished Jun 07 07:08:48 PM PDT 24
Peak memory 207884 kb
Host smart-ad5c5d4c-2463-45db-bd17-afd4f6bc8828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874051050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.874051050
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2365428477
Short name T744
Test name
Test status
Simulation time 1372740908 ps
CPU time 28.42 seconds
Started Jun 07 07:08:41 PM PDT 24
Finished Jun 07 07:09:12 PM PDT 24
Peak memory 214572 kb
Host smart-45e7df62-29bb-407c-aab2-a36a8997e290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365428477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2365428477
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3154860359
Short name T126
Test name
Test status
Simulation time 4465039996 ps
CPU time 10.63 seconds
Started Jun 07 07:08:40 PM PDT 24
Finished Jun 07 07:08:53 PM PDT 24
Peak memory 222764 kb
Host smart-d00f89e8-5ad8-4d88-8ddb-78778c9313a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154860359 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3154860359
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3700238314
Short name T568
Test name
Test status
Simulation time 228901050 ps
CPU time 3.97 seconds
Started Jun 07 07:08:44 PM PDT 24
Finished Jun 07 07:08:51 PM PDT 24
Peak memory 208020 kb
Host smart-ebc531ed-1275-4d54-a1cd-524c2c62a10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700238314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3700238314
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.462097733
Short name T2
Test name
Test status
Simulation time 203736151 ps
CPU time 1.97 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:46 PM PDT 24
Peak memory 209916 kb
Host smart-0873293b-1064-469b-9542-11ec163c3278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462097733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.462097733
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1752088215
Short name T863
Test name
Test status
Simulation time 24230336 ps
CPU time 0.76 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:45 PM PDT 24
Peak memory 205972 kb
Host smart-c061dc4c-b68d-4c92-83b5-bab7fd418ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752088215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1752088215
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.4066299569
Short name T865
Test name
Test status
Simulation time 52312426 ps
CPU time 3.2 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:08:49 PM PDT 24
Peak memory 215172 kb
Host smart-cb5d0f5b-4628-4d3f-832c-221114eca67c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066299569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4066299569
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.4043168675
Short name T30
Test name
Test status
Simulation time 118014772 ps
CPU time 5.05 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:49 PM PDT 24
Peak memory 209636 kb
Host smart-dd9724ec-6258-4555-9d0c-adb1b1aa5083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043168675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.4043168675
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3332611177
Short name T502
Test name
Test status
Simulation time 24826566 ps
CPU time 1.9 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:08:48 PM PDT 24
Peak memory 208060 kb
Host smart-30bf1d04-bfb1-4c27-943c-d206161107a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332611177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3332611177
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2248003851
Short name T911
Test name
Test status
Simulation time 32401214 ps
CPU time 2.12 seconds
Started Jun 07 07:08:41 PM PDT 24
Finished Jun 07 07:08:45 PM PDT 24
Peak memory 214420 kb
Host smart-1cbd4407-5f46-41ca-b2ba-862974cc186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248003851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2248003851
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2455199894
Short name T804
Test name
Test status
Simulation time 126509983 ps
CPU time 6.39 seconds
Started Jun 07 07:08:41 PM PDT 24
Finished Jun 07 07:08:50 PM PDT 24
Peak memory 214936 kb
Host smart-c12ff6b2-e17b-4940-a7c7-25b0bd572e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455199894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2455199894
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3757330053
Short name T711
Test name
Test status
Simulation time 115958655 ps
CPU time 3.95 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:08:50 PM PDT 24
Peak memory 210232 kb
Host smart-30b35bb7-e421-442a-8163-e865ca256ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757330053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3757330053
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4104818065
Short name T633
Test name
Test status
Simulation time 463932332 ps
CPU time 4.86 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:49 PM PDT 24
Peak memory 214344 kb
Host smart-5f7d7be1-1046-41c1-adb6-3815f001e993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104818065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4104818065
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.464238194
Short name T4
Test name
Test status
Simulation time 88280138 ps
CPU time 2.96 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:48 PM PDT 24
Peak memory 206896 kb
Host smart-f3c3cbf5-57a3-496b-82c4-618534a26330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464238194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.464238194
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3755580954
Short name T135
Test name
Test status
Simulation time 874999950 ps
CPU time 6.11 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:08:52 PM PDT 24
Peak memory 208888 kb
Host smart-55a844e4-9cdd-4fe7-9633-a86986f07135
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755580954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3755580954
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2861378291
Short name T317
Test name
Test status
Simulation time 595571737 ps
CPU time 5.18 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:08:51 PM PDT 24
Peak memory 208000 kb
Host smart-d1595ac2-ac56-4303-9907-e8428a4040f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861378291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2861378291
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3502458458
Short name T138
Test name
Test status
Simulation time 1700272642 ps
CPU time 23.19 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:09:08 PM PDT 24
Peak memory 207928 kb
Host smart-018f89d5-bd95-4586-aa95-9b151bac3628
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502458458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3502458458
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1159593997
Short name T84
Test name
Test status
Simulation time 362851037 ps
CPU time 3.32 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:48 PM PDT 24
Peak memory 208480 kb
Host smart-8a3dcee2-ffff-432b-aa2e-682019c71368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159593997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1159593997
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3220889232
Short name T425
Test name
Test status
Simulation time 49973005 ps
CPU time 2.57 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:47 PM PDT 24
Peak memory 207048 kb
Host smart-403212fa-7835-490c-b6fa-7c2db0eee592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220889232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3220889232
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3027986603
Short name T263
Test name
Test status
Simulation time 1653585350 ps
CPU time 41.71 seconds
Started Jun 07 07:08:41 PM PDT 24
Finished Jun 07 07:09:25 PM PDT 24
Peak memory 222444 kb
Host smart-2ebd1591-8b96-4bd4-b77c-5e256e84e529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027986603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3027986603
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1721582641
Short name T188
Test name
Test status
Simulation time 1635470091 ps
CPU time 16.82 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:09:02 PM PDT 24
Peak memory 221032 kb
Host smart-7fd58247-9418-4b49-9941-5a2093477bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721582641 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1721582641
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2237312889
Short name T254
Test name
Test status
Simulation time 193836467 ps
CPU time 2.81 seconds
Started Jun 07 07:08:44 PM PDT 24
Finished Jun 07 07:08:50 PM PDT 24
Peak memory 207916 kb
Host smart-dcd7b4e2-b005-4f46-a21b-b931f8f63f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237312889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2237312889
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3302090425
Short name T851
Test name
Test status
Simulation time 541030203 ps
CPU time 8.54 seconds
Started Jun 07 07:08:42 PM PDT 24
Finished Jun 07 07:08:53 PM PDT 24
Peak memory 210308 kb
Host smart-d146c4dd-d688-4e53-836b-9ac5a0b36621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302090425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3302090425
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.382062386
Short name T793
Test name
Test status
Simulation time 115295412 ps
CPU time 0.82 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:08:55 PM PDT 24
Peak memory 205976 kb
Host smart-cc29b9f9-4c85-4fc7-9a45-8e55e95f2d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382062386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.382062386
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2302532596
Short name T464
Test name
Test status
Simulation time 277356515 ps
CPU time 4.42 seconds
Started Jun 07 07:08:50 PM PDT 24
Finished Jun 07 07:09:00 PM PDT 24
Peak memory 209924 kb
Host smart-c0b74f21-0232-483b-8a05-195a056ab566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302532596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2302532596
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2512631879
Short name T618
Test name
Test status
Simulation time 2086066353 ps
CPU time 10.45 seconds
Started Jun 07 07:08:51 PM PDT 24
Finished Jun 07 07:09:06 PM PDT 24
Peak memory 218352 kb
Host smart-54ed3159-4d84-44d5-a810-a351bcc6e46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512631879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2512631879
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3763673469
Short name T738
Test name
Test status
Simulation time 111560188 ps
CPU time 2.3 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:08:56 PM PDT 24
Peak memory 214264 kb
Host smart-cc85f0ff-617c-4e56-9875-676e391eecab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763673469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3763673469
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2662222259
Short name T685
Test name
Test status
Simulation time 352096489 ps
CPU time 3.81 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:08:58 PM PDT 24
Peak memory 220880 kb
Host smart-04c23faf-663e-454c-be15-3cf6c114ba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662222259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2662222259
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1292625028
Short name T201
Test name
Test status
Simulation time 2820784842 ps
CPU time 4.85 seconds
Started Jun 07 07:08:48 PM PDT 24
Finished Jun 07 07:08:58 PM PDT 24
Peak memory 214404 kb
Host smart-fa8ec5ea-4f2c-45bd-8cf7-8611f6f7e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292625028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1292625028
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2467677763
Short name T624
Test name
Test status
Simulation time 124160917 ps
CPU time 2.43 seconds
Started Jun 07 07:08:40 PM PDT 24
Finished Jun 07 07:08:44 PM PDT 24
Peak memory 207000 kb
Host smart-052e048d-a562-473f-9e02-927edd33035d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467677763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2467677763
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.428453448
Short name T453
Test name
Test status
Simulation time 551732999 ps
CPU time 10.62 seconds
Started Jun 07 07:08:48 PM PDT 24
Finished Jun 07 07:09:04 PM PDT 24
Peak memory 208908 kb
Host smart-3739289a-a0d7-4f13-91c8-6a1ca165305d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428453448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.428453448
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1175916145
Short name T355
Test name
Test status
Simulation time 632574373 ps
CPU time 17.92 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:09:03 PM PDT 24
Peak memory 208092 kb
Host smart-b0ae2c3c-aeb6-4fe8-99c0-ed03f1940d5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175916145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1175916145
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3026390293
Short name T559
Test name
Test status
Simulation time 338107807 ps
CPU time 3.9 seconds
Started Jun 07 07:08:48 PM PDT 24
Finished Jun 07 07:08:57 PM PDT 24
Peak memory 209028 kb
Host smart-2554355e-564b-48d6-9307-561d69257560
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026390293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3026390293
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2622915422
Short name T235
Test name
Test status
Simulation time 154883241 ps
CPU time 4.27 seconds
Started Jun 07 07:08:48 PM PDT 24
Finished Jun 07 07:08:58 PM PDT 24
Peak memory 208604 kb
Host smart-52099493-2cd2-47a9-a1b5-391a2aa2d736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622915422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2622915422
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3294963979
Short name T710
Test name
Test status
Simulation time 32594387 ps
CPU time 2.32 seconds
Started Jun 07 07:08:43 PM PDT 24
Finished Jun 07 07:08:48 PM PDT 24
Peak memory 206128 kb
Host smart-6d816ee1-fc1f-487b-848f-c161fd5f55d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294963979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3294963979
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1229096457
Short name T61
Test name
Test status
Simulation time 378667714 ps
CPU time 18.78 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:09:13 PM PDT 24
Peak memory 221224 kb
Host smart-078f3f75-81ec-4a39-be47-e1f6b1adcc70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229096457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1229096457
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3389472437
Short name T625
Test name
Test status
Simulation time 203950214 ps
CPU time 6.22 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:09:00 PM PDT 24
Peak memory 207444 kb
Host smart-a1022538-d591-450d-9a4c-a2316d7274a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389472437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3389472437
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3841598486
Short name T35
Test name
Test status
Simulation time 111313966 ps
CPU time 1.67 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:08:56 PM PDT 24
Peak memory 209620 kb
Host smart-5f82820c-f0bf-422a-8824-7260eaa210f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841598486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3841598486
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2466950282
Short name T105
Test name
Test status
Simulation time 180373135 ps
CPU time 0.75 seconds
Started Jun 07 07:08:51 PM PDT 24
Finished Jun 07 07:08:57 PM PDT 24
Peak memory 205900 kb
Host smart-298f9b84-25eb-46a4-a073-ffd9c058086d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466950282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2466950282
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.470122683
Short name T262
Test name
Test status
Simulation time 380861172 ps
CPU time 10.3 seconds
Started Jun 07 07:08:50 PM PDT 24
Finished Jun 07 07:09:06 PM PDT 24
Peak memory 214844 kb
Host smart-d06ea627-6a0d-4edb-87bb-f453bb98f31d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470122683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.470122683
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1870553559
Short name T514
Test name
Test status
Simulation time 2781976857 ps
CPU time 40.98 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:09:35 PM PDT 24
Peak memory 210376 kb
Host smart-b345c334-1548-43ba-99ab-d643552e97f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870553559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1870553559
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.990768011
Short name T886
Test name
Test status
Simulation time 61957301 ps
CPU time 2.47 seconds
Started Jun 07 07:08:50 PM PDT 24
Finished Jun 07 07:08:57 PM PDT 24
Peak memory 214224 kb
Host smart-6b4889d1-aca9-4eb1-8aa1-f0a3c856b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990768011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.990768011
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1293368299
Short name T344
Test name
Test status
Simulation time 292900490 ps
CPU time 4.13 seconds
Started Jun 07 07:08:52 PM PDT 24
Finished Jun 07 07:09:01 PM PDT 24
Peak memory 222408 kb
Host smart-6c1487b6-2086-4420-8e24-1e5e772152cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293368299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1293368299
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2115098236
Short name T221
Test name
Test status
Simulation time 102368624 ps
CPU time 4.41 seconds
Started Jun 07 07:08:52 PM PDT 24
Finished Jun 07 07:09:01 PM PDT 24
Peak memory 214296 kb
Host smart-e908e480-7fd7-4274-8c43-18c78346304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115098236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2115098236
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3822918375
Short name T827
Test name
Test status
Simulation time 129304792 ps
CPU time 3.15 seconds
Started Jun 07 07:08:51 PM PDT 24
Finished Jun 07 07:08:59 PM PDT 24
Peak memory 208928 kb
Host smart-a4477d98-5b12-49bf-bb42-6d551f30d9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822918375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3822918375
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.789101089
Short name T309
Test name
Test status
Simulation time 218039375 ps
CPU time 3.01 seconds
Started Jun 07 07:08:48 PM PDT 24
Finished Jun 07 07:08:56 PM PDT 24
Peak memory 207160 kb
Host smart-2c7426dc-183e-48d0-ac0b-ce29241df756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789101089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.789101089
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3682789411
Short name T855
Test name
Test status
Simulation time 41543710 ps
CPU time 2.42 seconds
Started Jun 07 07:08:50 PM PDT 24
Finished Jun 07 07:08:58 PM PDT 24
Peak memory 206888 kb
Host smart-ce60ca72-8f07-43b4-8531-51a6b9a3dc69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682789411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3682789411
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2651259410
Short name T330
Test name
Test status
Simulation time 651107190 ps
CPU time 5.79 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:09:00 PM PDT 24
Peak memory 208432 kb
Host smart-3615cd0c-7bfd-4b36-980e-553c5d472402
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651259410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2651259410
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.244309640
Short name T887
Test name
Test status
Simulation time 595575458 ps
CPU time 3.17 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:08:57 PM PDT 24
Peak memory 206936 kb
Host smart-24e4d6b0-f370-48be-910e-51f8526a2b7c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244309640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.244309640
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2167587138
Short name T776
Test name
Test status
Simulation time 100122616 ps
CPU time 4.34 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:08:58 PM PDT 24
Peak memory 218436 kb
Host smart-ea14cec5-2b3d-4dee-8c72-e039d4ea3faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167587138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2167587138
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.231719903
Short name T548
Test name
Test status
Simulation time 320658852 ps
CPU time 2.82 seconds
Started Jun 07 07:08:50 PM PDT 24
Finished Jun 07 07:08:58 PM PDT 24
Peak memory 206852 kb
Host smart-6efb93d4-6607-4f59-8486-b6fd8bb40366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231719903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.231719903
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2346185119
Short name T657
Test name
Test status
Simulation time 1014058930 ps
CPU time 5.22 seconds
Started Jun 07 07:08:48 PM PDT 24
Finished Jun 07 07:08:57 PM PDT 24
Peak memory 209996 kb
Host smart-522175f5-9356-4fe3-8ea7-7349d0f8d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346185119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2346185119
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2470890861
Short name T421
Test name
Test status
Simulation time 80728956 ps
CPU time 2.44 seconds
Started Jun 07 07:08:49 PM PDT 24
Finished Jun 07 07:08:56 PM PDT 24
Peak memory 209936 kb
Host smart-34b6c18c-a64d-4e2f-ad98-d87648388e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470890861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2470890861
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%