Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4825

1

T1

12

T2

5

T3

4

auto[1]

550

1

T12

5

T14

2

T43

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4825

1

T1

12

T2

5

T3

4

auto[1]

550

1

T12

5

T14

2

T43

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4829

1

T1

12

T2

4

T3

3

auto[1]

546

1

T2

1

T3

1

T14

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4829

1

T1

12

T2

4

T3

3

auto[1]

546

1

T2

1

T3

1

T14

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	465	1			T1	4		T14	1		T17	1
auto[OpGenId]	1143	1			T1	4		T2	1		T3	1
auto[OpGenSwOut]	1125	1			T1	2		T2	3		T11	1
auto[OpGenHwOut]	2576	1			T1	2		T2	1		T3	3
auto[OpDisable]	66	1			T48	1		T50	1		T59	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	465	1			T1	4		T14	1		T17	1
auto[OpGenId]	1143	1			T1	4		T2	1		T3	1
auto[OpGenSwOut]	1125	1			T1	2		T2	3		T11	1
auto[OpGenHwOut]	2576	1			T1	2		T2	1		T3	3
auto[OpDisable]	66	1			T48	1		T50	1		T59	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4845

1

T1

12

T2

5

T3

1

auto[1]

530

1

T3

3

T26

1

T42

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4845

1

T1

12

T2

5

T3

1

auto[1]

530

1

T3

3

T26

1

T42

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5085

1

T1

3

T2

5

T3

4

auto[1]

290

1

T1

9

T11

4

T123

11

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1830	1			T1	1		T2	1		T3	1
auto[1]	743	1			T2	2		T3	2		T12	1
auto[2]	659	1			T3	1		T11	1		T12	2
auto[3]	686	1			T14	2		T16	1		T89	2
auto[4]	363	1			T1	1		T13	1		T16	1
auto[5]	359	1			T1	10		T12	3		T17	1
auto[6]	354	1			T2	1		T13	2		T26	1
auto[7]	381	1			T2	1		T11	3		T12	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1457	1			T1	11		T2	2		T11	3
clear_one[1]	743	1			T2	2		T3	2		T12	1
clear_one[2]	659	1			T3	1		T11	1		T12	2
clear_one[3]	686	1			T14	2		T16	1		T89	2
clear_none	1830	1			T1	1		T2	1		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1058	1			T1	2		T12	4		T13	1
auto[StInit]	667	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	547	1			T1	1		T11	1		T12	1
auto[StOwnerIntKey]	507	1			T1	4		T3	1		T12	1
auto[StOwnerKey]	471	1			T1	1		T11	2		T12	1
auto[StDisabled]	1851	1			T1	3		T2	4		T3	2
auto[StInvalid]	274	1			T16	4		T17	4		T36	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1058	1			T1	2		T12	4		T13	1
auto[StInit]	667	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	547	1			T1	1		T11	1		T12	1
auto[StOwnerIntKey]	507	1			T1	4		T3	1		T12	1
auto[StOwnerKey]	471	1			T1	1		T11	2		T12	1
auto[StDisabled]	1851	1			T1	3		T2	4		T3	2
auto[StInvalid]	274	1			T16	4		T17	4		T36	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StOwnerIntKey]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T221	1		T222	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	158	1			T196	1		T51	1		T44	3
auto[0]	auto[StReset]	auto[OpGenSwOut]	180	1			T1	1		T13	1		T16	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	277	1			T12	1		T89	1		T43	1
auto[0]	auto[StInit]	auto[OpAdvance]	39	1			T151	1		T24	1		T27	1
auto[0]	auto[StInit]	auto[OpGenId]	98	1			T11	2		T152	1		T90	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	88	1			T2	1		T48	1		T201	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	176	1			T3	1		T42	1		T147	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T14	1		T141	1		T223	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	57	1			T150	1		T135	1		T93	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	24	1			T61	1		T65	1		T224	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	68	1			T43	1		T44	1		T145	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T23	1		T123	1		T141	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	28	1			T152	4		T225	1		T226	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T50	1		T118	1		T227	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	46	1			T12	1		T26	1		T147	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T31	1		T210	1		T74	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	19	1			T228	1		T74	1		T229	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T197	1		T118	1		T230	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T42	1		T87	1		T231	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	37	1			T200	1		T154	1		T232	1
auto[0]	auto[StDisabled]	auto[OpGenId]	67	1			T14	1		T196	1		T44	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T141	1		T98	1		T57	3
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T12	3		T89	2		T43	1
auto[0]	auto[StDisabled]	auto[OpDisable]	25	1			T60	1		T69	1		T72	2
auto[0]	auto[StInvalid]	auto[OpAdvance]	15	1			T103	1		T137	1		T104	1
auto[0]	auto[StInvalid]	auto[OpGenId]	21	1			T51	1		T233	1		T234	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	23	1			T16	1		T36	1		T51	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	22	1			T17	1		T36	1		T233	1
auto[1]	auto[StReset]	auto[OpGenId]	21	1			T70	1		T235	1		T68	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	23	1			T134	1		T20	1		T59	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	45	1			T12	1		T16	2		T145	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T123	1		T6	1		T236	1
auto[1]	auto[StInit]	auto[OpGenId]	14	1			T49	1		T24	1		T68	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	13	1			T91	2		T56	1		T237	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	17	1			T43	1		T83	1		T238	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T154	1		T239	1		T240	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	21	1			T47	1		T93	1		T69	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T123	1		T22	1		T241	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T147	1		T201	1		T140	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T153	1		T22	1		T154	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T242	1		T93	1		T243	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T48	1		T90	1		T57	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T3	1		T208	1		T73	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T73	1		T211	2		T224	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	12	1			T74	1		T244	1		T221	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T245	1		T74	1		T246	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T138	1		T247	1		T60	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	37	1			T248	1		T72	1		T65	1
auto[1]	auto[StDisabled]	auto[OpGenId]	62	1			T2	1		T3	1		T197	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T2	1		T44	1		T95	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T14	1		T89	1		T145	1
auto[1]	auto[StDisabled]	auto[OpDisable]	12	1			T50	1		T59	1		T74	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T103	1		T249	1		T250	1
auto[1]	auto[StInvalid]	auto[OpGenId]	8	1			T36	1		T94	1		T251	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T36	1		T233	1		T94	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T252	1		T253	1		T254	1
auto[2]	auto[StReset]	auto[OpGenId]	20	1			T44	1		T55	1		T134	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	20	1			T44	1		T205	1		T255	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	48	1			T12	1		T55	1		T208	1
auto[2]	auto[StInit]	auto[OpAdvance]	13	1			T37	1		T96	1		T256	1
auto[2]	auto[StInit]	auto[OpGenId]	11	1			T24	1		T72	1		T74	2
auto[2]	auto[StInit]	auto[OpGenSwOut]	10	1			T55	1		T45	1		T22	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	20	1			T89	1		T73	1		T257	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T123	2		T93	1		T68	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T11	1		T44	1		T199	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T71	1		T68	1		T211	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	42	1			T13	1		T95	1		T206	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T258	1		T112	1		T259	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T260	1		T261	1		T74	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T123	1		T262	1		T263	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	31	1			T123	1		T138	1		T140	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T262	1		T74	1		T264	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	12	1			T26	1		T95	1		T57	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T73	1		T5	1		T69	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T43	1		T145	1		T140	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	26	1			T141	1		T232	1		T65	1
auto[2]	auto[StDisabled]	auto[OpGenId]	46	1			T26	1		T95	1		T73	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T197	1		T136	1		T248	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	140	1			T3	1		T12	1		T43	1
auto[2]	auto[StDisabled]	auto[OpDisable]	5	1			T68	1		T265	1		T266	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T137	1		T94	1		T267	1
auto[2]	auto[StInvalid]	auto[OpGenId]	8	1			T16	2		T51	1		T268	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T104	1		T269	1		T270	2
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T55	1		T234	2		T270	2
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T271	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	15	1			T55	1		T37	1		T117	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	23	1			T46	1		T248	1		T84	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	46	1			T86	1		T72	1		T272	1
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T273	1		T274	1		T275	2
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T6	1		T68	1		T127	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	19	1			T204	1		T95	1		T235	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	17	1			T44	1		T145	1		T208	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T65	1		T68	1		T276	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T196	1		T57	2		T225	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T74	1		T68	1		T277	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	29	1			T278	1		T83	1		T279	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T74	1		T280	1		T281	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T282	1		T74	1		T283	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T59	1		T72	1		T65	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T89	1		T207	1		T284	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T65	1		T273	1		T285	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	23	1			T47	1		T57	1		T142	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T14	1		T261	1		T286	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T89	1		T44	1		T147	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	16	1			T123	1		T150	1		T202	1
auto[3]	auto[StDisabled]	auto[OpGenId]	40	1			T57	1		T228	1		T60	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T14	1		T197	1		T22	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T42	2		T123	1		T147	2
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T74	1		T68	1		T75	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T103	1		T287	1		T249	1
auto[3]	auto[StInvalid]	auto[OpGenId]	9	1			T268	1		T288	1		T289	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T51	1		T233	1		T287	2
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T16	1		T51	1		T268	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T268	1		T68	1		T290	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T73	1		T69	1		T74	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T16	1		T57	1		T291	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T292	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	10	1			T47	1		T91	1		T293	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	8	1			T211	2		T294	1		T295	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	8	1			T279	1		T69	1		T296	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T194	1		T297	1		T298	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T211	1		T299	1		T300	2
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T227	1		T93	1		T74	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T42	1		T291	1		T93	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T203	1		T84	1		T293	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T72	1		T68	1		T106	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T42	1		T86	1		T301	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T153	1		T65	1		T302	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	9	1			T153	2		T303	1		T304	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T152	3		T242	1		T305	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T208	1		T284	1		T206	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	15	1			T153	1		T306	1		T307	1
auto[4]	auto[StDisabled]	auto[OpGenId]	26	1			T196	1		T48	1		T47	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T1	1		T13	1		T57	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	96	1			T89	1		T42	1		T147	1
auto[4]	auto[StDisabled]	auto[OpDisable]	4	1			T48	1		T308	1		T213	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T137	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T17	1		T309	1		T310	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T311	1		T312	1		T298	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T55	1		T104	1		T313	2
auto[5]	auto[StReset]	auto[OpAdvance]	1	1			T1	1		-	-		-	-
auto[5]	auto[StReset]	auto[OpGenId]	9	1			T134	1		T84	1		T155	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T248	1		T29	1		T52	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	21	1			T12	1		T70	1		T314	1
auto[5]	auto[StInit]	auto[OpAdvance]	6	1			T1	1		T57	1		T315	1
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T46	1		T269	1		T316	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	4	1			T317	1		T318	1		T54	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T196	1		T319	1		T320	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T1	1		T205	1		T221	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T57	1		T294	1		T321	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T322	1		T323	1		T186	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T12	1		T87	1		T72	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T57	1		T221	1		T224	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T1	2		T255	1		T211	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T213	1		T324	1		T325	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T1	2		T43	1		T145	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T1	1		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	4	1			T326	1		T327	1		T328	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T255	1		T296	1		T306	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T12	1		T72	1		T329	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	16	1			T152	1		T228	1		T235	1
auto[5]	auto[StDisabled]	auto[OpGenId]	28	1			T1	2		T282	1		T228	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T88	1		T255	1		T74	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T43	1		T44	1		T150	1
auto[5]	auto[StDisabled]	auto[OpDisable]	2	1			T6	1		T305	1		-	-
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T319	1		T330	1		T331	1
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T137	1		T331	1		T332	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T333	1		T251	1		T334	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T17	1		T289	1		T330	1
auto[6]	auto[StReset]	auto[OpGenId]	12	1			T95	1		T205	1		T84	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T60	1		T127	1		T335	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T199	1		T336	1		T59	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T154	1		T307	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T13	1		T337	1		T338	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T205	1		T142	1		T339	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	13	1			T24	1		T71	1		T340	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T115	1		T341	1		T342	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T211	1		T335	1		T186	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T134	1		T72	1		T343	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	27	1			T89	1		T57	1		T154	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T115	1		T72	1		T344	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T6	1		T74	1		T345	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T127	1		T258	1		T346	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T70	1		T87	1		T66	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T22	1		T68	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T127	1		T347	1		T348	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T349	1		T307	2		T322	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T13	1		T350	1		T83	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	19	1			T351	1		T221	2		T112	2
auto[6]	auto[StDisabled]	auto[OpGenId]	26	1			T44	1		T65	1		T74	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T26	1		T57	2		T260	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T2	1		T138	1		T350	2
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T77	1		T142	1		T352	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	1	1			T334	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	7	1			T233	1		T319	1		T252	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T269	1		T353	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T354	1		T355	1		T356	1
auto[7]	auto[StReset]	auto[OpAdvance]	1	1			T248	1		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	11	1			T57	2		T68	1		T127	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	18	1			T36	1		T357	1		T21	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T86	1		T291	1		T358	1
auto[7]	auto[StInit]	auto[OpAdvance]	6	1			T255	1		T359	4		T360	1
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T6	1		T346	1		T194	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T24	1		T72	1		T361	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	18	1			T12	1		T86	1		T362	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T57	1		T240	1		T363	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T98	1		T59	1		T255	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T265	1		T364	1		T220	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T284	1		T93	1		T92	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T72	1		T365	1		T366	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T199	1		T201	1		T211	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T295	1		T367	1		T361	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T336	1		T368	1		T369	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T11	1		T248	1		T68	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T11	1		T203	1		T359	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T86	1		T291	1		T370	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	15	1			T123	2		T248	1		T357	1
auto[7]	auto[StDisabled]	auto[OpGenId]	21	1			T123	3		T65	1		T127	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T2	1		T242	1		T72	4
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T11	1		T42	1		T43	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T68	1		T129	1		T371	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T17	1		T287	1		T251	1
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T103	1		T311	1		T319	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T313	1		T372	1		T373	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T104	1		T374	1		T375	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1457

1

T1

11

T2

2

T11

3

clear_one[1]

auto[0]

auto[0]

auto[0]

414

1

T2

1

T12

1

T16

2

clear_one[1]

auto[0]

auto[0]

auto[1]

126

1

T3

1

T197

1

T48

1

clear_one[1]

auto[0]

auto[1]

auto[0]

154

1

T2

1

T14

1

T89

1

clear_one[1]

auto[0]

auto[1]

auto[1]

49

1

T3

1

T44

2

T150

1

clear_one[2]

auto[0]

auto[0]

auto[0]

399

1

T11

1

T12

1

T13

1

clear_one[2]

auto[0]

auto[0]

auto[1]

114

1

T3

1

T26

1

T199

1

clear_one[2]

auto[1]

auto[0]

auto[0]

117

1

T12

1

T43

2

T197

1

clear_one[2]

auto[1]

auto[0]

auto[1]

29

1

T141

1

T245

1

T349

1

clear_one[3]

auto[0]

auto[0]

auto[0]

400

1

T16

1

T42

2

T196

1

clear_one[3]

auto[0]

auto[1]

auto[0]

102

1

T89

2

T197

1

T147

3

clear_one[3]

auto[1]

auto[0]

auto[0]

149

1

T14

1

T284

1

T206

1

clear_one[3]

auto[1]

auto[1]

auto[0]

35

1

T14

1

T44

1

T202

1

clear_none

auto[0]

auto[0]

auto[0]

1343

1

T1

1

T2

1

T3

1

clear_none

auto[0]

auto[0]

auto[1]

122

1

T42

1

T207

2

T208

2

clear_none

auto[0]

auto[1]

auto[0]

118

1

T14

1

T89

2

T44

1

clear_none

auto[0]

auto[1]

auto[1]

27

1

T44

2

T200

1

T57

1

clear_none

auto[1]

auto[0]

auto[0]

122

1

T12

4

T43

2

T123

2

clear_none

auto[1]

auto[0]

auto[1]

37

1

T232

1

T31

1

T6

1

clear_none

auto[1]

auto[1]

auto[0]

35

1

T123

2

T141

2

T60

1

clear_none

auto[1]

auto[1]

auto[1]

26

1

T23

1

T90

1

T202

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1356	1			T1	2		T2	2		T12	4
clear_all	auto[1]	101	1			T1	9		T11	3		T123	3
clear_one[1]	auto[0]	709	1			T2	2		T3	2		T12	1
clear_one[1]	auto[1]	34	1			T123	1		T154	1		T376	2
clear_one[2]	auto[0]	625	1			T3	1		T11	1		T12	2
clear_one[2]	auto[1]	34	1			T123	3		T141	1		T377	2
clear_one[3]	auto[0]	647	1			T14	2		T16	1		T89	2
clear_one[3]	auto[1]	39	1			T123	1		T273	3		T304	2
clear_none	auto[0]	1748	1			T1	1		T2	1		T3	1
clear_none	auto[1]	82	1			T11	1		T123	3		T152	5