Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11148

1

T1

11

T2

3

T3

4

auto[Attestation]

7679

1

T1

7

T2

5

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2709	1			T1	3		T2	3		T3	1
auto[Aes]	3379	1			T11	3		T12	15		T13	9
auto[Kmac]	3501	1			T1	2		T2	3		T3	2
auto[Otbn]	3356	1			T1	5		T2	1		T3	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7531	1			T1	8		T2	8		T3	8
auto[OpGenId]	5882	1			T1	8		T2	1		T3	2
auto[OpGenSwOut]	5952	1			T1	4		T2	3		T3	2
auto[OpGenHwOut]	6993	1			T1	6		T2	4		T3	4
auto[OpDisable]	130	1			T48	1		T49	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10604

1

T1

9

T2

8

T3

8

auto[OpDoneFail]

15884

1

T1

17

T2

8

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6624	1			T1	5		T2	1		T3	1
auto[StInit]	3693	1			T1	3		T2	2		T3	2
auto[StCreatorRootKey]	3189	1			T1	1		T2	2		T3	2
auto[StOwnerIntKey]	2742	1			T1	5		T2	2		T3	2
auto[StOwnerKey]	2497	1			T1	1		T2	2		T3	2
auto[StDisabled]	7743	1			T1	11		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	356	1			T16	1		T18	2		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T196	1		T197	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T34	1		T197	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	64	1			T11	1		T144	1		T118	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T11	1		T18	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	214	1			T1	1		T196	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	328	1			T13	1		T18	2		T34	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	104	1			T11	1		T35	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	90	1			T13	1		T198	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	63	1			T123	1		T62	1		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	65	1			T14	1		T23	1		T144	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	211	1			T14	1		T18	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	348	1			T13	2		T16	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	97	1			T2	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	67	1			T11	1		T152	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T151	1		T152	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T14	1		T201	1		T202	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	235	1			T13	1		T26	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	346	1			T1	1		T13	2		T16	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	102	1			T1	1		T35	1		T146	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T34	1		T143	1		T201	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	62	1			T150	1		T151	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	67	1			T197	1		T48	1		T118	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	211	1			T3	1		T14	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	81	1			T57	1		T59	2		T69	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	105	1			T14	1		T34	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T90	1		T22	1		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T90	1		T201	1		T203	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	64	1			T26	1		T23	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	186	1			T2	1		T11	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	81	1			T57	3		T69	5		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	97	1			T34	1		T23	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	84	1			T196	1		T146	1		T123	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	86	1			T13	1		T48	1		T123	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	60	1			T73	1		T98	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	207	1			T11	1		T13	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	81	1			T57	1		T59	1		T69	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	99	1			T11	1		T26	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T144	1		T204	2		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T11	1		T146	1		T150	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	73	1			T152	1		T153	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	223	1			T1	1		T2	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	79	1			T36	1		T57	2		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	120	1			T18	1		T197	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T44	1		T118	1		T141	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T11	1		T13	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	59	1			T23	1		T143	1		T98	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	222	1			T3	1		T11	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	302	1			T13	2		T16	1		T34	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	77	1			T15	1		T22	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	62	1			T72	1		T74	2		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	72	1			T2	1		T26	1		T95	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T199	1		T95	1		T57	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	168	1			T1	1		T3	1		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	466	1			T12	7		T13	2		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	125	1			T34	1		T196	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T12	1		T13	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	85	1			T14	1		T123	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T12	1		T43	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	299	1			T12	2		T14	1		T26	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	540	1			T13	1		T16	1		T89	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	129	1			T3	1		T89	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	108	1			T44	1		T145	1		T202	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	102	1			T145	1		T151	1		T62	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	89	1			T11	1		T26	1		T89	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	273	1			T89	2		T23	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	438	1			T1	1		T16	2		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	112	1			T11	1		T42	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T42	1		T196	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	71	1			T1	1		T3	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T26	1		T47	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	266	1			T11	2		T13	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	49	1			T57	3		T59	2		T74	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	90	1			T11	1		T14	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T2	1		T151	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	60	1			T123	2		T200	2		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T23	1		T201	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	166	1			T1	1		T150	2		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T36	2		T57	2		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T12	1		T43	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	108	1			T23	1		T48	1		T204	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	97	1			T12	1		T14	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	106	1			T11	1		T44	2		T201	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	255	1			T12	2		T13	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	55	1			T36	1		T57	1		T59	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	118	1			T15	1		T44	1		T147	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T89	1		T23	1		T147	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T89	1		T44	1		T147	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	99	1			T2	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	277	1			T1	1		T11	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	63	1			T57	4		T69	6		T6	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	105	1			T1	1		T44	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T27	1		T153	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T42	1		T207	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	106	1			T14	1		T42	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	280	1			T2	1		T13	1		T42	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	189	1			T11	2		T18	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	690	1			T1	1		T16	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	202	1			T14	1		T23	1		T144	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	659	1			T11	1		T13	2		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	175	1			T11	1		T14	1		T151	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	697	1			T2	1		T13	3		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	204	1			T34	1		T197	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	671	1			T1	2		T3	1		T13	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	204	1			T26	1		T23	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	390	1			T2	1		T11	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	213	1			T13	1		T196	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	402	1			T11	1		T13	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T11	1		T144	1		T146	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	418	1			T1	1		T2	1		T11	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T11	1		T13	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	433	1			T3	1		T11	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	169	1			T2	1		T26	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	569	1			T1	1		T3	1		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	259	1			T12	2		T14	1		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	904	1			T12	9		T13	3		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T11	1		T26	1		T89	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	961	1			T3	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	258	1			T1	1		T3	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	832	1			T1	1		T11	3		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	177	1			T2	1		T23	1		T123	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	321	1			T1	1		T11	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	297	1			T11	1		T12	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	443	1			T12	3		T13	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	295	1			T2	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	466	1			T1	1		T11	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	297	1			T14	1		T42	2		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	465	1			T1	1		T2	1		T13	1