Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32389

1

T1

30

T2

21

T3

19

auto[1]

291

1

T1

1

T11

5

T123

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32400	1			T1	30		T2	21		T3	19
auto[134217728:268435455]	7	1			T273	1		T307	1		T222	1
auto[268435456:402653183]	7	1			T255	1		T273	1		T323	1
auto[402653184:536870911]	4	1			T141	1		T307	1		T406	2
auto[536870912:671088639]	14	1			T152	2		T141	1		T222	1
auto[671088640:805306367]	10	1			T377	1		T307	1		T304	1
auto[805306368:939524095]	13	1			T152	1		T248	1		T394	1
auto[939524096:1073741823]	11	1			T11	2		T123	1		T359	1
auto[1073741824:1207959551]	8	1			T141	1		T359	1		T407	1
auto[1207959552:1342177279]	9	1			T239	2		T408	2		T280	1
auto[1342177280:1476395007]	12	1			T153	1		T221	2		T259	1
auto[1476395008:1610612735]	10	1			T376	1		T304	1		T222	1
auto[1610612736:1744830463]	16	1			T152	2		T304	1		T222	1
auto[1744830464:1879048191]	9	1			T152	2		T409	1		T280	1
auto[1879048192:2013265919]	11	1			T152	1		T273	1		T323	1
auto[2013265920:2147483647]	5	1			T152	1		T304	1		T410	1
auto[2147483648:2281701375]	7	1			T152	1		T307	1		T222	1
auto[2281701376:2415919103]	9	1			T123	1		T394	1		T259	1
auto[2415919104:2550136831]	8	1			T307	1		T359	1		T411	1
auto[2550136832:2684354559]	6	1			T154	1		T221	1		T410	1
auto[2684354560:2818572287]	10	1			T11	1		T323	1		T240	1
auto[2818572288:2952790015]	8	1			T1	1		T255	1		T323	1
auto[2952790016:3087007743]	7	1			T315	1		T411	1		T412	1
auto[3087007744:3221225471]	12	1			T11	1		T153	1		T239	1
auto[3221225472:3355443199]	10	1			T141	1		T255	1		T323	2
auto[3355443200:3489660927]	5	1			T221	1		T239	1		T413	1
auto[3489660928:3623878655]	5	1			T123	1		T152	1		T221	1
auto[3623878656:3758096383]	6	1			T123	1		T255	1		T315	1
auto[3758096384:3892314111]	9	1			T152	1		T141	1		T377	1
auto[3892314112:4026531839]	11	1			T221	1		T273	1		T359	1
auto[4026531840:4160749567]	9	1			T304	1		T408	1		T410	1
auto[4160749568:4294967295]	12	1			T255	1		T222	2		T408	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32389	1			T1	30		T2	21		T3	19
auto[0:134217727]	auto[1]	11	1			T11	1		T123	1		T222	1
auto[134217728:268435455]	auto[1]	7	1			T273	1		T307	1		T222	1
auto[268435456:402653183]	auto[1]	7	1			T255	1		T273	1		T323	1
auto[402653184:536870911]	auto[1]	4	1			T141	1		T307	1		T406	2
auto[536870912:671088639]	auto[1]	14	1			T152	2		T141	1		T222	1
auto[671088640:805306367]	auto[1]	10	1			T377	1		T307	1		T304	1
auto[805306368:939524095]	auto[1]	13	1			T152	1		T248	1		T394	1
auto[939524096:1073741823]	auto[1]	11	1			T11	2		T123	1		T359	1
auto[1073741824:1207959551]	auto[1]	8	1			T141	1		T359	1		T407	1
auto[1207959552:1342177279]	auto[1]	9	1			T239	2		T408	2		T280	1
auto[1342177280:1476395007]	auto[1]	12	1			T153	1		T221	2		T259	1
auto[1476395008:1610612735]	auto[1]	10	1			T376	1		T304	1		T222	1
auto[1610612736:1744830463]	auto[1]	16	1			T152	2		T304	1		T222	1
auto[1744830464:1879048191]	auto[1]	9	1			T152	2		T409	1		T280	1
auto[1879048192:2013265919]	auto[1]	11	1			T152	1		T273	1		T323	1
auto[2013265920:2147483647]	auto[1]	5	1			T152	1		T304	1		T410	1
auto[2147483648:2281701375]	auto[1]	7	1			T152	1		T307	1		T222	1
auto[2281701376:2415919103]	auto[1]	9	1			T123	1		T394	1		T259	1
auto[2415919104:2550136831]	auto[1]	8	1			T307	1		T359	1		T411	1
auto[2550136832:2684354559]	auto[1]	6	1			T154	1		T221	1		T410	1
auto[2684354560:2818572287]	auto[1]	10	1			T11	1		T323	1		T240	1
auto[2818572288:2952790015]	auto[1]	8	1			T1	1		T255	1		T323	1
auto[2952790016:3087007743]	auto[1]	7	1			T315	1		T411	1		T412	1
auto[3087007744:3221225471]	auto[1]	12	1			T11	1		T153	1		T239	1
auto[3221225472:3355443199]	auto[1]	10	1			T141	1		T255	1		T323	2
auto[3355443200:3489660927]	auto[1]	5	1			T221	1		T239	1		T413	1
auto[3489660928:3623878655]	auto[1]	5	1			T123	1		T152	1		T221	1
auto[3623878656:3758096383]	auto[1]	6	1			T123	1		T255	1		T315	1
auto[3758096384:3892314111]	auto[1]	9	1			T152	1		T141	1		T377	1
auto[3892314112:4026531839]	auto[1]	11	1			T221	1		T273	1		T359	1
auto[4026531840:4160749567]	auto[1]	9	1			T304	1		T408	1		T410	1
auto[4160749568:4294967295]	auto[1]	12	1			T255	1		T222	2		T408	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1591

1

T1

2

T11

2

T13

2

auto[1]

1767

1

T1

2

T11

2

T13

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T1	1		T17	1		T23	2
auto[134217728:268435455]	104	1			T36	1		T51	1		T201	1
auto[268435456:402653183]	109	1			T36	1		T44	1		T47	2
auto[402653184:536870911]	100	1			T16	1		T51	1		T150	1
auto[536870912:671088639]	106	1			T15	1		T16	1		T47	1
auto[671088640:805306367]	113	1			T13	1		T196	1		T49	1
auto[805306368:939524095]	94	1			T16	1		T4	1		T134	1
auto[939524096:1073741823]	98	1			T36	1		T47	1		T103	1
auto[1073741824:1207959551]	132	1			T1	1		T17	1		T36	2
auto[1207959552:1342177279]	103	1			T13	1		T17	1		T196	1
auto[1342177280:1476395007]	124	1			T13	1		T36	1		T51	1
auto[1476395008:1610612735]	94	1			T44	1		T204	1		T135	2
auto[1610612736:1744830463]	115	1			T11	1		T197	1		T44	2
auto[1744830464:1879048191]	119	1			T14	1		T196	1		T44	4
auto[1879048192:2013265919]	106	1			T1	1		T44	1		T199	1
auto[2013265920:2147483647]	92	1			T13	1		T14	1		T196	1
auto[2147483648:2281701375]	98	1			T26	1		T44	2		T4	1
auto[2281701376:2415919103]	102	1			T16	1		T23	1		T44	2
auto[2415919104:2550136831]	93	1			T16	1		T17	1		T26	1
auto[2550136832:2684354559]	112	1			T196	1		T51	1		T44	1
auto[2684354560:2818572287]	91	1			T51	1		T44	1		T234	1
auto[2818572288:2952790015]	102	1			T14	1		T16	1		T26	1
auto[2952790016:3087007743]	114	1			T26	1		T44	1		T199	1
auto[3087007744:3221225471]	102	1			T16	1		T36	1		T47	1
auto[3221225472:3355443199]	100	1			T13	2		T23	1		T44	1
auto[3355443200:3489660927]	100	1			T15	1		T16	1		T44	2
auto[3489660928:3623878655]	93	1			T36	1		T44	2		T95	1
auto[3623878656:3758096383]	118	1			T48	1		T123	1		T55	1
auto[3758096384:3892314111]	101	1			T11	1		T196	1		T150	1
auto[3892314112:4026531839]	98	1			T17	1		T23	1		T103	1
auto[4026531840:4160749567]	99	1			T1	1		T11	1		T44	1
auto[4160749568:4294967295]	122	1			T11	1		T48	1		T44	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T17	1		T268	1		T154	1
auto[0:134217727]	auto[1]	51	1			T1	1		T23	2		T44	1
auto[134217728:268435455]	auto[0]	54	1			T51	1		T234	1		T268	1
auto[134217728:268435455]	auto[1]	50	1			T36	1		T201	1		T65	2
auto[268435456:402653183]	auto[0]	49	1			T44	1		T47	1		T199	1
auto[268435456:402653183]	auto[1]	60	1			T36	1		T47	1		T242	1
auto[402653184:536870911]	auto[0]	46	1			T16	1		T51	1		T24	1
auto[402653184:536870911]	auto[1]	54	1			T150	1		T24	1		T228	1
auto[536870912:671088639]	auto[0]	51	1			T15	1		T16	1		T55	1
auto[536870912:671088639]	auto[1]	55	1			T47	1		T45	1		T118	1
auto[671088640:805306367]	auto[0]	46	1			T13	1		T234	1		T5	1
auto[671088640:805306367]	auto[1]	67	1			T196	1		T49	1		T27	1
auto[805306368:939524095]	auto[0]	44	1			T16	1		T4	1		T404	1
auto[805306368:939524095]	auto[1]	50	1			T134	1		T57	1		T228	1
auto[939524096:1073741823]	auto[0]	42	1			T36	1		T47	1		T248	1
auto[939524096:1073741823]	auto[1]	56	1			T103	1		T98	1		T70	1
auto[1073741824:1207959551]	auto[0]	58	1			T1	1		T17	1		T36	1
auto[1073741824:1207959551]	auto[1]	74	1			T36	1		T44	1		T47	1
auto[1207959552:1342177279]	auto[0]	43	1			T17	1		T233	1		T84	1
auto[1207959552:1342177279]	auto[1]	60	1			T13	1		T196	1		T150	1
auto[1342177280:1476395007]	auto[0]	52	1			T13	1		T36	1		T51	1
auto[1342177280:1476395007]	auto[1]	72	1			T50	1		T202	1		T57	2
auto[1476395008:1610612735]	auto[0]	50	1			T44	1		T204	1		T135	2
auto[1476395008:1610612735]	auto[1]	44	1			T141	2		T248	1		T72	1
auto[1610612736:1744830463]	auto[0]	64	1			T11	1		T197	1		T44	1
auto[1610612736:1744830463]	auto[1]	51	1			T44	1		T262	1		T351	1
auto[1744830464:1879048191]	auto[0]	63	1			T14	1		T44	4		T123	1
auto[1744830464:1879048191]	auto[1]	56	1			T196	1		T151	1		T28	1
auto[1879048192:2013265919]	auto[0]	41	1			T205	1		T57	1		T70	1
auto[1879048192:2013265919]	auto[1]	65	1			T1	1		T44	1		T199	1
auto[2013265920:2147483647]	auto[0]	41	1			T150	1		T24	1		T199	1
auto[2013265920:2147483647]	auto[1]	51	1			T13	1		T14	1		T196	1
auto[2147483648:2281701375]	auto[0]	54	1			T26	1		T44	1		T4	1
auto[2147483648:2281701375]	auto[1]	44	1			T44	1		T22	1		T68	2
auto[2281701376:2415919103]	auto[0]	55	1			T16	1		T44	1		T135	2
auto[2281701376:2415919103]	auto[1]	47	1			T23	1		T44	1		T19	1
auto[2415919104:2550136831]	auto[0]	49	1			T16	1		T17	1		T26	1
auto[2415919104:2550136831]	auto[1]	44	1			T23	1		T51	1		T118	1
auto[2550136832:2684354559]	auto[0]	61	1			T51	1		T44	1		T153	1
auto[2550136832:2684354559]	auto[1]	51	1			T196	1		T57	1		T72	2
auto[2684354560:2818572287]	auto[0]	42	1			T51	1		T234	1		T84	1
auto[2684354560:2818572287]	auto[1]	49	1			T44	1		T56	1		T85	1
auto[2818572288:2952790015]	auto[0]	48	1			T16	1		T197	1		T55	1
auto[2818572288:2952790015]	auto[1]	54	1			T14	1		T26	1		T137	1
auto[2952790016:3087007743]	auto[0]	53	1			T26	1		T200	1		T205	1
auto[2952790016:3087007743]	auto[1]	61	1			T44	1		T199	1		T152	1
auto[3087007744:3221225471]	auto[0]	47	1			T36	1		T45	2		T98	1
auto[3087007744:3221225471]	auto[1]	55	1			T16	1		T47	1		T150	1
auto[3221225472:3355443199]	auto[0]	43	1			T23	1		T44	1		T28	1
auto[3221225472:3355443199]	auto[1]	57	1			T13	2		T19	1		T204	1
auto[3355443200:3489660927]	auto[0]	42	1			T15	1		T44	2		T95	1
auto[3355443200:3489660927]	auto[1]	58	1			T16	1		T4	1		T134	2
auto[3489660928:3623878655]	auto[0]	47	1			T36	1		T95	1		T57	1
auto[3489660928:3623878655]	auto[1]	46	1			T44	2		T118	1		T46	1
auto[3623878656:3758096383]	auto[0]	56	1			T55	1		T90	1		T22	1
auto[3623878656:3758096383]	auto[1]	62	1			T48	1		T123	1		T199	1
auto[3758096384:3892314111]	auto[0]	43	1			T56	1		T57	1		T59	1
auto[3758096384:3892314111]	auto[1]	58	1			T11	1		T196	1		T150	1
auto[3892314112:4026531839]	auto[0]	49	1			T17	1		T23	1		T56	1
auto[3892314112:4026531839]	auto[1]	49	1			T103	1		T153	1		T201	1
auto[4026531840:4160749567]	auto[0]	50	1			T1	1		T44	1		T95	1
auto[4026531840:4160749567]	auto[1]	49	1			T11	1		T57	1		T5	1
auto[4160749568:4294967295]	auto[0]	55	1			T11	1		T44	2		T123	1
auto[4160749568:4294967295]	auto[1]	67	1			T48	1		T202	1		T118	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1606

1

T1

2

T11

1

T13

3

auto[1]

1752

1

T1

2

T11

3

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T13	1		T196	1		T44	3
auto[134217728:268435455]	85	1			T50	1		T153	2		T46	1
auto[268435456:402653183]	134	1			T17	1		T23	1		T44	1
auto[402653184:536870911]	90	1			T1	1		T15	1		T16	1
auto[536870912:671088639]	100	1			T103	1		T95	2		T98	1
auto[671088640:805306367]	96	1			T36	1		T51	1		T44	1
auto[805306368:939524095]	112	1			T36	1		T23	1		T44	3
auto[939524096:1073741823]	111	1			T16	1		T44	1		T49	1
auto[1073741824:1207959551]	90	1			T1	1		T16	1		T95	1
auto[1207959552:1342177279]	93	1			T16	1		T197	1		T44	2
auto[1342177280:1476395007]	107	1			T36	1		T44	1		T150	1
auto[1476395008:1610612735]	111	1			T44	1		T47	1		T45	1
auto[1610612736:1744830463]	100	1			T1	1		T51	1		T103	1
auto[1744830464:1879048191]	122	1			T196	1		T44	1		T4	1
auto[1879048192:2013265919]	116	1			T11	1		T26	1		T23	1
auto[2013265920:2147483647]	106	1			T11	2		T14	2		T17	1
auto[2147483648:2281701375]	106	1			T13	1		T17	1		T196	1
auto[2281701376:2415919103]	104	1			T26	1		T48	1		T150	1
auto[2415919104:2550136831]	109	1			T15	1		T26	1		T197	1
auto[2550136832:2684354559]	111	1			T1	1		T44	1		T152	1
auto[2684354560:2818572287]	106	1			T36	1		T51	1		T44	1
auto[2818572288:2952790015]	106	1			T44	2		T4	2		T90	1
auto[2952790016:3087007743]	111	1			T11	1		T16	2		T51	1
auto[3087007744:3221225471]	108	1			T17	1		T23	1		T55	2
auto[3221225472:3355443199]	101	1			T13	1		T16	1		T17	1
auto[3355443200:3489660927]	101	1			T13	2		T44	1		T123	1
auto[3489660928:3623878655]	87	1			T196	1		T23	1		T28	1
auto[3623878656:3758096383]	104	1			T51	1		T44	1		T199	1
auto[3758096384:3892314111]	98	1			T197	1		T48	1		T51	1
auto[3892314112:4026531839]	93	1			T14	1		T16	1		T23	1
auto[4026531840:4160749567]	108	1			T26	1		T36	1		T44	2
auto[4160749568:4294967295]	126	1			T13	1		T36	1		T150	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T44	2		T242	1		T84	1
auto[0:134217727]	auto[1]	60	1			T13	1		T196	1		T44	1
auto[134217728:268435455]	auto[0]	47	1			T46	1		T104	1		T233	1
auto[134217728:268435455]	auto[1]	38	1			T50	1		T153	2		T57	1
auto[268435456:402653183]	auto[0]	69	1			T17	1		T44	1		T123	1
auto[268435456:402653183]	auto[1]	65	1			T23	1		T90	1		T57	1
auto[402653184:536870911]	auto[0]	40	1			T15	1		T16	1		T36	1
auto[402653184:536870911]	auto[1]	50	1			T1	1		T196	2		T44	1
auto[536870912:671088639]	auto[0]	44	1			T103	1		T95	1		T98	1
auto[536870912:671088639]	auto[1]	56	1			T95	1		T59	1		T37	1
auto[671088640:805306367]	auto[0]	54	1			T36	1		T51	1		T24	1
auto[671088640:805306367]	auto[1]	42	1			T44	1		T260	2		T66	1
auto[805306368:939524095]	auto[0]	50	1			T36	1		T23	1		T44	3
auto[805306368:939524095]	auto[1]	62	1			T150	1		T201	1		T57	1
auto[939524096:1073741823]	auto[0]	55	1			T199	1		T56	1		T57	1
auto[939524096:1073741823]	auto[1]	56	1			T16	1		T44	1		T49	1
auto[1073741824:1207959551]	auto[0]	36	1			T1	1		T135	1		T59	1
auto[1073741824:1207959551]	auto[1]	54	1			T16	1		T95	1		T22	1
auto[1207959552:1342177279]	auto[0]	55	1			T16	1		T197	1		T44	2
auto[1207959552:1342177279]	auto[1]	38	1			T202	1		T57	1		T154	1
auto[1342177280:1476395007]	auto[0]	58	1			T44	1		T137	1		T203	1
auto[1342177280:1476395007]	auto[1]	49	1			T36	1		T150	1		T201	1
auto[1476395008:1610612735]	auto[0]	59	1			T44	1		T45	1		T50	1
auto[1476395008:1610612735]	auto[1]	52	1			T47	1		T152	1		T57	2
auto[1610612736:1744830463]	auto[0]	51	1			T103	1		T199	1		T46	1
auto[1610612736:1744830463]	auto[1]	49	1			T1	1		T51	1		T27	1
auto[1744830464:1879048191]	auto[0]	49	1			T44	1		T45	1		T104	1
auto[1744830464:1879048191]	auto[1]	73	1			T196	1		T4	1		T45	1
auto[1879048192:2013265919]	auto[0]	53	1			T26	1		T55	1		T103	1
auto[1879048192:2013265919]	auto[1]	63	1			T11	1		T23	1		T44	1
auto[2013265920:2147483647]	auto[0]	46	1			T11	1		T17	1		T103	1
auto[2013265920:2147483647]	auto[1]	60	1			T11	1		T14	2		T36	1
auto[2147483648:2281701375]	auto[0]	50	1			T13	1		T17	1		T4	1
auto[2147483648:2281701375]	auto[1]	56	1			T196	1		T19	1		T199	1
auto[2281701376:2415919103]	auto[0]	45	1			T26	1		T55	1		T45	1
auto[2281701376:2415919103]	auto[1]	59	1			T48	1		T150	1		T118	1
auto[2415919104:2550136831]	auto[0]	48	1			T15	1		T44	1		T57	2
auto[2415919104:2550136831]	auto[1]	61	1			T26	1		T197	1		T47	1
auto[2550136832:2684354559]	auto[0]	58	1			T1	1		T73	1		T91	1
auto[2550136832:2684354559]	auto[1]	53	1			T44	1		T152	1		T56	1
auto[2684354560:2818572287]	auto[0]	60	1			T51	1		T44	1		T45	1
auto[2684354560:2818572287]	auto[1]	46	1			T36	1		T199	1		T5	1
auto[2818572288:2952790015]	auto[0]	45	1			T44	1		T4	2		T95	1
auto[2818572288:2952790015]	auto[1]	61	1			T44	1		T90	1		T141	1
auto[2952790016:3087007743]	auto[0]	57	1			T16	1		T51	1		T153	1
auto[2952790016:3087007743]	auto[1]	54	1			T11	1		T16	1		T50	1
auto[3087007744:3221225471]	auto[0]	46	1			T17	1		T55	1		T19	1
auto[3087007744:3221225471]	auto[1]	62	1			T23	1		T55	1		T103	1
auto[3221225472:3355443199]	auto[0]	52	1			T13	1		T16	1		T17	1
auto[3221225472:3355443199]	auto[1]	49	1			T22	1		T357	1		T68	1
auto[3355443200:3489660927]	auto[0]	43	1			T44	1		T123	1		T204	1
auto[3355443200:3489660927]	auto[1]	58	1			T13	2		T199	1		T153	1
auto[3489660928:3623878655]	auto[0]	42	1			T91	1		T70	1		T88	1
auto[3489660928:3623878655]	auto[1]	45	1			T196	1		T23	1		T28	1
auto[3623878656:3758096383]	auto[0]	44	1			T90	1		T135	1		T56	1
auto[3623878656:3758096383]	auto[1]	60	1			T51	1		T44	1		T199	1
auto[3758096384:3892314111]	auto[0]	53	1			T51	1		T44	1		T47	1
auto[3758096384:3892314111]	auto[1]	45	1			T197	1		T48	1		T242	1
auto[3892314112:4026531839]	auto[0]	44	1			T14	1		T16	1		T44	1
auto[3892314112:4026531839]	auto[1]	49	1			T23	1		T137	1		T242	1
auto[4026531840:4160749567]	auto[0]	47	1			T26	1		T36	1		T44	1
auto[4026531840:4160749567]	auto[1]	61	1			T44	1		T47	1		T134	1
auto[4160749568:4294967295]	auto[0]	60	1			T13	1		T36	1		T45	1
auto[4160749568:4294967295]	auto[1]	66	1			T150	1		T204	1		T202	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1616

1

T1

2

T11

2

T13

2

auto[1]

1741

1

T1

2

T11

2

T13

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T196	1		T95	1		T73	1
auto[134217728:268435455]	100	1			T1	1		T51	1		T44	2
auto[268435456:402653183]	100	1			T13	2		T16	1		T44	2
auto[402653184:536870911]	90	1			T17	1		T150	1		T19	2
auto[536870912:671088639]	118	1			T49	1		T4	1		T201	1
auto[671088640:805306367]	100	1			T196	1		T123	1		T47	1
auto[805306368:939524095]	94	1			T16	1		T23	1		T51	2
auto[939524096:1073741823]	82	1			T44	1		T73	1		T98	1
auto[1073741824:1207959551]	112	1			T13	1		T16	1		T26	1
auto[1207959552:1342177279]	85	1			T44	1		T55	1		T199	1
auto[1342177280:1476395007]	99	1			T11	1		T45	1		T201	1
auto[1476395008:1610612735]	100	1			T14	1		T44	2		T55	1
auto[1610612736:1744830463]	108	1			T196	1		T4	1		T199	1
auto[1744830464:1879048191]	120	1			T17	1		T36	1		T44	1
auto[1879048192:2013265919]	110	1			T44	2		T103	1		T204	1
auto[2013265920:2147483647]	102	1			T36	1		T44	2		T137	1
auto[2147483648:2281701375]	105	1			T197	1		T44	1		T47	1
auto[2281701376:2415919103]	110	1			T11	1		T14	1		T17	1
auto[2415919104:2550136831]	117	1			T17	1		T196	1		T36	1
auto[2550136832:2684354559]	116	1			T15	1		T197	1		T51	1
auto[2684354560:2818572287]	106	1			T36	1		T23	1		T199	1
auto[2818572288:2952790015]	109	1			T44	1		T204	1		T200	1
auto[2952790016:3087007743]	102	1			T13	1		T26	1		T23	1
auto[3087007744:3221225471]	105	1			T11	1		T26	1		T36	1
auto[3221225472:3355443199]	101	1			T13	1		T16	1		T44	1
auto[3355443200:3489660927]	118	1			T23	1		T48	1		T51	1
auto[3489660928:3623878655]	116	1			T13	1		T16	2		T196	1
auto[3623878656:3758096383]	107	1			T1	1		T16	1		T51	1
auto[3758096384:3892314111]	106	1			T15	1		T44	2		T202	1
auto[3892314112:4026531839]	107	1			T14	1		T16	1		T17	1
auto[4026531840:4160749567]	95	1			T11	1		T23	1		T44	2
auto[4160749568:4294967295]	112	1			T1	2		T23	1		T44	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T95	1		T98	1		T205	1
auto[0:134217727]	auto[1]	46	1			T196	1		T73	1		T57	1
auto[134217728:268435455]	auto[0]	51	1			T44	1		T153	1		T233	1
auto[134217728:268435455]	auto[1]	49	1			T1	1		T51	1		T44	1
auto[268435456:402653183]	auto[0]	42	1			T13	1		T16	1		T44	1
auto[268435456:402653183]	auto[1]	58	1			T13	1		T44	1		T4	1
auto[402653184:536870911]	auto[0]	43	1			T17	1		T91	1		T72	1
auto[402653184:536870911]	auto[1]	47	1			T150	1		T19	2		T57	1
auto[536870912:671088639]	auto[0]	56	1			T4	1		T201	1		T57	1
auto[536870912:671088639]	auto[1]	62	1			T49	1		T98	1		T242	1
auto[671088640:805306367]	auto[0]	45	1			T47	1		T95	1		T73	1
auto[671088640:805306367]	auto[1]	55	1			T196	1		T123	1		T118	1
auto[805306368:939524095]	auto[0]	46	1			T16	1		T23	1		T51	2
auto[805306368:939524095]	auto[1]	48	1			T57	1		T93	1		T357	1
auto[939524096:1073741823]	auto[0]	39	1			T98	1		T70	1		T268	1
auto[939524096:1073741823]	auto[1]	43	1			T44	1		T73	1		T205	1
auto[1073741824:1207959551]	auto[0]	57	1			T13	1		T16	1		T26	1
auto[1073741824:1207959551]	auto[1]	55	1			T47	1		T118	1		T57	1
auto[1207959552:1342177279]	auto[0]	37	1			T44	1		T55	1		T98	1
auto[1207959552:1342177279]	auto[1]	48	1			T199	1		T141	1		T155	2
auto[1342177280:1476395007]	auto[0]	48	1			T11	1		T45	1		T201	1
auto[1342177280:1476395007]	auto[1]	51	1			T242	1		T57	1		T60	1
auto[1476395008:1610612735]	auto[0]	53	1			T44	2		T55	1		T45	1
auto[1476395008:1610612735]	auto[1]	47	1			T14	1		T151	1		T134	1
auto[1610612736:1744830463]	auto[0]	52	1			T4	1		T199	1		T141	1
auto[1610612736:1744830463]	auto[1]	56	1			T196	1		T50	1		T202	1
auto[1744830464:1879048191]	auto[0]	59	1			T17	1		T123	1		T153	1
auto[1744830464:1879048191]	auto[1]	61	1			T36	1		T44	1		T28	1
auto[1879048192:2013265919]	auto[0]	48	1			T44	1		T204	1		T135	1
auto[1879048192:2013265919]	auto[1]	62	1			T44	1		T103	1		T95	1
auto[2013265920:2147483647]	auto[0]	49	1			T36	1		T44	2		T137	1
auto[2013265920:2147483647]	auto[1]	53	1			T57	1		T223	1		T293	1
auto[2147483648:2281701375]	auto[0]	50	1			T44	1		T24	1		T242	1
auto[2147483648:2281701375]	auto[1]	55	1			T197	1		T47	1		T28	1
auto[2281701376:2415919103]	auto[0]	51	1			T11	1		T14	1		T17	1
auto[2281701376:2415919103]	auto[1]	59	1			T150	1		T55	1		T90	1
auto[2415919104:2550136831]	auto[0]	60	1			T17	1		T36	1		T55	1
auto[2415919104:2550136831]	auto[1]	57	1			T196	1		T150	1		T90	1
auto[2550136832:2684354559]	auto[0]	64	1			T15	1		T197	1		T51	1
auto[2550136832:2684354559]	auto[1]	52	1			T20	1		T57	1		T228	1
auto[2684354560:2818572287]	auto[0]	46	1			T104	2		T84	1		T88	1
auto[2684354560:2818572287]	auto[1]	60	1			T36	1		T23	1		T199	1
auto[2818572288:2952790015]	auto[0]	45	1			T57	1		T154	1		T5	2
auto[2818572288:2952790015]	auto[1]	64	1			T44	1		T204	1		T200	1
auto[2952790016:3087007743]	auto[0]	44	1			T26	1		T55	1		T45	1
auto[2952790016:3087007743]	auto[1]	58	1			T13	1		T23	1		T103	1
auto[3087007744:3221225471]	auto[0]	44	1			T36	1		T95	1		T73	1
auto[3087007744:3221225471]	auto[1]	61	1			T11	1		T26	1		T48	1
auto[3221225472:3355443199]	auto[0]	57	1			T44	1		T150	1		T200	1
auto[3221225472:3355443199]	auto[1]	44	1			T13	1		T16	1		T248	1
auto[3355443200:3489660927]	auto[0]	57	1			T51	1		T44	1		T205	1
auto[3355443200:3489660927]	auto[1]	61	1			T23	1		T48	1		T199	1
auto[3489660928:3623878655]	auto[0]	60	1			T16	1		T44	1		T55	1
auto[3489660928:3623878655]	auto[1]	56	1			T13	1		T16	1		T196	1
auto[3623878656:3758096383]	auto[0]	50	1			T51	1		T24	1		T46	1
auto[3623878656:3758096383]	auto[1]	57	1			T1	1		T16	1		T47	1
auto[3758096384:3892314111]	auto[0]	54	1			T15	1		T44	1		T135	1
auto[3758096384:3892314111]	auto[1]	52	1			T44	1		T202	1		T248	1
auto[3892314112:4026531839]	auto[0]	56	1			T16	1		T17	1		T44	1
auto[3892314112:4026531839]	auto[1]	51	1			T14	1		T26	1		T196	1
auto[4026531840:4160749567]	auto[0]	39	1			T44	1		T24	1		T57	1
auto[4026531840:4160749567]	auto[1]	56	1			T11	1		T23	1		T44	1
auto[4160749568:4294967295]	auto[0]	55	1			T1	2		T23	1		T44	1
auto[4160749568:4294967295]	auto[1]	57	1			T44	1		T47	1		T150	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1630

1

T1

2

T11

3

T13

3

auto[1]

1727

1

T1

2

T11

1

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	124	1			T16	1		T36	1		T150	1
auto[134217728:268435455]	91	1			T17	1		T26	1		T36	1
auto[268435456:402653183]	119	1			T11	1		T47	1		T19	2
auto[402653184:536870911]	84	1			T26	1		T44	1		T150	1
auto[536870912:671088639]	110	1			T13	1		T36	1		T44	1
auto[671088640:805306367]	104	1			T197	1		T202	1		T118	1
auto[805306368:939524095]	98	1			T11	1		T151	1		T45	1
auto[939524096:1073741823]	109	1			T17	1		T44	1		T45	1
auto[1073741824:1207959551]	128	1			T1	1		T13	1		T16	1
auto[1207959552:1342177279]	97	1			T15	1		T196	1		T44	2
auto[1342177280:1476395007]	108	1			T4	1		T55	1		T199	1
auto[1476395008:1610612735]	115	1			T1	1		T13	1		T36	1
auto[1610612736:1744830463]	95	1			T55	1		T27	1		T45	1
auto[1744830464:1879048191]	113	1			T17	1		T23	1		T44	3
auto[1879048192:2013265919]	94	1			T44	2		T134	1		T234	1
auto[2013265920:2147483647]	86	1			T16	1		T23	1		T47	1
auto[2147483648:2281701375]	104	1			T1	1		T13	1		T48	1
auto[2281701376:2415919103]	102	1			T13	1		T14	1		T17	1
auto[2415919104:2550136831]	102	1			T23	1		T51	1		T44	2
auto[2550136832:2684354559]	89	1			T16	1		T36	1		T197	1
auto[2684354560:2818572287]	104	1			T16	1		T103	1		T152	1
auto[2818572288:2952790015]	129	1			T16	1		T123	1		T103	1
auto[2952790016:3087007743]	104	1			T11	1		T26	1		T23	1
auto[3087007744:3221225471]	97	1			T36	1		T48	1		T44	1
auto[3221225472:3355443199]	110	1			T14	1		T16	1		T196	1
auto[3355443200:3489660927]	108	1			T14	1		T36	1		T51	1
auto[3489660928:3623878655]	92	1			T16	1		T196	1		T44	1
auto[3623878656:3758096383]	120	1			T1	1		T44	2		T24	1
auto[3758096384:3892314111]	108	1			T15	1		T26	1		T196	1
auto[3892314112:4026531839]	103	1			T197	1		T55	1		T234	1
auto[4026531840:4160749567]	99	1			T13	1		T17	1		T44	2
auto[4160749568:4294967295]	111	1			T11	1		T196	1		T23	1