Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2967

1

T1

4

T11

4

T13

6

auto[1]

262

1

T1

4

T11

6

T123

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T123	1		T55	1		T152	1
auto[134217728:268435455]	96	1			T197	1		T51	1		T123	1
auto[268435456:402653183]	79	1			T11	1		T196	1		T50	1
auto[402653184:536870911]	107	1			T1	2		T23	1		T55	1
auto[536870912:671088639]	116	1			T36	1		T51	1		T123	1
auto[671088640:805306367]	81	1			T11	1		T14	1		T16	1
auto[805306368:939524095]	88	1			T1	1		T17	1		T23	1
auto[939524096:1073741823]	93	1			T11	1		T47	1		T50	1
auto[1073741824:1207959551]	111	1			T13	1		T55	1		T201	1
auto[1207959552:1342177279]	99	1			T26	1		T196	1		T44	2
auto[1342177280:1476395007]	106	1			T36	1		T123	1		T4	1
auto[1476395008:1610612735]	114	1			T14	1		T51	1		T44	1
auto[1610612736:1744830463]	105	1			T13	1		T16	1		T17	1
auto[1744830464:1879048191]	117	1			T36	1		T152	1		T118	1
auto[1879048192:2013265919]	96	1			T1	2		T11	1		T16	1
auto[2013265920:2147483647]	104	1			T11	1		T13	1		T48	2
auto[2147483648:2281701375]	102	1			T13	1		T26	1		T36	1
auto[2281701376:2415919103]	100	1			T16	3		T17	1		T36	1
auto[2415919104:2550136831]	101	1			T26	1		T44	1		T47	1
auto[2550136832:2684354559]	86	1			T51	1		T123	2		T103	1
auto[2684354560:2818572287]	93	1			T11	1		T13	1		T16	1
auto[2818572288:2952790015]	90	1			T44	2		T153	1		T201	1
auto[2952790016:3087007743]	94	1			T11	1		T15	1		T196	1
auto[3087007744:3221225471]	108	1			T123	1		T150	3		T55	1
auto[3221225472:3355443199]	113	1			T103	1		T90	1		T153	1
auto[3355443200:3489660927]	97	1			T1	1		T51	1		T44	1
auto[3489660928:3623878655]	91	1			T1	1		T11	1		T196	1
auto[3623878656:3758096383]	113	1			T1	1		T23	1		T44	1
auto[3758096384:3892314111]	125	1			T11	1		T13	1		T26	1
auto[3892314112:4026531839]	93	1			T23	1		T44	2		T24	1
auto[4026531840:4160749567]	116	1			T14	1		T16	1		T17	1
auto[4160749568:4294967295]	95	1			T11	1		T36	1		T44	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	88	1			T55	1		T28	1		T134	1
auto[0:134217727]	auto[1]	12	1			T123	1		T152	1		T255	1
auto[134217728:268435455]	auto[0]	89	1			T197	1		T51	1		T118	1
auto[134217728:268435455]	auto[1]	7	1			T123	1		T255	1		T239	1
auto[268435456:402653183]	auto[0]	71	1			T196	1		T50	1		T137	1
auto[268435456:402653183]	auto[1]	8	1			T11	1		T153	1		T408	1
auto[402653184:536870911]	auto[0]	95	1			T1	2		T23	1		T55	1
auto[402653184:536870911]	auto[1]	12	1			T153	1		T273	1		T307	1
auto[536870912:671088639]	auto[0]	104	1			T36	1		T51	1		T123	1
auto[536870912:671088639]	auto[1]	12	1			T152	2		T222	1		T323	1
auto[671088640:805306367]	auto[0]	72	1			T14	1		T16	1		T196	1
auto[671088640:805306367]	auto[1]	9	1			T11	1		T273	1		T304	1
auto[805306368:939524095]	auto[0]	85	1			T1	1		T17	1		T23	1
auto[805306368:939524095]	auto[1]	3	1			T123	1		T409	1		T418	1
auto[939524096:1073741823]	auto[0]	87	1			T11	1		T47	1		T50	1
auto[939524096:1073741823]	auto[1]	6	1			T273	1		T222	1		T411	2
auto[1073741824:1207959551]	auto[0]	104	1			T13	1		T55	1		T201	1
auto[1073741824:1207959551]	auto[1]	7	1			T240	1		T414	1		T406	1
auto[1207959552:1342177279]	auto[0]	92	1			T26	1		T196	1		T44	2
auto[1207959552:1342177279]	auto[1]	7	1			T123	1		T152	1		T255	1
auto[1342177280:1476395007]	auto[0]	98	1			T36	1		T4	1		T73	1
auto[1342177280:1476395007]	auto[1]	8	1			T123	1		T394	1		T376	1
auto[1476395008:1610612735]	auto[0]	103	1			T14	1		T51	1		T44	1
auto[1476395008:1610612735]	auto[1]	11	1			T123	1		T153	1		T248	1
auto[1610612736:1744830463]	auto[0]	97	1			T13	1		T16	1		T17	1
auto[1610612736:1744830463]	auto[1]	8	1			T153	1		T376	1		T239	1
auto[1744830464:1879048191]	auto[0]	107	1			T36	1		T118	1		T141	1
auto[1744830464:1879048191]	auto[1]	10	1			T152	1		T376	1		T307	1
auto[1879048192:2013265919]	auto[0]	82	1			T1	1		T16	1		T51	1
auto[1879048192:2013265919]	auto[1]	14	1			T1	1		T11	1		T152	1
auto[2013265920:2147483647]	auto[0]	99	1			T11	1		T13	1		T48	2
auto[2013265920:2147483647]	auto[1]	5	1			T248	1		T376	1		T273	1
auto[2147483648:2281701375]	auto[0]	92	1			T13	1		T26	1		T36	1
auto[2147483648:2281701375]	auto[1]	10	1			T154	2		T255	1		T359	1
auto[2281701376:2415919103]	auto[0]	96	1			T16	3		T17	1		T36	1
auto[2281701376:2415919103]	auto[1]	4	1			T141	1		T239	1		T359	1
auto[2415919104:2550136831]	auto[0]	90	1			T26	1		T44	1		T47	1
auto[2415919104:2550136831]	auto[1]	11	1			T228	1		T394	1		T221	1
auto[2550136832:2684354559]	auto[0]	79	1			T51	1		T123	1		T103	1
auto[2550136832:2684354559]	auto[1]	7	1			T123	1		T152	1		T376	1
auto[2684354560:2818572287]	auto[0]	86	1			T13	1		T16	1		T17	1
auto[2684354560:2818572287]	auto[1]	7	1			T11	1		T255	1		T359	1
auto[2818572288:2952790015]	auto[0]	82	1			T44	2		T201	1		T141	1
auto[2818572288:2952790015]	auto[1]	8	1			T153	1		T273	1		T307	1
auto[2952790016:3087007743]	auto[0]	85	1			T15	1		T196	1		T44	1
auto[2952790016:3087007743]	auto[1]	9	1			T11	1		T153	1		T307	1
auto[3087007744:3221225471]	auto[0]	101	1			T123	1		T150	3		T55	1
auto[3087007744:3221225471]	auto[1]	7	1			T141	1		T222	1		T407	1
auto[3221225472:3355443199]	auto[0]	107	1			T103	1		T90	1		T98	1
auto[3221225472:3355443199]	auto[1]	6	1			T153	1		T221	1		T414	2
auto[3355443200:3489660927]	auto[0]	89	1			T51	1		T44	1		T47	2
auto[3355443200:3489660927]	auto[1]	8	1			T1	1		T123	1		T273	1
auto[3489660928:3623878655]	auto[0]	84	1			T196	1		T44	1		T123	1
auto[3489660928:3623878655]	auto[1]	7	1			T1	1		T11	1		T152	1
auto[3623878656:3758096383]	auto[0]	103	1			T23	1		T44	1		T103	1
auto[3623878656:3758096383]	auto[1]	10	1			T1	1		T123	1		T152	2
auto[3758096384:3892314111]	auto[0]	114	1			T11	1		T13	1		T26	1
auto[3758096384:3892314111]	auto[1]	11	1			T141	2		T222	1		T240	1
auto[3892314112:4026531839]	auto[0]	86	1			T23	1		T44	2		T24	1
auto[3892314112:4026531839]	auto[1]	7	1			T141	1		T239	1		T259	1
auto[4026531840:4160749567]	auto[0]	109	1			T14	1		T16	1		T17	1
auto[4026531840:4160749567]	auto[1]	7	1			T255	1		T359	1		T323	1
auto[4160749568:4294967295]	auto[0]	91	1			T11	1		T36	1		T44	2
auto[4160749568:4294967295]	auto[1]	4	1			T359	1		T323	1		T280	2