Unified Coverage Report :: Group Instance : attest_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1611

1

T1

2

T11

2

T13

4

auto[1]

1746

1

T1

2

T11

2

T13

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T14	1		T26	1		T123	1
auto[134217728:268435455]	101	1			T1	1		T17	1		T26	1
auto[268435456:402653183]	98	1			T11	1		T23	1		T48	1
auto[402653184:536870911]	117	1			T13	1		T15	1		T16	2
auto[536870912:671088639]	105	1			T196	1		T51	1		T44	1
auto[671088640:805306367]	111	1			T17	1		T26	1		T44	2
auto[805306368:939524095]	89	1			T1	1		T11	1		T202	1
auto[939524096:1073741823]	97	1			T11	1		T17	1		T47	1
auto[1073741824:1207959551]	106	1			T51	1		T44	1		T4	1
auto[1207959552:1342177279]	114	1			T16	1		T23	1		T44	3
auto[1342177280:1476395007]	93	1			T13	1		T14	1		T23	1
auto[1476395008:1610612735]	104	1			T44	1		T55	2		T153	1
auto[1610612736:1744830463]	114	1			T15	1		T44	3		T123	1
auto[1744830464:1879048191]	103	1			T13	1		T196	1		T51	1
auto[1879048192:2013265919]	94	1			T55	1		T90	1		T153	1
auto[2013265920:2147483647]	92	1			T4	1		T103	1		T95	1
auto[2147483648:2281701375]	94	1			T26	1		T23	1		T197	1
auto[2281701376:2415919103]	100	1			T196	1		T44	1		T152	1
auto[2415919104:2550136831]	109	1			T1	1		T16	1		T196	1
auto[2550136832:2684354559]	111	1			T17	1		T196	1		T36	3
auto[2684354560:2818572287]	105	1			T16	1		T23	1		T199	2
auto[2818572288:2952790015]	113	1			T11	1		T36	1		T44	2
auto[2952790016:3087007743]	93	1			T196	1		T44	1		T201	1
auto[3087007744:3221225471]	85	1			T23	1		T197	1		T24	1
auto[3221225472:3355443199]	110	1			T13	1		T44	1		T24	1
auto[3355443200:3489660927]	93	1			T36	1		T44	2		T47	1
auto[3489660928:3623878655]	107	1			T13	1		T45	1		T134	1
auto[3623878656:3758096383]	134	1			T13	1		T44	1		T151	1
auto[3758096384:3892314111]	131	1			T16	1		T153	1		T200	2
auto[3892314112:4026531839]	104	1			T14	1		T16	1		T17	1
auto[4026531840:4160749567]	119	1			T1	1		T16	1		T44	2
auto[4160749568:4294967295]	108	1			T36	1		T44	1		T103	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	39	1			T26	1		T4	1		T210	1
auto[0:134217727]	auto[1]	64	1			T14	1		T123	1		T47	1
auto[134217728:268435455]	auto[0]	46	1			T17	1		T66	1		T404	1
auto[134217728:268435455]	auto[1]	55	1			T1	1		T26	1		T44	1
auto[268435456:402653183]	auto[0]	49	1			T23	1		T51	1		T24	1
auto[268435456:402653183]	auto[1]	49	1			T11	1		T48	1		T242	1
auto[402653184:536870911]	auto[0]	64	1			T13	1		T15	1		T16	2
auto[402653184:536870911]	auto[1]	53	1			T197	1		T46	1		T242	1
auto[536870912:671088639]	auto[0]	51	1			T204	1		T45	1		T134	1
auto[536870912:671088639]	auto[1]	54	1			T196	1		T51	1		T44	1
auto[671088640:805306367]	auto[0]	52	1			T17	1		T26	1		T55	1
auto[671088640:805306367]	auto[1]	59	1			T44	2		T150	1		T153	1
auto[805306368:939524095]	auto[0]	40	1			T1	1		T73	1		T84	1
auto[805306368:939524095]	auto[1]	49	1			T11	1		T202	1		T137	1
auto[939524096:1073741823]	auto[0]	46	1			T11	1		T17	1		T205	1
auto[939524096:1073741823]	auto[1]	51	1			T47	1		T27	1		T50	1
auto[1073741824:1207959551]	auto[0]	50	1			T51	1		T44	1		T4	1
auto[1073741824:1207959551]	auto[1]	56	1			T199	1		T73	1		T268	1
auto[1207959552:1342177279]	auto[0]	58	1			T16	1		T23	1		T44	2
auto[1207959552:1342177279]	auto[1]	56	1			T44	1		T204	1		T248	1
auto[1342177280:1476395007]	auto[0]	42	1			T13	1		T47	1		T103	1
auto[1342177280:1476395007]	auto[1]	51	1			T14	1		T23	1		T51	1
auto[1476395008:1610612735]	auto[0]	48	1			T44	1		T55	1		T153	1
auto[1476395008:1610612735]	auto[1]	56	1			T55	1		T59	1		T84	1
auto[1610612736:1744830463]	auto[0]	64	1			T15	1		T44	1		T123	1
auto[1610612736:1744830463]	auto[1]	50	1			T44	2		T150	1		T137	1
auto[1744830464:1879048191]	auto[0]	51	1			T51	1		T44	1		T137	1
auto[1744830464:1879048191]	auto[1]	52	1			T13	1		T196	1		T202	1
auto[1879048192:2013265919]	auto[0]	40	1			T55	1		T56	1		T268	1
auto[1879048192:2013265919]	auto[1]	54	1			T90	1		T153	1		T20	1
auto[2013265920:2147483647]	auto[0]	43	1			T4	1		T95	1		T234	1
auto[2013265920:2147483647]	auto[1]	49	1			T103	1		T134	1		T22	1
auto[2147483648:2281701375]	auto[0]	46	1			T23	1		T197	1		T44	1
auto[2147483648:2281701375]	auto[1]	48	1			T26	1		T57	1		T268	1
auto[2281701376:2415919103]	auto[0]	41	1			T44	1		T73	1		T205	1
auto[2281701376:2415919103]	auto[1]	59	1			T196	1		T152	1		T141	1
auto[2415919104:2550136831]	auto[0]	44	1			T16	1		T22	1		T104	1
auto[2415919104:2550136831]	auto[1]	65	1			T1	1		T196	1		T48	1
auto[2550136832:2684354559]	auto[0]	59	1			T17	1		T36	3		T44	1
auto[2550136832:2684354559]	auto[1]	52	1			T196	1		T44	1		T47	1
auto[2684354560:2818572287]	auto[0]	50	1			T16	1		T199	1		T45	1
auto[2684354560:2818572287]	auto[1]	55	1			T23	1		T199	1		T56	1
auto[2818572288:2952790015]	auto[0]	54	1			T11	1		T44	1		T103	1
auto[2818572288:2952790015]	auto[1]	59	1			T36	1		T44	1		T150	1
auto[2952790016:3087007743]	auto[0]	47	1			T44	1		T57	2		T84	1
auto[2952790016:3087007743]	auto[1]	46	1			T196	1		T201	1		T57	2
auto[3087007744:3221225471]	auto[0]	47	1			T197	1		T24	1		T95	1
auto[3087007744:3221225471]	auto[1]	38	1			T23	1		T72	2		T65	1
auto[3221225472:3355443199]	auto[0]	50	1			T13	1		T44	1		T24	1
auto[3221225472:3355443199]	auto[1]	60	1			T118	1		T98	1		T248	1
auto[3355443200:3489660927]	auto[0]	42	1			T36	1		T19	1		T141	1
auto[3355443200:3489660927]	auto[1]	51	1			T44	2		T47	1		T150	1
auto[3489660928:3623878655]	auto[0]	55	1			T13	1		T45	1		T57	2
auto[3489660928:3623878655]	auto[1]	52	1			T134	1		T57	1		T69	1
auto[3623878656:3758096383]	auto[0]	73	1			T44	1		T98	1		T46	2
auto[3623878656:3758096383]	auto[1]	61	1			T13	1		T151	1		T248	1
auto[3758096384:3892314111]	auto[0]	59	1			T153	1		T200	1		T135	1
auto[3758096384:3892314111]	auto[1]	72	1			T16	1		T200	1		T223	1
auto[3892314112:4026531839]	auto[0]	53	1			T14	1		T17	1		T51	1
auto[3892314112:4026531839]	auto[1]	51	1			T16	1		T36	1		T103	1
auto[4026531840:4160749567]	auto[0]	59	1			T1	1		T16	1		T44	2
auto[4026531840:4160749567]	auto[1]	60	1			T199	1		T357	1		T232	1
auto[4160749568:4294967295]	auto[0]	49	1			T44	1		T103	1		T56	1
auto[4160749568:4294967295]	auto[1]	59	1			T36	1		T24	1		T152	1