Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.04 98.15 98.24 100.00 99.02 98.41 91.17


Total test records in report: 1087
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T1006 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4040350913 Jun 09 12:43:30 PM PDT 24 Jun 09 12:43:32 PM PDT 24 13043988 ps
T1007 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2920475056 Jun 09 12:43:28 PM PDT 24 Jun 09 12:43:39 PM PDT 24 1747980942 ps
T1008 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3379197374 Jun 09 12:43:06 PM PDT 24 Jun 09 12:43:07 PM PDT 24 15146048 ps
T1009 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.816197677 Jun 09 12:43:12 PM PDT 24 Jun 09 12:43:17 PM PDT 24 279257347 ps
T165 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4063108817 Jun 09 12:43:18 PM PDT 24 Jun 09 12:43:27 PM PDT 24 433306533 ps
T1010 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2604196522 Jun 09 12:43:29 PM PDT 24 Jun 09 12:43:33 PM PDT 24 594549107 ps
T180 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1117233925 Jun 09 12:43:27 PM PDT 24 Jun 09 12:43:33 PM PDT 24 1967091685 ps
T1011 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.359778811 Jun 09 12:43:23 PM PDT 24 Jun 09 12:43:25 PM PDT 24 121970567 ps
T1012 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2429611890 Jun 09 12:43:33 PM PDT 24 Jun 09 12:43:35 PM PDT 24 1001026540 ps
T1013 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.37808486 Jun 09 12:43:07 PM PDT 24 Jun 09 12:43:09 PM PDT 24 104224642 ps
T1014 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1376435544 Jun 09 12:43:40 PM PDT 24 Jun 09 12:43:41 PM PDT 24 34108445 ps
T1015 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2299071596 Jun 09 12:43:30 PM PDT 24 Jun 09 12:43:32 PM PDT 24 43068712 ps
T1016 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3117065006 Jun 09 12:43:41 PM PDT 24 Jun 09 12:43:42 PM PDT 24 10377166 ps
T1017 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1737643017 Jun 09 12:43:33 PM PDT 24 Jun 09 12:43:36 PM PDT 24 55997683 ps
T1018 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1921292824 Jun 09 12:43:21 PM PDT 24 Jun 09 12:43:23 PM PDT 24 76853658 ps
T1019 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2158776785 Jun 09 12:43:12 PM PDT 24 Jun 09 12:43:18 PM PDT 24 523683005 ps
T1020 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3993765271 Jun 09 12:43:11 PM PDT 24 Jun 09 12:43:13 PM PDT 24 136390486 ps
T1021 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2833486705 Jun 09 12:43:37 PM PDT 24 Jun 09 12:43:38 PM PDT 24 16870012 ps
T1022 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.230448621 Jun 09 12:43:12 PM PDT 24 Jun 09 12:43:13 PM PDT 24 34513314 ps
T1023 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3413246307 Jun 09 12:43:21 PM PDT 24 Jun 09 12:43:23 PM PDT 24 18459770 ps
T1024 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3532844338 Jun 09 12:43:20 PM PDT 24 Jun 09 12:43:25 PM PDT 24 499077215 ps
T1025 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.385639427 Jun 09 12:43:33 PM PDT 24 Jun 09 12:43:35 PM PDT 24 30444591 ps
T1026 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1385062198 Jun 09 12:43:11 PM PDT 24 Jun 09 12:43:13 PM PDT 24 79781213 ps
T1027 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1514854087 Jun 09 12:43:27 PM PDT 24 Jun 09 12:43:31 PM PDT 24 61839002 ps
T1028 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.589170844 Jun 09 12:43:36 PM PDT 24 Jun 09 12:43:38 PM PDT 24 138275454 ps
T1029 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2140985874 Jun 09 12:43:07 PM PDT 24 Jun 09 12:43:17 PM PDT 24 7246425696 ps
T1030 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1157078453 Jun 09 12:43:13 PM PDT 24 Jun 09 12:43:17 PM PDT 24 147538689 ps
T1031 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.920078459 Jun 09 12:43:30 PM PDT 24 Jun 09 12:43:31 PM PDT 24 8285165 ps
T1032 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1683217607 Jun 09 12:43:46 PM PDT 24 Jun 09 12:43:48 PM PDT 24 21706482 ps
T1033 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3056961109 Jun 09 12:43:12 PM PDT 24 Jun 09 12:43:14 PM PDT 24 169065586 ps
T1034 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2873455448 Jun 09 12:43:37 PM PDT 24 Jun 09 12:43:39 PM PDT 24 13009157 ps
T1035 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.78465260 Jun 09 12:43:38 PM PDT 24 Jun 09 12:43:39 PM PDT 24 18127649 ps
T1036 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3440584406 Jun 09 12:43:33 PM PDT 24 Jun 09 12:43:35 PM PDT 24 128984279 ps
T1037 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.630659856 Jun 09 12:43:27 PM PDT 24 Jun 09 12:43:29 PM PDT 24 26987170 ps
T1038 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2021096676 Jun 09 12:43:03 PM PDT 24 Jun 09 12:43:11 PM PDT 24 291747607 ps
T1039 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2471254149 Jun 09 12:43:42 PM PDT 24 Jun 09 12:43:44 PM PDT 24 20775116 ps
T1040 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1169196238 Jun 09 12:43:07 PM PDT 24 Jun 09 12:43:13 PM PDT 24 206735505 ps
T1041 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1997156673 Jun 09 12:43:12 PM PDT 24 Jun 09 12:43:16 PM PDT 24 468025211 ps
T1042 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3684111313 Jun 09 12:43:21 PM PDT 24 Jun 09 12:43:23 PM PDT 24 113510405 ps
T1043 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.886044700 Jun 09 12:43:35 PM PDT 24 Jun 09 12:43:36 PM PDT 24 122565583 ps
T1044 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3193820711 Jun 09 12:43:27 PM PDT 24 Jun 09 12:43:33 PM PDT 24 2344959815 ps
T1045 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.359345716 Jun 09 12:43:05 PM PDT 24 Jun 09 12:43:07 PM PDT 24 93633526 ps
T1046 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.730907309 Jun 09 12:43:30 PM PDT 24 Jun 09 12:43:36 PM PDT 24 304779751 ps
T1047 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.455025045 Jun 09 12:43:19 PM PDT 24 Jun 09 12:43:22 PM PDT 24 31474789 ps
T1048 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2711126209 Jun 09 12:42:58 PM PDT 24 Jun 09 12:43:09 PM PDT 24 646222850 ps
T1049 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.646304081 Jun 09 12:43:27 PM PDT 24 Jun 09 12:43:34 PM PDT 24 223767379 ps
T1050 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3145036015 Jun 09 12:43:29 PM PDT 24 Jun 09 12:43:32 PM PDT 24 568568083 ps
T1051 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1126617125 Jun 09 12:43:33 PM PDT 24 Jun 09 12:43:36 PM PDT 24 206775428 ps
T1052 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3520717083 Jun 09 12:43:26 PM PDT 24 Jun 09 12:43:33 PM PDT 24 209957561 ps
T1053 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1080570571 Jun 09 12:43:24 PM PDT 24 Jun 09 12:43:27 PM PDT 24 211835597 ps
T1054 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.159144587 Jun 09 12:43:14 PM PDT 24 Jun 09 12:43:15 PM PDT 24 19985292 ps
T1055 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3870425763 Jun 09 12:43:23 PM PDT 24 Jun 09 12:43:25 PM PDT 24 55479746 ps
T1056 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2697576398 Jun 09 12:43:13 PM PDT 24 Jun 09 12:43:15 PM PDT 24 43257325 ps
T1057 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.485217943 Jun 09 12:43:39 PM PDT 24 Jun 09 12:43:40 PM PDT 24 31291594 ps
T1058 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1961985107 Jun 09 12:43:19 PM PDT 24 Jun 09 12:43:22 PM PDT 24 208728954 ps
T1059 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2533390950 Jun 09 12:43:30 PM PDT 24 Jun 09 12:43:32 PM PDT 24 82280404 ps
T176 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1238515025 Jun 09 12:43:00 PM PDT 24 Jun 09 12:43:05 PM PDT 24 148690791 ps
T1060 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.135407445 Jun 09 12:43:08 PM PDT 24 Jun 09 12:43:13 PM PDT 24 86323451 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1500838541 Jun 09 12:43:21 PM PDT 24 Jun 09 12:43:25 PM PDT 24 437005956 ps
T1062 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3200332013 Jun 09 12:43:35 PM PDT 24 Jun 09 12:43:38 PM PDT 24 148543591 ps
T1063 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3760754094 Jun 09 12:43:00 PM PDT 24 Jun 09 12:43:13 PM PDT 24 2796199583 ps
T1064 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3357344447 Jun 09 12:43:37 PM PDT 24 Jun 09 12:43:39 PM PDT 24 119901118 ps
T1065 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1297523949 Jun 09 12:43:13 PM PDT 24 Jun 09 12:43:15 PM PDT 24 156830617 ps
T1066 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1972881451 Jun 09 12:43:37 PM PDT 24 Jun 09 12:43:39 PM PDT 24 51505997 ps
T166 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1459031104 Jun 09 12:43:29 PM PDT 24 Jun 09 12:43:35 PM PDT 24 441414914 ps
T177 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3521188952 Jun 09 12:43:27 PM PDT 24 Jun 09 12:43:33 PM PDT 24 2300878646 ps
T1067 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3667345383 Jun 09 12:43:03 PM PDT 24 Jun 09 12:43:07 PM PDT 24 299002528 ps
T1068 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1857908821 Jun 09 12:43:37 PM PDT 24 Jun 09 12:43:38 PM PDT 24 11452841 ps
T1069 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1158036425 Jun 09 12:43:30 PM PDT 24 Jun 09 12:43:33 PM PDT 24 354052627 ps
T1070 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.134100572 Jun 09 12:43:00 PM PDT 24 Jun 09 12:43:12 PM PDT 24 1016332288 ps
T1071 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3710265922 Jun 09 12:43:23 PM PDT 24 Jun 09 12:43:24 PM PDT 24 18318061 ps
T1072 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.239883990 Jun 09 12:43:23 PM PDT 24 Jun 09 12:43:27 PM PDT 24 299921743 ps
T1073 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3662440503 Jun 09 12:43:29 PM PDT 24 Jun 09 12:43:32 PM PDT 24 494140069 ps
T1074 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2521626372 Jun 09 12:43:11 PM PDT 24 Jun 09 12:43:15 PM PDT 24 167224528 ps
T1075 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.724685832 Jun 09 12:43:35 PM PDT 24 Jun 09 12:43:36 PM PDT 24 8821196 ps
T1076 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1842400305 Jun 09 12:43:06 PM PDT 24 Jun 09 12:43:11 PM PDT 24 116423123 ps
T1077 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3771948207 Jun 09 12:43:30 PM PDT 24 Jun 09 12:43:32 PM PDT 24 306162698 ps
T1078 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.9493637 Jun 09 12:43:13 PM PDT 24 Jun 09 12:43:20 PM PDT 24 1453322685 ps
T1079 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4058187800 Jun 09 12:43:25 PM PDT 24 Jun 09 12:43:28 PM PDT 24 129313147 ps
T1080 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.895976611 Jun 09 12:43:13 PM PDT 24 Jun 09 12:43:15 PM PDT 24 20964744 ps
T1081 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.461015061 Jun 09 12:43:22 PM PDT 24 Jun 09 12:43:23 PM PDT 24 26766430 ps
T1082 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.122439758 Jun 09 12:43:04 PM PDT 24 Jun 09 12:43:05 PM PDT 24 18639493 ps
T1083 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3187375413 Jun 09 12:43:03 PM PDT 24 Jun 09 12:43:05 PM PDT 24 168453699 ps
T1084 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1607732430 Jun 09 12:43:34 PM PDT 24 Jun 09 12:43:36 PM PDT 24 94965088 ps
T1085 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3385192535 Jun 09 12:43:34 PM PDT 24 Jun 09 12:43:35 PM PDT 24 14680977 ps
T1086 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2365137288 Jun 09 12:43:33 PM PDT 24 Jun 09 12:43:35 PM PDT 24 55961035 ps
T1087 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.27634151 Jun 09 12:43:35 PM PDT 24 Jun 09 12:43:36 PM PDT 24 54739235 ps

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2777065114
Short name T13
Test name
Test status
Simulation time 43639169 ps
CPU time 3.02 seconds
Started Jun 09 02:27:37 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 222580 kb
Host smart-7f0feda4-c6d4-478f-935f-b145e8ce6aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777065114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2777065114
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2334186802
Short name T44
Test name
Test status
Simulation time 2676471496 ps
CPU time 17.91 seconds
Started Jun 09 02:27:20 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 215760 kb
Host smart-4a6a5e21-bf48-4982-af65-d4c45479c914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334186802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2334186802
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3418517469
Short name T57
Test name
Test status
Simulation time 7852089687 ps
CPU time 52.25 seconds
Started Jun 09 02:27:58 PM PDT 24
Finished Jun 09 02:28:51 PM PDT 24
Peak memory 217284 kb
Host smart-df331256-8c31-4eff-af25-2b734a1f1c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418517469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3418517469
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1031103687
Short name T59
Test name
Test status
Simulation time 463080732 ps
CPU time 17.85 seconds
Started Jun 09 02:27:50 PM PDT 24
Finished Jun 09 02:28:08 PM PDT 24
Peak memory 222600 kb
Host smart-cb8e2050-b79e-47de-8a98-6cde906dea9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031103687 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1031103687
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2166962915
Short name T74
Test name
Test status
Simulation time 1414079067 ps
CPU time 34.13 seconds
Started Jun 09 02:27:37 PM PDT 24
Finished Jun 09 02:28:12 PM PDT 24
Peak memory 215836 kb
Host smart-7a895f7c-3e67-47ee-a1fa-cb8c65fec4db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166962915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2166962915
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2919620570
Short name T8
Test name
Test status
Simulation time 618864878 ps
CPU time 12.9 seconds
Started Jun 09 02:26:38 PM PDT 24
Finished Jun 09 02:26:51 PM PDT 24
Peak memory 232904 kb
Host smart-745013cc-bca0-4883-a3d7-f514905efc95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919620570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2919620570
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1171182242
Short name T68
Test name
Test status
Simulation time 1354277609 ps
CPU time 53.13 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:28:34 PM PDT 24
Peak memory 216752 kb
Host smart-f3933caa-97e6-4837-81de-877437a9a7ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171182242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1171182242
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.818039409
Short name T16
Test name
Test status
Simulation time 194870371 ps
CPU time 4.12 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:51 PM PDT 24
Peak memory 214320 kb
Host smart-3fee9116-2fb9-4240-a38c-fba0b2247837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818039409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.818039409
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2351119244
Short name T11
Test name
Test status
Simulation time 172520077 ps
CPU time 4.28 seconds
Started Jun 09 02:26:55 PM PDT 24
Finished Jun 09 02:27:00 PM PDT 24
Peak memory 214288 kb
Host smart-4bf1d259-7a06-4bba-b586-93f62e8fd95a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2351119244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2351119244
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.182711075
Short name T119
Test name
Test status
Simulation time 2891964174 ps
CPU time 4.8 seconds
Started Jun 09 12:43:32 PM PDT 24
Finished Jun 09 12:43:37 PM PDT 24
Peak memory 220124 kb
Host smart-95587b6c-707c-40d6-9d42-4c27ad9df1e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182711075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.182711075
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2235926274
Short name T7
Test name
Test status
Simulation time 71964597 ps
CPU time 1.83 seconds
Started Jun 09 02:26:53 PM PDT 24
Finished Jun 09 02:26:55 PM PDT 24
Peak memory 219664 kb
Host smart-613ce409-e462-4062-8930-6d8fef898594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235926274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2235926274
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2371522717
Short name T152
Test name
Test status
Simulation time 4537276721 ps
CPU time 53.06 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:29:04 PM PDT 24
Peak memory 214988 kb
Host smart-ad01c1b5-0df8-45e3-a6a5-1741e87db0da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371522717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2371522717
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1969925950
Short name T72
Test name
Test status
Simulation time 3612080178 ps
CPU time 98.37 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:30:17 PM PDT 24
Peak memory 222580 kb
Host smart-5712f15d-ffa1-45e3-9d72-d6e4b1a02ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969925950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1969925950
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2988786443
Short name T271
Test name
Test status
Simulation time 690516595 ps
CPU time 13.76 seconds
Started Jun 09 02:27:32 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 214364 kb
Host smart-781060dc-ce4b-4709-b1b2-ad88a406efb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988786443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2988786443
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2357696697
Short name T23
Test name
Test status
Simulation time 3733943554 ps
CPU time 30.83 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:29:06 PM PDT 24
Peak memory 214384 kb
Host smart-5a4e9ff0-59df-4b69-9b4b-edd5276553cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357696697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2357696697
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2282000565
Short name T58
Test name
Test status
Simulation time 80780799 ps
CPU time 2.65 seconds
Started Jun 09 02:26:58 PM PDT 24
Finished Jun 09 02:27:01 PM PDT 24
Peak memory 210028 kb
Host smart-b0b8da7b-2387-4ff8-984d-c8b139828761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282000565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2282000565
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3026774447
Short name T73
Test name
Test status
Simulation time 164208205 ps
CPU time 10.58 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:36 PM PDT 24
Peak memory 222532 kb
Host smart-81f70ec7-45ea-4672-b299-a0a07d3574f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026774447 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3026774447
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3333874025
Short name T307
Test name
Test status
Simulation time 635818333 ps
CPU time 34.46 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:29:10 PM PDT 24
Peak memory 214488 kb
Host smart-f65be55c-c7a3-4e4f-adf5-3062b09e0c8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3333874025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3333874025
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3015035626
Short name T411
Test name
Test status
Simulation time 805169838 ps
CPU time 11.43 seconds
Started Jun 09 02:27:47 PM PDT 24
Finished Jun 09 02:27:59 PM PDT 24
Peak memory 215596 kb
Host smart-34a1b475-eff2-4332-959c-f037f0ad7eb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015035626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3015035626
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2837940547
Short name T22
Test name
Test status
Simulation time 252409168 ps
CPU time 6.36 seconds
Started Jun 09 02:26:46 PM PDT 24
Finished Jun 09 02:26:52 PM PDT 24
Peak memory 214324 kb
Host smart-63796792-f40e-487f-accb-1328fab7a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837940547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2837940547
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.247454694
Short name T123
Test name
Test status
Simulation time 339487671 ps
CPU time 18.37 seconds
Started Jun 09 02:28:44 PM PDT 24
Finished Jun 09 02:29:03 PM PDT 24
Peak memory 215752 kb
Host smart-a08cadef-9c90-4698-b486-5c18c389b734
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247454694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.247454694
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3136823504
Short name T115
Test name
Test status
Simulation time 444781857 ps
CPU time 6.73 seconds
Started Jun 09 02:26:28 PM PDT 24
Finished Jun 09 02:26:35 PM PDT 24
Peak memory 218268 kb
Host smart-9cb26634-1de4-4cfe-80d0-a8ffad3b5bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136823504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3136823504
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2978278417
Short name T407
Test name
Test status
Simulation time 282694646 ps
CPU time 14.09 seconds
Started Jun 09 02:26:38 PM PDT 24
Finished Jun 09 02:26:53 PM PDT 24
Peak memory 222444 kb
Host smart-e7a9397a-b794-46dc-a84e-20a30c2f2abf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978278417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2978278417
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1908577740
Short name T122
Test name
Test status
Simulation time 289928693 ps
CPU time 2.31 seconds
Started Jun 09 12:43:06 PM PDT 24
Finished Jun 09 12:43:09 PM PDT 24
Peak memory 214192 kb
Host smart-aa74568d-a634-457f-a5c9-530d6d938dfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908577740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1908577740
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.20879789
Short name T19
Test name
Test status
Simulation time 58156714 ps
CPU time 1.63 seconds
Started Jun 09 02:27:20 PM PDT 24
Finished Jun 09 02:27:22 PM PDT 24
Peak memory 216440 kb
Host smart-5d2a3bbd-9699-45bc-94ba-3bbb5c415be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20879789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.20879789
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3585716122
Short name T37
Test name
Test status
Simulation time 592236118 ps
CPU time 6.05 seconds
Started Jun 09 02:26:33 PM PDT 24
Finished Jun 09 02:26:40 PM PDT 24
Peak memory 218392 kb
Host smart-73cde06c-295f-43e0-94ea-78b16f4e7f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585716122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3585716122
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2146079986
Short name T24
Test name
Test status
Simulation time 5454449603 ps
CPU time 14.3 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:28:01 PM PDT 24
Peak memory 222480 kb
Host smart-fdc973a7-49d8-4227-b3c5-42e3ff4e730c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146079986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2146079986
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.657003044
Short name T239
Test name
Test status
Simulation time 291678731 ps
CPU time 8.52 seconds
Started Jun 09 02:26:54 PM PDT 24
Finished Jun 09 02:27:03 PM PDT 24
Peak memory 215096 kb
Host smart-a3aac408-c2f0-48ce-823e-b6eaa01897ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=657003044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.657003044
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2981196886
Short name T30
Test name
Test status
Simulation time 548027672 ps
CPU time 5.37 seconds
Started Jun 09 02:27:37 PM PDT 24
Finished Jun 09 02:27:43 PM PDT 24
Peak memory 210528 kb
Host smart-ef2a2653-e6ac-4536-9ec3-cec71ba8af53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981196886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2981196886
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1354239417
Short name T6
Test name
Test status
Simulation time 14746175258 ps
CPU time 81.2 seconds
Started Jun 09 02:27:26 PM PDT 24
Finished Jun 09 02:28:47 PM PDT 24
Peak memory 217004 kb
Host smart-b335c947-908c-485f-8666-b85cb56b5357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354239417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1354239417
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.174654099
Short name T211
Test name
Test status
Simulation time 698488964 ps
CPU time 31.01 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:27:09 PM PDT 24
Peak memory 222516 kb
Host smart-dae4c93f-689a-4076-93b5-f1376842f3f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174654099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.174654099
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2661839337
Short name T153
Test name
Test status
Simulation time 1623920970 ps
CPU time 21.58 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:29:00 PM PDT 24
Peak memory 222500 kb
Host smart-dddd6642-1771-4119-ba80-666e18c107fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661839337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2661839337
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.4199429673
Short name T52
Test name
Test status
Simulation time 654481372 ps
CPU time 22.79 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:28:10 PM PDT 24
Peak memory 216576 kb
Host smart-7ea45192-c017-4e32-8994-f5792da48fed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199429673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4199429673
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.886858603
Short name T443
Test name
Test status
Simulation time 15052081 ps
CPU time 0.72 seconds
Started Jun 09 02:26:32 PM PDT 24
Finished Jun 09 02:26:33 PM PDT 24
Peak memory 205936 kb
Host smart-8e62c12c-7ee8-40b4-ad44-e9735e8824a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886858603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.886858603
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1181858304
Short name T179
Test name
Test status
Simulation time 857751845 ps
CPU time 9.01 seconds
Started Jun 09 12:43:25 PM PDT 24
Finished Jun 09 12:43:35 PM PDT 24
Peak memory 213736 kb
Host smart-1c6b0542-6c54-40a8-be5b-4f5b9c1202eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181858304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1181858304
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.4052845330
Short name T233
Test name
Test status
Simulation time 84997940 ps
CPU time 3.8 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 221408 kb
Host smart-1e3efbbf-dc49-4fc3-bfc2-aef14c246370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052845330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4052845330
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2336317933
Short name T172
Test name
Test status
Simulation time 261843533 ps
CPU time 6.45 seconds
Started Jun 09 12:43:10 PM PDT 24
Finished Jun 09 12:43:17 PM PDT 24
Peak memory 213828 kb
Host smart-1ffcfd73-8405-4149-b596-293fba8f5bea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336317933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2336317933
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1555735025
Short name T323
Test name
Test status
Simulation time 4575050186 ps
CPU time 60.53 seconds
Started Jun 09 02:27:29 PM PDT 24
Finished Jun 09 02:28:30 PM PDT 24
Peak memory 216044 kb
Host smart-26a50538-13a3-4a47-b198-77a20e0972a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1555735025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1555735025
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.900510096
Short name T1
Test name
Test status
Simulation time 46404114 ps
CPU time 3.27 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:13 PM PDT 24
Peak memory 215476 kb
Host smart-dc8ec789-d6c6-4514-ba7e-442ac4406d7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900510096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.900510096
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1114312716
Short name T620
Test name
Test status
Simulation time 222057260 ps
CPU time 2.89 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:37 PM PDT 24
Peak memory 221356 kb
Host smart-dff47bbd-99a5-4a40-b34b-17339f83daae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114312716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1114312716
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1304998416
Short name T40
Test name
Test status
Simulation time 6942220311 ps
CPU time 22.13 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:29:01 PM PDT 24
Peak memory 211244 kb
Host smart-b2a440b6-244d-44bb-a651-30f41da2ee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304998416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1304998416
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.475085871
Short name T103
Test name
Test status
Simulation time 131158119 ps
CPU time 4.54 seconds
Started Jun 09 02:27:56 PM PDT 24
Finished Jun 09 02:28:01 PM PDT 24
Peak memory 214376 kb
Host smart-ebf9d14f-df09-46ae-8c91-d40bc9dbf2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475085871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.475085871
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2114904626
Short name T258
Test name
Test status
Simulation time 3958766996 ps
CPU time 116.11 seconds
Started Jun 09 02:28:17 PM PDT 24
Finished Jun 09 02:30:13 PM PDT 24
Peak memory 217192 kb
Host smart-fc4a3cfb-d4be-4933-9b51-675f38789383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114904626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2114904626
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1807620102
Short name T415
Test name
Test status
Simulation time 463003317 ps
CPU time 7.94 seconds
Started Jun 09 02:28:31 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 214924 kb
Host smart-550020f9-83fb-42c5-b202-e01a369b9f65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807620102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1807620102
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3001787248
Short name T86
Test name
Test status
Simulation time 74387900 ps
CPU time 3.83 seconds
Started Jun 09 02:28:04 PM PDT 24
Finished Jun 09 02:28:09 PM PDT 24
Peak memory 208896 kb
Host smart-55b2fe5f-762a-413a-a683-0b5a8412f6e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001787248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3001787248
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.698766419
Short name T251
Test name
Test status
Simulation time 73604610 ps
CPU time 2.27 seconds
Started Jun 09 02:26:38 PM PDT 24
Finished Jun 09 02:26:40 PM PDT 24
Peak memory 214340 kb
Host smart-1fcc1ea0-50c9-467b-8c92-aaf62f32f888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698766419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.698766419
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1996561989
Short name T213
Test name
Test status
Simulation time 835316935 ps
CPU time 35.86 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:29:16 PM PDT 24
Peak memory 215228 kb
Host smart-1aeef2c4-2d95-48c9-bd90-459010022fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996561989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1996561989
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.277589931
Short name T170
Test name
Test status
Simulation time 209933549 ps
CPU time 6.55 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:37 PM PDT 24
Peak memory 216156 kb
Host smart-f4bf79e8-c5b9-4bc5-9681-b36572ec6cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277589931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.277589931
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1796744545
Short name T92
Test name
Test status
Simulation time 175264071 ps
CPU time 3.62 seconds
Started Jun 09 02:27:20 PM PDT 24
Finished Jun 09 02:27:24 PM PDT 24
Peak memory 214408 kb
Host smart-b8c665a3-dc56-4839-973e-d6d0884fd454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796744545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1796744545
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2937928827
Short name T984
Test name
Test status
Simulation time 3479338303 ps
CPU time 6.63 seconds
Started Jun 09 12:43:34 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 214176 kb
Host smart-668376a9-e9d1-4325-b66e-950f30d7b1f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937928827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2937928827
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.575359021
Short name T379
Test name
Test status
Simulation time 1979399661 ps
CPU time 23.24 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:26:57 PM PDT 24
Peak memory 221188 kb
Host smart-10a3acd3-fb97-47e6-a804-535818158b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575359021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.575359021
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1958337746
Short name T356
Test name
Test status
Simulation time 100162042 ps
CPU time 2.01 seconds
Started Jun 09 02:26:40 PM PDT 24
Finished Jun 09 02:26:43 PM PDT 24
Peak memory 214340 kb
Host smart-ea332c96-ba9b-498f-9682-2f42cd7f46a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958337746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1958337746
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1238515025
Short name T176
Test name
Test status
Simulation time 148690791 ps
CPU time 5.49 seconds
Started Jun 09 12:43:00 PM PDT 24
Finished Jun 09 12:43:05 PM PDT 24
Peak memory 213768 kb
Host smart-696c6064-75be-43f0-933f-2d0db021cade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238515025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1238515025
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3715713316
Short name T168
Test name
Test status
Simulation time 500525749 ps
CPU time 9.82 seconds
Started Jun 09 12:43:32 PM PDT 24
Finished Jun 09 12:43:42 PM PDT 24
Peak memory 213796 kb
Host smart-abf71602-52f1-46f1-823d-0787aa2e5843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715713316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3715713316
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4063108817
Short name T165
Test name
Test status
Simulation time 433306533 ps
CPU time 8.81 seconds
Started Jun 09 12:43:18 PM PDT 24
Finished Jun 09 12:43:27 PM PDT 24
Peak memory 213832 kb
Host smart-326cb249-45cc-4e05-91e7-604da209bacb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063108817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.4063108817
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3821991259
Short name T137
Test name
Test status
Simulation time 42179858 ps
CPU time 2.44 seconds
Started Jun 09 02:26:26 PM PDT 24
Finished Jun 09 02:26:29 PM PDT 24
Peak memory 222428 kb
Host smart-23f146db-a709-4050-b987-40721ba939bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821991259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3821991259
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.934762862
Short name T127
Test name
Test status
Simulation time 1758848957 ps
CPU time 14.79 seconds
Started Jun 09 02:27:06 PM PDT 24
Finished Jun 09 02:27:21 PM PDT 24
Peak memory 220172 kb
Host smart-8c624625-b682-44ac-9f79-4a739600e97a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934762862 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.934762862
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2615834086
Short name T400
Test name
Test status
Simulation time 2187121916 ps
CPU time 38.98 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:28:14 PM PDT 24
Peak memory 222512 kb
Host smart-e75c8970-7c9f-44c6-9a54-1ad0eaa412a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615834086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2615834086
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2350771890
Short name T255
Test name
Test status
Simulation time 116517688 ps
CPU time 4.39 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 215604 kb
Host smart-d7a52ca5-2041-4961-b674-9796b5a5a0e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350771890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2350771890
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1252053834
Short name T220
Test name
Test status
Simulation time 2223624531 ps
CPU time 31.19 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 222564 kb
Host smart-ae619070-4a3e-4208-bcd1-72e863cfc959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252053834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1252053834
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2154443021
Short name T203
Test name
Test status
Simulation time 116022895 ps
CPU time 2.43 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 214284 kb
Host smart-3e6f4151-a452-448f-a8d9-79da33aa74b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154443021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2154443021
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.813464493
Short name T174
Test name
Test status
Simulation time 62715689 ps
CPU time 1.87 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 210024 kb
Host smart-27a36d69-f5ee-4e7e-a86d-636bf9324891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813464493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.813464493
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1024076522
Short name T85
Test name
Test status
Simulation time 76398611 ps
CPU time 2.8 seconds
Started Jun 09 02:27:39 PM PDT 24
Finished Jun 09 02:27:43 PM PDT 24
Peak memory 217788 kb
Host smart-6711dcee-1965-4972-8f4c-b5da9e7e21f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024076522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1024076522
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2460497644
Short name T116
Test name
Test status
Simulation time 202631816 ps
CPU time 3.2 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 222688 kb
Host smart-54f43609-d66d-4f28-a2cb-d16b57bc4273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460497644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2460497644
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.39638492
Short name T117
Test name
Test status
Simulation time 130659431 ps
CPU time 5.23 seconds
Started Jun 09 02:26:32 PM PDT 24
Finished Jun 09 02:26:38 PM PDT 24
Peak memory 218540 kb
Host smart-05b3fedb-769f-4747-8f50-fd06b6513449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39638492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.39638492
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2033604683
Short name T15
Test name
Test status
Simulation time 254901446 ps
CPU time 2.61 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 217940 kb
Host smart-faef1208-ed8f-428a-ac6c-83e540ba3c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033604683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2033604683
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3132730863
Short name T297
Test name
Test status
Simulation time 73431527 ps
CPU time 2.68 seconds
Started Jun 09 02:26:25 PM PDT 24
Finished Jun 09 02:26:28 PM PDT 24
Peak memory 214324 kb
Host smart-49931670-20c3-4b9d-9de6-83bd8b07288e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132730863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3132730863
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.966021341
Short name T77
Test name
Test status
Simulation time 117208963 ps
CPU time 3.09 seconds
Started Jun 09 02:27:04 PM PDT 24
Finished Jun 09 02:27:08 PM PDT 24
Peak memory 207312 kb
Host smart-6c3db3db-b87a-4216-b0ce-35040cdba16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966021341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.966021341
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3937315643
Short name T311
Test name
Test status
Simulation time 135345568 ps
CPU time 5.37 seconds
Started Jun 09 02:27:22 PM PDT 24
Finished Jun 09 02:27:27 PM PDT 24
Peak memory 214244 kb
Host smart-fe38fb58-85bc-4835-be3f-afb39563b9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937315643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3937315643
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1117231008
Short name T330
Test name
Test status
Simulation time 99813404 ps
CPU time 3.75 seconds
Started Jun 09 02:27:27 PM PDT 24
Finished Jun 09 02:27:31 PM PDT 24
Peak memory 214320 kb
Host smart-5c63ca8e-40a1-428d-8c37-c0613164e8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117231008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1117231008
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3747834416
Short name T686
Test name
Test status
Simulation time 81582721 ps
CPU time 3.54 seconds
Started Jun 09 02:28:32 PM PDT 24
Finished Jun 09 02:28:36 PM PDT 24
Peak memory 208780 kb
Host smart-c1146fb2-5227-49ce-9014-267daa49274b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747834416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3747834416
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.603740711
Short name T422
Test name
Test status
Simulation time 665904277 ps
CPU time 10.1 seconds
Started Jun 09 02:27:50 PM PDT 24
Finished Jun 09 02:28:00 PM PDT 24
Peak memory 215368 kb
Host smart-39b43790-b13b-4ea9-9ded-3c169a63491d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603740711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.603740711
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1240620897
Short name T54
Test name
Test status
Simulation time 1909093599 ps
CPU time 46.84 seconds
Started Jun 09 02:28:21 PM PDT 24
Finished Jun 09 02:29:08 PM PDT 24
Peak memory 215656 kb
Host smart-c440102e-5f05-4be6-89ab-681da31517c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240620897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1240620897
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.200170783
Short name T313
Test name
Test status
Simulation time 357753600 ps
CPU time 6.17 seconds
Started Jun 09 02:28:30 PM PDT 24
Finished Jun 09 02:28:36 PM PDT 24
Peak memory 214448 kb
Host smart-8ca5e58e-abd3-41b3-9898-96977cff49b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200170783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.200170783
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.4010212453
Short name T708
Test name
Test status
Simulation time 41790188 ps
CPU time 2.7 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:28:49 PM PDT 24
Peak memory 219788 kb
Host smart-4264b1a6-7e64-4dbd-acb4-59957874be63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010212453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4010212453
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2737275059
Short name T386
Test name
Test status
Simulation time 98012999 ps
CPU time 2.4 seconds
Started Jun 09 02:28:51 PM PDT 24
Finished Jun 09 02:28:54 PM PDT 24
Peak memory 210080 kb
Host smart-75f9c055-acb3-49db-8b85-950d091aa97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737275059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2737275059
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1459031104
Short name T166
Test name
Test status
Simulation time 441414914 ps
CPU time 4.94 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:35 PM PDT 24
Peak memory 213812 kb
Host smart-ca4d6107-3224-4ded-a8e0-c0114cef086d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459031104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1459031104
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1176235315
Short name T175
Test name
Test status
Simulation time 420289155 ps
CPU time 4.79 seconds
Started Jun 09 12:43:12 PM PDT 24
Finished Jun 09 12:43:18 PM PDT 24
Peak memory 205844 kb
Host smart-ccf340d5-23f6-4fbd-98ec-e2fe117bae53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176235315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1176235315
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.4178034061
Short name T181
Test name
Test status
Simulation time 515494384 ps
CPU time 13.49 seconds
Started Jun 09 12:43:14 PM PDT 24
Finished Jun 09 12:43:28 PM PDT 24
Peak memory 213780 kb
Host smart-53bd2725-4fce-454d-b3b1-f764afe2d4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178034061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.4178034061
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2202448533
Short name T20
Test name
Test status
Simulation time 428002647 ps
CPU time 4 seconds
Started Jun 09 02:28:00 PM PDT 24
Finished Jun 09 02:28:05 PM PDT 24
Peak memory 222740 kb
Host smart-7f909392-e911-4786-8d89-f489ebd16b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202448533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2202448533
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.761955120
Short name T10
Test name
Test status
Simulation time 1783888082 ps
CPU time 11.69 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:26:46 PM PDT 24
Peak memory 235400 kb
Host smart-23ce7ead-d430-4e2a-981b-c9a1043f6ce9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761955120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.761955120
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1523299146
Short name T314
Test name
Test status
Simulation time 270789565 ps
CPU time 9.55 seconds
Started Jun 09 02:26:30 PM PDT 24
Finished Jun 09 02:26:40 PM PDT 24
Peak memory 208736 kb
Host smart-5456c083-d5c0-498d-8760-15a726e3178f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523299146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1523299146
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1573955688
Short name T378
Test name
Test status
Simulation time 185668291 ps
CPU time 5.7 seconds
Started Jun 09 02:26:26 PM PDT 24
Finished Jun 09 02:26:32 PM PDT 24
Peak memory 221224 kb
Host smart-57ec280d-5e1c-4fda-bcd8-3cd254dc331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573955688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1573955688
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3214536580
Short name T897
Test name
Test status
Simulation time 176951699 ps
CPU time 2.17 seconds
Started Jun 09 02:26:59 PM PDT 24
Finished Jun 09 02:27:01 PM PDT 24
Peak memory 205640 kb
Host smart-e24e71ca-898c-4cdd-9235-3e0e835d95ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214536580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3214536580
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.52278409
Short name T206
Test name
Test status
Simulation time 48596507 ps
CPU time 2.49 seconds
Started Jun 09 02:27:05 PM PDT 24
Finished Jun 09 02:27:08 PM PDT 24
Peak memory 208056 kb
Host smart-f41cf788-9a38-4ca8-a477-8334e2a580a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52278409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.52278409
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3557908348
Short name T640
Test name
Test status
Simulation time 238913952 ps
CPU time 3.3 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:38 PM PDT 24
Peak memory 208988 kb
Host smart-30e1417a-2347-4e06-b57a-f908ba346921
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557908348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3557908348
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3430532996
Short name T221
Test name
Test status
Simulation time 43955444 ps
CPU time 3.4 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:44 PM PDT 24
Peak memory 214320 kb
Host smart-58d1d1c5-596a-4912-8fe6-292ee7ffb5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3430532996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3430532996
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1183823253
Short name T409
Test name
Test status
Simulation time 2418116330 ps
CPU time 32 seconds
Started Jun 09 02:26:29 PM PDT 24
Finished Jun 09 02:27:01 PM PDT 24
Peak memory 215940 kb
Host smart-b347b7e8-143d-452b-b1c1-e0a5e434abbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183823253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1183823253
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.147029559
Short name T327
Test name
Test status
Simulation time 402138192 ps
CPU time 4.75 seconds
Started Jun 09 02:26:30 PM PDT 24
Finished Jun 09 02:26:35 PM PDT 24
Peak memory 218692 kb
Host smart-12140cf8-658e-4420-a801-ccc94fef3e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147029559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.147029559
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1575145171
Short name T367
Test name
Test status
Simulation time 193328790 ps
CPU time 2.98 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:37 PM PDT 24
Peak memory 207904 kb
Host smart-7e24276c-1342-46ef-b73e-b243174b4aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575145171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1575145171
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_random.1404852639
Short name T292
Test name
Test status
Simulation time 177456104 ps
CPU time 2.81 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 218568 kb
Host smart-4cab9b94-7003-487d-8c07-f1c9b150c0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404852639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1404852639
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4129404517
Short name T61
Test name
Test status
Simulation time 45061730 ps
CPU time 2.84 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:48 PM PDT 24
Peak memory 209868 kb
Host smart-61c85053-0833-492d-960d-174e473c0f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129404517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4129404517
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3015520274
Short name T91
Test name
Test status
Simulation time 204041246 ps
CPU time 3.02 seconds
Started Jun 09 02:26:32 PM PDT 24
Finished Jun 09 02:26:35 PM PDT 24
Peak memory 214304 kb
Host smart-c6fe19f9-e9a4-4b06-a3ef-a1ac2c927fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015520274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3015520274
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3749080773
Short name T215
Test name
Test status
Simulation time 489536801 ps
CPU time 3.96 seconds
Started Jun 09 02:28:17 PM PDT 24
Finished Jun 09 02:28:22 PM PDT 24
Peak memory 220328 kb
Host smart-cbdc6fda-ea14-4105-abf3-246706b87a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749080773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3749080773
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1736972753
Short name T248
Test name
Test status
Simulation time 35768011 ps
CPU time 2.74 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:32 PM PDT 24
Peak memory 222168 kb
Host smart-f902a933-981b-4179-a7e2-141225a62c44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736972753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1736972753
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1770196052
Short name T269
Test name
Test status
Simulation time 321757398 ps
CPU time 4.08 seconds
Started Jun 09 02:28:29 PM PDT 24
Finished Jun 09 02:28:34 PM PDT 24
Peak memory 222476 kb
Host smart-e33d4996-44ae-493b-a175-4985a49694a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770196052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1770196052
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2100077636
Short name T334
Test name
Test status
Simulation time 258201009 ps
CPU time 2.19 seconds
Started Jun 09 02:28:56 PM PDT 24
Finished Jun 09 02:28:59 PM PDT 24
Peak memory 214260 kb
Host smart-72a02ff8-116b-487f-841d-60e06a209c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100077636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2100077636
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2471875922
Short name T187
Test name
Test status
Simulation time 169620733 ps
CPU time 6.66 seconds
Started Jun 09 02:26:51 PM PDT 24
Finished Jun 09 02:26:58 PM PDT 24
Peak memory 222616 kb
Host smart-a190c3d8-f4bb-4bab-936f-325c6e80bab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471875922 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2471875922
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.453304142
Short name T1000
Test name
Test status
Simulation time 73029357 ps
CPU time 4.9 seconds
Started Jun 09 12:42:58 PM PDT 24
Finished Jun 09 12:43:03 PM PDT 24
Peak memory 205688 kb
Host smart-f5c3e5b7-3404-49d8-a177-b03494c81073
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453304142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.453304142
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.638187789
Short name T975
Test name
Test status
Simulation time 1715596647 ps
CPU time 15.26 seconds
Started Jun 09 12:43:00 PM PDT 24
Finished Jun 09 12:43:15 PM PDT 24
Peak memory 205668 kb
Host smart-aa3d4178-075f-4e9b-8aab-6bbb871fc027
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638187789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.638187789
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.58894434
Short name T955
Test name
Test status
Simulation time 14356362 ps
CPU time 1.13 seconds
Started Jun 09 12:42:59 PM PDT 24
Finished Jun 09 12:43:01 PM PDT 24
Peak memory 205548 kb
Host smart-1f46900e-0c93-43aa-8a97-021e031daf42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58894434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.58894434
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3664392415
Short name T990
Test name
Test status
Simulation time 184002875 ps
CPU time 1.66 seconds
Started Jun 09 12:43:00 PM PDT 24
Finished Jun 09 12:43:02 PM PDT 24
Peak memory 213832 kb
Host smart-c9068970-9101-4080-9561-23bb793c3ac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664392415 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3664392415
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3657286974
Short name T957
Test name
Test status
Simulation time 29576833 ps
CPU time 1.14 seconds
Started Jun 09 12:42:58 PM PDT 24
Finished Jun 09 12:43:00 PM PDT 24
Peak memory 205620 kb
Host smart-eeb3bc63-5e06-4dac-9536-ec8f653b8ab3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657286974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3657286974
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1480966845
Short name T985
Test name
Test status
Simulation time 28117414 ps
CPU time 0.71 seconds
Started Jun 09 12:43:00 PM PDT 24
Finished Jun 09 12:43:01 PM PDT 24
Peak memory 205312 kb
Host smart-bad77663-92e3-4b63-87a4-e0900e055099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480966845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1480966845
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3809696812
Short name T981
Test name
Test status
Simulation time 83251626 ps
CPU time 1.95 seconds
Started Jun 09 12:43:04 PM PDT 24
Finished Jun 09 12:43:07 PM PDT 24
Peak memory 205564 kb
Host smart-bc7f17be-72b3-4c84-8b28-6b3345890efb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809696812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3809696812
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2916535084
Short name T978
Test name
Test status
Simulation time 101369376 ps
CPU time 2.27 seconds
Started Jun 09 12:43:03 PM PDT 24
Finished Jun 09 12:43:06 PM PDT 24
Peak memory 214108 kb
Host smart-c4638215-f9bc-4a3b-9d87-c69a8de60ac8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916535084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2916535084
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.9243055
Short name T125
Test name
Test status
Simulation time 712725772 ps
CPU time 7.78 seconds
Started Jun 09 12:43:00 PM PDT 24
Finished Jun 09 12:43:08 PM PDT 24
Peak memory 220084 kb
Host smart-e343ddaf-b700-4dee-9a41-24fd26a85e9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9243055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_S
EQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.key
mgr_shadow_reg_errors_with_csr_rw.9243055
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1990305978
Short name T919
Test name
Test status
Simulation time 55680039 ps
CPU time 3.56 seconds
Started Jun 09 12:42:58 PM PDT 24
Finished Jun 09 12:43:02 PM PDT 24
Peak memory 213744 kb
Host smart-e2dffd80-d127-4f25-81f6-2ca9012cf2e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990305978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1990305978
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2711126209
Short name T1048
Test name
Test status
Simulation time 646222850 ps
CPU time 10.01 seconds
Started Jun 09 12:42:58 PM PDT 24
Finished Jun 09 12:43:09 PM PDT 24
Peak memory 213832 kb
Host smart-98393ace-fc83-4623-aee0-e5f3ee4ce85b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711126209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2711126209
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.134100572
Short name T1070
Test name
Test status
Simulation time 1016332288 ps
CPU time 10.93 seconds
Started Jun 09 12:43:00 PM PDT 24
Finished Jun 09 12:43:12 PM PDT 24
Peak memory 205564 kb
Host smart-84bde61a-ada0-41ad-91ec-46b0b4e2dc53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134100572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.134100572
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3157584896
Short name T395
Test name
Test status
Simulation time 5761043234 ps
CPU time 26.49 seconds
Started Jun 09 12:43:04 PM PDT 24
Finished Jun 09 12:43:31 PM PDT 24
Peak memory 205712 kb
Host smart-6f7e0859-f8da-4405-b199-6e94f4fe8991
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157584896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
157584896
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1992961547
Short name T942
Test name
Test status
Simulation time 20672487 ps
CPU time 1.01 seconds
Started Jun 09 12:43:05 PM PDT 24
Finished Jun 09 12:43:06 PM PDT 24
Peak memory 205620 kb
Host smart-753605cf-3fc0-4f33-b1c7-886827ccd416
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992961547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
992961547
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2591940142
Short name T924
Test name
Test status
Simulation time 451743599 ps
CPU time 2.38 seconds
Started Jun 09 12:43:02 PM PDT 24
Finished Jun 09 12:43:05 PM PDT 24
Peak memory 214160 kb
Host smart-d730d0fe-fac2-40e4-9dfb-51af7810cc81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591940142 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2591940142
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3036023258
Short name T980
Test name
Test status
Simulation time 41169322 ps
CPU time 1.14 seconds
Started Jun 09 12:42:57 PM PDT 24
Finished Jun 09 12:42:59 PM PDT 24
Peak memory 205660 kb
Host smart-2d0d26cf-8073-4a58-9134-7566e2ce556a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036023258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3036023258
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2518575277
Short name T969
Test name
Test status
Simulation time 6854441 ps
CPU time 0.77 seconds
Started Jun 09 12:42:59 PM PDT 24
Finished Jun 09 12:43:00 PM PDT 24
Peak memory 205256 kb
Host smart-c1974131-2ab3-4b8e-abf3-fda96a030805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518575277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2518575277
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.946256080
Short name T941
Test name
Test status
Simulation time 35148709 ps
CPU time 2.11 seconds
Started Jun 09 12:43:04 PM PDT 24
Finished Jun 09 12:43:07 PM PDT 24
Peak memory 205672 kb
Host smart-69289973-c259-4636-8427-6c34f392fa20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946256080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.946256080
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3474591824
Short name T1004
Test name
Test status
Simulation time 82928706 ps
CPU time 1.8 seconds
Started Jun 09 12:42:59 PM PDT 24
Finished Jun 09 12:43:01 PM PDT 24
Peak memory 214212 kb
Host smart-446d07de-863f-41af-8915-e5f8309a939b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474591824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3474591824
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3760754094
Short name T1063
Test name
Test status
Simulation time 2796199583 ps
CPU time 13.18 seconds
Started Jun 09 12:43:00 PM PDT 24
Finished Jun 09 12:43:13 PM PDT 24
Peak memory 214232 kb
Host smart-eda9a893-922e-431f-ad62-afa7be1c11a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760754094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3760754094
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3187375413
Short name T1083
Test name
Test status
Simulation time 168453699 ps
CPU time 1.92 seconds
Started Jun 09 12:43:03 PM PDT 24
Finished Jun 09 12:43:05 PM PDT 24
Peak memory 214840 kb
Host smart-1ffd5259-db42-46f5-a53d-98f084c177b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187375413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3187375413
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3870425763
Short name T1055
Test name
Test status
Simulation time 55479746 ps
CPU time 1.31 seconds
Started Jun 09 12:43:23 PM PDT 24
Finished Jun 09 12:43:25 PM PDT 24
Peak memory 205576 kb
Host smart-f2bfefa0-cec2-4b86-8e71-1a550ffb38f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870425763 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3870425763
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2453952653
Short name T916
Test name
Test status
Simulation time 18069660 ps
CPU time 1.08 seconds
Started Jun 09 12:43:25 PM PDT 24
Finished Jun 09 12:43:26 PM PDT 24
Peak memory 205452 kb
Host smart-94f9c515-8bc3-40b0-bdf1-aaf584180947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453952653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2453952653
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2752850858
Short name T962
Test name
Test status
Simulation time 13134038 ps
CPU time 0.73 seconds
Started Jun 09 12:43:26 PM PDT 24
Finished Jun 09 12:43:27 PM PDT 24
Peak memory 205244 kb
Host smart-b1e7a9a8-3388-4690-9edd-6be7d886505a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752850858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2752850858
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2075094810
Short name T162
Test name
Test status
Simulation time 237279707 ps
CPU time 4.26 seconds
Started Jun 09 12:43:27 PM PDT 24
Finished Jun 09 12:43:32 PM PDT 24
Peak memory 205684 kb
Host smart-596922a6-a473-4ed0-8057-f9875a89fd49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075094810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2075094810
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1080570571
Short name T1053
Test name
Test status
Simulation time 211835597 ps
CPU time 3.12 seconds
Started Jun 09 12:43:24 PM PDT 24
Finished Jun 09 12:43:27 PM PDT 24
Peak memory 214112 kb
Host smart-003f5641-300f-4414-82f2-82392c426b1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080570571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1080570571
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3520717083
Short name T1052
Test name
Test status
Simulation time 209957561 ps
CPU time 7.15 seconds
Started Jun 09 12:43:26 PM PDT 24
Finished Jun 09 12:43:33 PM PDT 24
Peak memory 214124 kb
Host smart-718f58a6-0d0a-4dab-87ec-ea8e4efdfedf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520717083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3520717083
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1298020931
Short name T947
Test name
Test status
Simulation time 119595205 ps
CPU time 4.37 seconds
Started Jun 09 12:43:27 PM PDT 24
Finished Jun 09 12:43:32 PM PDT 24
Peak memory 222020 kb
Host smart-fc30f516-dc89-4fcb-a172-0abc9ddb1c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298020931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1298020931
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1670889202
Short name T944
Test name
Test status
Simulation time 96255599 ps
CPU time 1.45 seconds
Started Jun 09 12:43:25 PM PDT 24
Finished Jun 09 12:43:27 PM PDT 24
Peak memory 213804 kb
Host smart-77e5a01b-832f-4d79-9da7-4c4dd008d98a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670889202 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1670889202
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3710265922
Short name T1071
Test name
Test status
Simulation time 18318061 ps
CPU time 1.19 seconds
Started Jun 09 12:43:23 PM PDT 24
Finished Jun 09 12:43:24 PM PDT 24
Peak memory 205616 kb
Host smart-4a880a3a-dfe7-476c-8e28-9051f6a83069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710265922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3710265922
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3264402721
Short name T971
Test name
Test status
Simulation time 13199542 ps
CPU time 0.88 seconds
Started Jun 09 12:43:24 PM PDT 24
Finished Jun 09 12:43:25 PM PDT 24
Peak memory 205492 kb
Host smart-28c4d181-dd03-475c-b5e3-f3547ad3b204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264402721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3264402721
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.896947720
Short name T960
Test name
Test status
Simulation time 129281833 ps
CPU time 2.98 seconds
Started Jun 09 12:43:24 PM PDT 24
Finished Jun 09 12:43:28 PM PDT 24
Peak memory 205660 kb
Host smart-64a149fb-1825-4c70-adbe-4a805c4075d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896947720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.896947720
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.646304081
Short name T1049
Test name
Test status
Simulation time 223767379 ps
CPU time 5.76 seconds
Started Jun 09 12:43:27 PM PDT 24
Finished Jun 09 12:43:34 PM PDT 24
Peak memory 214132 kb
Host smart-b56dd2f3-8a85-440a-8446-73ba893710c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646304081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.646304081
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2920475056
Short name T1007
Test name
Test status
Simulation time 1747980942 ps
CPU time 9.98 seconds
Started Jun 09 12:43:28 PM PDT 24
Finished Jun 09 12:43:39 PM PDT 24
Peak memory 214184 kb
Host smart-654548b9-6be3-4c8e-8db3-ae7efcc76d89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920475056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2920475056
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2120439937
Short name T976
Test name
Test status
Simulation time 140718323 ps
CPU time 2.15 seconds
Started Jun 09 12:43:25 PM PDT 24
Finished Jun 09 12:43:27 PM PDT 24
Peak memory 213900 kb
Host smart-2447f6d1-19e3-4fc0-96b7-7f42378fa139
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120439937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2120439937
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1514854087
Short name T1027
Test name
Test status
Simulation time 61839002 ps
CPU time 3.38 seconds
Started Jun 09 12:43:27 PM PDT 24
Finished Jun 09 12:43:31 PM PDT 24
Peak memory 213740 kb
Host smart-166c77ed-79de-4b6f-8fa0-645f1e806b13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514854087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1514854087
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3145036015
Short name T1050
Test name
Test status
Simulation time 568568083 ps
CPU time 2.31 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:32 PM PDT 24
Peak memory 213884 kb
Host smart-15876e41-27da-4f4a-ac1f-1f0c05db4561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145036015 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3145036015
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3440584406
Short name T1036
Test name
Test status
Simulation time 128984279 ps
CPU time 1.6 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:35 PM PDT 24
Peak memory 205624 kb
Host smart-6e245e01-d8dc-47f3-bd38-e5143794f1fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440584406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3440584406
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1767155567
Short name T923
Test name
Test status
Simulation time 32080712 ps
CPU time 0.81 seconds
Started Jun 09 12:43:36 PM PDT 24
Finished Jun 09 12:43:38 PM PDT 24
Peak memory 205308 kb
Host smart-cd33a3a3-eb37-43bf-b69b-59cf5b555936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767155567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1767155567
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3498733684
Short name T968
Test name
Test status
Simulation time 88650924 ps
CPU time 3.36 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:34 PM PDT 24
Peak memory 205576 kb
Host smart-1c247f01-1c74-45ac-be2b-dedc95abc493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498733684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3498733684
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4058187800
Short name T1079
Test name
Test status
Simulation time 129313147 ps
CPU time 2.84 seconds
Started Jun 09 12:43:25 PM PDT 24
Finished Jun 09 12:43:28 PM PDT 24
Peak memory 214168 kb
Host smart-a21329ea-cf36-437e-bc4d-e22b41314ca7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058187800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.4058187800
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.628241303
Short name T997
Test name
Test status
Simulation time 432246755 ps
CPU time 4.43 seconds
Started Jun 09 12:43:25 PM PDT 24
Finished Jun 09 12:43:30 PM PDT 24
Peak memory 214196 kb
Host smart-14fb9158-dbed-4776-9bf2-4745331fb9a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628241303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.628241303
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3582006494
Short name T938
Test name
Test status
Simulation time 731771549 ps
CPU time 2.22 seconds
Started Jun 09 12:43:26 PM PDT 24
Finished Jun 09 12:43:29 PM PDT 24
Peak memory 217200 kb
Host smart-2928da25-9a57-48dd-9257-708e9aa1aed4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582006494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3582006494
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3990164940
Short name T928
Test name
Test status
Simulation time 107395879 ps
CPU time 4.48 seconds
Started Jun 09 12:43:36 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 213836 kb
Host smart-e1d8ae17-55d4-4c48-ac95-77fdf459265c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990164940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3990164940
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2182825578
Short name T983
Test name
Test status
Simulation time 178678740 ps
CPU time 2.19 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:31 PM PDT 24
Peak memory 213884 kb
Host smart-12e1d1b0-27d7-4a1a-ab5a-2989344a51af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182825578 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2182825578
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2365137288
Short name T1086
Test name
Test status
Simulation time 55961035 ps
CPU time 1.08 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:35 PM PDT 24
Peak memory 205548 kb
Host smart-2966059c-de2e-49cf-bf7e-f1048f9d91cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365137288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2365137288
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.920078459
Short name T1031
Test name
Test status
Simulation time 8285165 ps
CPU time 0.82 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:31 PM PDT 24
Peak memory 205316 kb
Host smart-cb3102df-a22f-4425-84e3-5cd3b485eca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920078459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.920078459
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2299071596
Short name T1015
Test name
Test status
Simulation time 43068712 ps
CPU time 1.94 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:32 PM PDT 24
Peak memory 205624 kb
Host smart-96c0f979-ba7d-4e26-8827-7fd35e1bee19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299071596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2299071596
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.730907309
Short name T1046
Test name
Test status
Simulation time 304779751 ps
CPU time 4.97 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:36 PM PDT 24
Peak memory 214164 kb
Host smart-8b213088-bb78-467a-af05-a882e3ea25de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730907309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.730907309
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.324276855
Short name T934
Test name
Test status
Simulation time 45025221 ps
CPU time 2.78 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:32 PM PDT 24
Peak memory 213924 kb
Host smart-e103a957-50ef-42b6-9ff3-b8c431495f29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324276855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.324276855
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1117233925
Short name T180
Test name
Test status
Simulation time 1967091685 ps
CPU time 4.97 seconds
Started Jun 09 12:43:27 PM PDT 24
Finished Jun 09 12:43:33 PM PDT 24
Peak memory 213812 kb
Host smart-d3c33806-c112-4cba-aade-5fe9192e19b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117233925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1117233925
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3597266726
Short name T925
Test name
Test status
Simulation time 90585582 ps
CPU time 1.13 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:30 PM PDT 24
Peak memory 205640 kb
Host smart-b29bfe5b-a50d-48a9-abba-61aa575724e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597266726 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3597266726
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4040350913
Short name T1006
Test name
Test status
Simulation time 13043988 ps
CPU time 1.23 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:32 PM PDT 24
Peak memory 205468 kb
Host smart-43802c1a-4d00-4295-96d4-2db86e620d69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040350913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.4040350913
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1856772428
Short name T1003
Test name
Test status
Simulation time 54144976 ps
CPU time 0.88 seconds
Started Jun 09 12:43:28 PM PDT 24
Finished Jun 09 12:43:30 PM PDT 24
Peak memory 205208 kb
Host smart-15ef126f-4d75-4601-86a4-65fbc8b74377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856772428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1856772428
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2533390950
Short name T1059
Test name
Test status
Simulation time 82280404 ps
CPU time 1.68 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:32 PM PDT 24
Peak memory 205600 kb
Host smart-bbe9fbe9-d942-461f-94b9-6d9393645019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533390950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2533390950
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3662440503
Short name T1073
Test name
Test status
Simulation time 494140069 ps
CPU time 2.6 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:32 PM PDT 24
Peak memory 214184 kb
Host smart-53870f81-4fd5-48e2-8740-957a2db1332c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662440503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3662440503
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3378372368
Short name T954
Test name
Test status
Simulation time 625793067 ps
CPU time 8.22 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:38 PM PDT 24
Peak memory 220300 kb
Host smart-66fba539-0daf-4f1a-8f04-6c2dcb9fe76d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378372368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3378372368
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2500825518
Short name T929
Test name
Test status
Simulation time 22946322 ps
CPU time 1.68 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:31 PM PDT 24
Peak memory 213844 kb
Host smart-04cbcaad-1d64-4fa6-bc80-11edeaa9980e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500825518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2500825518
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3521188952
Short name T177
Test name
Test status
Simulation time 2300878646 ps
CPU time 6.31 seconds
Started Jun 09 12:43:27 PM PDT 24
Finished Jun 09 12:43:33 PM PDT 24
Peak memory 213860 kb
Host smart-dc52c671-1118-4800-aa0b-769729bad62f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521188952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3521188952
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.630659856
Short name T1037
Test name
Test status
Simulation time 26987170 ps
CPU time 1.45 seconds
Started Jun 09 12:43:27 PM PDT 24
Finished Jun 09 12:43:29 PM PDT 24
Peak memory 213908 kb
Host smart-1074aaff-8446-4cd6-9364-504bbe89fc95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630659856 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.630659856
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4248044248
Short name T964
Test name
Test status
Simulation time 59822347 ps
CPU time 1.62 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:31 PM PDT 24
Peak memory 205644 kb
Host smart-449ca47e-70a6-4f7b-8bd1-676e838a864a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248044248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.4248044248
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3245983767
Short name T917
Test name
Test status
Simulation time 23244372 ps
CPU time 0.8 seconds
Started Jun 09 12:43:31 PM PDT 24
Finished Jun 09 12:43:32 PM PDT 24
Peak memory 205224 kb
Host smart-0fb82d2e-7263-4398-ae80-b3bde1280073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245983767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3245983767
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1158036425
Short name T1069
Test name
Test status
Simulation time 354052627 ps
CPU time 2.65 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:33 PM PDT 24
Peak memory 205556 kb
Host smart-cb3bd227-4a38-491e-a6ef-7fa286b95e55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158036425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1158036425
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3771948207
Short name T1077
Test name
Test status
Simulation time 306162698 ps
CPU time 2.31 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:32 PM PDT 24
Peak memory 214144 kb
Host smart-b936a2e1-f0e1-4b02-a67d-040798e101e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771948207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3771948207
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.332643723
Short name T124
Test name
Test status
Simulation time 1728823315 ps
CPU time 12.25 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 221192 kb
Host smart-c34344c3-062a-42d5-be1e-8533f883fd3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332643723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.332643723
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1676235186
Short name T972
Test name
Test status
Simulation time 566748503 ps
CPU time 4.62 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:35 PM PDT 24
Peak memory 213736 kb
Host smart-305fc556-1502-42a0-84e3-17e673a9a55a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676235186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1676235186
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.385639427
Short name T1025
Test name
Test status
Simulation time 30444591 ps
CPU time 1.52 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:35 PM PDT 24
Peak memory 213880 kb
Host smart-a4818c2b-181b-49ab-a09e-65876b17e0f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385639427 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.385639427
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2503923473
Short name T943
Test name
Test status
Simulation time 74163756 ps
CPU time 1.01 seconds
Started Jun 09 12:43:35 PM PDT 24
Finished Jun 09 12:43:36 PM PDT 24
Peak memory 205616 kb
Host smart-47f41133-2679-4ade-9406-da27d3bb975a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503923473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2503923473
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3385192535
Short name T1085
Test name
Test status
Simulation time 14680977 ps
CPU time 0.75 seconds
Started Jun 09 12:43:34 PM PDT 24
Finished Jun 09 12:43:35 PM PDT 24
Peak memory 205236 kb
Host smart-36d41216-6bc0-4658-b15f-568de089742c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385192535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3385192535
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.589170844
Short name T1028
Test name
Test status
Simulation time 138275454 ps
CPU time 2.14 seconds
Started Jun 09 12:43:36 PM PDT 24
Finished Jun 09 12:43:38 PM PDT 24
Peak memory 205592 kb
Host smart-c0b89d33-e33b-4f99-86b1-b17cde83dcbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589170844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.589170844
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2604196522
Short name T1010
Test name
Test status
Simulation time 594549107 ps
CPU time 3.1 seconds
Started Jun 09 12:43:29 PM PDT 24
Finished Jun 09 12:43:33 PM PDT 24
Peak memory 214180 kb
Host smart-0fc43b02-5ccf-4913-8e1d-ce5f4ae4de66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604196522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2604196522
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3193820711
Short name T1044
Test name
Test status
Simulation time 2344959815 ps
CPU time 6.02 seconds
Started Jun 09 12:43:27 PM PDT 24
Finished Jun 09 12:43:33 PM PDT 24
Peak memory 214104 kb
Host smart-80200040-9c4c-460c-94c3-76e66818e970
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193820711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3193820711
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4011610938
Short name T995
Test name
Test status
Simulation time 67211240 ps
CPU time 1.4 seconds
Started Jun 09 12:43:36 PM PDT 24
Finished Jun 09 12:43:38 PM PDT 24
Peak memory 213764 kb
Host smart-eb4488c6-394a-496b-ac48-70f15f43125b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011610938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4011610938
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1126617125
Short name T1051
Test name
Test status
Simulation time 206775428 ps
CPU time 2.3 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:36 PM PDT 24
Peak memory 213896 kb
Host smart-e34875ab-b727-4fcf-8eae-d43ef0073c02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126617125 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1126617125
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2873455448
Short name T1034
Test name
Test status
Simulation time 13009157 ps
CPU time 1.16 seconds
Started Jun 09 12:43:37 PM PDT 24
Finished Jun 09 12:43:39 PM PDT 24
Peak memory 205432 kb
Host smart-d9b781f3-6ac3-431b-849a-4a0cc8f22228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873455448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2873455448
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2833486705
Short name T1021
Test name
Test status
Simulation time 16870012 ps
CPU time 0.79 seconds
Started Jun 09 12:43:37 PM PDT 24
Finished Jun 09 12:43:38 PM PDT 24
Peak memory 205232 kb
Host smart-89dd5d83-95e0-4fb7-b591-610ead0e8d10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833486705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2833486705
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3100994587
Short name T161
Test name
Test status
Simulation time 49035088 ps
CPU time 1.7 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:35 PM PDT 24
Peak memory 205700 kb
Host smart-02ca4aec-89a2-4b65-bedc-e366f79d1b13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100994587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3100994587
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1392312991
Short name T126
Test name
Test status
Simulation time 657620608 ps
CPU time 2.87 seconds
Started Jun 09 12:43:38 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 214208 kb
Host smart-30c27de2-fe8c-4859-9852-50ba8788f5dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392312991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1392312991
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.735139652
Short name T993
Test name
Test status
Simulation time 156257907 ps
CPU time 3.6 seconds
Started Jun 09 12:43:30 PM PDT 24
Finished Jun 09 12:43:34 PM PDT 24
Peak memory 214144 kb
Host smart-924ae412-93ce-4ad9-9ab7-24f40640ab6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735139652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.735139652
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2792637099
Short name T932
Test name
Test status
Simulation time 322687062 ps
CPU time 3.09 seconds
Started Jun 09 12:43:37 PM PDT 24
Finished Jun 09 12:43:40 PM PDT 24
Peak memory 213768 kb
Host smart-4b66d455-8ab2-4a74-a336-beae8572c8fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792637099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2792637099
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.935680236
Short name T164
Test name
Test status
Simulation time 390231437 ps
CPU time 11.31 seconds
Started Jun 09 12:43:37 PM PDT 24
Finished Jun 09 12:43:49 PM PDT 24
Peak memory 205656 kb
Host smart-79fd01c5-1dc6-4dc0-af04-d71f5983927b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935680236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.935680236
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1607732430
Short name T1084
Test name
Test status
Simulation time 94965088 ps
CPU time 1.92 seconds
Started Jun 09 12:43:34 PM PDT 24
Finished Jun 09 12:43:36 PM PDT 24
Peak memory 217956 kb
Host smart-e8485911-2c57-4f05-8656-17cad66fb5c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607732430 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1607732430
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.886044700
Short name T1043
Test name
Test status
Simulation time 122565583 ps
CPU time 1.19 seconds
Started Jun 09 12:43:35 PM PDT 24
Finished Jun 09 12:43:36 PM PDT 24
Peak memory 205584 kb
Host smart-b6d0cd66-a56c-4b42-9823-980af7680f02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886044700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.886044700
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2955346155
Short name T945
Test name
Test status
Simulation time 22108124 ps
CPU time 0.73 seconds
Started Jun 09 12:43:32 PM PDT 24
Finished Jun 09 12:43:33 PM PDT 24
Peak memory 205148 kb
Host smart-e06a2a73-f046-4835-aa21-63b162cfa304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955346155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2955346155
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1737643017
Short name T1017
Test name
Test status
Simulation time 55997683 ps
CPU time 2.59 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:36 PM PDT 24
Peak memory 205560 kb
Host smart-5ff1edf7-a1d0-4cd0-9760-ff434a843f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737643017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1737643017
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3200332013
Short name T1062
Test name
Test status
Simulation time 148543591 ps
CPU time 2.14 seconds
Started Jun 09 12:43:35 PM PDT 24
Finished Jun 09 12:43:38 PM PDT 24
Peak memory 214180 kb
Host smart-acc6d802-bc39-45f6-88e5-747e0ccbce01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200332013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3200332013
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3683676035
Short name T120
Test name
Test status
Simulation time 338700515 ps
CPU time 4.21 seconds
Started Jun 09 12:43:40 PM PDT 24
Finished Jun 09 12:43:45 PM PDT 24
Peak memory 214092 kb
Host smart-def24ad2-6e97-429e-a532-46a6275f458d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683676035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3683676035
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1504771066
Short name T1005
Test name
Test status
Simulation time 554900931 ps
CPU time 4.43 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:38 PM PDT 24
Peak memory 213820 kb
Host smart-e7bc6654-9982-46e2-9d50-9a60cee8cbe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504771066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1504771066
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3357344447
Short name T1064
Test name
Test status
Simulation time 119901118 ps
CPU time 1.31 seconds
Started Jun 09 12:43:37 PM PDT 24
Finished Jun 09 12:43:39 PM PDT 24
Peak memory 205620 kb
Host smart-45c59a42-09bf-4bef-aaed-70544fa53f82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357344447 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3357344447
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3336120225
Short name T946
Test name
Test status
Simulation time 37497672 ps
CPU time 1.19 seconds
Started Jun 09 12:43:41 PM PDT 24
Finished Jun 09 12:43:42 PM PDT 24
Peak memory 205472 kb
Host smart-6e744d75-71fa-45dd-a19e-9dda80e77f4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336120225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3336120225
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1857908821
Short name T1068
Test name
Test status
Simulation time 11452841 ps
CPU time 0.72 seconds
Started Jun 09 12:43:37 PM PDT 24
Finished Jun 09 12:43:38 PM PDT 24
Peak memory 205064 kb
Host smart-1d7a50f1-91cc-4da0-89b8-c81c44f98703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857908821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1857908821
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2620883398
Short name T951
Test name
Test status
Simulation time 190808029 ps
CPU time 3.33 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:37 PM PDT 24
Peak memory 205608 kb
Host smart-e773030a-8032-4d61-ae16-d8ed3f463ddb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620883398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2620883398
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2429611890
Short name T1012
Test name
Test status
Simulation time 1001026540 ps
CPU time 1.48 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:35 PM PDT 24
Peak memory 214204 kb
Host smart-85a4649e-e21f-40d9-bbba-2d473187357b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429611890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2429611890
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2117030891
Short name T967
Test name
Test status
Simulation time 60612860 ps
CPU time 2.57 seconds
Started Jun 09 12:43:36 PM PDT 24
Finished Jun 09 12:43:39 PM PDT 24
Peak memory 215980 kb
Host smart-7604755d-b89b-463c-b169-01382d5f0049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117030891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2117030891
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.425069033
Short name T171
Test name
Test status
Simulation time 101133966 ps
CPU time 3.39 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:37 PM PDT 24
Peak memory 205576 kb
Host smart-15da2d12-be8c-49ca-909a-df231d39ad4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425069033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.425069033
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2021096676
Short name T1038
Test name
Test status
Simulation time 291747607 ps
CPU time 7.93 seconds
Started Jun 09 12:43:03 PM PDT 24
Finished Jun 09 12:43:11 PM PDT 24
Peak memory 205624 kb
Host smart-68077d3e-9368-49be-927b-c5426e8ffbea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021096676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
021096676
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1501346016
Short name T933
Test name
Test status
Simulation time 514913557 ps
CPU time 6.43 seconds
Started Jun 09 12:43:04 PM PDT 24
Finished Jun 09 12:43:11 PM PDT 24
Peak memory 205640 kb
Host smart-09e4ac39-ecb9-46af-8e2c-6889dc6ad509
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501346016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
501346016
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.122439758
Short name T1082
Test name
Test status
Simulation time 18639493 ps
CPU time 1.16 seconds
Started Jun 09 12:43:04 PM PDT 24
Finished Jun 09 12:43:05 PM PDT 24
Peak memory 205692 kb
Host smart-5860dc64-f764-4f8e-84cb-24cd855de5cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122439758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.122439758
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.359345716
Short name T1045
Test name
Test status
Simulation time 93633526 ps
CPU time 2.11 seconds
Started Jun 09 12:43:05 PM PDT 24
Finished Jun 09 12:43:07 PM PDT 24
Peak memory 213932 kb
Host smart-7cd23e99-882a-4a9d-b3eb-137bf0bf39ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359345716 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.359345716
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.941493873
Short name T989
Test name
Test status
Simulation time 15751551 ps
CPU time 1.17 seconds
Started Jun 09 12:43:05 PM PDT 24
Finished Jun 09 12:43:07 PM PDT 24
Peak memory 205656 kb
Host smart-43f238e6-47ba-49f6-a1c5-25168bb195eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941493873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.941493873
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2060716921
Short name T959
Test name
Test status
Simulation time 25216628 ps
CPU time 0.74 seconds
Started Jun 09 12:43:05 PM PDT 24
Finished Jun 09 12:43:06 PM PDT 24
Peak memory 205312 kb
Host smart-3b60bb89-3310-4e7d-be1e-4e1b74dd5619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060716921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2060716921
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1374585999
Short name T988
Test name
Test status
Simulation time 215408337 ps
CPU time 1.79 seconds
Started Jun 09 12:43:04 PM PDT 24
Finished Jun 09 12:43:06 PM PDT 24
Peak memory 205716 kb
Host smart-d08b2e14-2beb-4cfa-abe7-f6446a3e1235
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374585999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1374585999
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3667345383
Short name T1067
Test name
Test status
Simulation time 299002528 ps
CPU time 3.66 seconds
Started Jun 09 12:43:03 PM PDT 24
Finished Jun 09 12:43:07 PM PDT 24
Peak memory 214172 kb
Host smart-4760a463-7e80-497b-9e30-993e403635de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667345383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3667345383
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.986614890
Short name T956
Test name
Test status
Simulation time 340291428 ps
CPU time 8.51 seconds
Started Jun 09 12:43:05 PM PDT 24
Finished Jun 09 12:43:14 PM PDT 24
Peak memory 220360 kb
Host smart-371ae89b-8d4b-4a37-b821-c0cd4a78de60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986614890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.986614890
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2509666855
Short name T961
Test name
Test status
Simulation time 352134504 ps
CPU time 2.8 seconds
Started Jun 09 12:43:04 PM PDT 24
Finished Jun 09 12:43:07 PM PDT 24
Peak memory 213852 kb
Host smart-8ccb7068-b193-4619-9989-58b75f3975a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509666855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2509666855
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2208868222
Short name T1002
Test name
Test status
Simulation time 267390919 ps
CPU time 4.01 seconds
Started Jun 09 12:43:02 PM PDT 24
Finished Jun 09 12:43:07 PM PDT 24
Peak memory 213812 kb
Host smart-02f4af76-5800-49d3-914d-e5d156aa7f88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208868222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2208868222
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1972881451
Short name T1066
Test name
Test status
Simulation time 51505997 ps
CPU time 0.84 seconds
Started Jun 09 12:43:37 PM PDT 24
Finished Jun 09 12:43:39 PM PDT 24
Peak memory 205308 kb
Host smart-d0fb5318-37df-46e3-b4b6-5ffc44c93dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972881451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1972881451
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2705613398
Short name T930
Test name
Test status
Simulation time 37016726 ps
CPU time 0.83 seconds
Started Jun 09 12:43:41 PM PDT 24
Finished Jun 09 12:43:42 PM PDT 24
Peak memory 205124 kb
Host smart-e6cf18fc-2452-4c03-9ff1-5b350bedcd14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705613398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2705613398
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2100036131
Short name T920
Test name
Test status
Simulation time 28353465 ps
CPU time 0.75 seconds
Started Jun 09 12:43:33 PM PDT 24
Finished Jun 09 12:43:34 PM PDT 24
Peak memory 205232 kb
Host smart-a727a97c-840f-4f6b-9634-02623c7811d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100036131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2100036131
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3193746626
Short name T953
Test name
Test status
Simulation time 9436980 ps
CPU time 0.82 seconds
Started Jun 09 12:43:37 PM PDT 24
Finished Jun 09 12:43:38 PM PDT 24
Peak memory 205308 kb
Host smart-6c36dd8c-640d-458e-998d-23974d9e6413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193746626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3193746626
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.27634151
Short name T1087
Test name
Test status
Simulation time 54739235 ps
CPU time 0.81 seconds
Started Jun 09 12:43:35 PM PDT 24
Finished Jun 09 12:43:36 PM PDT 24
Peak memory 205284 kb
Host smart-1c52d9c6-e678-400a-9ea1-bd412e8bfe2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27634151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.27634151
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3351975270
Short name T940
Test name
Test status
Simulation time 8510163 ps
CPU time 0.71 seconds
Started Jun 09 12:43:38 PM PDT 24
Finished Jun 09 12:43:39 PM PDT 24
Peak memory 205244 kb
Host smart-6ee0bdc4-4c86-4bbc-91fb-cc01f63c7e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351975270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3351975270
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1175029470
Short name T999
Test name
Test status
Simulation time 28409158 ps
CPU time 0.69 seconds
Started Jun 09 12:43:36 PM PDT 24
Finished Jun 09 12:43:37 PM PDT 24
Peak memory 205304 kb
Host smart-bd0ed594-93ff-4f43-9bd9-87745f2b54ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175029470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1175029470
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.724685832
Short name T1075
Test name
Test status
Simulation time 8821196 ps
CPU time 0.78 seconds
Started Jun 09 12:43:35 PM PDT 24
Finished Jun 09 12:43:36 PM PDT 24
Peak memory 205192 kb
Host smart-91167e15-3c94-426e-b77e-2803ec393eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724685832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.724685832
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3885336803
Short name T952
Test name
Test status
Simulation time 37843892 ps
CPU time 0.8 seconds
Started Jun 09 12:43:40 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 205304 kb
Host smart-415b956b-b43b-4b09-8a9e-9d5c48b914bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885336803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3885336803
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2178844361
Short name T986
Test name
Test status
Simulation time 30849819 ps
CPU time 0.82 seconds
Started Jun 09 12:43:40 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 205308 kb
Host smart-0d96ff92-5047-465f-bbc3-276a1e75ccbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178844361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2178844361
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2458431272
Short name T160
Test name
Test status
Simulation time 264600751 ps
CPU time 4.69 seconds
Started Jun 09 12:43:07 PM PDT 24
Finished Jun 09 12:43:12 PM PDT 24
Peak memory 205684 kb
Host smart-de52a186-f4c1-445e-bde5-ecdbcf683668
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458431272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
458431272
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2140985874
Short name T1029
Test name
Test status
Simulation time 7246425696 ps
CPU time 9.71 seconds
Started Jun 09 12:43:07 PM PDT 24
Finished Jun 09 12:43:17 PM PDT 24
Peak memory 205752 kb
Host smart-cc486054-dd39-463f-a232-6ae1fbf839d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140985874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
140985874
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.37808486
Short name T1013
Test name
Test status
Simulation time 104224642 ps
CPU time 1.4 seconds
Started Jun 09 12:43:07 PM PDT 24
Finished Jun 09 12:43:09 PM PDT 24
Peak memory 205616 kb
Host smart-2354add4-1bb0-4408-a601-bb6a25d43d64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37808486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.37808486
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.667382613
Short name T1001
Test name
Test status
Simulation time 21645324 ps
CPU time 1.65 seconds
Started Jun 09 12:43:12 PM PDT 24
Finished Jun 09 12:43:14 PM PDT 24
Peak memory 213976 kb
Host smart-346d93c4-d112-4502-8a36-3754945c6582
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667382613 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.667382613
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3664487871
Short name T156
Test name
Test status
Simulation time 13478813 ps
CPU time 1.15 seconds
Started Jun 09 12:43:11 PM PDT 24
Finished Jun 09 12:43:13 PM PDT 24
Peak memory 205720 kb
Host smart-c59dc8e3-d9b2-4f36-8813-54b2ff630f99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664487871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3664487871
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3379197374
Short name T1008
Test name
Test status
Simulation time 15146048 ps
CPU time 0.7 seconds
Started Jun 09 12:43:06 PM PDT 24
Finished Jun 09 12:43:07 PM PDT 24
Peak memory 205312 kb
Host smart-1143fe22-22ce-45cc-8e97-993efdb7a8a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379197374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3379197374
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1997156673
Short name T1041
Test name
Test status
Simulation time 468025211 ps
CPU time 4.11 seconds
Started Jun 09 12:43:12 PM PDT 24
Finished Jun 09 12:43:16 PM PDT 24
Peak memory 205620 kb
Host smart-4097d547-e283-4c47-acc2-cf3a33d2eca7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997156673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1997156673
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2521626372
Short name T1074
Test name
Test status
Simulation time 167224528 ps
CPU time 3.52 seconds
Started Jun 09 12:43:11 PM PDT 24
Finished Jun 09 12:43:15 PM PDT 24
Peak memory 214248 kb
Host smart-b6c7cbae-68f2-4a01-9e67-10499bc31903
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521626372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2521626372
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.135407445
Short name T1060
Test name
Test status
Simulation time 86323451 ps
CPU time 4.01 seconds
Started Jun 09 12:43:08 PM PDT 24
Finished Jun 09 12:43:13 PM PDT 24
Peak memory 220148 kb
Host smart-a847c3f0-54d9-46b1-b4d4-95d805b5586b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135407445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.135407445
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1842400305
Short name T1076
Test name
Test status
Simulation time 116423123 ps
CPU time 4.52 seconds
Started Jun 09 12:43:06 PM PDT 24
Finished Jun 09 12:43:11 PM PDT 24
Peak memory 213824 kb
Host smart-ff12d8a3-84b1-426b-9edb-5ee59274764f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842400305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1842400305
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.485217943
Short name T1057
Test name
Test status
Simulation time 31291594 ps
CPU time 0.8 seconds
Started Jun 09 12:43:39 PM PDT 24
Finished Jun 09 12:43:40 PM PDT 24
Peak memory 205248 kb
Host smart-adcbfd1f-ddb5-4fe0-9614-26503843b7b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485217943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.485217943
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.287782258
Short name T973
Test name
Test status
Simulation time 13997031 ps
CPU time 0.77 seconds
Started Jun 09 12:43:39 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 205296 kb
Host smart-e6262a5b-4f20-42e9-a1b3-879ce18c6c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287782258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.287782258
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.314266478
Short name T921
Test name
Test status
Simulation time 30516289 ps
CPU time 0.8 seconds
Started Jun 09 12:43:39 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 205316 kb
Host smart-aca15a97-523e-46ac-9bc1-45e322db64dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314266478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.314266478
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2817883936
Short name T996
Test name
Test status
Simulation time 28947560 ps
CPU time 0.74 seconds
Started Jun 09 12:43:41 PM PDT 24
Finished Jun 09 12:43:43 PM PDT 24
Peak memory 205284 kb
Host smart-2a617b39-d8f8-4bd5-b744-1c21e67ee6dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817883936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2817883936
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1359838306
Short name T992
Test name
Test status
Simulation time 10531646 ps
CPU time 0.75 seconds
Started Jun 09 12:43:38 PM PDT 24
Finished Jun 09 12:43:39 PM PDT 24
Peak memory 205248 kb
Host smart-0f6f744a-1cf8-47f2-b2a0-46bb4a799088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359838306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1359838306
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1789733179
Short name T915
Test name
Test status
Simulation time 19731008 ps
CPU time 0.76 seconds
Started Jun 09 12:43:40 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 205228 kb
Host smart-1e6eab41-01a7-4fe8-943e-44eb9cc557a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789733179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1789733179
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4226418586
Short name T939
Test name
Test status
Simulation time 36205732 ps
CPU time 0.72 seconds
Started Jun 09 12:43:39 PM PDT 24
Finished Jun 09 12:43:40 PM PDT 24
Peak memory 205232 kb
Host smart-6744c8d7-7ad1-4760-8c0e-bc74474bf8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226418586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4226418586
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2809614592
Short name T994
Test name
Test status
Simulation time 9093007 ps
CPU time 0.79 seconds
Started Jun 09 12:43:38 PM PDT 24
Finished Jun 09 12:43:40 PM PDT 24
Peak memory 205232 kb
Host smart-12f59012-efcf-4847-a206-75a63f7ce00d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809614592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2809614592
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.690662581
Short name T949
Test name
Test status
Simulation time 42104551 ps
CPU time 0.85 seconds
Started Jun 09 12:43:36 PM PDT 24
Finished Jun 09 12:43:37 PM PDT 24
Peak memory 205580 kb
Host smart-ff85c3dc-7383-4c4a-ac4d-b27cf2c4415b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690662581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.690662581
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.78465260
Short name T1035
Test name
Test status
Simulation time 18127649 ps
CPU time 0.95 seconds
Started Jun 09 12:43:38 PM PDT 24
Finished Jun 09 12:43:39 PM PDT 24
Peak memory 205496 kb
Host smart-c98fc0fb-3104-4b75-90ed-3509e40aad2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78465260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.78465260
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1830424758
Short name T977
Test name
Test status
Simulation time 494054888 ps
CPU time 9.28 seconds
Started Jun 09 12:43:13 PM PDT 24
Finished Jun 09 12:43:23 PM PDT 24
Peak memory 205540 kb
Host smart-5566ca31-421f-4c0e-a91e-7b6f566bd53a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830424758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
830424758
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2158776785
Short name T1019
Test name
Test status
Simulation time 523683005 ps
CPU time 6.37 seconds
Started Jun 09 12:43:12 PM PDT 24
Finished Jun 09 12:43:18 PM PDT 24
Peak memory 205624 kb
Host smart-847b93a6-817a-4dc2-9821-cdb81d546990
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158776785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
158776785
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.230448621
Short name T1022
Test name
Test status
Simulation time 34513314 ps
CPU time 1.04 seconds
Started Jun 09 12:43:12 PM PDT 24
Finished Jun 09 12:43:13 PM PDT 24
Peak memory 205352 kb
Host smart-618f883b-b799-4a29-b81c-af075afb6847
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230448621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.230448621
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1297523949
Short name T1065
Test name
Test status
Simulation time 156830617 ps
CPU time 1.63 seconds
Started Jun 09 12:43:13 PM PDT 24
Finished Jun 09 12:43:15 PM PDT 24
Peak memory 213836 kb
Host smart-dce9f726-5515-4071-97c0-fd4f51c681ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297523949 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1297523949
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.97241955
Short name T163
Test name
Test status
Simulation time 224455294 ps
CPU time 1.2 seconds
Started Jun 09 12:43:13 PM PDT 24
Finished Jun 09 12:43:14 PM PDT 24
Peak memory 205580 kb
Host smart-b785a0bf-dc08-4a9f-bf8b-d51181f7873a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97241955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.97241955
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3993765271
Short name T1020
Test name
Test status
Simulation time 136390486 ps
CPU time 0.74 seconds
Started Jun 09 12:43:11 PM PDT 24
Finished Jun 09 12:43:13 PM PDT 24
Peak memory 205188 kb
Host smart-b4604dbf-b70c-4281-921f-05ef24dd69cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993765271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3993765271
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2389246559
Short name T157
Test name
Test status
Simulation time 118051891 ps
CPU time 2.91 seconds
Started Jun 09 12:43:12 PM PDT 24
Finished Jun 09 12:43:15 PM PDT 24
Peak memory 205900 kb
Host smart-ded05380-d726-43a5-bced-347fd108586a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389246559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2389246559
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1169196238
Short name T1040
Test name
Test status
Simulation time 206735505 ps
CPU time 5.46 seconds
Started Jun 09 12:43:07 PM PDT 24
Finished Jun 09 12:43:13 PM PDT 24
Peak memory 214060 kb
Host smart-6963f3d1-d575-454a-bb1d-f81e95eb8776
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169196238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1169196238
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2049463759
Short name T935
Test name
Test status
Simulation time 31646478 ps
CPU time 1.37 seconds
Started Jun 09 12:43:09 PM PDT 24
Finished Jun 09 12:43:11 PM PDT 24
Peak memory 213880 kb
Host smart-44fc5326-47d1-4929-b141-a89d58dc2f50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049463759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2049463759
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1317659011
Short name T987
Test name
Test status
Simulation time 46986562 ps
CPU time 0.71 seconds
Started Jun 09 12:43:41 PM PDT 24
Finished Jun 09 12:43:42 PM PDT 24
Peak memory 205232 kb
Host smart-a06233d6-31a8-4445-a9d2-857e8f456b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317659011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1317659011
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.891076928
Short name T927
Test name
Test status
Simulation time 10736072 ps
CPU time 0.81 seconds
Started Jun 09 12:43:40 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 205316 kb
Host smart-a77d1f5b-c1b0-4c32-9dab-3aee182c30ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891076928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.891076928
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3364553306
Short name T998
Test name
Test status
Simulation time 47980930 ps
CPU time 0.91 seconds
Started Jun 09 12:43:40 PM PDT 24
Finished Jun 09 12:43:42 PM PDT 24
Peak memory 205308 kb
Host smart-af975f95-40d9-4aae-b1e7-12c31e22d6cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364553306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3364553306
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1904941035
Short name T913
Test name
Test status
Simulation time 10334794 ps
CPU time 0.81 seconds
Started Jun 09 12:43:39 PM PDT 24
Finished Jun 09 12:43:40 PM PDT 24
Peak memory 205312 kb
Host smart-85d470f4-0540-48e4-a2cc-61574e9fd79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904941035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1904941035
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.240060626
Short name T979
Test name
Test status
Simulation time 12642264 ps
CPU time 0.91 seconds
Started Jun 09 12:43:40 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 205264 kb
Host smart-f2a302cf-5f1a-4f19-b821-ecf3a624573e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240060626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.240060626
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1376435544
Short name T1014
Test name
Test status
Simulation time 34108445 ps
CPU time 0.83 seconds
Started Jun 09 12:43:40 PM PDT 24
Finished Jun 09 12:43:41 PM PDT 24
Peak memory 205284 kb
Host smart-c1615a99-ad07-4d5d-a4c0-d2eecb5ac7bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376435544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1376435544
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3117065006
Short name T1016
Test name
Test status
Simulation time 10377166 ps
CPU time 0.85 seconds
Started Jun 09 12:43:41 PM PDT 24
Finished Jun 09 12:43:42 PM PDT 24
Peak memory 205596 kb
Host smart-cb2c7409-03fb-49a8-a8b1-8456ecfe44c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117065006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3117065006
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1683217607
Short name T1032
Test name
Test status
Simulation time 21706482 ps
CPU time 0.83 seconds
Started Jun 09 12:43:46 PM PDT 24
Finished Jun 09 12:43:48 PM PDT 24
Peak memory 205236 kb
Host smart-49c41d55-b411-40f9-ad84-697f8837578d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683217607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1683217607
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2471254149
Short name T1039
Test name
Test status
Simulation time 20775116 ps
CPU time 0.72 seconds
Started Jun 09 12:43:42 PM PDT 24
Finished Jun 09 12:43:44 PM PDT 24
Peak memory 205232 kb
Host smart-3dd30823-814e-46dd-b138-616175fcbae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471254149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2471254149
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.382651433
Short name T914
Test name
Test status
Simulation time 21878951 ps
CPU time 0.78 seconds
Started Jun 09 12:43:46 PM PDT 24
Finished Jun 09 12:43:47 PM PDT 24
Peak memory 205316 kb
Host smart-c94a8adf-ee31-4271-9c4a-685f8bf52a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382651433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.382651433
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1385062198
Short name T1026
Test name
Test status
Simulation time 79781213 ps
CPU time 1.97 seconds
Started Jun 09 12:43:11 PM PDT 24
Finished Jun 09 12:43:13 PM PDT 24
Peak memory 213864 kb
Host smart-92a92803-a2c9-49b8-8955-d14aee11e7e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385062198 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1385062198
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3056961109
Short name T1033
Test name
Test status
Simulation time 169065586 ps
CPU time 1.34 seconds
Started Jun 09 12:43:12 PM PDT 24
Finished Jun 09 12:43:14 PM PDT 24
Peak memory 205568 kb
Host smart-43370fd4-93c2-41e7-802e-008f69431f1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056961109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3056961109
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2414801982
Short name T922
Test name
Test status
Simulation time 24523839 ps
CPU time 0.84 seconds
Started Jun 09 12:43:11 PM PDT 24
Finished Jun 09 12:43:12 PM PDT 24
Peak memory 205536 kb
Host smart-b2e74463-5858-4cc7-8992-cb470f45283a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414801982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2414801982
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.359778811
Short name T1011
Test name
Test status
Simulation time 121970567 ps
CPU time 1.89 seconds
Started Jun 09 12:43:23 PM PDT 24
Finished Jun 09 12:43:25 PM PDT 24
Peak memory 205488 kb
Host smart-180c36a8-4627-41cd-a292-74bb3992e95a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359778811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.359778811
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1157078453
Short name T1030
Test name
Test status
Simulation time 147538689 ps
CPU time 3.08 seconds
Started Jun 09 12:43:13 PM PDT 24
Finished Jun 09 12:43:17 PM PDT 24
Peak memory 214244 kb
Host smart-e3f66d14-ad0e-4ec5-9fe5-a89c7f360504
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157078453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1157078453
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.239883990
Short name T1072
Test name
Test status
Simulation time 299921743 ps
CPU time 3.94 seconds
Started Jun 09 12:43:23 PM PDT 24
Finished Jun 09 12:43:27 PM PDT 24
Peak memory 214072 kb
Host smart-cf13d489-4983-402d-a290-ecf585a7b15a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239883990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.239883990
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.926749379
Short name T948
Test name
Test status
Simulation time 160863021 ps
CPU time 5.29 seconds
Started Jun 09 12:43:16 PM PDT 24
Finished Jun 09 12:43:22 PM PDT 24
Peak memory 213812 kb
Host smart-b009d596-0ed3-46e9-b1ff-9b3518a451b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926749379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.926749379
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3413246307
Short name T1023
Test name
Test status
Simulation time 18459770 ps
CPU time 1.05 seconds
Started Jun 09 12:43:21 PM PDT 24
Finished Jun 09 12:43:23 PM PDT 24
Peak memory 205392 kb
Host smart-d9839ee6-0979-4b5a-a319-24a28d6c99cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413246307 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3413246307
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.159144587
Short name T1054
Test name
Test status
Simulation time 19985292 ps
CPU time 0.97 seconds
Started Jun 09 12:43:14 PM PDT 24
Finished Jun 09 12:43:15 PM PDT 24
Peak memory 205360 kb
Host smart-f9767f93-43a5-4905-8cc1-5c091c0281a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159144587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.159144587
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1856288733
Short name T937
Test name
Test status
Simulation time 17765408 ps
CPU time 0.84 seconds
Started Jun 09 12:43:15 PM PDT 24
Finished Jun 09 12:43:16 PM PDT 24
Peak memory 205300 kb
Host smart-e4eca34d-5466-47d7-8355-3ae024f8d399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856288733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1856288733
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.895976611
Short name T1080
Test name
Test status
Simulation time 20964744 ps
CPU time 1.28 seconds
Started Jun 09 12:43:13 PM PDT 24
Finished Jun 09 12:43:15 PM PDT 24
Peak memory 205608 kb
Host smart-145092c6-fc9f-483a-bcac-4c83fe4ed917
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895976611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.895976611
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2697576398
Short name T1056
Test name
Test status
Simulation time 43257325 ps
CPU time 1.55 seconds
Started Jun 09 12:43:13 PM PDT 24
Finished Jun 09 12:43:15 PM PDT 24
Peak memory 214184 kb
Host smart-ca2cc916-c5e7-47dc-849c-463ca8a44589
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697576398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2697576398
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.9493637
Short name T1078
Test name
Test status
Simulation time 1453322685 ps
CPU time 6.75 seconds
Started Jun 09 12:43:13 PM PDT 24
Finished Jun 09 12:43:20 PM PDT 24
Peak memory 214164 kb
Host smart-1075de9e-85f4-430e-a29c-9bd1f27c881b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9493637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_S
EQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.key
mgr_shadow_reg_errors_with_csr_rw.9493637
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3743907916
Short name T936
Test name
Test status
Simulation time 196439625 ps
CPU time 1.88 seconds
Started Jun 09 12:43:23 PM PDT 24
Finished Jun 09 12:43:25 PM PDT 24
Peak memory 213732 kb
Host smart-35db5d60-416a-455c-961a-745381553115
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743907916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3743907916
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.816197677
Short name T1009
Test name
Test status
Simulation time 279257347 ps
CPU time 4.08 seconds
Started Jun 09 12:43:12 PM PDT 24
Finished Jun 09 12:43:17 PM PDT 24
Peak memory 205612 kb
Host smart-d03257ef-bdbe-4b59-821a-7b8d1a7c3bb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816197677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
816197677
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3684111313
Short name T1042
Test name
Test status
Simulation time 113510405 ps
CPU time 2.03 seconds
Started Jun 09 12:43:21 PM PDT 24
Finished Jun 09 12:43:23 PM PDT 24
Peak memory 221988 kb
Host smart-e7e345f5-2daa-49d8-85e3-4df3605108bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684111313 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3684111313
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2188209639
Short name T958
Test name
Test status
Simulation time 30732651 ps
CPU time 1.05 seconds
Started Jun 09 12:43:18 PM PDT 24
Finished Jun 09 12:43:20 PM PDT 24
Peak memory 205348 kb
Host smart-a2f21134-1363-4d7d-945f-a79a3076a3ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188209639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2188209639
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3686418694
Short name T991
Test name
Test status
Simulation time 22098240 ps
CPU time 0.77 seconds
Started Jun 09 12:43:18 PM PDT 24
Finished Jun 09 12:43:19 PM PDT 24
Peak memory 205324 kb
Host smart-815236d2-11db-4b1c-aabe-908ea8ca7d1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686418694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3686418694
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2001374934
Short name T159
Test name
Test status
Simulation time 67093526 ps
CPU time 2.03 seconds
Started Jun 09 12:43:18 PM PDT 24
Finished Jun 09 12:43:21 PM PDT 24
Peak memory 205576 kb
Host smart-f215388c-32f2-493a-8f37-abffb6edb359
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001374934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2001374934
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3532844338
Short name T1024
Test name
Test status
Simulation time 499077215 ps
CPU time 3.87 seconds
Started Jun 09 12:43:20 PM PDT 24
Finished Jun 09 12:43:25 PM PDT 24
Peak memory 214180 kb
Host smart-2a7402f5-6df0-4c06-9674-2c91f74b9068
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532844338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3532844338
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1448865135
Short name T966
Test name
Test status
Simulation time 840187144 ps
CPU time 9.46 seconds
Started Jun 09 12:43:23 PM PDT 24
Finished Jun 09 12:43:33 PM PDT 24
Peak memory 214200 kb
Host smart-2a5e797c-cf3b-4e1a-895f-cb3830c2ef76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448865135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1448865135
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2913228134
Short name T926
Test name
Test status
Simulation time 89187666 ps
CPU time 2.49 seconds
Started Jun 09 12:43:24 PM PDT 24
Finished Jun 09 12:43:27 PM PDT 24
Peak memory 213788 kb
Host smart-d88d06ee-ba33-4647-9668-890ed316ae5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913228134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2913228134
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.573452308
Short name T918
Test name
Test status
Simulation time 175873190 ps
CPU time 1.66 seconds
Started Jun 09 12:43:19 PM PDT 24
Finished Jun 09 12:43:21 PM PDT 24
Peak memory 213920 kb
Host smart-630cb5e1-706d-4a83-9c45-0d4872567e3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573452308 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.573452308
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.461015061
Short name T1081
Test name
Test status
Simulation time 26766430 ps
CPU time 1.14 seconds
Started Jun 09 12:43:22 PM PDT 24
Finished Jun 09 12:43:23 PM PDT 24
Peak memory 205552 kb
Host smart-ee0df57a-9b18-4578-a827-4be71fc0f6f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461015061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.461015061
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2336443552
Short name T931
Test name
Test status
Simulation time 88289889 ps
CPU time 0.76 seconds
Started Jun 09 12:43:19 PM PDT 24
Finished Jun 09 12:43:20 PM PDT 24
Peak memory 205320 kb
Host smart-d3bf3cc3-87b8-4ec2-83fc-60e3b9976853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336443552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2336443552
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1961985107
Short name T1058
Test name
Test status
Simulation time 208728954 ps
CPU time 1.76 seconds
Started Jun 09 12:43:19 PM PDT 24
Finished Jun 09 12:43:22 PM PDT 24
Peak memory 205560 kb
Host smart-96909c01-b154-4ed3-90e5-600b84b76b78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961985107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1961985107
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.792668264
Short name T965
Test name
Test status
Simulation time 827278865 ps
CPU time 2.43 seconds
Started Jun 09 12:43:23 PM PDT 24
Finished Jun 09 12:43:26 PM PDT 24
Peak memory 214072 kb
Host smart-f2416d89-195d-456d-8549-e0d92ef2e30e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792668264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.792668264
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1688060302
Short name T974
Test name
Test status
Simulation time 667425057 ps
CPU time 11.75 seconds
Started Jun 09 12:43:23 PM PDT 24
Finished Jun 09 12:43:35 PM PDT 24
Peak memory 220256 kb
Host smart-b7bf1d3c-0097-40e3-a76a-023839d3d133
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688060302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1688060302
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2942323134
Short name T950
Test name
Test status
Simulation time 132028526 ps
CPU time 2.86 seconds
Started Jun 09 12:43:19 PM PDT 24
Finished Jun 09 12:43:22 PM PDT 24
Peak memory 213824 kb
Host smart-392feef3-1dbb-43c5-a951-8c57b76f795d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942323134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2942323134
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3068228434
Short name T970
Test name
Test status
Simulation time 114766302 ps
CPU time 4.74 seconds
Started Jun 09 12:43:23 PM PDT 24
Finished Jun 09 12:43:28 PM PDT 24
Peak memory 213720 kb
Host smart-cffe6068-f4e9-45f3-af6d-97623793cf1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068228434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3068228434
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1921292824
Short name T1018
Test name
Test status
Simulation time 76853658 ps
CPU time 1.36 seconds
Started Jun 09 12:43:21 PM PDT 24
Finished Jun 09 12:43:23 PM PDT 24
Peak memory 205632 kb
Host smart-4823d861-8360-4664-8e26-9eac978ca84d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921292824 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1921292824
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3056029201
Short name T158
Test name
Test status
Simulation time 22862797 ps
CPU time 0.91 seconds
Started Jun 09 12:43:20 PM PDT 24
Finished Jun 09 12:43:21 PM PDT 24
Peak memory 205392 kb
Host smart-90096014-9a28-49ec-b8df-6ff9b86c58f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056029201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3056029201
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1163271184
Short name T982
Test name
Test status
Simulation time 8791643 ps
CPU time 0.8 seconds
Started Jun 09 12:43:22 PM PDT 24
Finished Jun 09 12:43:23 PM PDT 24
Peak memory 205308 kb
Host smart-4ac00394-31f3-4850-9a69-178be81a9739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163271184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1163271184
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1500838541
Short name T1061
Test name
Test status
Simulation time 437005956 ps
CPU time 2.8 seconds
Started Jun 09 12:43:21 PM PDT 24
Finished Jun 09 12:43:25 PM PDT 24
Peak memory 205632 kb
Host smart-90299175-8fb2-4ccc-af46-ad24b873e338
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500838541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1500838541
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.665094936
Short name T963
Test name
Test status
Simulation time 216367553 ps
CPU time 2.1 seconds
Started Jun 09 12:43:19 PM PDT 24
Finished Jun 09 12:43:21 PM PDT 24
Peak memory 214228 kb
Host smart-9a8082a2-f7cf-4fc6-a49a-8ffd93deb4a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665094936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.665094936
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3991150285
Short name T121
Test name
Test status
Simulation time 1162511553 ps
CPU time 9.35 seconds
Started Jun 09 12:43:21 PM PDT 24
Finished Jun 09 12:43:31 PM PDT 24
Peak memory 214220 kb
Host smart-5db292cb-56d8-4ce5-8e36-696171c89d15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991150285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3991150285
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.455025045
Short name T1047
Test name
Test status
Simulation time 31474789 ps
CPU time 1.83 seconds
Started Jun 09 12:43:19 PM PDT 24
Finished Jun 09 12:43:22 PM PDT 24
Peak memory 215880 kb
Host smart-233decd2-138f-4406-a636-29a0c73356e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455025045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.455025045
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2989874043
Short name T182
Test name
Test status
Simulation time 165161863 ps
CPU time 5.44 seconds
Started Jun 09 12:43:21 PM PDT 24
Finished Jun 09 12:43:26 PM PDT 24
Peak memory 214128 kb
Host smart-965e16ca-14e9-49dd-bed2-8fda9d93c2eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989874043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2989874043
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2235728010
Short name T458
Test name
Test status
Simulation time 33530542 ps
CPU time 0.76 seconds
Started Jun 09 02:26:43 PM PDT 24
Finished Jun 09 02:26:44 PM PDT 24
Peak memory 205932 kb
Host smart-ca76b797-6b22-4bc1-899b-ce2985bd28ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235728010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2235728010
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3517991521
Short name T467
Test name
Test status
Simulation time 132384002 ps
CPU time 2.82 seconds
Started Jun 09 02:26:27 PM PDT 24
Finished Jun 09 02:26:30 PM PDT 24
Peak memory 222460 kb
Host smart-4fd90718-a0f2-4719-8a81-eaa0b5e0717a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517991521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3517991521
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1564205992
Short name T909
Test name
Test status
Simulation time 122603328 ps
CPU time 1.94 seconds
Started Jun 09 02:26:24 PM PDT 24
Finished Jun 09 02:26:26 PM PDT 24
Peak memory 207596 kb
Host smart-78dab63c-7e68-4475-91af-8d30123560dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564205992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1564205992
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1404794310
Short name T94
Test name
Test status
Simulation time 96329453 ps
CPU time 2.15 seconds
Started Jun 09 02:26:33 PM PDT 24
Finished Jun 09 02:26:35 PM PDT 24
Peak memory 214920 kb
Host smart-64c11a59-436c-4278-8178-cad1a0f1b756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404794310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1404794310
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.150679411
Short name T4
Test name
Test status
Simulation time 69180674 ps
CPU time 2.81 seconds
Started Jun 09 02:26:28 PM PDT 24
Finished Jun 09 02:26:31 PM PDT 24
Peak memory 214928 kb
Host smart-48a2fe11-a4ae-4114-b124-4ca2f34968e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150679411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.150679411
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.878212075
Short name T402
Test name
Test status
Simulation time 721776317 ps
CPU time 6.72 seconds
Started Jun 09 02:26:27 PM PDT 24
Finished Jun 09 02:26:34 PM PDT 24
Peak memory 207672 kb
Host smart-5304fc32-ab5d-4309-b7d4-b12992a74723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878212075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.878212075
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2036192046
Short name T41
Test name
Test status
Simulation time 1153327116 ps
CPU time 9.61 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:26:44 PM PDT 24
Peak memory 238300 kb
Host smart-16be572f-d4eb-451f-8422-1bb41dbabb75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036192046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2036192046
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3814494204
Short name T484
Test name
Test status
Simulation time 199423004 ps
CPU time 2.67 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:26:37 PM PDT 24
Peak memory 206948 kb
Host smart-03d1d969-3983-4a3c-a614-12307c5f3bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814494204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3814494204
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3130544951
Short name T748
Test name
Test status
Simulation time 63319009 ps
CPU time 3.19 seconds
Started Jun 09 02:26:25 PM PDT 24
Finished Jun 09 02:26:29 PM PDT 24
Peak memory 206960 kb
Host smart-6af9230f-0965-4156-b398-4ed8d40a9113
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130544951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3130544951
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1931257035
Short name T780
Test name
Test status
Simulation time 259486866 ps
CPU time 5.64 seconds
Started Jun 09 02:26:26 PM PDT 24
Finished Jun 09 02:26:32 PM PDT 24
Peak memory 208120 kb
Host smart-40a34ca4-45cb-44c3-b0de-108340b36cf8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931257035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1931257035
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2796664421
Short name T338
Test name
Test status
Simulation time 123019223 ps
CPU time 4.85 seconds
Started Jun 09 02:26:25 PM PDT 24
Finished Jun 09 02:26:31 PM PDT 24
Peak memory 210252 kb
Host smart-400c0ba9-c515-4f09-a0a4-55d339be17cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796664421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2796664421
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3042160984
Short name T473
Test name
Test status
Simulation time 3369054801 ps
CPU time 26.41 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:27:00 PM PDT 24
Peak memory 208660 kb
Host smart-3ec5405b-f6e6-4e62-9060-2e49b4266cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042160984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3042160984
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2575847506
Short name T809
Test name
Test status
Simulation time 1931098733 ps
CPU time 26.26 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:27:01 PM PDT 24
Peak memory 222584 kb
Host smart-4d6b56ab-6fff-4578-9c3d-753179d4e928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575847506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2575847506
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3043701663
Short name T226
Test name
Test status
Simulation time 305529744 ps
CPU time 7.28 seconds
Started Jun 09 02:26:30 PM PDT 24
Finished Jun 09 02:26:37 PM PDT 24
Peak memory 209692 kb
Host smart-ce3854ce-ce52-4c61-99e6-21c44440dcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043701663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3043701663
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.4127843582
Short name T634
Test name
Test status
Simulation time 90639718 ps
CPU time 3.37 seconds
Started Jun 09 02:26:29 PM PDT 24
Finished Jun 09 02:26:33 PM PDT 24
Peak memory 210164 kb
Host smart-41510e39-a91f-4817-bcc8-13ba8cec5e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127843582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4127843582
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.532478123
Short name T859
Test name
Test status
Simulation time 86062772 ps
CPU time 1.97 seconds
Started Jun 09 02:26:26 PM PDT 24
Finished Jun 09 02:26:28 PM PDT 24
Peak memory 214340 kb
Host smart-c28ccb9c-86b3-4958-ac17-ad33419e3f82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532478123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.532478123
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1951979377
Short name T308
Test name
Test status
Simulation time 1683850600 ps
CPU time 16.37 seconds
Started Jun 09 02:26:23 PM PDT 24
Finished Jun 09 02:26:40 PM PDT 24
Peak memory 214272 kb
Host smart-22a29b4a-4a00-4b7f-8def-1fa3c7653e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951979377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1951979377
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2233882427
Short name T576
Test name
Test status
Simulation time 40048481 ps
CPU time 2.36 seconds
Started Jun 09 02:26:24 PM PDT 24
Finished Jun 09 02:26:27 PM PDT 24
Peak memory 216752 kb
Host smart-5a40b674-50fb-406a-a6e5-89d041071c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233882427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2233882427
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3229048575
Short name T66
Test name
Test status
Simulation time 279068636 ps
CPU time 4.95 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:42 PM PDT 24
Peak memory 209184 kb
Host smart-208d1a01-32ba-4021-b82d-7987a0a3a759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229048575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3229048575
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2667343178
Short name T605
Test name
Test status
Simulation time 2709998387 ps
CPU time 5.21 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:43 PM PDT 24
Peak memory 207964 kb
Host smart-3fcc2643-5997-410e-a1c6-9f95b4be845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667343178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2667343178
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2163465715
Short name T9
Test name
Test status
Simulation time 601611542 ps
CPU time 9.78 seconds
Started Jun 09 02:26:32 PM PDT 24
Finished Jun 09 02:26:43 PM PDT 24
Peak memory 230732 kb
Host smart-ac578c17-9449-4938-8bee-989a16f7446c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163465715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2163465715
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.139894363
Short name T716
Test name
Test status
Simulation time 73782396 ps
CPU time 3.29 seconds
Started Jun 09 02:26:27 PM PDT 24
Finished Jun 09 02:26:31 PM PDT 24
Peak memory 208956 kb
Host smart-c17b8fdb-afa1-4196-9b83-a6c5883c5362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139894363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.139894363
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.813477926
Short name T709
Test name
Test status
Simulation time 125810769 ps
CPU time 2.5 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:26:37 PM PDT 24
Peak memory 208704 kb
Host smart-60e34315-5405-4c50-a92f-dc2519e9b230
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813477926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.813477926
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2950825104
Short name T726
Test name
Test status
Simulation time 6693707158 ps
CPU time 65.75 seconds
Started Jun 09 02:26:27 PM PDT 24
Finished Jun 09 02:27:33 PM PDT 24
Peak memory 209068 kb
Host smart-7d80f9ee-520c-4afc-8687-0a85c0a7a225
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950825104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2950825104
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.723881365
Short name T457
Test name
Test status
Simulation time 54773169 ps
CPU time 3.07 seconds
Started Jun 09 02:26:24 PM PDT 24
Finished Jun 09 02:26:27 PM PDT 24
Peak memory 207900 kb
Host smart-814b50ea-fd3a-40de-b0cd-a4311cfb3b35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723881365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.723881365
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.382327734
Short name T557
Test name
Test status
Simulation time 582180577 ps
CPU time 2.11 seconds
Started Jun 09 02:26:25 PM PDT 24
Finished Jun 09 02:26:27 PM PDT 24
Peak memory 208796 kb
Host smart-8b9e60b7-3fc8-475d-a779-68365a50808f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382327734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.382327734
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2956983093
Short name T398
Test name
Test status
Simulation time 62907729 ps
CPU time 1.69 seconds
Started Jun 09 02:26:29 PM PDT 24
Finished Jun 09 02:26:31 PM PDT 24
Peak memory 206376 kb
Host smart-9c25ffc6-203c-4378-9415-1218b72eb1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956983093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2956983093
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3939220783
Short name T704
Test name
Test status
Simulation time 5465531935 ps
CPU time 18.21 seconds
Started Jun 09 02:26:24 PM PDT 24
Finished Jun 09 02:26:42 PM PDT 24
Peak memory 215300 kb
Host smart-8ad8ff91-7e18-4149-9530-46a11eb0bd91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939220783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3939220783
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2961340583
Short name T854
Test name
Test status
Simulation time 235616877 ps
CPU time 3.64 seconds
Started Jun 09 02:26:40 PM PDT 24
Finished Jun 09 02:26:44 PM PDT 24
Peak memory 210552 kb
Host smart-9cf7c9c4-c41c-4dfc-badb-c2f84c5c3e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961340583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2961340583
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.742190833
Short name T390
Test name
Test status
Simulation time 35513684 ps
CPU time 1.72 seconds
Started Jun 09 02:26:27 PM PDT 24
Finished Jun 09 02:26:29 PM PDT 24
Peak memory 209864 kb
Host smart-4a535107-0c5c-41d7-9579-4560938e79c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742190833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.742190833
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2471304469
Short name T785
Test name
Test status
Simulation time 42153483 ps
CPU time 0.88 seconds
Started Jun 09 02:27:05 PM PDT 24
Finished Jun 09 02:27:06 PM PDT 24
Peak memory 205928 kb
Host smart-9e8fa1c4-2da4-494d-b28b-dbdd2460ae23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471304469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2471304469
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3352656232
Short name T420
Test name
Test status
Simulation time 119810066 ps
CPU time 6.21 seconds
Started Jun 09 02:27:08 PM PDT 24
Finished Jun 09 02:27:14 PM PDT 24
Peak memory 214320 kb
Host smart-5983bf70-877e-4273-824e-a78adbb8d0f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3352656232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3352656232
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1042331559
Short name T760
Test name
Test status
Simulation time 89759631 ps
CPU time 2.77 seconds
Started Jun 09 02:27:05 PM PDT 24
Finished Jun 09 02:27:08 PM PDT 24
Peak memory 210184 kb
Host smart-530e9fb8-8a1a-41f7-b7ec-d67ab30eb17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042331559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1042331559
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3481648264
Short name T234
Test name
Test status
Simulation time 93969429 ps
CPU time 2.17 seconds
Started Jun 09 02:27:03 PM PDT 24
Finished Jun 09 02:27:06 PM PDT 24
Peak memory 214344 kb
Host smart-79b23c3e-e1cc-4500-9704-94e7ca29da63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481648264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3481648264
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3772762528
Short name T621
Test name
Test status
Simulation time 67153397 ps
CPU time 3.35 seconds
Started Jun 09 02:27:04 PM PDT 24
Finished Jun 09 02:27:08 PM PDT 24
Peak memory 222556 kb
Host smart-2ff76226-c8bc-4058-b5a2-fb13005deae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772762528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3772762528
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.205284293
Short name T366
Test name
Test status
Simulation time 45318720 ps
CPU time 3.18 seconds
Started Jun 09 02:27:03 PM PDT 24
Finished Jun 09 02:27:06 PM PDT 24
Peak memory 218252 kb
Host smart-3ab04824-447b-4e8d-84ce-1389bd24b119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205284293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.205284293
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1797856017
Short name T722
Test name
Test status
Simulation time 351158422 ps
CPU time 5.83 seconds
Started Jun 09 02:27:07 PM PDT 24
Finished Jun 09 02:27:13 PM PDT 24
Peak memory 208052 kb
Host smart-abc177d0-36b5-476c-8b89-da1a2dc0d1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797856017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1797856017
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3679455090
Short name T794
Test name
Test status
Simulation time 183701697 ps
CPU time 1.83 seconds
Started Jun 09 02:27:04 PM PDT 24
Finished Jun 09 02:27:06 PM PDT 24
Peak memory 206812 kb
Host smart-b1f4fd0f-a9dc-41c2-a0f5-48b5f15639f0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679455090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3679455090
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.4137013602
Short name T42
Test name
Test status
Simulation time 542671585 ps
CPU time 3.22 seconds
Started Jun 09 02:26:53 PM PDT 24
Finished Jun 09 02:26:56 PM PDT 24
Peak memory 207024 kb
Host smart-ce29afd6-6dc4-4c6c-84a0-2184b90df084
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137013602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.4137013602
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1541079908
Short name T230
Test name
Test status
Simulation time 267074014 ps
CPU time 2.8 seconds
Started Jun 09 02:27:03 PM PDT 24
Finished Jun 09 02:27:07 PM PDT 24
Peak memory 209580 kb
Host smart-99ff7ca4-ccdd-4564-8847-4cb741e5aecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541079908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1541079908
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2574375332
Short name T146
Test name
Test status
Simulation time 389309596 ps
CPU time 3.12 seconds
Started Jun 09 02:27:06 PM PDT 24
Finished Jun 09 02:27:10 PM PDT 24
Peak memory 208168 kb
Host smart-415d2813-3214-43af-88b9-77a0d61034a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574375332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2574375332
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3444949693
Short name T752
Test name
Test status
Simulation time 414200009 ps
CPU time 12.65 seconds
Started Jun 09 02:27:07 PM PDT 24
Finished Jun 09 02:27:20 PM PDT 24
Peak memory 220052 kb
Host smart-75c49b21-49dc-4159-a058-9259f54a5293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444949693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3444949693
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2019758732
Short name T84
Test name
Test status
Simulation time 619212517 ps
CPU time 7.48 seconds
Started Jun 09 02:27:05 PM PDT 24
Finished Jun 09 02:27:13 PM PDT 24
Peak memory 218188 kb
Host smart-a16e4255-90c0-42a2-aee9-9969ef92c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019758732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2019758732
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3877290841
Short name T535
Test name
Test status
Simulation time 60448487 ps
CPU time 0.83 seconds
Started Jun 09 02:27:24 PM PDT 24
Finished Jun 09 02:27:25 PM PDT 24
Peak memory 205896 kb
Host smart-6d21cab4-e4e2-4a4b-a9d4-c43bee05e2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877290841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3877290841
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.431059530
Short name T376
Test name
Test status
Simulation time 78287022 ps
CPU time 4.66 seconds
Started Jun 09 02:27:04 PM PDT 24
Finished Jun 09 02:27:09 PM PDT 24
Peak memory 215636 kb
Host smart-7ea1e713-eeb8-4eed-b179-b7017b21bc24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431059530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.431059530
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2989192979
Short name T912
Test name
Test status
Simulation time 663806786 ps
CPU time 4.05 seconds
Started Jun 09 02:27:22 PM PDT 24
Finished Jun 09 02:27:27 PM PDT 24
Peak memory 209912 kb
Host smart-332a970e-07e0-4cf3-81b2-9a1c4e9835ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989192979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2989192979
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2151068043
Short name T337
Test name
Test status
Simulation time 159575600 ps
CPU time 2.02 seconds
Started Jun 09 02:27:24 PM PDT 24
Finished Jun 09 02:27:26 PM PDT 24
Peak memory 209904 kb
Host smart-c8b583d4-ee60-411a-9968-16482a4125fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151068043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2151068043
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2910323624
Short name T846
Test name
Test status
Simulation time 118389280 ps
CPU time 2.47 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:28 PM PDT 24
Peak memory 214308 kb
Host smart-589ced6d-1288-4641-b6d0-0d8bff8e4fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910323624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2910323624
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2711244681
Short name T655
Test name
Test status
Simulation time 78881998 ps
CPU time 1.95 seconds
Started Jun 09 02:27:16 PM PDT 24
Finished Jun 09 02:27:18 PM PDT 24
Peak memory 219824 kb
Host smart-0c2a6485-6430-444f-8d25-8c932f952716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711244681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2711244681
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3674437034
Short name T318
Test name
Test status
Simulation time 371918807 ps
CPU time 4.74 seconds
Started Jun 09 02:27:07 PM PDT 24
Finished Jun 09 02:27:12 PM PDT 24
Peak memory 214332 kb
Host smart-a87c367b-722d-4af9-97d9-9cd259bb4f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674437034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3674437034
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1735478058
Short name T718
Test name
Test status
Simulation time 148856088 ps
CPU time 2.29 seconds
Started Jun 09 02:27:06 PM PDT 24
Finished Jun 09 02:27:09 PM PDT 24
Peak memory 206848 kb
Host smart-45a72598-5c89-4f90-86cc-af6d2dbc9ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735478058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1735478058
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.652715012
Short name T478
Test name
Test status
Simulation time 919463123 ps
CPU time 9.55 seconds
Started Jun 09 02:27:03 PM PDT 24
Finished Jun 09 02:27:13 PM PDT 24
Peak memory 208860 kb
Host smart-e68b069c-bfb8-41a4-93bc-3a9fd11cba95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652715012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.652715012
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2871162916
Short name T238
Test name
Test status
Simulation time 163837989 ps
CPU time 3.4 seconds
Started Jun 09 02:27:02 PM PDT 24
Finished Jun 09 02:27:06 PM PDT 24
Peak memory 208624 kb
Host smart-7dd6f0c2-ff89-4f5c-94f0-7535420a6f77
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871162916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2871162916
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2574514786
Short name T727
Test name
Test status
Simulation time 396441454 ps
CPU time 3.32 seconds
Started Jun 09 02:27:01 PM PDT 24
Finished Jun 09 02:27:05 PM PDT 24
Peak memory 206924 kb
Host smart-bc074c81-07ad-4a67-9e6a-2fd55e720bf5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574514786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2574514786
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3845526615
Short name T261
Test name
Test status
Simulation time 2732080057 ps
CPU time 53.97 seconds
Started Jun 09 02:27:18 PM PDT 24
Finished Jun 09 02:28:12 PM PDT 24
Peak memory 220436 kb
Host smart-164fa324-0cc0-480d-8a25-4931580f9267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845526615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3845526615
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2235584856
Short name T143
Test name
Test status
Simulation time 141624152 ps
CPU time 2.93 seconds
Started Jun 09 02:27:04 PM PDT 24
Finished Jun 09 02:27:07 PM PDT 24
Peak memory 206836 kb
Host smart-b5a3e0b7-0ff6-480c-b266-3e0851ec8dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235584856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2235584856
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3061314346
Short name T286
Test name
Test status
Simulation time 2303570959 ps
CPU time 17.53 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 215800 kb
Host smart-ad892df6-af7f-4904-a242-90e9792fed82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061314346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3061314346
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2413178694
Short name T822
Test name
Test status
Simulation time 546808919 ps
CPU time 6.94 seconds
Started Jun 09 02:27:19 PM PDT 24
Finished Jun 09 02:27:27 PM PDT 24
Peak memory 221136 kb
Host smart-f0c50f83-cf38-4e54-9225-0743439a9273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413178694 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2413178694
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.209676573
Short name T202
Test name
Test status
Simulation time 96898676 ps
CPU time 3.93 seconds
Started Jun 09 02:27:27 PM PDT 24
Finished Jun 09 02:27:32 PM PDT 24
Peak memory 208320 kb
Host smart-2266d0dc-7a33-4681-98cc-26a025e150bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209676573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.209676573
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3833378191
Short name T552
Test name
Test status
Simulation time 252813552 ps
CPU time 2.64 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:29 PM PDT 24
Peak memory 209540 kb
Host smart-4b77d3af-8656-4661-9dc2-1184f266e3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833378191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3833378191
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1907880778
Short name T874
Test name
Test status
Simulation time 16118172 ps
CPU time 0.96 seconds
Started Jun 09 02:27:16 PM PDT 24
Finished Jun 09 02:27:17 PM PDT 24
Peak memory 206120 kb
Host smart-0fc4d795-8ec2-4be4-9f0f-dc62e2000463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907880778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1907880778
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.710571856
Short name T240
Test name
Test status
Simulation time 93052228 ps
CPU time 5.63 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:31 PM PDT 24
Peak memory 215228 kb
Host smart-c1b04892-599b-4d09-88da-f3fc16325a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=710571856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.710571856
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1185259300
Short name T610
Test name
Test status
Simulation time 222294247 ps
CPU time 3.5 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:30 PM PDT 24
Peak memory 214260 kb
Host smart-d70eb989-763e-4d48-b823-c5d0c4f3b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185259300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1185259300
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3429683868
Short name T728
Test name
Test status
Simulation time 140859255 ps
CPU time 2.38 seconds
Started Jun 09 02:27:20 PM PDT 24
Finished Jun 09 02:27:23 PM PDT 24
Peak memory 214316 kb
Host smart-36afdfd9-10cf-4b43-92c9-158369945e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429683868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3429683868
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1475145576
Short name T104
Test name
Test status
Simulation time 791480026 ps
CPU time 2.67 seconds
Started Jun 09 02:27:20 PM PDT 24
Finished Jun 09 02:27:23 PM PDT 24
Peak memory 214244 kb
Host smart-0418e0fb-3592-4245-8400-f67e9fdce570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475145576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1475145576
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.857707462
Short name T712
Test name
Test status
Simulation time 377841729 ps
CPU time 4.9 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:27:36 PM PDT 24
Peak memory 210060 kb
Host smart-7f4c5102-07da-4534-9d27-8da30685c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857707462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.857707462
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.617818213
Short name T274
Test name
Test status
Simulation time 358110930 ps
CPU time 5.43 seconds
Started Jun 09 02:27:22 PM PDT 24
Finished Jun 09 02:27:28 PM PDT 24
Peak memory 218272 kb
Host smart-75289aab-5b70-402c-adfe-3920a3964c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617818213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.617818213
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1538428816
Short name T466
Test name
Test status
Simulation time 2256637557 ps
CPU time 16.64 seconds
Started Jun 09 02:27:22 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 208020 kb
Host smart-5e6becca-7463-484a-abfb-bc1d447f542d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538428816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1538428816
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1253282892
Short name T501
Test name
Test status
Simulation time 75023275 ps
CPU time 3.45 seconds
Started Jun 09 02:27:21 PM PDT 24
Finished Jun 09 02:27:25 PM PDT 24
Peak memory 207012 kb
Host smart-35ad4bea-ab17-4f31-b3aa-400d35dc5215
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253282892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1253282892
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1987244063
Short name T671
Test name
Test status
Simulation time 321719388 ps
CPU time 2.92 seconds
Started Jun 09 02:27:20 PM PDT 24
Finished Jun 09 02:27:23 PM PDT 24
Peak memory 208772 kb
Host smart-993d0c00-3194-4693-a219-0270948d0952
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987244063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1987244063
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.776003447
Short name T738
Test name
Test status
Simulation time 232978904 ps
CPU time 6.21 seconds
Started Jun 09 02:27:24 PM PDT 24
Finished Jun 09 02:27:30 PM PDT 24
Peak memory 208412 kb
Host smart-b35bc9a6-b3c7-40ab-9e7e-8b73c5b5c33b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776003447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.776003447
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3152339782
Short name T654
Test name
Test status
Simulation time 1031755196 ps
CPU time 14.54 seconds
Started Jun 09 02:27:21 PM PDT 24
Finished Jun 09 02:27:35 PM PDT 24
Peak memory 209260 kb
Host smart-340fb7f3-efdd-4cb1-8b60-ff9d975eb1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152339782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3152339782
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.231290305
Short name T795
Test name
Test status
Simulation time 29491379 ps
CPU time 2.09 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:27:34 PM PDT 24
Peak memory 208916 kb
Host smart-60fb56d7-9b4c-4d96-bfcc-b64106cf9ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231290305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.231290305
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1683321064
Short name T806
Test name
Test status
Simulation time 199376069 ps
CPU time 3.45 seconds
Started Jun 09 02:27:17 PM PDT 24
Finished Jun 09 02:27:20 PM PDT 24
Peak memory 207240 kb
Host smart-074daf53-69c7-4feb-aa91-ec43a541b55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683321064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1683321064
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.552163846
Short name T178
Test name
Test status
Simulation time 48222651 ps
CPU time 1.65 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:27 PM PDT 24
Peak memory 209700 kb
Host smart-6c2fde79-e4cc-4967-9dff-8b24673e1464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552163846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.552163846
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.416072556
Short name T444
Test name
Test status
Simulation time 11415070 ps
CPU time 0.75 seconds
Started Jun 09 02:27:21 PM PDT 24
Finished Jun 09 02:27:22 PM PDT 24
Peak memory 205968 kb
Host smart-73c42e41-297a-47c3-8a9f-6b85dffe9cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416072556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.416072556
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2151832813
Short name T418
Test name
Test status
Simulation time 216886139 ps
CPU time 4.28 seconds
Started Jun 09 02:27:26 PM PDT 24
Finished Jun 09 02:27:31 PM PDT 24
Peak memory 214316 kb
Host smart-c40eb340-fe24-4d40-85bb-38d5e1a40f8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151832813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2151832813
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2946624783
Short name T753
Test name
Test status
Simulation time 134578858 ps
CPU time 5.45 seconds
Started Jun 09 02:27:09 PM PDT 24
Finished Jun 09 02:27:15 PM PDT 24
Peak memory 210396 kb
Host smart-1e84e93d-dead-4deb-9e6f-5dd5f2ea7957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946624783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2946624783
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3866936191
Short name T887
Test name
Test status
Simulation time 255077573 ps
CPU time 6.16 seconds
Started Jun 09 02:27:26 PM PDT 24
Finished Jun 09 02:27:33 PM PDT 24
Peak memory 209668 kb
Host smart-3176d192-ce26-4853-b3be-eb23a476e7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866936191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3866936191
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.516051141
Short name T309
Test name
Test status
Simulation time 68179375 ps
CPU time 2.63 seconds
Started Jun 09 02:27:24 PM PDT 24
Finished Jun 09 02:27:27 PM PDT 24
Peak memory 214268 kb
Host smart-71281095-e9cd-4d61-8bd6-8054d5052a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516051141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.516051141
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4235394258
Short name T342
Test name
Test status
Simulation time 1775398103 ps
CPU time 4.2 seconds
Started Jun 09 02:27:20 PM PDT 24
Finished Jun 09 02:27:25 PM PDT 24
Peak memory 214312 kb
Host smart-a5310e2d-fbd9-461c-bae4-213a9d2a09be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235394258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4235394258
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.147054985
Short name T528
Test name
Test status
Simulation time 1379128204 ps
CPU time 10.21 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:36 PM PDT 24
Peak memory 209832 kb
Host smart-8f9cec9b-e570-485f-b4b6-c8650c8a9159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147054985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.147054985
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1253889379
Short name T730
Test name
Test status
Simulation time 132873601 ps
CPU time 3.94 seconds
Started Jun 09 02:27:16 PM PDT 24
Finished Jun 09 02:27:21 PM PDT 24
Peak memory 208392 kb
Host smart-f7f74bb5-4971-4d96-9688-af2016b62150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253889379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1253889379
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1367450173
Short name T604
Test name
Test status
Simulation time 213221256 ps
CPU time 3 seconds
Started Jun 09 02:27:32 PM PDT 24
Finished Jun 09 02:27:36 PM PDT 24
Peak memory 208484 kb
Host smart-d1b5939b-d979-4494-ae9d-7d6465d1d30d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367450173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1367450173
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1480074172
Short name T549
Test name
Test status
Simulation time 51120993 ps
CPU time 2.86 seconds
Started Jun 09 02:27:18 PM PDT 24
Finished Jun 09 02:27:21 PM PDT 24
Peak memory 207020 kb
Host smart-3b0c1988-3d88-4308-8923-a8de2481b095
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480074172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1480074172
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.4238916716
Short name T597
Test name
Test status
Simulation time 65165943 ps
CPU time 2.92 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:28 PM PDT 24
Peak memory 206988 kb
Host smart-0730f6af-aa26-4484-b1b8-2a5efba10635
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238916716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4238916716
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1806750420
Short name T799
Test name
Test status
Simulation time 136509077 ps
CPU time 2.63 seconds
Started Jun 09 02:27:27 PM PDT 24
Finished Jun 09 02:27:30 PM PDT 24
Peak memory 215856 kb
Host smart-6ac7cd93-ae72-43b7-8be1-8b0144fde485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806750420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1806750420
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3859225520
Short name T432
Test name
Test status
Simulation time 91016260 ps
CPU time 3.53 seconds
Started Jun 09 02:27:26 PM PDT 24
Finished Jun 09 02:27:30 PM PDT 24
Peak memory 207816 kb
Host smart-389021b5-b0c6-4262-a71c-488973b40ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859225520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3859225520
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3436036491
Short name T281
Test name
Test status
Simulation time 2342389351 ps
CPU time 53.73 seconds
Started Jun 09 02:27:22 PM PDT 24
Finished Jun 09 02:28:16 PM PDT 24
Peak memory 214980 kb
Host smart-46dd650b-02a2-4c35-b053-a2fd2d5e694f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436036491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3436036491
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.945565071
Short name T235
Test name
Test status
Simulation time 208178975 ps
CPU time 5.91 seconds
Started Jun 09 02:27:23 PM PDT 24
Finished Jun 09 02:27:29 PM PDT 24
Peak memory 210100 kb
Host smart-29e28a19-e40d-4709-94ef-00e822e29b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945565071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.945565071
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3130506419
Short name T149
Test name
Test status
Simulation time 142773907 ps
CPU time 3.1 seconds
Started Jun 09 02:27:19 PM PDT 24
Finished Jun 09 02:27:23 PM PDT 24
Peak memory 210416 kb
Host smart-0740d277-5178-46bf-a904-e465e5a43205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130506419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3130506419
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1378541544
Short name T82
Test name
Test status
Simulation time 9997760 ps
CPU time 0.74 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:26 PM PDT 24
Peak memory 205932 kb
Host smart-b5896e17-a63f-4f32-acda-12be912878be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378541544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1378541544
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2798473975
Short name T423
Test name
Test status
Simulation time 1070073243 ps
CPU time 7.57 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:33 PM PDT 24
Peak memory 215592 kb
Host smart-3c202531-5dd5-4da5-9ea1-f8337c2362d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798473975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2798473975
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4061228143
Short name T38
Test name
Test status
Simulation time 157026110 ps
CPU time 5.98 seconds
Started Jun 09 02:27:22 PM PDT 24
Finished Jun 09 02:27:29 PM PDT 24
Peak memory 209664 kb
Host smart-2a5fe8f2-362b-4acd-a1ec-bbf923b1d9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061228143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4061228143
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2689662900
Short name T283
Test name
Test status
Simulation time 364693467 ps
CPU time 3.22 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:27:34 PM PDT 24
Peak memory 209724 kb
Host smart-7f9128b4-5990-4ea2-9f5a-e2a82c7d5063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689662900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2689662900
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2214004995
Short name T893
Test name
Test status
Simulation time 31943513703 ps
CPU time 78.1 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:28:50 PM PDT 24
Peak memory 214440 kb
Host smart-5f382937-3a54-4984-915a-2a533e1ecc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214004995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2214004995
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1156711583
Short name T250
Test name
Test status
Simulation time 53100893 ps
CPU time 2.02 seconds
Started Jun 09 02:27:26 PM PDT 24
Finished Jun 09 02:27:28 PM PDT 24
Peak memory 214256 kb
Host smart-d489381b-6285-4af1-b16d-0dafa7496436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156711583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1156711583
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3664665459
Short name T776
Test name
Test status
Simulation time 94256820 ps
CPU time 4.02 seconds
Started Jun 09 02:27:24 PM PDT 24
Finished Jun 09 02:27:28 PM PDT 24
Peak memory 220172 kb
Host smart-d3c57ac2-a488-420d-9282-e90b1255f808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664665459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3664665459
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1470631135
Short name T702
Test name
Test status
Simulation time 36916757 ps
CPU time 2.65 seconds
Started Jun 09 02:27:17 PM PDT 24
Finished Jun 09 02:27:20 PM PDT 24
Peak memory 207400 kb
Host smart-9c5afe7d-c0ff-4475-8e2c-98d133a5cfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470631135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1470631135
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1897509600
Short name T3
Test name
Test status
Simulation time 715311653 ps
CPU time 25.69 seconds
Started Jun 09 02:27:20 PM PDT 24
Finished Jun 09 02:27:46 PM PDT 24
Peak memory 208024 kb
Host smart-1b8371be-d18c-4935-b1f0-dd6d02b8fc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897509600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1897509600
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3549760370
Short name T757
Test name
Test status
Simulation time 33726204 ps
CPU time 2.29 seconds
Started Jun 09 02:27:18 PM PDT 24
Finished Jun 09 02:27:21 PM PDT 24
Peak memory 206864 kb
Host smart-6b786e93-4523-4bed-9a53-fdc25943f4c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549760370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3549760370
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3487588396
Short name T606
Test name
Test status
Simulation time 184983281 ps
CPU time 5.6 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:31 PM PDT 24
Peak memory 208608 kb
Host smart-a0ea9185-2f22-47dd-8121-112404eac5f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487588396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3487588396
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2464663080
Short name T851
Test name
Test status
Simulation time 151416654 ps
CPU time 2.53 seconds
Started Jun 09 02:27:23 PM PDT 24
Finished Jun 09 02:27:26 PM PDT 24
Peak memory 206880 kb
Host smart-cefaa846-dbf3-4641-95c1-5134ae2138ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464663080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2464663080
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2263498031
Short name T818
Test name
Test status
Simulation time 155512750 ps
CPU time 2.33 seconds
Started Jun 09 02:27:26 PM PDT 24
Finished Jun 09 02:27:29 PM PDT 24
Peak memory 207892 kb
Host smart-5048cbec-4116-498c-9424-567e1908d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263498031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2263498031
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3421204275
Short name T431
Test name
Test status
Simulation time 1253665284 ps
CPU time 3.86 seconds
Started Jun 09 02:27:18 PM PDT 24
Finished Jun 09 02:27:22 PM PDT 24
Peak memory 208548 kb
Host smart-354da264-44b0-4525-b997-f6a81b015357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421204275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3421204275
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1409820183
Short name T564
Test name
Test status
Simulation time 190297748 ps
CPU time 4.41 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:30 PM PDT 24
Peak memory 214432 kb
Host smart-91806278-efc4-4ce3-a435-873f375376ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409820183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1409820183
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2926841004
Short name T706
Test name
Test status
Simulation time 65529492 ps
CPU time 2.28 seconds
Started Jun 09 02:27:32 PM PDT 24
Finished Jun 09 02:27:36 PM PDT 24
Peak memory 210168 kb
Host smart-857883b2-faf8-437d-9e74-2abca520e13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926841004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2926841004
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1006681998
Short name T100
Test name
Test status
Simulation time 13445982 ps
CPU time 0.81 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:27:32 PM PDT 24
Peak memory 205944 kb
Host smart-6dc010ea-2d52-41a9-a8ac-5b87c86550f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006681998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1006681998
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3169934422
Short name T394
Test name
Test status
Simulation time 79339965 ps
CPU time 3.21 seconds
Started Jun 09 02:27:20 PM PDT 24
Finished Jun 09 02:27:24 PM PDT 24
Peak memory 215116 kb
Host smart-f5c74e86-9bee-4b40-87de-ef1e9df1a299
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169934422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3169934422
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.4283711963
Short name T908
Test name
Test status
Simulation time 602390449 ps
CPU time 7.03 seconds
Started Jun 09 02:27:26 PM PDT 24
Finished Jun 09 02:27:33 PM PDT 24
Peak memory 208216 kb
Host smart-254bac64-89b3-45e6-8a53-a2b823f0b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283711963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.4283711963
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2817315846
Short name T816
Test name
Test status
Simulation time 162039412 ps
CPU time 4.06 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:29 PM PDT 24
Peak memory 214340 kb
Host smart-1e096aae-1eb9-47e1-816a-bfcec010830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817315846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2817315846
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.332115624
Short name T372
Test name
Test status
Simulation time 35380562 ps
CPU time 2.18 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:27:33 PM PDT 24
Peak memory 214280 kb
Host smart-d3a969d4-a407-4c99-b8ba-9d77e17a481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332115624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.332115624
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1505566522
Short name T498
Test name
Test status
Simulation time 457232068 ps
CPU time 3.48 seconds
Started Jun 09 02:27:21 PM PDT 24
Finished Jun 09 02:27:25 PM PDT 24
Peak memory 215612 kb
Host smart-bb9189eb-7a6a-4d21-a424-530787a1bb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505566522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1505566522
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1945583785
Short name T680
Test name
Test status
Simulation time 371624297 ps
CPU time 7.82 seconds
Started Jun 09 02:27:28 PM PDT 24
Finished Jun 09 02:27:36 PM PDT 24
Peak memory 209568 kb
Host smart-6c5e59fb-f57b-48cc-a6ee-12124c83508d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945583785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1945583785
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1376048262
Short name T438
Test name
Test status
Simulation time 189918081 ps
CPU time 2.48 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:29 PM PDT 24
Peak memory 206116 kb
Host smart-34086b49-aa79-48b7-b44b-44a781d9c334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376048262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1376048262
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3767029724
Short name T284
Test name
Test status
Simulation time 450825473 ps
CPU time 2.47 seconds
Started Jun 09 02:27:24 PM PDT 24
Finished Jun 09 02:27:26 PM PDT 24
Peak memory 206904 kb
Host smart-8ab49e49-94b7-42ad-87fc-c7e3b61d5e51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767029724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3767029724
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.508071865
Short name T521
Test name
Test status
Simulation time 28847769 ps
CPU time 2.08 seconds
Started Jun 09 02:27:25 PM PDT 24
Finished Jun 09 02:27:28 PM PDT 24
Peak memory 206672 kb
Host smart-fd147449-d000-4b28-9a64-eb6a0051001f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508071865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.508071865
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2238145615
Short name T890
Test name
Test status
Simulation time 34842337 ps
CPU time 2.33 seconds
Started Jun 09 02:27:20 PM PDT 24
Finished Jun 09 02:27:22 PM PDT 24
Peak memory 207012 kb
Host smart-f9aba994-225b-41d3-b4e7-c7c67ec94c30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238145615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2238145615
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3626738561
Short name T653
Test name
Test status
Simulation time 49812313 ps
CPU time 2.3 seconds
Started Jun 09 02:27:27 PM PDT 24
Finished Jun 09 02:27:29 PM PDT 24
Peak memory 208892 kb
Host smart-1eb73568-856c-482a-bcc3-d945b06945bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626738561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3626738561
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1159162967
Short name T426
Test name
Test status
Simulation time 92333293 ps
CPU time 2.73 seconds
Started Jun 09 02:27:23 PM PDT 24
Finished Jun 09 02:27:26 PM PDT 24
Peak memory 207020 kb
Host smart-9b180573-a220-43fb-a9d2-c241e63d4cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159162967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1159162967
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.592397483
Short name T112
Test name
Test status
Simulation time 2780727854 ps
CPU time 27.5 seconds
Started Jun 09 02:27:29 PM PDT 24
Finished Jun 09 02:27:57 PM PDT 24
Peak memory 216096 kb
Host smart-4764af70-75a3-414e-a736-99c04f9685dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592397483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.592397483
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.409701795
Short name T80
Test name
Test status
Simulation time 611600276 ps
CPU time 10.51 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:44 PM PDT 24
Peak memory 222488 kb
Host smart-9239f751-83f8-4906-a59a-6d99d79405be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409701795 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.409701795
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.173783581
Short name T499
Test name
Test status
Simulation time 47315908 ps
CPU time 2.89 seconds
Started Jun 09 02:27:21 PM PDT 24
Finished Jun 09 02:27:24 PM PDT 24
Peak memory 208768 kb
Host smart-c6cb7bb7-73e8-4e23-8979-a266320d8053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173783581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.173783581
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.4214380460
Short name T633
Test name
Test status
Simulation time 201318469 ps
CPU time 3.79 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 219348 kb
Host smart-7253b9a8-7297-48fb-a1e7-f89882caefc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214380460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.4214380460
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.109671183
Short name T469
Test name
Test status
Simulation time 22768539 ps
CPU time 0.84 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:37 PM PDT 24
Peak memory 205956 kb
Host smart-9f207acc-281b-461b-9b94-9750e9d82f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109671183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.109671183
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3148898656
Short name T28
Test name
Test status
Simulation time 148122485 ps
CPU time 4.66 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 209400 kb
Host smart-ab2f6d02-e4a7-4395-a599-d1a1234cdbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148898656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3148898656
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.497524661
Short name T523
Test name
Test status
Simulation time 383967407 ps
CPU time 2.66 seconds
Started Jun 09 02:27:27 PM PDT 24
Finished Jun 09 02:27:30 PM PDT 24
Peak memory 210388 kb
Host smart-fdfb469f-3e4b-4241-bfec-32c3b1267100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497524661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.497524661
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3214524019
Short name T93
Test name
Test status
Simulation time 347994937 ps
CPU time 6.13 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 218920 kb
Host smart-d5ecd8eb-b57e-4df0-aa26-506df2a6df36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214524019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3214524019
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3129905399
Short name T811
Test name
Test status
Simulation time 697328382 ps
CPU time 5.16 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 214280 kb
Host smart-e7379d5d-7d33-4dc6-9213-618d9b5144fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129905399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3129905399
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.39990118
Short name T436
Test name
Test status
Simulation time 83482619 ps
CPU time 3.17 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:37 PM PDT 24
Peak memory 216100 kb
Host smart-f7872929-2526-4508-b523-3bd58397643a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39990118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.39990118
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.249036822
Short name T766
Test name
Test status
Simulation time 514017700 ps
CPU time 3.32 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 207972 kb
Host smart-86f682c2-2d3d-419b-ae43-1a00a98a027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249036822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.249036822
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.900407547
Short name T835
Test name
Test status
Simulation time 24655959 ps
CPU time 1.91 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:27:34 PM PDT 24
Peak memory 206912 kb
Host smart-5b99b88a-c41b-484e-930c-0ed286b5bd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900407547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.900407547
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2329506722
Short name T278
Test name
Test status
Simulation time 115561025 ps
CPU time 2.97 seconds
Started Jun 09 02:27:29 PM PDT 24
Finished Jun 09 02:27:33 PM PDT 24
Peak memory 207024 kb
Host smart-090b3943-0dff-409b-898e-2ef025043836
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329506722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2329506722
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1358259809
Short name T508
Test name
Test status
Simulation time 2801988510 ps
CPU time 9.8 seconds
Started Jun 09 02:27:29 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 208916 kb
Host smart-aba2fcd3-575a-4d39-bb25-32848b91a95c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358259809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1358259809
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.888105542
Short name T488
Test name
Test status
Simulation time 273345181 ps
CPU time 4.63 seconds
Started Jun 09 02:27:32 PM PDT 24
Finished Jun 09 02:27:37 PM PDT 24
Peak memory 208036 kb
Host smart-03e3bd84-7de4-4136-9765-054ba2f44a81
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888105542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.888105542
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.405282851
Short name T531
Test name
Test status
Simulation time 272930763 ps
CPU time 3.3 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:27:35 PM PDT 24
Peak memory 209668 kb
Host smart-fb575399-3f66-4177-8ab9-b223c7b90b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405282851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.405282851
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.4104618727
Short name T882
Test name
Test status
Simulation time 1877081098 ps
CPU time 11.84 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:51 PM PDT 24
Peak memory 208220 kb
Host smart-04f254f2-add9-48f8-91fd-b8d8f151ed6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104618727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.4104618727
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1781795730
Short name T657
Test name
Test status
Simulation time 19094917 ps
CPU time 0.76 seconds
Started Jun 09 02:27:32 PM PDT 24
Finished Jun 09 02:27:34 PM PDT 24
Peak memory 205968 kb
Host smart-c07912e0-cba6-4a5c-b9d4-13061dc51fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781795730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1781795730
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2341595172
Short name T439
Test name
Test status
Simulation time 419394175 ps
CPU time 3.64 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 207276 kb
Host smart-8be0370d-794a-45c7-a453-edf53eeb87a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341595172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2341595172
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2561249299
Short name T545
Test name
Test status
Simulation time 86361901 ps
CPU time 2.6 seconds
Started Jun 09 02:27:32 PM PDT 24
Finished Jun 09 02:27:36 PM PDT 24
Peak memory 210312 kb
Host smart-774d56a7-072f-4c62-b4cb-dabaf6c7424d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561249299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2561249299
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2591889279
Short name T665
Test name
Test status
Simulation time 49389384 ps
CPU time 0.77 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 205972 kb
Host smart-484584ff-3af6-4c27-a3a4-63b06025cac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591889279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2591889279
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.441198640
Short name T494
Test name
Test status
Simulation time 654813664 ps
CPU time 5.48 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 220360 kb
Host smart-6677f9e7-6be5-48d2-8829-d8a75589af92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441198640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.441198640
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3304815017
Short name T447
Test name
Test status
Simulation time 57402822 ps
CPU time 1.71 seconds
Started Jun 09 02:27:32 PM PDT 24
Finished Jun 09 02:27:35 PM PDT 24
Peak memory 218092 kb
Host smart-d814eac5-3a06-4dd5-aaf6-396808f84c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304815017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3304815017
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1313401693
Short name T483
Test name
Test status
Simulation time 51424630 ps
CPU time 2.97 seconds
Started Jun 09 02:27:36 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 214328 kb
Host smart-60da184f-f050-49ec-b467-251689606f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313401693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1313401693
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1728232280
Short name T355
Test name
Test status
Simulation time 407995753 ps
CPU time 4.39 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 214304 kb
Host smart-7e63b00f-8110-4678-9e9f-cae4ebce70bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728232280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1728232280
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1951011916
Short name T212
Test name
Test status
Simulation time 1074525548 ps
CPU time 5.98 seconds
Started Jun 09 02:27:32 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 219780 kb
Host smart-49aa4a7c-a6c6-4eb9-84ad-62dcc63d61e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951011916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1951011916
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3673135061
Short name T351
Test name
Test status
Simulation time 56620343 ps
CPU time 2.92 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 208600 kb
Host smart-a5ae4327-dc58-46ec-9617-3e2b15dd06a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673135061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3673135061
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2385604095
Short name T290
Test name
Test status
Simulation time 166266304 ps
CPU time 3.5 seconds
Started Jun 09 02:27:32 PM PDT 24
Finished Jun 09 02:27:37 PM PDT 24
Peak memory 208620 kb
Host smart-574d3462-cbbf-435c-8420-f8efc3fa2d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385604095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2385604095
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2731938484
Short name T453
Test name
Test status
Simulation time 32225645 ps
CPU time 2.28 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:38 PM PDT 24
Peak memory 206852 kb
Host smart-02132f77-6b79-4854-9ca3-09ce6ebd4cef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731938484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2731938484
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2849906042
Short name T589
Test name
Test status
Simulation time 693766159 ps
CPU time 6.28 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 207864 kb
Host smart-f65e4337-624b-486e-bf46-e80a7a422c2d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849906042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2849906042
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2176871643
Short name T567
Test name
Test status
Simulation time 732355347 ps
CPU time 3.53 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 209608 kb
Host smart-a81048b9-4af8-433d-9c58-bf7333cfaf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176871643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2176871643
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.4071726680
Short name T108
Test name
Test status
Simulation time 267257050 ps
CPU time 2.81 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:38 PM PDT 24
Peak memory 208484 kb
Host smart-3b9ad49d-5263-49c1-b451-ce9055887523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071726680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.4071726680
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3490771869
Short name T243
Test name
Test status
Simulation time 99106930 ps
CPU time 4.79 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 207220 kb
Host smart-0808b9ef-88e5-4d47-b20c-ea2b3d8c7c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490771869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3490771869
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3843312108
Short name T389
Test name
Test status
Simulation time 38563307 ps
CPU time 2.27 seconds
Started Jun 09 02:27:39 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 210432 kb
Host smart-ab0d09a2-7c8e-41bc-a568-bf30562783e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843312108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3843312108
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2861234733
Short name T527
Test name
Test status
Simulation time 78614587 ps
CPU time 0.7 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:37 PM PDT 24
Peak memory 205964 kb
Host smart-81a10d49-1ccb-4858-b984-6006aff7b311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861234733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2861234733
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2878997205
Short name T419
Test name
Test status
Simulation time 412402528 ps
CPU time 4.09 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 214556 kb
Host smart-4f8ee34f-4829-40f3-9480-5920b5362b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878997205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2878997205
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.488306757
Short name T265
Test name
Test status
Simulation time 145973113 ps
CPU time 2.22 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:38 PM PDT 24
Peak memory 218568 kb
Host smart-fe0ae3f4-9dcc-4e47-9419-bd0cca8d4a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488306757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.488306757
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2641425446
Short name T733
Test name
Test status
Simulation time 238465826 ps
CPU time 3.24 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 214348 kb
Host smart-51f6b6e7-d6b4-46a6-ab9e-cfb9c503eed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641425446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2641425446
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.683398318
Short name T267
Test name
Test status
Simulation time 614509492 ps
CPU time 4.5 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 214300 kb
Host smart-9135dd7f-27b6-47de-a965-9c58b4898497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683398318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.683398318
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4168954804
Short name T884
Test name
Test status
Simulation time 29289094 ps
CPU time 1.96 seconds
Started Jun 09 02:27:41 PM PDT 24
Finished Jun 09 02:27:43 PM PDT 24
Peak memory 220296 kb
Host smart-7c4a395f-3683-44bc-a274-2f097c9a7300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168954804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4168954804
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1522028082
Short name T751
Test name
Test status
Simulation time 95176730 ps
CPU time 3.58 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 209548 kb
Host smart-0601c3c0-5a96-4cf3-95b7-bc816dc29dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522028082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1522028082
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3874072026
Short name T245
Test name
Test status
Simulation time 95853928 ps
CPU time 3.59 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 206728 kb
Host smart-6734722a-086b-41cb-86f6-6af7dc7b13c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874072026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3874072026
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.650107157
Short name T257
Test name
Test status
Simulation time 3428199972 ps
CPU time 53.05 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:28:28 PM PDT 24
Peak memory 208624 kb
Host smart-53219c74-f19b-4f48-9189-1eeb8e897c17
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650107157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.650107157
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3718670103
Short name T616
Test name
Test status
Simulation time 373600164 ps
CPU time 3.54 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:27:35 PM PDT 24
Peak memory 208520 kb
Host smart-9873dbe0-921e-4d5e-b7c9-a1b5546f614c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718670103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3718670103
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.866660741
Short name T624
Test name
Test status
Simulation time 136644562 ps
CPU time 2.91 seconds
Started Jun 09 02:27:29 PM PDT 24
Finished Jun 09 02:27:33 PM PDT 24
Peak memory 206912 kb
Host smart-679d4bdd-8e4e-4efd-bdef-e4c363cf0db2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866660741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.866660741
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.989015706
Short name T636
Test name
Test status
Simulation time 75220922 ps
CPU time 2.1 seconds
Started Jun 09 02:27:32 PM PDT 24
Finished Jun 09 02:27:36 PM PDT 24
Peak memory 208704 kb
Host smart-493ebf23-2548-4496-a881-89fb6d89e334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989015706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.989015706
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1380981240
Short name T487
Test name
Test status
Simulation time 140937547 ps
CPU time 3.15 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 208464 kb
Host smart-87c999e6-3ce8-48b5-9602-da8cdeb9543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380981240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1380981240
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1075293545
Short name T790
Test name
Test status
Simulation time 1093755892 ps
CPU time 21.04 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:57 PM PDT 24
Peak memory 222340 kb
Host smart-9dc3cdce-3e77-45d1-888e-54b018fa4ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075293545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1075293545
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.571192034
Short name T518
Test name
Test status
Simulation time 171320914 ps
CPU time 4.39 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 208164 kb
Host smart-dbcbf704-0209-4fe8-919f-ddb0d280aaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571192034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.571192034
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.465805118
Short name T383
Test name
Test status
Simulation time 183104286 ps
CPU time 2.41 seconds
Started Jun 09 02:27:24 PM PDT 24
Finished Jun 09 02:27:27 PM PDT 24
Peak memory 210192 kb
Host smart-d3076547-b3ce-4296-93b3-e306c4012ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465805118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.465805118
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2879667966
Short name T102
Test name
Test status
Simulation time 19196886 ps
CPU time 0.78 seconds
Started Jun 09 02:27:43 PM PDT 24
Finished Jun 09 02:27:44 PM PDT 24
Peak memory 205940 kb
Host smart-42a42392-7bc6-431a-ac43-9a60c3272a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879667966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2879667966
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1763224304
Short name T561
Test name
Test status
Simulation time 438798742 ps
CPU time 3.83 seconds
Started Jun 09 02:27:31 PM PDT 24
Finished Jun 09 02:27:36 PM PDT 24
Peak memory 222840 kb
Host smart-6a395214-2231-4e66-86e7-f9093a4afe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763224304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1763224304
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1451567734
Short name T625
Test name
Test status
Simulation time 40002019 ps
CPU time 1.54 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:37 PM PDT 24
Peak memory 222392 kb
Host smart-55942344-c0d4-4986-a7e1-5b2eaa8675c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451567734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1451567734
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2437625968
Short name T331
Test name
Test status
Simulation time 132895223 ps
CPU time 2.06 seconds
Started Jun 09 02:27:28 PM PDT 24
Finished Jun 09 02:27:30 PM PDT 24
Peak memory 214488 kb
Host smart-109c5902-ff3c-48bb-9ef0-2529c396d6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437625968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2437625968
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.4276415684
Short name T691
Test name
Test status
Simulation time 327628625 ps
CPU time 3.1 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 214288 kb
Host smart-9e85459b-98e0-4318-b74f-32afeddfd1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276415684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4276415684
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1822171038
Short name T53
Test name
Test status
Simulation time 37053899 ps
CPU time 2.51 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:43 PM PDT 24
Peak memory 219632 kb
Host smart-d9e8db0a-4ace-4897-9db6-2dc19feeacd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822171038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1822171038
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.31644308
Short name T14
Test name
Test status
Simulation time 47854942 ps
CPU time 2.67 seconds
Started Jun 09 02:27:15 PM PDT 24
Finished Jun 09 02:27:18 PM PDT 24
Peak memory 207548 kb
Host smart-46bbdada-fcdf-4ce9-a1d7-f0d1bb35ef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31644308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.31644308
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3826022969
Short name T241
Test name
Test status
Simulation time 611441924 ps
CPU time 4.81 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 206780 kb
Host smart-99a52697-7c86-4e1a-95c0-c7995b791434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826022969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3826022969
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3301428754
Short name T43
Test name
Test status
Simulation time 311789565 ps
CPU time 3.84 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:44 PM PDT 24
Peak memory 207304 kb
Host smart-3f21d99a-7ac9-47b1-a3a0-5c2116a1eaba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301428754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3301428754
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1256732657
Short name T672
Test name
Test status
Simulation time 270973283 ps
CPU time 5.64 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 208800 kb
Host smart-f9678df1-2850-4c2c-a55f-9798507212ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256732657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1256732657
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.526091404
Short name T814
Test name
Test status
Simulation time 360434538 ps
CPU time 11.81 seconds
Started Jun 09 02:27:35 PM PDT 24
Finished Jun 09 02:27:48 PM PDT 24
Peak memory 208056 kb
Host smart-789eee7c-2400-4c9d-bb9f-c4a4586845e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526091404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.526091404
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2886841452
Short name T607
Test name
Test status
Simulation time 94652638 ps
CPU time 2.31 seconds
Started Jun 09 02:27:36 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 209196 kb
Host smart-020f5e24-1462-4e88-9eaf-de503e8f15dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886841452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2886841452
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2009663551
Short name T538
Test name
Test status
Simulation time 301869233 ps
CPU time 2.69 seconds
Started Jun 09 02:27:41 PM PDT 24
Finished Jun 09 02:27:44 PM PDT 24
Peak memory 208560 kb
Host smart-ba9e7c98-0db3-49c2-a007-c0ce80b41a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009663551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2009663551
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2538092570
Short name T299
Test name
Test status
Simulation time 2678578016 ps
CPU time 32.49 seconds
Started Jun 09 02:27:39 PM PDT 24
Finished Jun 09 02:28:12 PM PDT 24
Peak memory 222356 kb
Host smart-ab31b7a3-f9f9-46d6-8649-0ec669d7c5c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538092570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2538092570
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.606350594
Short name T142
Test name
Test status
Simulation time 439063799 ps
CPU time 18.88 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:28:03 PM PDT 24
Peak memory 222564 kb
Host smart-40e3f439-b68d-45b9-8d2c-fe151afa1e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606350594 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.606350594
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2408885803
Short name T491
Test name
Test status
Simulation time 755810605 ps
CPU time 3.9 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 207496 kb
Host smart-6efef833-2e27-4f8c-a063-8e3711df44f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408885803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2408885803
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.928743445
Short name T63
Test name
Test status
Simulation time 105496959 ps
CPU time 2.42 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:38 PM PDT 24
Peak memory 210244 kb
Host smart-37ed9df6-a224-43d7-a01d-b5be43acc95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928743445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.928743445
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2386246254
Short name T480
Test name
Test status
Simulation time 21862718 ps
CPU time 0.72 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:38 PM PDT 24
Peak memory 205944 kb
Host smart-a260e761-e10c-41b4-aaf9-aee18d556a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386246254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2386246254
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.803434386
Short name T31
Test name
Test status
Simulation time 244505678 ps
CPU time 6.06 seconds
Started Jun 09 02:26:33 PM PDT 24
Finished Jun 09 02:26:40 PM PDT 24
Peak memory 210228 kb
Host smart-3988c55f-1d91-4bba-9af0-5dbe2dc06163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803434386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.803434386
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1906240941
Short name T48
Test name
Test status
Simulation time 132673817 ps
CPU time 4.9 seconds
Started Jun 09 02:26:27 PM PDT 24
Finished Jun 09 02:26:33 PM PDT 24
Peak memory 208564 kb
Host smart-0fc91915-5039-40bd-9a23-e4cf24064de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906240941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1906240941
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1870570638
Short name T373
Test name
Test status
Simulation time 614168277 ps
CPU time 6.17 seconds
Started Jun 09 02:26:31 PM PDT 24
Finished Jun 09 02:26:38 PM PDT 24
Peak memory 222472 kb
Host smart-086a0327-87ce-4833-9141-7b732bdf3c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870570638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1870570638
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.4153475182
Short name T613
Test name
Test status
Simulation time 103975039 ps
CPU time 2.88 seconds
Started Jun 09 02:26:28 PM PDT 24
Finished Jun 09 02:26:31 PM PDT 24
Peak memory 209212 kb
Host smart-a39065fe-e1a4-4e86-b286-dbfffc658488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153475182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.4153475182
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3349406262
Short name T486
Test name
Test status
Simulation time 3545488290 ps
CPU time 28.33 seconds
Started Jun 09 02:26:31 PM PDT 24
Finished Jun 09 02:27:00 PM PDT 24
Peak memory 208908 kb
Host smart-833de2a5-da3b-42b2-b3f9-027d3bc522f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349406262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3349406262
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.958133902
Short name T105
Test name
Test status
Simulation time 1004327038 ps
CPU time 9.2 seconds
Started Jun 09 02:26:30 PM PDT 24
Finished Jun 09 02:26:44 PM PDT 24
Peak memory 237676 kb
Host smart-f1be709d-1765-4493-ba98-8b7f770ddd4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958133902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.958133902
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1280477779
Short name T544
Test name
Test status
Simulation time 147709474 ps
CPU time 2.19 seconds
Started Jun 09 02:26:32 PM PDT 24
Finished Jun 09 02:26:35 PM PDT 24
Peak memory 206860 kb
Host smart-6d699c8e-cd0b-4cc1-90d1-dcb796dfc08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280477779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1280477779
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3961574392
Short name T369
Test name
Test status
Simulation time 455650377 ps
CPU time 11.2 seconds
Started Jun 09 02:26:31 PM PDT 24
Finished Jun 09 02:26:42 PM PDT 24
Peak memory 208084 kb
Host smart-61b0d237-848d-40c8-91af-48cbc103bc29
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961574392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3961574392
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1061054973
Short name T547
Test name
Test status
Simulation time 220648104 ps
CPU time 6.08 seconds
Started Jun 09 02:26:30 PM PDT 24
Finished Jun 09 02:26:37 PM PDT 24
Peak memory 208740 kb
Host smart-522b479e-8b8b-4a1c-b001-733d93b30283
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061054973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1061054973
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.994144648
Short name T110
Test name
Test status
Simulation time 172791165 ps
CPU time 4.22 seconds
Started Jun 09 02:26:39 PM PDT 24
Finished Jun 09 02:26:44 PM PDT 24
Peak memory 208968 kb
Host smart-e1e802e3-3edd-4166-943a-04b200fc098d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994144648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.994144648
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.621598703
Short name T649
Test name
Test status
Simulation time 88728634 ps
CPU time 3.41 seconds
Started Jun 09 02:26:32 PM PDT 24
Finished Jun 09 02:26:36 PM PDT 24
Peak memory 209736 kb
Host smart-539388cc-cec8-42b7-87c5-d806b76e354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621598703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.621598703
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2654036472
Short name T622
Test name
Test status
Simulation time 431253004 ps
CPU time 3.57 seconds
Started Jun 09 02:26:27 PM PDT 24
Finished Jun 09 02:26:31 PM PDT 24
Peak memory 208492 kb
Host smart-375455c9-b187-4889-b62e-c5a1586cd297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654036472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2654036472
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2785388273
Short name T188
Test name
Test status
Simulation time 220396260 ps
CPU time 8.65 seconds
Started Jun 09 02:26:30 PM PDT 24
Finished Jun 09 02:26:39 PM PDT 24
Peak memory 217540 kb
Host smart-35558a99-6982-460b-af1a-17fb164173ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785388273 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2785388273
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.4094784800
Short name T871
Test name
Test status
Simulation time 502942698 ps
CPU time 5.44 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:42 PM PDT 24
Peak memory 208312 kb
Host smart-030d5fcc-41ac-46da-8998-cd1aaeecbc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094784800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.4094784800
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1809875970
Short name T391
Test name
Test status
Simulation time 175943813 ps
CPU time 5.08 seconds
Started Jun 09 02:26:29 PM PDT 24
Finished Jun 09 02:26:34 PM PDT 24
Peak memory 210496 kb
Host smart-fee926ec-6bcc-4b93-b11e-ff87cec53d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809875970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1809875970
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3110384581
Short name T500
Test name
Test status
Simulation time 43400353 ps
CPU time 0.74 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 205932 kb
Host smart-728655b3-ab75-491b-b6b7-d436e842aed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110384581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3110384581
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1904870395
Short name T273
Test name
Test status
Simulation time 49185546 ps
CPU time 3.56 seconds
Started Jun 09 02:27:41 PM PDT 24
Finished Jun 09 02:27:45 PM PDT 24
Peak memory 215316 kb
Host smart-a3de2be9-e04a-4c85-af8a-86e3a2a36d58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904870395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1904870395
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3112366373
Short name T891
Test name
Test status
Simulation time 1415920476 ps
CPU time 8.75 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:43 PM PDT 24
Peak memory 209724 kb
Host smart-e4154cd0-a6d4-4649-a53e-f6b8b2122427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112366373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3112366373
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2011131743
Short name T49
Test name
Test status
Simulation time 111978101 ps
CPU time 1.77 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:46 PM PDT 24
Peak memory 209788 kb
Host smart-b9fa6b9e-0ff1-425c-bbf8-dec69de0e6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011131743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2011131743
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3742328071
Short name T375
Test name
Test status
Simulation time 25968719 ps
CPU time 1.62 seconds
Started Jun 09 02:27:41 PM PDT 24
Finished Jun 09 02:27:43 PM PDT 24
Peak memory 214392 kb
Host smart-dd9bc75a-540b-4d60-b690-a51a493d671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742328071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3742328071
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1137120355
Short name T695
Test name
Test status
Simulation time 392943700 ps
CPU time 5.03 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 221024 kb
Host smart-52d2151c-3134-4e94-afb0-b17c1c564f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137120355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1137120355
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3994240064
Short name T862
Test name
Test status
Simulation time 973460711 ps
CPU time 5.15 seconds
Started Jun 09 02:27:28 PM PDT 24
Finished Jun 09 02:27:33 PM PDT 24
Peak memory 210408 kb
Host smart-defc70de-08a4-4b78-90e6-983de60b6e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994240064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3994240064
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3943047538
Short name T306
Test name
Test status
Simulation time 178284415 ps
CPU time 4.74 seconds
Started Jun 09 02:27:37 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 207468 kb
Host smart-c0a61fa4-14a6-4ab3-977e-c4fc42b9e7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943047538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3943047538
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2218826293
Short name T868
Test name
Test status
Simulation time 1316400526 ps
CPU time 9.29 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 207936 kb
Host smart-5f503726-5c24-4e44-87b8-ed19849dc95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218826293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2218826293
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2616263480
Short name T568
Test name
Test status
Simulation time 642711508 ps
CPU time 19.85 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:58 PM PDT 24
Peak memory 208144 kb
Host smart-7cf4d060-1206-481f-bab5-9fff24990f59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616263480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2616263480
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2370878787
Short name T886
Test name
Test status
Simulation time 78663385 ps
CPU time 2.5 seconds
Started Jun 09 02:27:12 PM PDT 24
Finished Jun 09 02:27:15 PM PDT 24
Peak memory 207036 kb
Host smart-dedea993-b58a-496b-a93c-798d50ea0f8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370878787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2370878787
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1658768529
Short name T724
Test name
Test status
Simulation time 70599546 ps
CPU time 3.22 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:48 PM PDT 24
Peak memory 206904 kb
Host smart-c850e2a4-f499-4291-8bda-55a0c3ef384c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658768529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1658768529
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3768297695
Short name T608
Test name
Test status
Simulation time 148513894 ps
CPU time 4.68 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:38 PM PDT 24
Peak memory 215768 kb
Host smart-597ae6f7-6e55-4dd3-868f-59c99df53768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768297695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3768297695
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3385358811
Short name T717
Test name
Test status
Simulation time 4391561495 ps
CPU time 22.84 seconds
Started Jun 09 02:27:43 PM PDT 24
Finished Jun 09 02:28:07 PM PDT 24
Peak memory 209120 kb
Host smart-f1f9212e-001c-471b-91fd-9862e43e202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385358811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3385358811
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1912313537
Short name T660
Test name
Test status
Simulation time 116438035 ps
CPU time 6.86 seconds
Started Jun 09 02:27:28 PM PDT 24
Finished Jun 09 02:27:35 PM PDT 24
Peak memory 215120 kb
Host smart-3fc1e3ee-d527-4191-8081-be37f289afb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912313537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1912313537
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1841862083
Short name T62
Test name
Test status
Simulation time 109694919 ps
CPU time 2.61 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 210212 kb
Host smart-af3847dc-71d7-48b1-b19e-3da8540d7b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841862083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1841862083
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1865395328
Short name T452
Test name
Test status
Simulation time 15322785 ps
CPU time 0.97 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 206104 kb
Host smart-313ea20a-99de-416a-b322-597468608687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865395328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1865395328
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.131456505
Short name T259
Test name
Test status
Simulation time 1024691773 ps
CPU time 56.77 seconds
Started Jun 09 02:27:37 PM PDT 24
Finished Jun 09 02:28:35 PM PDT 24
Peak memory 214580 kb
Host smart-1f0460b1-5497-4c90-931f-cea97ad17c64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131456505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.131456505
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3554670085
Short name T832
Test name
Test status
Simulation time 112954366 ps
CPU time 3.21 seconds
Started Jun 09 02:27:39 PM PDT 24
Finished Jun 09 02:27:43 PM PDT 24
Peak memory 214940 kb
Host smart-6adece79-a958-48b6-9a59-f6169647a2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554670085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3554670085
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1710356053
Short name T639
Test name
Test status
Simulation time 84038158 ps
CPU time 2.51 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:38 PM PDT 24
Peak memory 214324 kb
Host smart-9245c210-8c97-4571-b697-40b46d024ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710356053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1710356053
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3728872879
Short name T256
Test name
Test status
Simulation time 181575432 ps
CPU time 9.21 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 215472 kb
Host smart-adb3db87-b7f7-40f5-adeb-12ea643f72c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728872879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3728872879
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.852797077
Short name T888
Test name
Test status
Simulation time 70667964 ps
CPU time 3.29 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:37 PM PDT 24
Peak memory 209692 kb
Host smart-55a6fc13-71a7-4c03-ba99-af0dd8eb5f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852797077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.852797077
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3094885800
Short name T662
Test name
Test status
Simulation time 50346168 ps
CPU time 2.52 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:44 PM PDT 24
Peak memory 206788 kb
Host smart-4d6e9bd4-5852-4302-9ad5-e680f36e2bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094885800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3094885800
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2992257599
Short name T279
Test name
Test status
Simulation time 505956672 ps
CPU time 4.2 seconds
Started Jun 09 02:27:37 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 208920 kb
Host smart-ffbf8ead-f507-49c9-b32d-d92a34dd2fd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992257599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2992257599
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1380986912
Short name T340
Test name
Test status
Simulation time 9890690194 ps
CPU time 64.6 seconds
Started Jun 09 02:27:39 PM PDT 24
Finished Jun 09 02:28:44 PM PDT 24
Peak memory 209720 kb
Host smart-d30f51c4-c320-4156-aa35-99ac25b6694b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380986912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1380986912
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.449454846
Short name T571
Test name
Test status
Simulation time 227494801 ps
CPU time 3.13 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 208780 kb
Host smart-3f619bdd-e578-44c0-af82-f626e271a80b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449454846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.449454846
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.802312714
Short name T623
Test name
Test status
Simulation time 191381762 ps
CPU time 2.13 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:43 PM PDT 24
Peak memory 209444 kb
Host smart-363df0d0-c20b-4cef-bd31-2fee43f5f056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802312714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.802312714
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.234171824
Short name T448
Test name
Test status
Simulation time 76662313 ps
CPU time 1.8 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:36 PM PDT 24
Peak memory 206980 kb
Host smart-66b2576a-d92c-45ca-b01d-ec548ae3ebbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234171824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.234171824
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3572389814
Short name T860
Test name
Test status
Simulation time 249546295 ps
CPU time 8.8 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 222784 kb
Host smart-88fa5274-1cd9-4a6d-b5e5-b626cc6d9343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572389814 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3572389814
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2167048489
Short name T504
Test name
Test status
Simulation time 462673793 ps
CPU time 5.39 seconds
Started Jun 09 02:27:33 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 207168 kb
Host smart-543c7f86-c305-4bdc-8564-e62c11629bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167048489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2167048489
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2479900606
Short name T584
Test name
Test status
Simulation time 406463867 ps
CPU time 7.4 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 210892 kb
Host smart-8e3dfea0-cbeb-4057-a5e4-cfb856cd7ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479900606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2479900606
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.905426147
Short name T819
Test name
Test status
Simulation time 9383752 ps
CPU time 0.85 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:48 PM PDT 24
Peak memory 205956 kb
Host smart-c50e06cc-c2c8-4150-aa2d-c8a9434e0c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905426147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.905426147
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2673719237
Short name T424
Test name
Test status
Simulation time 52701984 ps
CPU time 3.83 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 214316 kb
Host smart-6ccb3007-a20b-4602-b9f5-edc3e6c01b89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673719237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2673719237
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.370449186
Short name T76
Test name
Test status
Simulation time 738821689 ps
CPU time 8.31 seconds
Started Jun 09 02:27:43 PM PDT 24
Finished Jun 09 02:27:52 PM PDT 24
Peak memory 214340 kb
Host smart-e1c060df-55bd-47c1-9470-fe7593b56fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370449186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.370449186
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3339434945
Short name T97
Test name
Test status
Simulation time 516904806 ps
CPU time 3.63 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:51 PM PDT 24
Peak memory 220768 kb
Host smart-f7308be5-7c99-4a46-a849-7ebcfb3adef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339434945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3339434945
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.365449617
Short name T333
Test name
Test status
Simulation time 782027456 ps
CPU time 2.15 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 214272 kb
Host smart-18a3ab57-9e31-4223-bd8f-0a1c01040843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365449617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.365449617
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.498867091
Short name T5
Test name
Test status
Simulation time 77932374 ps
CPU time 3.87 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 220360 kb
Host smart-f2343ae5-b2ee-4202-bac3-58c524e712b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498867091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.498867091
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.396000835
Short name T663
Test name
Test status
Simulation time 72951189 ps
CPU time 3.86 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:48 PM PDT 24
Peak memory 218228 kb
Host smart-1795ba26-d875-4d41-b42e-432eb45cdc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396000835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.396000835
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1040033215
Short name T282
Test name
Test status
Simulation time 5533357576 ps
CPU time 51.72 seconds
Started Jun 09 02:27:39 PM PDT 24
Finished Jun 09 02:28:31 PM PDT 24
Peak memory 208868 kb
Host smart-ffb398f6-2bfb-4ce8-8778-28d265c0debc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040033215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1040033215
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3056893425
Short name T627
Test name
Test status
Simulation time 254687276 ps
CPU time 5.34 seconds
Started Jun 09 02:27:43 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 207032 kb
Host smart-85d6ce8c-e96b-485f-856e-0cbd14288370
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056893425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3056893425
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.648263751
Short name T715
Test name
Test status
Simulation time 128209342 ps
CPU time 3.26 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 209160 kb
Host smart-4015dcb8-e782-489a-9db1-02788286769d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648263751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.648263751
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1016579549
Short name T301
Test name
Test status
Simulation time 339580753 ps
CPU time 4.49 seconds
Started Jun 09 02:27:42 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 207036 kb
Host smart-2c47e48e-e544-439f-ba06-e99ee92f4276
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016579549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1016579549
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.761918035
Short name T587
Test name
Test status
Simulation time 70686840 ps
CPU time 2.51 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 209684 kb
Host smart-91dd6799-09d4-470a-8d0a-e2a2dbcbfc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761918035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.761918035
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3586341236
Short name T899
Test name
Test status
Simulation time 2198956079 ps
CPU time 24.28 seconds
Started Jun 09 02:27:34 PM PDT 24
Finished Jun 09 02:27:59 PM PDT 24
Peak memory 208096 kb
Host smart-5b7cffcf-d5c6-41db-aee9-c553dce2dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586341236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3586341236
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.4078150701
Short name T459
Test name
Test status
Simulation time 1524831795 ps
CPU time 14.45 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:28:00 PM PDT 24
Peak memory 215320 kb
Host smart-74305d59-c71b-47e3-a7a4-3754d101c97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078150701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4078150701
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3796409482
Short name T689
Test name
Test status
Simulation time 153149557 ps
CPU time 4.53 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 207696 kb
Host smart-a6e97b08-c8b5-480f-a0f5-14657876ab55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796409482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3796409482
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4074378009
Short name T479
Test name
Test status
Simulation time 35193277 ps
CPU time 0.81 seconds
Started Jun 09 02:27:54 PM PDT 24
Finished Jun 09 02:27:55 PM PDT 24
Peak memory 205924 kb
Host smart-5aba796c-f8ef-4709-a07a-875cd12c7437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074378009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4074378009
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1840604705
Short name T410
Test name
Test status
Simulation time 556061532 ps
CPU time 6.39 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:52 PM PDT 24
Peak memory 214516 kb
Host smart-0dce67a0-3abc-462d-96f4-030fc2b5a60b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840604705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1840604705
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.369621940
Short name T107
Test name
Test status
Simulation time 35491698 ps
CPU time 2.26 seconds
Started Jun 09 02:27:43 PM PDT 24
Finished Jun 09 02:27:46 PM PDT 24
Peak memory 210068 kb
Host smart-03502025-e1ac-472c-9f38-a052b86e4047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369621940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.369621940
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.144460653
Short name T71
Test name
Test status
Simulation time 248823741 ps
CPU time 2.56 seconds
Started Jun 09 02:27:36 PM PDT 24
Finished Jun 09 02:27:39 PM PDT 24
Peak memory 218428 kb
Host smart-368fb057-8a8e-401b-8a26-ba35ef3b9eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144460653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.144460653
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1292969788
Short name T295
Test name
Test status
Simulation time 142037835 ps
CPU time 2.54 seconds
Started Jun 09 02:27:39 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 209748 kb
Host smart-7b2bc05e-3641-4325-ad89-ffd877fa83bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292969788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1292969788
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.4048271824
Short name T885
Test name
Test status
Simulation time 37981786 ps
CPU time 2.67 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 214260 kb
Host smart-438088f7-3dc1-4114-b513-8a0dd4f715cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048271824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4048271824
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1780431863
Short name T673
Test name
Test status
Simulation time 778413685 ps
CPU time 3.37 seconds
Started Jun 09 02:27:43 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 209640 kb
Host smart-ceaeab33-1fd6-4b14-8b84-eda40e95beef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780431863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1780431863
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2645073341
Short name T490
Test name
Test status
Simulation time 302852621 ps
CPU time 4.68 seconds
Started Jun 09 02:27:27 PM PDT 24
Finished Jun 09 02:27:32 PM PDT 24
Peak memory 207984 kb
Host smart-ac89d2b3-b1a1-4532-b4c5-665cb84b1c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645073341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2645073341
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2527031399
Short name T792
Test name
Test status
Simulation time 696596900 ps
CPU time 18.52 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:57 PM PDT 24
Peak memory 208960 kb
Host smart-3236a87f-4d92-4c2f-a738-29ce641c47e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527031399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2527031399
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2418248693
Short name T900
Test name
Test status
Simulation time 1773701044 ps
CPU time 19.06 seconds
Started Jun 09 02:27:41 PM PDT 24
Finished Jun 09 02:28:01 PM PDT 24
Peak memory 209096 kb
Host smart-98a242b5-0e03-4c0e-89ba-b15467ffb02c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418248693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2418248693
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3675906108
Short name T350
Test name
Test status
Simulation time 510871166 ps
CPU time 5.59 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:52 PM PDT 24
Peak memory 207988 kb
Host smart-a733aa9d-0c56-4047-be28-b4dd559d1ff2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675906108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3675906108
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.44168376
Short name T526
Test name
Test status
Simulation time 158137254 ps
CPU time 2.14 seconds
Started Jun 09 02:27:43 PM PDT 24
Finished Jun 09 02:27:46 PM PDT 24
Peak memory 207360 kb
Host smart-5bead59c-2249-4239-8fe5-2e6d0c81981a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44168376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.44168376
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2003344759
Short name T139
Test name
Test status
Simulation time 626732011 ps
CPU time 12.76 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:28:00 PM PDT 24
Peak memory 207984 kb
Host smart-e9eb2463-2e6d-44fc-a6dc-1e0c57bcc8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003344759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2003344759
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3938562619
Short name T325
Test name
Test status
Simulation time 69725738 ps
CPU time 4.24 seconds
Started Jun 09 02:27:37 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 214348 kb
Host smart-11fc89b8-b96b-412f-8d36-ae5c23829038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938562619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3938562619
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1829272407
Short name T262
Test name
Test status
Simulation time 68295969 ps
CPU time 3.32 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 207460 kb
Host smart-c228e30e-16b6-442e-9a45-51e71dd4b5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829272407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1829272407
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3148639217
Short name T167
Test name
Test status
Simulation time 194920717 ps
CPU time 4.62 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:52 PM PDT 24
Peak memory 210248 kb
Host smart-1479c3f0-0037-41f0-b315-7281c1ef2812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148639217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3148639217
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3989793528
Short name T831
Test name
Test status
Simulation time 14245042 ps
CPU time 0.74 seconds
Started Jun 09 02:27:41 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 205912 kb
Host smart-c652812f-82d6-42bf-9f47-e490821dc23c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989793528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3989793528
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1219550989
Short name T39
Test name
Test status
Simulation time 194762102 ps
CPU time 2.11 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 209360 kb
Host smart-92f52e2a-03a4-4766-90f5-ce926a7191a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219550989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1219550989
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2036102658
Short name T703
Test name
Test status
Simulation time 535267708 ps
CPU time 11.07 seconds
Started Jun 09 02:28:32 PM PDT 24
Finished Jun 09 02:28:44 PM PDT 24
Peak memory 209112 kb
Host smart-a49cceb2-e555-420d-88ea-f7cde111e5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036102658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2036102658
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1200079747
Short name T877
Test name
Test status
Simulation time 222744581 ps
CPU time 3.3 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:44 PM PDT 24
Peak memory 214304 kb
Host smart-112a6b55-687a-4898-83e8-fc5703f93f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200079747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1200079747
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2808154285
Short name T254
Test name
Test status
Simulation time 775761054 ps
CPU time 5.12 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:28:41 PM PDT 24
Peak memory 222464 kb
Host smart-2e502725-394e-4415-9ac4-c77218377368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808154285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2808154285
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2377953754
Short name T879
Test name
Test status
Simulation time 209826428 ps
CPU time 5.17 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 215136 kb
Host smart-93d8ec62-8b03-43f2-81ee-1bbbc8dc7366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377953754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2377953754
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3201011058
Short name T637
Test name
Test status
Simulation time 520305243 ps
CPU time 4.33 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:28:41 PM PDT 24
Peak memory 218492 kb
Host smart-c7c1f5b6-c0cc-42fb-ae18-4d8163e0fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201011058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3201011058
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1802532084
Short name T347
Test name
Test status
Simulation time 120856840 ps
CPU time 4.05 seconds
Started Jun 09 02:27:43 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 208004 kb
Host smart-9ae1b22b-3801-4f77-80f6-03bdc5262da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802532084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1802532084
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.4246734925
Short name T543
Test name
Test status
Simulation time 128360983 ps
CPU time 2.42 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:48 PM PDT 24
Peak memory 208816 kb
Host smart-51d3613d-bc5a-4fea-812c-52484377edac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246734925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4246734925
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2799659159
Short name T291
Test name
Test status
Simulation time 74428927 ps
CPU time 2.14 seconds
Started Jun 09 02:27:38 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 208752 kb
Host smart-de40310c-3fd7-440f-b814-3999d72814fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799659159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2799659159
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3644058261
Short name T207
Test name
Test status
Simulation time 76969679 ps
CPU time 2.84 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 206880 kb
Host smart-49a759f9-472d-4f02-ae53-cb709586fb39
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644058261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3644058261
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3480618633
Short name T530
Test name
Test status
Simulation time 179157899 ps
CPU time 2.51 seconds
Started Jun 09 02:27:42 PM PDT 24
Finished Jun 09 02:27:45 PM PDT 24
Peak memory 208760 kb
Host smart-1db8fd3c-7e74-451f-9ce7-8fe4426044af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480618633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3480618633
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.274978685
Short name T629
Test name
Test status
Simulation time 69439748 ps
CPU time 2.2 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:46 PM PDT 24
Peak memory 206764 kb
Host smart-3c497539-872d-4324-9a82-68dc310b5a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274978685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.274978685
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1166190619
Short name T191
Test name
Test status
Simulation time 738053694 ps
CPU time 7.43 seconds
Started Jun 09 02:27:41 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 220208 kb
Host smart-f4594fb0-b8dd-4974-9c72-4741365365e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166190619 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1166190619
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2723518433
Short name T150
Test name
Test status
Simulation time 1737000894 ps
CPU time 11.16 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:58 PM PDT 24
Peak memory 208860 kb
Host smart-df8ae85d-25be-4176-88df-ea4007b40835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723518433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2723518433
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1251224105
Short name T617
Test name
Test status
Simulation time 358199801 ps
CPU time 6.5 seconds
Started Jun 09 02:27:42 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 210896 kb
Host smart-16279831-1107-4344-9a61-91dd869338d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251224105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1251224105
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3416986670
Short name T101
Test name
Test status
Simulation time 13097777 ps
CPU time 0.85 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:46 PM PDT 24
Peak memory 205940 kb
Host smart-e6150a67-eaa3-4bc8-92e9-ea3024e7f7ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416986670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3416986670
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2309709636
Short name T421
Test name
Test status
Simulation time 1786711561 ps
CPU time 8.41 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:54 PM PDT 24
Peak memory 215036 kb
Host smart-12db14dd-e28c-4f37-8f63-11c2b6935d79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309709636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2309709636
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1597566836
Short name T872
Test name
Test status
Simulation time 23474149 ps
CPU time 1.81 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 208344 kb
Host smart-6d608604-ae09-43f4-bc67-d00bd68a68eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597566836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1597566836
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1072238545
Short name T609
Test name
Test status
Simulation time 263692518 ps
CPU time 4.14 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 222420 kb
Host smart-0e8304e0-fbf2-4e0a-8615-146dbba43e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072238545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1072238545
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_random.3575936314
Short name T302
Test name
Test status
Simulation time 155361967 ps
CPU time 2.84 seconds
Started Jun 09 02:28:32 PM PDT 24
Finished Jun 09 02:28:35 PM PDT 24
Peak memory 207380 kb
Host smart-4565799f-2f45-4c3c-b97b-a79c66f02cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575936314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3575936314
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3493274418
Short name T449
Test name
Test status
Simulation time 366200476 ps
CPU time 3.88 seconds
Started Jun 09 02:27:42 PM PDT 24
Finished Jun 09 02:27:46 PM PDT 24
Peak memory 208020 kb
Host smart-8ebcaf5b-0699-421e-8072-6065215e2238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493274418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3493274418
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2840078666
Short name T705
Test name
Test status
Simulation time 60397539 ps
CPU time 3.02 seconds
Started Jun 09 02:27:41 PM PDT 24
Finished Jun 09 02:27:45 PM PDT 24
Peak memory 206948 kb
Host smart-96e77a74-59e0-46da-9830-b9338fdcb3b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840078666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2840078666
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.4011067300
Short name T208
Test name
Test status
Simulation time 527961099 ps
CPU time 5.66 seconds
Started Jun 09 02:27:42 PM PDT 24
Finished Jun 09 02:27:48 PM PDT 24
Peak memory 208596 kb
Host smart-0976744b-7bc9-4bf3-aa58-4f5ead00453b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011067300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4011067300
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1612413192
Short name T348
Test name
Test status
Simulation time 48367342 ps
CPU time 3.2 seconds
Started Jun 09 02:27:37 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 214376 kb
Host smart-46921d05-f400-4c4f-a0c8-4b04f0de2688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612413192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1612413192
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2431150628
Short name T461
Test name
Test status
Simulation time 441408505 ps
CPU time 3.56 seconds
Started Jun 09 02:28:32 PM PDT 24
Finished Jun 09 02:28:37 PM PDT 24
Peak memory 208848 kb
Host smart-c2fd142d-c6c4-4691-ae60-00d2e4106a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431150628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2431150628
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.4080194550
Short name T403
Test name
Test status
Simulation time 1537986335 ps
CPU time 19.86 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:28:05 PM PDT 24
Peak memory 208464 kb
Host smart-5f90c1cc-ef56-42aa-a9df-451fbe352300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080194550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.4080194550
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.137154424
Short name T830
Test name
Test status
Simulation time 93124238 ps
CPU time 3.1 seconds
Started Jun 09 02:27:37 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 210436 kb
Host smart-ed6256e8-48e1-4ebf-8e39-9820e7666331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137154424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.137154424
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2579592636
Short name T781
Test name
Test status
Simulation time 75977109 ps
CPU time 0.81 seconds
Started Jun 09 02:27:41 PM PDT 24
Finished Jun 09 02:27:42 PM PDT 24
Peak memory 205944 kb
Host smart-9e10938d-8617-4e77-9f18-14b786d6e29c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579592636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2579592636
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1795186848
Short name T763
Test name
Test status
Simulation time 48985969 ps
CPU time 2.74 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 208004 kb
Host smart-4b21809e-946a-440b-b3fa-3e077151d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795186848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1795186848
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1217032260
Short name T895
Test name
Test status
Simulation time 61877116 ps
CPU time 2.03 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 209264 kb
Host smart-4eae39c3-76e0-4086-8a7f-66134fb5ce20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217032260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1217032260
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2867773486
Short name T861
Test name
Test status
Simulation time 30475299 ps
CPU time 2.37 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 209588 kb
Host smart-5be342e9-b876-4ee7-8cc0-c2842af33c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867773486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2867773486
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.4191165044
Short name T45
Test name
Test status
Simulation time 182472627 ps
CPU time 4.33 seconds
Started Jun 09 02:27:47 PM PDT 24
Finished Jun 09 02:27:52 PM PDT 24
Peak memory 220780 kb
Host smart-f949623d-5f66-4e25-94d3-f108cba61cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191165044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.4191165044
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4245485419
Short name T849
Test name
Test status
Simulation time 435974002 ps
CPU time 14.53 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:28:00 PM PDT 24
Peak memory 219304 kb
Host smart-f802d190-0531-42b4-9381-0931ac066e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245485419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4245485419
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1496262643
Short name T645
Test name
Test status
Simulation time 148141412 ps
CPU time 2.6 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 208652 kb
Host smart-c2e4c2d7-22e5-4c49-bda8-88922a454f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496262643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1496262643
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3765598247
Short name T596
Test name
Test status
Simulation time 107839988 ps
CPU time 4.49 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 208960 kb
Host smart-e50aff38-d116-4b7c-ac0d-976514ce4a1a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765598247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3765598247
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3792281473
Short name T736
Test name
Test status
Simulation time 59447420 ps
CPU time 3.14 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:55 PM PDT 24
Peak memory 208360 kb
Host smart-79f781ea-8950-4a05-8537-7260fb86ef7b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792281473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3792281473
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2047389276
Short name T796
Test name
Test status
Simulation time 102087445 ps
CPU time 4.55 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 209192 kb
Host smart-3356ad9a-9926-4b36-8eab-ccaf89b32222
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047389276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2047389276
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.492941789
Short name T345
Test name
Test status
Simulation time 311330359 ps
CPU time 4.12 seconds
Started Jun 09 02:27:48 PM PDT 24
Finished Jun 09 02:27:53 PM PDT 24
Peak memory 208876 kb
Host smart-6746c297-5cdd-4a2d-b500-6700a4b32387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492941789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.492941789
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3629161225
Short name T841
Test name
Test status
Simulation time 19984146 ps
CPU time 1.61 seconds
Started Jun 09 02:27:42 PM PDT 24
Finished Jun 09 02:27:44 PM PDT 24
Peak memory 206848 kb
Host smart-ceb8d6e6-1d00-4370-98e6-0897b6a31f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629161225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3629161225
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.802286138
Short name T81
Test name
Test status
Simulation time 25851840932 ps
CPU time 66.34 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:29:00 PM PDT 24
Peak memory 216612 kb
Host smart-7369e847-60af-460b-9593-8dda145bca41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802286138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.802286138
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3490121201
Short name T525
Test name
Test status
Simulation time 293876519 ps
CPU time 5.2 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:52 PM PDT 24
Peak memory 219744 kb
Host smart-c53a2721-cb99-4e7b-a398-4f1c191183c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490121201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3490121201
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2012792272
Short name T173
Test name
Test status
Simulation time 108514412 ps
CPU time 1.8 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:27:55 PM PDT 24
Peak memory 210040 kb
Host smart-e064a593-3361-456e-8451-f0b98585e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012792272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2012792272
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2886240591
Short name T428
Test name
Test status
Simulation time 20176160 ps
CPU time 0.73 seconds
Started Jun 09 02:27:39 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 205964 kb
Host smart-81377a09-af82-4d1c-bd63-0372fa6f9fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886240591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2886240591
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1034327052
Short name T33
Test name
Test status
Simulation time 585611594 ps
CPU time 10.03 seconds
Started Jun 09 02:27:50 PM PDT 24
Finished Jun 09 02:28:00 PM PDT 24
Peak memory 214560 kb
Host smart-672af592-4299-4e2f-8edc-cf200afdb60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034327052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1034327052
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3234590126
Short name T664
Test name
Test status
Simulation time 54578524 ps
CPU time 2.47 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 207520 kb
Host smart-673ebfae-022e-4835-8de6-759134c8e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234590126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3234590126
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4127825804
Short name T17
Test name
Test status
Simulation time 203494189 ps
CPU time 2.31 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 214324 kb
Host smart-3c3203c1-b33d-43e5-93a7-4175f0a5299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127825804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4127825804
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3567194647
Short name T46
Test name
Test status
Simulation time 26025947 ps
CPU time 1.99 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 222416 kb
Host smart-708669e4-a6d7-4f4e-bd99-b420ef39b02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567194647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3567194647
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.4136544319
Short name T364
Test name
Test status
Simulation time 338016201 ps
CPU time 4.74 seconds
Started Jun 09 02:27:50 PM PDT 24
Finished Jun 09 02:27:55 PM PDT 24
Peak memory 207488 kb
Host smart-c5c50f43-93b0-434b-b3e9-4ccf3561854d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136544319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.4136544319
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3545860537
Short name T701
Test name
Test status
Simulation time 1353562327 ps
CPU time 17.11 seconds
Started Jun 09 02:27:50 PM PDT 24
Finished Jun 09 02:28:07 PM PDT 24
Peak memory 207948 kb
Host smart-e61df0b3-daef-4acd-a857-16429d96dcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545860537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3545860537
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.4108049114
Short name T140
Test name
Test status
Simulation time 175351255 ps
CPU time 3.06 seconds
Started Jun 09 02:27:37 PM PDT 24
Finished Jun 09 02:27:40 PM PDT 24
Peak memory 206860 kb
Host smart-dcb68ac5-24b3-4196-97bd-abc6ea77f498
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108049114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.4108049114
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3736573226
Short name T370
Test name
Test status
Simulation time 209003118 ps
CPU time 2.98 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 206928 kb
Host smart-04bbad57-ba50-4fb9-abbe-c303d7fd516b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736573226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3736573226
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1025931167
Short name T817
Test name
Test status
Simulation time 238974703 ps
CPU time 2.99 seconds
Started Jun 09 02:27:50 PM PDT 24
Finished Jun 09 02:27:53 PM PDT 24
Peak memory 206900 kb
Host smart-0ee5432d-ca43-4c15-aeb1-7dfe393503eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025931167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1025931167
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.4141822848
Short name T572
Test name
Test status
Simulation time 437176114 ps
CPU time 9.82 seconds
Started Jun 09 02:27:39 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 208328 kb
Host smart-3846e7d6-77d1-4a1f-a36f-2ac73bc28555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141822848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.4141822848
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3267202414
Short name T550
Test name
Test status
Simulation time 435279750 ps
CPU time 4.44 seconds
Started Jun 09 02:27:48 PM PDT 24
Finished Jun 09 02:27:53 PM PDT 24
Peak memory 206848 kb
Host smart-aa60c8db-3e2b-4a3c-b78d-2592de382f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267202414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3267202414
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2736525887
Short name T812
Test name
Test status
Simulation time 1431883510 ps
CPU time 26.51 seconds
Started Jun 09 02:28:03 PM PDT 24
Finished Jun 09 02:28:30 PM PDT 24
Peak memory 216604 kb
Host smart-393c46b1-ee2e-4578-a5fc-24087ebbdf16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736525887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2736525887
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2153945663
Short name T631
Test name
Test status
Simulation time 1144563994 ps
CPU time 11.14 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:58 PM PDT 24
Peak memory 220192 kb
Host smart-7719755b-9f25-479d-9e12-854d174f959d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153945663 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2153945663
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.999051589
Short name T575
Test name
Test status
Simulation time 558299684 ps
CPU time 2.88 seconds
Started Jun 09 02:27:50 PM PDT 24
Finished Jun 09 02:27:53 PM PDT 24
Peak memory 208612 kb
Host smart-d7d3b7d9-e5a3-463c-ab34-154c40208fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999051589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.999051589
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2541564686
Short name T132
Test name
Test status
Simulation time 88940143 ps
CPU time 1.83 seconds
Started Jun 09 02:27:39 PM PDT 24
Finished Jun 09 02:27:41 PM PDT 24
Peak memory 210420 kb
Host smart-49179707-022f-4c46-a729-f9fd5e73e793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541564686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2541564686
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2474729932
Short name T536
Test name
Test status
Simulation time 19675286 ps
CPU time 0.82 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:27:55 PM PDT 24
Peak memory 205920 kb
Host smart-883ec8ef-d928-4d36-a59a-5d19d097e3c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474729932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2474729932
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.212013186
Short name T141
Test name
Test status
Simulation time 86322811 ps
CPU time 4.75 seconds
Started Jun 09 02:27:47 PM PDT 24
Finished Jun 09 02:27:52 PM PDT 24
Peak memory 214308 kb
Host smart-74d41705-2cf7-4079-b191-1f4cb9f089e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212013186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.212013186
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.67683831
Short name T218
Test name
Test status
Simulation time 648873476 ps
CPU time 5.31 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:46 PM PDT 24
Peak memory 209040 kb
Host smart-a14ab4b1-38af-4595-80aa-f6a6add38f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67683831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.67683831
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.732058619
Short name T514
Test name
Test status
Simulation time 179865572 ps
CPU time 2.36 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:27:56 PM PDT 24
Peak memory 209316 kb
Host smart-8ed11eff-d120-465b-a1de-47e96fc201aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732058619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.732058619
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.712736467
Short name T90
Test name
Test status
Simulation time 193364739 ps
CPU time 4.25 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:27:58 PM PDT 24
Peak memory 222384 kb
Host smart-71e731df-6fc5-49ce-8c25-cc5adcdc8b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712736467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.712736467
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3940713391
Short name T298
Test name
Test status
Simulation time 107511189 ps
CPU time 4.93 seconds
Started Jun 09 02:27:48 PM PDT 24
Finished Jun 09 02:27:53 PM PDT 24
Peak memory 222428 kb
Host smart-27448b42-b31c-4a98-8fc0-9cca690bc555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940713391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3940713391
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1060991931
Short name T506
Test name
Test status
Simulation time 182250895 ps
CPU time 4.54 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:27:58 PM PDT 24
Peak memory 220096 kb
Host smart-0f022c04-e644-4809-8b78-62273a9ac245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060991931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1060991931
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1691974810
Short name T643
Test name
Test status
Simulation time 1371442720 ps
CPU time 10.36 seconds
Started Jun 09 02:27:40 PM PDT 24
Finished Jun 09 02:27:51 PM PDT 24
Peak memory 209308 kb
Host smart-24adca89-fef0-49a4-8827-ea5f73dab9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691974810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1691974810
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3333112418
Short name T463
Test name
Test status
Simulation time 73882501 ps
CPU time 1.82 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 206808 kb
Host smart-d3499621-9220-4593-b0c8-70f92d896ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333112418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3333112418
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1059462246
Short name T793
Test name
Test status
Simulation time 88198623 ps
CPU time 2.62 seconds
Started Jun 09 02:27:48 PM PDT 24
Finished Jun 09 02:27:51 PM PDT 24
Peak memory 207044 kb
Host smart-b9e0ad69-435b-4a22-9fad-4ecde4d6280e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059462246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1059462246
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3582222253
Short name T847
Test name
Test status
Simulation time 251699758 ps
CPU time 3.11 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:27:57 PM PDT 24
Peak memory 208720 kb
Host smart-41384b2d-b328-4dc0-b177-a7026561c2fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582222253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3582222253
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1077155660
Short name T659
Test name
Test status
Simulation time 71147035 ps
CPU time 3.45 seconds
Started Jun 09 02:27:55 PM PDT 24
Finished Jun 09 02:28:04 PM PDT 24
Peak memory 208908 kb
Host smart-cf989851-566a-4b60-90fb-7a976d61ad4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077155660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1077155660
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3317143271
Short name T456
Test name
Test status
Simulation time 1299913191 ps
CPU time 4.12 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:51 PM PDT 24
Peak memory 209256 kb
Host smart-4a5f3ea1-9b26-4f06-92d3-12ad498b752e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317143271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3317143271
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.283973826
Short name T520
Test name
Test status
Simulation time 1531876877 ps
CPU time 2.99 seconds
Started Jun 09 02:27:48 PM PDT 24
Finished Jun 09 02:27:51 PM PDT 24
Peak memory 206916 kb
Host smart-36ab19fa-54ed-4d39-99ea-409bfb009342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283973826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.283973826
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1987485602
Short name T185
Test name
Test status
Simulation time 443565804 ps
CPU time 9.66 seconds
Started Jun 09 02:27:42 PM PDT 24
Finished Jun 09 02:27:52 PM PDT 24
Peak memory 215116 kb
Host smart-0e51a273-3a7b-4fca-9428-12b31e1159df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987485602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1987485602
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2158695992
Short name T129
Test name
Test status
Simulation time 841741103 ps
CPU time 14.89 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:28:01 PM PDT 24
Peak memory 222600 kb
Host smart-68eb2f22-e573-4784-a7c2-152a25eeb616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158695992 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2158695992
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.784516149
Short name T684
Test name
Test status
Simulation time 235866687 ps
CPU time 6.68 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:28:00 PM PDT 24
Peak memory 207796 kb
Host smart-35527749-792d-4774-b96a-2c93a79159c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784516149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.784516149
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1545866971
Short name T128
Test name
Test status
Simulation time 178880772 ps
CPU time 2.42 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 210444 kb
Host smart-b60fba15-2489-4f8f-b253-66cde45247be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545866971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1545866971
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2925848577
Short name T433
Test name
Test status
Simulation time 53193428 ps
CPU time 0.94 seconds
Started Jun 09 02:27:48 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 206108 kb
Host smart-33d57b66-f8e9-439a-9abd-636c59f17b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925848577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2925848577
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.254814467
Short name T826
Test name
Test status
Simulation time 368383275 ps
CPU time 2.74 seconds
Started Jun 09 02:27:43 PM PDT 24
Finished Jun 09 02:27:46 PM PDT 24
Peak memory 214440 kb
Host smart-f1325b97-093a-4947-ac13-2d700cbc66fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254814467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.254814467
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.422125366
Short name T511
Test name
Test status
Simulation time 346209979 ps
CPU time 2.95 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:48 PM PDT 24
Peak memory 206944 kb
Host smart-79857c31-abfc-4b17-a676-1d2a0f94137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422125366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.422125366
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.608759483
Short name T889
Test name
Test status
Simulation time 32287727 ps
CPU time 2.34 seconds
Started Jun 09 02:27:47 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 214356 kb
Host smart-48c2cce9-a7c3-4093-8e6f-a107658d2c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608759483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.608759483
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1421156841
Short name T843
Test name
Test status
Simulation time 35461055 ps
CPU time 2.99 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:27:56 PM PDT 24
Peak memory 220148 kb
Host smart-f94a62ef-b314-44a9-b024-617e52e98790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421156841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1421156841
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.526817488
Short name T647
Test name
Test status
Simulation time 154795589 ps
CPU time 2.44 seconds
Started Jun 09 02:27:48 PM PDT 24
Finished Jun 09 02:27:51 PM PDT 24
Peak memory 217988 kb
Host smart-542225f3-570b-4584-9fb3-2e114197e129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526817488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.526817488
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1965694044
Short name T630
Test name
Test status
Simulation time 282165512 ps
CPU time 4.68 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 207312 kb
Host smart-c8f88f53-5c1b-4e60-ad96-dda7af9ab796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965694044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1965694044
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3609577159
Short name T848
Test name
Test status
Simulation time 69382809 ps
CPU time 1.67 seconds
Started Jun 09 02:27:47 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 206832 kb
Host smart-dc932268-06ac-4bb3-bacf-fe4c74b7174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609577159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3609577159
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2389442212
Short name T566
Test name
Test status
Simulation time 323952312 ps
CPU time 12 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:59 PM PDT 24
Peak memory 207064 kb
Host smart-f77e8052-1918-412e-84fd-a6718be88edc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389442212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2389442212
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2715687343
Short name T824
Test name
Test status
Simulation time 13112438505 ps
CPU time 25.43 seconds
Started Jun 09 02:27:44 PM PDT 24
Finished Jun 09 02:28:10 PM PDT 24
Peak memory 208728 kb
Host smart-d344c34f-3df2-43d4-88e4-1ef48dcd970b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715687343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2715687343
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1077742848
Short name T758
Test name
Test status
Simulation time 455635234 ps
CPU time 4.05 seconds
Started Jun 09 02:27:47 PM PDT 24
Finished Jun 09 02:27:51 PM PDT 24
Peak memory 208852 kb
Host smart-190c3106-3af4-4c9c-a128-252e815482c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077742848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1077742848
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2019091070
Short name T749
Test name
Test status
Simulation time 1657011931 ps
CPU time 5.58 seconds
Started Jun 09 02:27:47 PM PDT 24
Finished Jun 09 02:27:53 PM PDT 24
Peak memory 208960 kb
Host smart-daead484-4969-4b73-9ccf-131c206cc1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019091070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2019091070
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1396930591
Short name T742
Test name
Test status
Simulation time 36722527 ps
CPU time 1.75 seconds
Started Jun 09 02:27:46 PM PDT 24
Finished Jun 09 02:27:49 PM PDT 24
Peak memory 207012 kb
Host smart-4e7a6567-73a6-4243-a261-361d903eb8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396930591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1396930591
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.748021718
Short name T805
Test name
Test status
Simulation time 3069559048 ps
CPU time 31.72 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:28:25 PM PDT 24
Peak memory 215320 kb
Host smart-afa32624-1b0f-4cc0-bbc9-33a6fe3699a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748021718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.748021718
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.900006905
Short name T570
Test name
Test status
Simulation time 177616550 ps
CPU time 4.2 seconds
Started Jun 09 02:27:50 PM PDT 24
Finished Jun 09 02:27:55 PM PDT 24
Peak memory 214268 kb
Host smart-06cb9e7d-a7d9-46d0-b02e-20556ca2378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900006905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.900006905
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3895186896
Short name T384
Test name
Test status
Simulation time 126196247 ps
CPU time 1.88 seconds
Started Jun 09 02:27:48 PM PDT 24
Finished Jun 09 02:27:50 PM PDT 24
Peak memory 214412 kb
Host smart-147c6362-897a-46b3-afb9-9c7380d49c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895186896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3895186896
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2402743086
Short name T676
Test name
Test status
Simulation time 41461655 ps
CPU time 0.85 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:38 PM PDT 24
Peak memory 205940 kb
Host smart-275f7103-9b9a-4bc1-abe5-1b000844753f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402743086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2402743086
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3723432591
Short name T228
Test name
Test status
Simulation time 62493083 ps
CPU time 2.89 seconds
Started Jun 09 02:26:32 PM PDT 24
Finished Jun 09 02:26:35 PM PDT 24
Peak memory 214320 kb
Host smart-59e460e2-fd94-4ece-be6a-ef501c81ffec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3723432591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3723432591
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3756086916
Short name T352
Test name
Test status
Simulation time 80432343 ps
CPU time 3.56 seconds
Started Jun 09 02:26:31 PM PDT 24
Finished Jun 09 02:26:34 PM PDT 24
Peak memory 214396 kb
Host smart-299de196-3aa3-412a-8245-b851baaf494f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756086916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3756086916
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.660663902
Short name T823
Test name
Test status
Simulation time 164397590 ps
CPU time 6.59 seconds
Started Jun 09 02:26:40 PM PDT 24
Finished Jun 09 02:26:47 PM PDT 24
Peak memory 206868 kb
Host smart-7af4946a-8127-494e-8fa3-3a6984738738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660663902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.660663902
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2271928558
Short name T737
Test name
Test status
Simulation time 860729008 ps
CPU time 3.15 seconds
Started Jun 09 02:26:33 PM PDT 24
Finished Jun 09 02:26:36 PM PDT 24
Peak memory 220140 kb
Host smart-c4f2b66f-4a6a-4bf6-aa1f-5cf4bd0fb937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271928558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2271928558
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2844333657
Short name T615
Test name
Test status
Simulation time 183842565 ps
CPU time 4.63 seconds
Started Jun 09 02:26:30 PM PDT 24
Finished Jun 09 02:26:35 PM PDT 24
Peak memory 208216 kb
Host smart-eeb48f24-8a7f-4be0-b54c-24b01764e758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844333657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2844333657
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1717800801
Short name T768
Test name
Test status
Simulation time 139799274 ps
CPU time 2.2 seconds
Started Jun 09 02:26:30 PM PDT 24
Finished Jun 09 02:26:32 PM PDT 24
Peak memory 206968 kb
Host smart-430d069e-9aa6-4b56-b186-10adec7e8f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717800801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1717800801
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3154650750
Short name T767
Test name
Test status
Simulation time 32812363 ps
CPU time 2.24 seconds
Started Jun 09 02:26:29 PM PDT 24
Finished Jun 09 02:26:31 PM PDT 24
Peak memory 206972 kb
Host smart-d399afa1-39f5-42e1-8856-d817618d0712
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154650750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3154650750
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.542094418
Short name T89
Test name
Test status
Simulation time 43378826 ps
CPU time 2.46 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:26:37 PM PDT 24
Peak memory 208720 kb
Host smart-bad0540b-907a-40c2-b627-7ff2fbe01079
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542094418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.542094418
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1988604128
Short name T828
Test name
Test status
Simulation time 160437286 ps
CPU time 2.26 seconds
Started Jun 09 02:26:29 PM PDT 24
Finished Jun 09 02:26:32 PM PDT 24
Peak memory 206880 kb
Host smart-913d53ed-5cb3-48f8-84d4-24795c034881
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988604128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1988604128
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2870153470
Short name T264
Test name
Test status
Simulation time 125627608 ps
CPU time 2.59 seconds
Started Jun 09 02:26:38 PM PDT 24
Finished Jun 09 02:26:41 PM PDT 24
Peak memory 214320 kb
Host smart-73c31ee4-fe6b-431f-85c3-4ff8b2b228b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870153470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2870153470
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2109731563
Short name T198
Test name
Test status
Simulation time 848019501 ps
CPU time 3.01 seconds
Started Jun 09 02:26:27 PM PDT 24
Finished Jun 09 02:26:31 PM PDT 24
Peak memory 208228 kb
Host smart-134a60ee-dba2-4f4a-93d2-253f2840ee34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109731563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2109731563
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1396217173
Short name T755
Test name
Test status
Simulation time 2045058694 ps
CPU time 48.27 seconds
Started Jun 09 02:26:33 PM PDT 24
Finished Jun 09 02:27:22 PM PDT 24
Peak memory 222484 kb
Host smart-3f372fa7-8e0b-44bb-b548-1e07021e1282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396217173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1396217173
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1193102181
Short name T199
Test name
Test status
Simulation time 70956430 ps
CPU time 4.52 seconds
Started Jun 09 02:26:32 PM PDT 24
Finished Jun 09 02:26:37 PM PDT 24
Peak memory 220224 kb
Host smart-746d158f-7013-4501-8a3b-441beb91d852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193102181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1193102181
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3030740708
Short name T393
Test name
Test status
Simulation time 249074491 ps
CPU time 2.65 seconds
Started Jun 09 02:26:40 PM PDT 24
Finished Jun 09 02:26:43 PM PDT 24
Peak memory 210164 kb
Host smart-c72151f8-fd08-4f96-8974-8d8fbcebcff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030740708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3030740708
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2397321814
Short name T764
Test name
Test status
Simulation time 19020010 ps
CPU time 0.84 seconds
Started Jun 09 02:28:04 PM PDT 24
Finished Jun 09 02:28:05 PM PDT 24
Peak memory 205920 kb
Host smart-ed0294d0-0660-437a-86a4-56f17d1aa191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397321814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2397321814
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2307883315
Short name T406
Test name
Test status
Simulation time 113459387 ps
CPU time 5.6 seconds
Started Jun 09 02:28:02 PM PDT 24
Finished Jun 09 02:28:08 PM PDT 24
Peak memory 214320 kb
Host smart-6e1cf954-fa42-4364-811d-901324ff43ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2307883315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2307883315
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3342165159
Short name T646
Test name
Test status
Simulation time 670940967 ps
CPU time 3.9 seconds
Started Jun 09 02:28:01 PM PDT 24
Finished Jun 09 02:28:05 PM PDT 24
Peak memory 221212 kb
Host smart-2ae9abbb-fc6c-459c-a0a2-bc375c1a2920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342165159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3342165159
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1615070467
Short name T648
Test name
Test status
Simulation time 1265002511 ps
CPU time 10.76 seconds
Started Jun 09 02:28:02 PM PDT 24
Finished Jun 09 02:28:13 PM PDT 24
Peak memory 208952 kb
Host smart-daa1bab9-8807-4b60-9554-31a7152090ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615070467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1615070467
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3944104862
Short name T910
Test name
Test status
Simulation time 48708721 ps
CPU time 3.31 seconds
Started Jun 09 02:28:00 PM PDT 24
Finished Jun 09 02:28:03 PM PDT 24
Peak memory 208940 kb
Host smart-27f1d168-55b0-428f-b620-94d0365ca525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944104862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3944104862
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2569948227
Short name T36
Test name
Test status
Simulation time 397395579 ps
CPU time 2.51 seconds
Started Jun 09 02:28:02 PM PDT 24
Finished Jun 09 02:28:05 PM PDT 24
Peak memory 221948 kb
Host smart-324f02ae-3b7c-4d94-9399-764052e586ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569948227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2569948227
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.629401070
Short name T866
Test name
Test status
Simulation time 44066637 ps
CPU time 2.96 seconds
Started Jun 09 02:27:56 PM PDT 24
Finished Jun 09 02:27:59 PM PDT 24
Peak memory 220404 kb
Host smart-30e6348a-a756-49a9-946c-30aaed62deb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629401070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.629401070
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.611544447
Short name T232
Test name
Test status
Simulation time 16453733022 ps
CPU time 34.52 seconds
Started Jun 09 02:27:53 PM PDT 24
Finished Jun 09 02:28:28 PM PDT 24
Peak memory 209232 kb
Host smart-15977121-00de-4907-8e3d-8f1793c9d891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611544447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.611544447
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.4164043093
Short name T2
Test name
Test status
Simulation time 230397240 ps
CPU time 2.59 seconds
Started Jun 09 02:27:50 PM PDT 24
Finished Jun 09 02:27:53 PM PDT 24
Peak memory 206676 kb
Host smart-8ad7660f-85d5-4652-b4a2-bec176d6d1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164043093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.4164043093
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2740446329
Short name T720
Test name
Test status
Simulation time 209903641 ps
CPU time 4.31 seconds
Started Jun 09 02:27:52 PM PDT 24
Finished Jun 09 02:27:57 PM PDT 24
Peak memory 208072 kb
Host smart-ce70a260-5000-45a0-b42c-0136980c5ad4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740446329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2740446329
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2806328345
Short name T723
Test name
Test status
Simulation time 51312417 ps
CPU time 2.93 seconds
Started Jun 09 02:27:48 PM PDT 24
Finished Jun 09 02:27:52 PM PDT 24
Peak memory 208924 kb
Host smart-a85f8228-f2a2-49dc-a440-c796590be5ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806328345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2806328345
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3858884753
Short name T661
Test name
Test status
Simulation time 37023621 ps
CPU time 2.71 seconds
Started Jun 09 02:27:56 PM PDT 24
Finished Jun 09 02:27:59 PM PDT 24
Peak memory 218348 kb
Host smart-e8ad4183-7dd4-4235-99d6-f0ece9454124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858884753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3858884753
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3835042280
Short name T775
Test name
Test status
Simulation time 31425402 ps
CPU time 2.08 seconds
Started Jun 09 02:27:45 PM PDT 24
Finished Jun 09 02:27:47 PM PDT 24
Peak memory 206816 kb
Host smart-198f5999-6e5a-4511-9678-66b6a1eef59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835042280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3835042280
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1730662318
Short name T658
Test name
Test status
Simulation time 2738131668 ps
CPU time 18.09 seconds
Started Jun 09 02:28:16 PM PDT 24
Finished Jun 09 02:28:34 PM PDT 24
Peak memory 222600 kb
Host smart-2da28a70-d874-4ffd-b104-92387750b0d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730662318 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1730662318
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2595032357
Short name T821
Test name
Test status
Simulation time 467167340 ps
CPU time 5.2 seconds
Started Jun 09 02:27:59 PM PDT 24
Finished Jun 09 02:28:05 PM PDT 24
Peak memory 209336 kb
Host smart-d76b2d1d-cdc3-4b97-99ca-a928b3f5e0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595032357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2595032357
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1650181573
Short name T388
Test name
Test status
Simulation time 463644949 ps
CPU time 4.3 seconds
Started Jun 09 02:28:03 PM PDT 24
Finished Jun 09 02:28:07 PM PDT 24
Peak memory 210656 kb
Host smart-44f35238-5dc3-4b3d-866d-f62b3cfd1119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650181573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1650181573
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.791363148
Short name T599
Test name
Test status
Simulation time 13878549 ps
CPU time 0.94 seconds
Started Jun 09 02:28:23 PM PDT 24
Finished Jun 09 02:28:24 PM PDT 24
Peak memory 206112 kb
Host smart-a41bab2d-46b0-4ac9-832c-a4fe0d478d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791363148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.791363148
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3606625098
Short name T414
Test name
Test status
Simulation time 861404984 ps
CPU time 12.36 seconds
Started Jun 09 02:28:11 PM PDT 24
Finished Jun 09 02:28:24 PM PDT 24
Peak memory 215516 kb
Host smart-4347d5a1-2bc1-457b-847d-b879b24194e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3606625098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3606625098
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1857597789
Short name T782
Test name
Test status
Simulation time 333659956 ps
CPU time 3.49 seconds
Started Jun 09 02:28:11 PM PDT 24
Finished Jun 09 02:28:15 PM PDT 24
Peak memory 210112 kb
Host smart-99a52e4b-e6c1-4b6d-a4eb-811ccc781489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857597789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1857597789
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1721390298
Short name T529
Test name
Test status
Simulation time 42609582 ps
CPU time 2.44 seconds
Started Jun 09 02:28:02 PM PDT 24
Finished Jun 09 02:28:04 PM PDT 24
Peak memory 209796 kb
Host smart-bccddca0-cd75-49c6-8f7e-1677e2ce0d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721390298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1721390298
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2730872758
Short name T381
Test name
Test status
Simulation time 331754206 ps
CPU time 3.54 seconds
Started Jun 09 02:28:01 PM PDT 24
Finished Jun 09 02:28:05 PM PDT 24
Peak memory 209076 kb
Host smart-b86e00d0-2628-4d6e-95be-705f020922f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730872758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2730872758
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2883589521
Short name T289
Test name
Test status
Simulation time 319287482 ps
CPU time 6.96 seconds
Started Jun 09 02:28:05 PM PDT 24
Finished Jun 09 02:28:12 PM PDT 24
Peak memory 222436 kb
Host smart-230429f0-86a1-4f6e-a363-f0476ddb3faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883589521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2883589521
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2312941164
Short name T698
Test name
Test status
Simulation time 58796366 ps
CPU time 3.58 seconds
Started Jun 09 02:28:01 PM PDT 24
Finished Jun 09 02:28:05 PM PDT 24
Peak memory 214364 kb
Host smart-1ad0fea1-720b-4ba9-b33f-d191270f249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312941164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2312941164
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4201979529
Short name T260
Test name
Test status
Simulation time 395368688 ps
CPU time 4.75 seconds
Started Jun 09 02:27:57 PM PDT 24
Finished Jun 09 02:28:02 PM PDT 24
Peak memory 209960 kb
Host smart-c19b207b-f07b-46e8-adb2-d1ef715e4e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201979529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4201979529
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2533247073
Short name T227
Test name
Test status
Simulation time 383953626 ps
CPU time 4.38 seconds
Started Jun 09 02:28:01 PM PDT 24
Finished Jun 09 02:28:06 PM PDT 24
Peak memory 208544 kb
Host smart-3dfe9c74-50a0-4962-a7d5-04a9205ce4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533247073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2533247073
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1213044
Short name T109
Test name
Test status
Simulation time 452073353 ps
CPU time 12.01 seconds
Started Jun 09 02:28:00 PM PDT 24
Finished Jun 09 02:28:12 PM PDT 24
Peak memory 208136 kb
Host smart-e335a932-8fda-42f2-961e-a98ba3830efc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1213044
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.360315559
Short name T492
Test name
Test status
Simulation time 567869704 ps
CPU time 5.22 seconds
Started Jun 09 02:28:04 PM PDT 24
Finished Jun 09 02:28:09 PM PDT 24
Peak memory 208584 kb
Host smart-30fb3e75-0702-42c3-afdd-c298e1e51c8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360315559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.360315559
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3432263530
Short name T358
Test name
Test status
Simulation time 470450187 ps
CPU time 4.03 seconds
Started Jun 09 02:28:06 PM PDT 24
Finished Jun 09 02:28:11 PM PDT 24
Peak memory 208572 kb
Host smart-8df21236-8d83-4997-b65c-510be27fc4e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432263530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3432263530
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3516377023
Short name T539
Test name
Test status
Simulation time 97102122 ps
CPU time 2.17 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:13 PM PDT 24
Peak memory 214348 kb
Host smart-a7c5515b-1c04-4122-997d-4941770c8af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516377023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3516377023
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.405239577
Short name T144
Test name
Test status
Simulation time 62504218 ps
CPU time 2.12 seconds
Started Jun 09 02:27:58 PM PDT 24
Finished Jun 09 02:28:00 PM PDT 24
Peak memory 206844 kb
Host smart-b15916c9-e3d6-4516-bab1-b2d34ae97ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405239577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.405239577
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2367322688
Short name T305
Test name
Test status
Simulation time 917340455 ps
CPU time 21.87 seconds
Started Jun 09 02:28:04 PM PDT 24
Finished Jun 09 02:28:26 PM PDT 24
Peak memory 215460 kb
Host smart-42f33908-3d7c-408a-9616-71dceead4a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367322688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2367322688
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.4011853886
Short name T869
Test name
Test status
Simulation time 223757671 ps
CPU time 7.03 seconds
Started Jun 09 02:27:58 PM PDT 24
Finished Jun 09 02:28:05 PM PDT 24
Peak memory 214420 kb
Host smart-b01fd7ac-b84d-4349-8322-af66a87f476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011853886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.4011853886
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2073117888
Short name T786
Test name
Test status
Simulation time 222770235 ps
CPU time 6.33 seconds
Started Jun 09 02:28:06 PM PDT 24
Finished Jun 09 02:28:13 PM PDT 24
Peak memory 210344 kb
Host smart-85bb4767-42cd-4098-abd6-cc2fc613cf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073117888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2073117888
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.290497482
Short name T485
Test name
Test status
Simulation time 53868904 ps
CPU time 0.95 seconds
Started Jun 09 02:28:16 PM PDT 24
Finished Jun 09 02:28:17 PM PDT 24
Peak memory 206112 kb
Host smart-c9e58a80-9212-4772-8667-ab95bc4c5b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290497482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.290497482
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4029472540
Short name T628
Test name
Test status
Simulation time 45198679 ps
CPU time 1.75 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:13 PM PDT 24
Peak memory 208652 kb
Host smart-489fb550-df77-41c2-b77c-062928f752a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029472540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4029472540
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1396725897
Short name T591
Test name
Test status
Simulation time 2064211567 ps
CPU time 9.04 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:20 PM PDT 24
Peak memory 214348 kb
Host smart-09a80e46-4a56-4a9c-8c59-7115f5776074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396725897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1396725897
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3390945971
Short name T268
Test name
Test status
Simulation time 151102375 ps
CPU time 2.92 seconds
Started Jun 09 02:28:07 PM PDT 24
Finished Jun 09 02:28:10 PM PDT 24
Peak memory 207372 kb
Host smart-ac8fbe90-a2f8-47dc-8022-b44889ea77a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390945971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3390945971
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1390850084
Short name T729
Test name
Test status
Simulation time 119035447 ps
CPU time 2.64 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:13 PM PDT 24
Peak memory 209244 kb
Host smart-1c9910c6-4e32-4b54-ab41-7753ef4ce794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390850084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1390850084
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3835331654
Short name T700
Test name
Test status
Simulation time 1099599131 ps
CPU time 8.06 seconds
Started Jun 09 02:28:06 PM PDT 24
Finished Jun 09 02:28:14 PM PDT 24
Peak memory 208676 kb
Host smart-7c6a342c-2517-41a5-ba45-b2d1ba1b9613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835331654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3835331654
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2965243647
Short name T682
Test name
Test status
Simulation time 107237675 ps
CPU time 2.87 seconds
Started Jun 09 02:28:04 PM PDT 24
Finished Jun 09 02:28:07 PM PDT 24
Peak memory 206832 kb
Host smart-d736489f-a8b9-4f67-92d8-e902e033d3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965243647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2965243647
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1543363582
Short name T556
Test name
Test status
Simulation time 334148500 ps
CPU time 4.03 seconds
Started Jun 09 02:28:07 PM PDT 24
Finished Jun 09 02:28:12 PM PDT 24
Peak memory 208720 kb
Host smart-65e275d4-db69-469a-b3d2-9205715f78d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543363582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1543363582
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3283868715
Short name T898
Test name
Test status
Simulation time 62442711 ps
CPU time 3.16 seconds
Started Jun 09 02:28:11 PM PDT 24
Finished Jun 09 02:28:15 PM PDT 24
Peak memory 208688 kb
Host smart-43eeb254-8f70-4170-b4ec-a442295af725
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283868715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3283868715
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2793945404
Short name T842
Test name
Test status
Simulation time 1819773756 ps
CPU time 23.83 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:34 PM PDT 24
Peak memory 208372 kb
Host smart-8ade851e-94db-4ba6-9d42-59570194c6c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793945404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2793945404
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3715619273
Short name T732
Test name
Test status
Simulation time 138633413 ps
CPU time 1.91 seconds
Started Jun 09 02:28:13 PM PDT 24
Finished Jun 09 02:28:15 PM PDT 24
Peak memory 209696 kb
Host smart-3b383c85-de51-4948-a83d-8395346252c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715619273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3715619273
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.248805681
Short name T840
Test name
Test status
Simulation time 2187625725 ps
CPU time 3.18 seconds
Started Jun 09 02:28:09 PM PDT 24
Finished Jun 09 02:28:13 PM PDT 24
Peak memory 208716 kb
Host smart-e3db8857-51ff-4ab2-98ff-84ce65f5e362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248805681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.248805681
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2232181478
Short name T193
Test name
Test status
Simulation time 2031416780 ps
CPU time 14.42 seconds
Started Jun 09 02:28:07 PM PDT 24
Finished Jun 09 02:28:21 PM PDT 24
Peak memory 220376 kb
Host smart-2c39d5af-1a65-496e-8636-58182fa5a2e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232181478 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2232181478
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2470448354
Short name T244
Test name
Test status
Simulation time 1794780886 ps
CPU time 28.55 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 214328 kb
Host smart-1c837c37-128f-4818-80c1-8c0b8fbe46e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470448354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2470448354
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2193572669
Short name T667
Test name
Test status
Simulation time 115290668 ps
CPU time 1.99 seconds
Started Jun 09 02:28:05 PM PDT 24
Finished Jun 09 02:28:07 PM PDT 24
Peak memory 210560 kb
Host smart-d3d2097d-2ded-470e-b41a-0d9cdc9f8905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193572669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2193572669
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2612510207
Short name T666
Test name
Test status
Simulation time 50043482 ps
CPU time 0.74 seconds
Started Jun 09 02:28:22 PM PDT 24
Finished Jun 09 02:28:23 PM PDT 24
Peak memory 205940 kb
Host smart-9c988d33-a9b4-42ad-b18d-cbb044fe2808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612510207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2612510207
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3144377433
Short name T377
Test name
Test status
Simulation time 154397275 ps
CPU time 3.35 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:14 PM PDT 24
Peak memory 215076 kb
Host smart-1b113e11-f19a-47ff-a31d-72c4cb629060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3144377433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3144377433
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3036396669
Short name T21
Test name
Test status
Simulation time 103189913 ps
CPU time 4.34 seconds
Started Jun 09 02:28:11 PM PDT 24
Finished Jun 09 02:28:16 PM PDT 24
Peak memory 214724 kb
Host smart-f77ff2f1-ecd2-42ba-8c73-3fe852f4f17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036396669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3036396669
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.4103033131
Short name T79
Test name
Test status
Simulation time 29776853 ps
CPU time 1.9 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:13 PM PDT 24
Peak memory 207820 kb
Host smart-bdb0038a-b5dd-4522-bf6b-515789e319c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103033131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.4103033131
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3835742500
Short name T382
Test name
Test status
Simulation time 715995865 ps
CPU time 5.28 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:20 PM PDT 24
Peak memory 220540 kb
Host smart-c289c688-cf11-4681-8e51-8ce327e6e7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835742500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3835742500
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3897738351
Short name T252
Test name
Test status
Simulation time 44001069 ps
CPU time 2.41 seconds
Started Jun 09 02:28:23 PM PDT 24
Finished Jun 09 02:28:26 PM PDT 24
Peak memory 214212 kb
Host smart-b4777614-df1a-4de6-9cf7-2d0d99f964bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897738351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3897738351
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4168044466
Short name T558
Test name
Test status
Simulation time 362150636 ps
CPU time 2.21 seconds
Started Jun 09 02:28:16 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 222568 kb
Host smart-8e8ea1f5-8e01-4d6f-9717-ff78a259115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168044466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4168044466
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1046186160
Short name T114
Test name
Test status
Simulation time 1332432391 ps
CPU time 7.8 seconds
Started Jun 09 02:28:12 PM PDT 24
Finished Jun 09 02:28:20 PM PDT 24
Peak memory 209892 kb
Host smart-b785f547-5ea6-41ea-8bcf-3ca6ddc36d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046186160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1046186160
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.713391802
Short name T896
Test name
Test status
Simulation time 142487754 ps
CPU time 2.36 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 206100 kb
Host smart-49831a1f-c4c5-4672-ab1c-8d4e9278d815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713391802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.713391802
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2937602029
Short name T362
Test name
Test status
Simulation time 31430939 ps
CPU time 2.34 seconds
Started Jun 09 02:28:12 PM PDT 24
Finished Jun 09 02:28:14 PM PDT 24
Peak memory 208716 kb
Host smart-6e48b513-9bbc-42d8-9ed4-8815032b3b37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937602029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2937602029
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2400043988
Short name T601
Test name
Test status
Simulation time 1605941635 ps
CPU time 9.77 seconds
Started Jun 09 02:28:11 PM PDT 24
Finished Jun 09 02:28:21 PM PDT 24
Peak memory 208652 kb
Host smart-6d61c498-dcaf-4afd-a44d-f196214a0367
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400043988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2400043988
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1298576384
Short name T524
Test name
Test status
Simulation time 150770312 ps
CPU time 3.47 seconds
Started Jun 09 02:28:11 PM PDT 24
Finished Jun 09 02:28:15 PM PDT 24
Peak memory 207004 kb
Host smart-49e132cb-9ab3-418f-a90a-8ef79ffae569
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298576384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1298576384
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3081281578
Short name T789
Test name
Test status
Simulation time 142755537 ps
CPU time 4.74 seconds
Started Jun 09 02:28:11 PM PDT 24
Finished Jun 09 02:28:16 PM PDT 24
Peak memory 206820 kb
Host smart-f52f738f-7708-46de-8619-544b143adaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081281578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3081281578
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.397732697
Short name T711
Test name
Test status
Simulation time 135312239 ps
CPU time 5.94 seconds
Started Jun 09 02:28:13 PM PDT 24
Finished Jun 09 02:28:20 PM PDT 24
Peak memory 219416 kb
Host smart-53b625f8-91c8-499f-a338-be6b028a7402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397732697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.397732697
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2075908420
Short name T189
Test name
Test status
Simulation time 583956066 ps
CPU time 16.93 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:28:52 PM PDT 24
Peak memory 220516 kb
Host smart-1e057ef3-299b-4030-813e-fe1673f27c28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075908420 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2075908420
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3205037280
Short name T482
Test name
Test status
Simulation time 151723936 ps
CPU time 4.15 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:15 PM PDT 24
Peak memory 208212 kb
Host smart-184e49f6-115f-419f-8c3b-6f0df4c6dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205037280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3205037280
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.246530833
Short name T67
Test name
Test status
Simulation time 318933612 ps
CPU time 2.49 seconds
Started Jun 09 02:28:11 PM PDT 24
Finished Jun 09 02:28:14 PM PDT 24
Peak memory 210488 kb
Host smart-3e2a1ed1-a550-4349-af21-811cd546c62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246530833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.246530833
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2929190660
Short name T595
Test name
Test status
Simulation time 29712752 ps
CPU time 0.9 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:12 PM PDT 24
Peak memory 206108 kb
Host smart-287aebcf-3387-4030-99f5-b43872f8e7a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929190660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2929190660
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.463280168
Short name T553
Test name
Test status
Simulation time 318438240 ps
CPU time 3.68 seconds
Started Jun 09 02:28:33 PM PDT 24
Finished Jun 09 02:28:37 PM PDT 24
Peak memory 209128 kb
Host smart-437a3398-3372-4f9c-81cc-88da86dc7f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463280168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.463280168
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.228397741
Short name T746
Test name
Test status
Simulation time 1074033230 ps
CPU time 15.74 seconds
Started Jun 09 02:28:24 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 210160 kb
Host smart-8a30d166-38e7-4771-97b3-30777bee06c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228397741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.228397741
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1281720988
Short name T96
Test name
Test status
Simulation time 76096581 ps
CPU time 2.88 seconds
Started Jun 09 02:28:33 PM PDT 24
Finished Jun 09 02:28:36 PM PDT 24
Peak memory 209364 kb
Host smart-a782968d-c19b-469b-b0d3-ec6151ad22fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281720988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1281720988
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.60608511
Short name T288
Test name
Test status
Simulation time 92609254 ps
CPU time 2.03 seconds
Started Jun 09 02:28:22 PM PDT 24
Finished Jun 09 02:28:25 PM PDT 24
Peak memory 218852 kb
Host smart-e849e1a4-842a-48c2-b7c9-e1214ae1cf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60608511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.60608511
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_random.517388208
Short name T839
Test name
Test status
Simulation time 225412237 ps
CPU time 3.25 seconds
Started Jun 09 02:28:14 PM PDT 24
Finished Jun 09 02:28:17 PM PDT 24
Peak memory 207552 kb
Host smart-91424730-4cdf-464e-9924-06a76b9680d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517388208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.517388208
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4001307691
Short name T837
Test name
Test status
Simulation time 700330126 ps
CPU time 17.61 seconds
Started Jun 09 02:28:06 PM PDT 24
Finished Jun 09 02:28:24 PM PDT 24
Peak memory 208228 kb
Host smart-1baa1304-6d04-4ada-aeb0-71fbc089641c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001307691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4001307691
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2934944844
Short name T707
Test name
Test status
Simulation time 93766465 ps
CPU time 1.92 seconds
Started Jun 09 02:28:08 PM PDT 24
Finished Jun 09 02:28:10 PM PDT 24
Peak memory 207420 kb
Host smart-14501f98-8bf8-4410-bbca-188b22962b67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934944844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2934944844
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2958324301
Short name T147
Test name
Test status
Simulation time 73293414 ps
CPU time 2.55 seconds
Started Jun 09 02:28:18 PM PDT 24
Finished Jun 09 02:28:20 PM PDT 24
Peak memory 207700 kb
Host smart-702234a9-a3cf-4021-bc9c-225522316873
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958324301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2958324301
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1758832490
Short name T231
Test name
Test status
Simulation time 132550246 ps
CPU time 2.96 seconds
Started Jun 09 02:28:09 PM PDT 24
Finished Jun 09 02:28:12 PM PDT 24
Peak memory 206988 kb
Host smart-845bb8d1-9dda-4c9d-8681-131a51a2409a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758832490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1758832490
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1454914193
Short name T721
Test name
Test status
Simulation time 145664322 ps
CPU time 2.06 seconds
Started Jun 09 02:28:19 PM PDT 24
Finished Jun 09 02:28:21 PM PDT 24
Peak memory 207052 kb
Host smart-c683d99d-1573-46a9-bcf0-53797284e22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454914193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1454914193
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3629374583
Short name T18
Test name
Test status
Simulation time 590589153 ps
CPU time 12.47 seconds
Started Jun 09 02:28:08 PM PDT 24
Finished Jun 09 02:28:21 PM PDT 24
Peak memory 208800 kb
Host smart-b37f8526-21fe-47b9-be6a-5fda341b220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629374583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3629374583
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1566545293
Short name T276
Test name
Test status
Simulation time 1159706171 ps
CPU time 29.12 seconds
Started Jun 09 02:28:11 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 215120 kb
Host smart-b87e7b48-8c03-49ca-8fa5-d59a3a981e49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566545293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1566545293
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3124057726
Short name T864
Test name
Test status
Simulation time 2799584613 ps
CPU time 14.35 seconds
Started Jun 09 02:28:26 PM PDT 24
Finished Jun 09 02:28:41 PM PDT 24
Peak memory 222776 kb
Host smart-65a6764e-323f-48a9-96a4-1e332f99f4f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124057726 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3124057726
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3418810708
Short name T791
Test name
Test status
Simulation time 348746949 ps
CPU time 4.7 seconds
Started Jun 09 02:28:07 PM PDT 24
Finished Jun 09 02:28:12 PM PDT 24
Peak memory 214352 kb
Host smart-6b6d39d4-f0c3-4529-b5da-4a2e778e2244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418810708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3418810708
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3180835055
Short name T783
Test name
Test status
Simulation time 286810354 ps
CPU time 2.67 seconds
Started Jun 09 02:28:33 PM PDT 24
Finished Jun 09 02:28:36 PM PDT 24
Peak memory 209956 kb
Host smart-e4f27f1c-0d99-4fed-856e-7e79c91bb532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180835055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3180835055
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3202348802
Short name T875
Test name
Test status
Simulation time 39070470 ps
CPU time 0.74 seconds
Started Jun 09 02:28:18 PM PDT 24
Finished Jun 09 02:28:19 PM PDT 24
Peak memory 205940 kb
Host smart-aa6772f1-5e1d-405a-9224-d125455ee99f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202348802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3202348802
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1383360820
Short name T408
Test name
Test status
Simulation time 142035770 ps
CPU time 5.24 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:16 PM PDT 24
Peak memory 215624 kb
Host smart-562bbed6-3dce-4698-aba3-4cfb14e4536c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383360820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1383360820
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.4020115319
Short name T588
Test name
Test status
Simulation time 162899715 ps
CPU time 5.51 seconds
Started Jun 09 02:28:21 PM PDT 24
Finished Jun 09 02:28:26 PM PDT 24
Peak memory 214236 kb
Host smart-3a39327e-9288-4f60-905b-e34d19537af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020115319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.4020115319
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.415811513
Short name T493
Test name
Test status
Simulation time 883673011 ps
CPU time 8.6 seconds
Started Jun 09 02:28:26 PM PDT 24
Finished Jun 09 02:28:35 PM PDT 24
Peak memory 208520 kb
Host smart-48c039af-2ee9-46b6-ad83-9a8419ef3be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415811513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.415811513
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2816496511
Short name T316
Test name
Test status
Simulation time 476840584 ps
CPU time 5.83 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:17 PM PDT 24
Peak memory 208692 kb
Host smart-dacbe722-17f2-41fa-8792-ad9ae131b34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816496511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2816496511
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2997978203
Short name T55
Test name
Test status
Simulation time 55474391 ps
CPU time 3.78 seconds
Started Jun 09 02:28:30 PM PDT 24
Finished Jun 09 02:28:34 PM PDT 24
Peak memory 214544 kb
Host smart-d02ee6a1-74cd-443d-a535-a9ef918e832d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997978203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2997978203
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.4127867534
Short name T47
Test name
Test status
Simulation time 489238712 ps
CPU time 3.08 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:14 PM PDT 24
Peak memory 209116 kb
Host smart-025e3715-6e13-4f1f-84af-bdf442d9bf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127867534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4127867534
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2139970072
Short name T593
Test name
Test status
Simulation time 1204808592 ps
CPU time 13.73 seconds
Started Jun 09 02:28:18 PM PDT 24
Finished Jun 09 02:28:32 PM PDT 24
Peak memory 208148 kb
Host smart-65df1e69-8422-458a-9d32-23e235d96780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139970072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2139970072
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3919806621
Short name T863
Test name
Test status
Simulation time 76923153 ps
CPU time 2.24 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:13 PM PDT 24
Peak memory 207152 kb
Host smart-cae26e70-1559-4297-88ef-fcaddcf7713d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919806621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3919806621
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.282433446
Short name T652
Test name
Test status
Simulation time 217956182 ps
CPU time 2.76 seconds
Started Jun 09 02:28:24 PM PDT 24
Finished Jun 09 02:28:27 PM PDT 24
Peak memory 208956 kb
Host smart-84b37bc3-07d7-41b5-92ed-904a0b3b53a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282433446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.282433446
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.857438182
Short name T551
Test name
Test status
Simulation time 337917693 ps
CPU time 2.64 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 208676 kb
Host smart-84ba93ac-6915-4c6a-93bc-7717d3192c2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857438182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.857438182
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1593234512
Short name T329
Test name
Test status
Simulation time 124819547 ps
CPU time 2.33 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 206984 kb
Host smart-44d44c46-49ed-48a3-9703-c8d9fe098e29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593234512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1593234512
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3028943470
Short name T540
Test name
Test status
Simulation time 95041369 ps
CPU time 2.57 seconds
Started Jun 09 02:28:32 PM PDT 24
Finished Jun 09 02:28:35 PM PDT 24
Peak memory 220524 kb
Host smart-4ae054e4-ea53-4963-981a-235ed4860a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028943470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3028943470
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3793541982
Short name T582
Test name
Test status
Simulation time 2368123485 ps
CPU time 12.88 seconds
Started Jun 09 02:28:09 PM PDT 24
Finished Jun 09 02:28:22 PM PDT 24
Peak memory 208360 kb
Host smart-d611413c-e54a-472a-b9e4-0fd5db8e1a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793541982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3793541982
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1204573777
Short name T60
Test name
Test status
Simulation time 233699319 ps
CPU time 8.15 seconds
Started Jun 09 02:28:10 PM PDT 24
Finished Jun 09 02:28:19 PM PDT 24
Peak memory 215096 kb
Host smart-35f507b8-ea1c-47d5-b7d9-15a50066c571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204573777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1204573777
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.855314485
Short name T361
Test name
Test status
Simulation time 2315924915 ps
CPU time 23.52 seconds
Started Jun 09 02:28:51 PM PDT 24
Finished Jun 09 02:29:15 PM PDT 24
Peak memory 222576 kb
Host smart-c1bf4871-1116-4c33-9b6a-89aee3008d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855314485 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.855314485
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1935459947
Short name T825
Test name
Test status
Simulation time 97179213 ps
CPU time 2.7 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 208792 kb
Host smart-e7829acb-d666-43c2-be86-d1465931e8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935459947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1935459947
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.430593489
Short name T714
Test name
Test status
Simulation time 40536986 ps
CPU time 1.4 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:38 PM PDT 24
Peak memory 209500 kb
Host smart-b64e6298-e3d1-40be-a0c3-9ef8a719d1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430593489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.430593489
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1227481316
Short name T476
Test name
Test status
Simulation time 66117872 ps
CPU time 0.94 seconds
Started Jun 09 02:28:31 PM PDT 24
Finished Jun 09 02:28:32 PM PDT 24
Peak memory 205952 kb
Host smart-6b9f2778-75f5-4744-bd14-3d3d2440b4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227481316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1227481316
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3128134251
Short name T413
Test name
Test status
Simulation time 1979946946 ps
CPU time 106.67 seconds
Started Jun 09 02:28:36 PM PDT 24
Finished Jun 09 02:30:24 PM PDT 24
Peak memory 213720 kb
Host smart-dd5b8525-d0e9-431e-a20f-c4b59c7f227a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128134251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3128134251
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.13320997
Short name T674
Test name
Test status
Simulation time 405897578 ps
CPU time 3.81 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:33 PM PDT 24
Peak memory 220936 kb
Host smart-e1f474b0-780f-40b6-93cc-f29c26212c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13320997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.13320997
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.231846340
Short name T417
Test name
Test status
Simulation time 96398515 ps
CPU time 1.52 seconds
Started Jun 09 02:28:22 PM PDT 24
Finished Jun 09 02:28:24 PM PDT 24
Peak memory 207536 kb
Host smart-5b1e076f-ab59-4cce-82ae-40814ff98dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231846340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.231846340
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2820174560
Short name T374
Test name
Test status
Simulation time 29493982 ps
CPU time 1.81 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:31 PM PDT 24
Peak memory 213856 kb
Host smart-17c80c7d-57ed-4425-8b9e-aecf0888db41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820174560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2820174560
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3436759939
Short name T332
Test name
Test status
Simulation time 386829645 ps
CPU time 4.13 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 214344 kb
Host smart-2edc94e8-ea4c-416a-b6a5-7d54b6f6d093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436759939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3436759939
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.93581316
Short name T219
Test name
Test status
Simulation time 124549933 ps
CPU time 3.54 seconds
Started Jun 09 02:28:28 PM PDT 24
Finished Jun 09 02:28:32 PM PDT 24
Peak memory 208604 kb
Host smart-009ad663-44bd-483a-9c31-6b0312dfe445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93581316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.93581316
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.826873510
Short name T224
Test name
Test status
Simulation time 246371117 ps
CPU time 5.15 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:29:51 PM PDT 24
Peak memory 208068 kb
Host smart-d2039ad0-5ec2-4b36-914b-b7b6f187af42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826873510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.826873510
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1593261528
Short name T454
Test name
Test status
Simulation time 117246896 ps
CPU time 2.79 seconds
Started Jun 09 02:28:19 PM PDT 24
Finished Jun 09 02:28:22 PM PDT 24
Peak memory 208132 kb
Host smart-30034c39-8570-4f3b-a8df-d3e1688f2caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593261528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1593261528
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.10191778
Short name T580
Test name
Test status
Simulation time 344521252 ps
CPU time 4.06 seconds
Started Jun 09 02:28:53 PM PDT 24
Finished Jun 09 02:28:57 PM PDT 24
Peak memory 208540 kb
Host smart-47d49667-5b12-4e8d-b761-0cd3d7557f6a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10191778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.10191778
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3131790227
Short name T517
Test name
Test status
Simulation time 48245745 ps
CPU time 2.59 seconds
Started Jun 09 02:28:11 PM PDT 24
Finished Jun 09 02:28:14 PM PDT 24
Peak memory 208760 kb
Host smart-032f0ea6-021e-455f-a672-c16c95683f09
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131790227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3131790227
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2960832753
Short name T565
Test name
Test status
Simulation time 144169934 ps
CPU time 2.35 seconds
Started Jun 09 02:28:22 PM PDT 24
Finished Jun 09 02:28:25 PM PDT 24
Peak memory 206924 kb
Host smart-2b3683a2-f722-44cd-8d37-844e21575f61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960832753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2960832753
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1495294676
Short name T328
Test name
Test status
Simulation time 97034809 ps
CPU time 2.79 seconds
Started Jun 09 02:28:43 PM PDT 24
Finished Jun 09 02:28:46 PM PDT 24
Peak memory 210084 kb
Host smart-d2cb5e8f-777a-4967-aa0c-0c8411c9a925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495294676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1495294676
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2599478277
Short name T510
Test name
Test status
Simulation time 64702319 ps
CPU time 2.81 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:52 PM PDT 24
Peak memory 208200 kb
Host smart-5e8f064e-d870-4472-889e-ebee9284d295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599478277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2599478277
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4282371246
Short name T578
Test name
Test status
Simulation time 1696272648 ps
CPU time 15.05 seconds
Started Jun 09 02:29:28 PM PDT 24
Finished Jun 09 02:29:43 PM PDT 24
Peak memory 215048 kb
Host smart-f51326ba-b56b-42b9-98e7-884c00c4c333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282371246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4282371246
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1143445325
Short name T214
Test name
Test status
Simulation time 2893426371 ps
CPU time 27.8 seconds
Started Jun 09 02:28:18 PM PDT 24
Finished Jun 09 02:28:46 PM PDT 24
Peak memory 222632 kb
Host smart-0505c6aa-97fc-4050-abee-d181fd4160a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143445325 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1143445325
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1321776834
Short name T339
Test name
Test status
Simulation time 181192324 ps
CPU time 5.85 seconds
Started Jun 09 02:29:28 PM PDT 24
Finished Jun 09 02:29:34 PM PDT 24
Peak memory 208396 kb
Host smart-7e73c180-963f-46dc-8b1d-e47e7475d577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321776834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1321776834
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3424400274
Short name T858
Test name
Test status
Simulation time 46584621 ps
CPU time 0.92 seconds
Started Jun 09 02:28:36 PM PDT 24
Finished Jun 09 02:28:38 PM PDT 24
Peak memory 206108 kb
Host smart-ed065d16-50ad-4a68-9500-a28500a19a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424400274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3424400274
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2371600140
Short name T29
Test name
Test status
Simulation time 130702981 ps
CPU time 5.43 seconds
Started Jun 09 02:28:21 PM PDT 24
Finished Jun 09 02:28:27 PM PDT 24
Peak memory 222724 kb
Host smart-510e7661-fbf7-482b-ae86-b087cc083a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371600140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2371600140
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2347876663
Short name T416
Test name
Test status
Simulation time 113232335 ps
CPU time 2.38 seconds
Started Jun 09 02:29:28 PM PDT 24
Finished Jun 09 02:29:36 PM PDT 24
Peak memory 217764 kb
Host smart-f250637e-4a15-4846-af6d-d2b6ff40e7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347876663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2347876663
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.714182824
Short name T324
Test name
Test status
Simulation time 431581858 ps
CPU time 4.76 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:20 PM PDT 24
Peak memory 219268 kb
Host smart-f6efcc46-23b4-4308-aea6-4b9426522e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714182824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.714182824
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1666901304
Short name T829
Test name
Test status
Simulation time 196394701 ps
CPU time 3.12 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:41 PM PDT 24
Peak memory 219728 kb
Host smart-630b615e-4bd2-4d79-8e1d-2f14bfcf8e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666901304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1666901304
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1780479637
Short name T865
Test name
Test status
Simulation time 201951781 ps
CPU time 7.09 seconds
Started Jun 09 02:28:27 PM PDT 24
Finished Jun 09 02:28:35 PM PDT 24
Peak memory 214324 kb
Host smart-a690f0a1-9952-4016-afda-271214bca050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780479637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1780479637
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.4085981663
Short name T237
Test name
Test status
Simulation time 740881561 ps
CPU time 8.22 seconds
Started Jun 09 02:28:32 PM PDT 24
Finished Jun 09 02:28:41 PM PDT 24
Peak memory 208592 kb
Host smart-ea327741-f144-41f8-8071-1d5da6e164fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085981663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.4085981663
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1833660202
Short name T626
Test name
Test status
Simulation time 174311964 ps
CPU time 2.57 seconds
Started Jun 09 02:28:16 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 208656 kb
Host smart-1965c561-b1c1-4f4c-83aa-f9e2146682e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833660202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1833660202
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.57617913
Short name T759
Test name
Test status
Simulation time 41216415 ps
CPU time 2.56 seconds
Started Jun 09 02:28:32 PM PDT 24
Finished Jun 09 02:28:34 PM PDT 24
Peak memory 208564 kb
Host smart-cacf5177-d9bd-4046-abc6-e97b95f453e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57617913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.57617913
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1070773390
Short name T770
Test name
Test status
Simulation time 781961136 ps
CPU time 6.02 seconds
Started Jun 09 02:28:30 PM PDT 24
Finished Jun 09 02:28:36 PM PDT 24
Peak memory 207968 kb
Host smart-05d06e27-f87c-4c2c-9dcc-26cffd767870
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070773390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1070773390
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1585081110
Short name T294
Test name
Test status
Simulation time 112164813 ps
CPU time 3.67 seconds
Started Jun 09 02:28:16 PM PDT 24
Finished Jun 09 02:28:20 PM PDT 24
Peak memory 218560 kb
Host smart-55953d31-dd7a-4f12-a382-2e3c9d0d5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585081110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1585081110
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1603073744
Short name T427
Test name
Test status
Simulation time 593582472 ps
CPU time 3.77 seconds
Started Jun 09 02:28:14 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 208184 kb
Host smart-d31dfd47-a5f7-4867-97a5-ad4a16cc591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603073744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1603073744
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.663178353
Short name T65
Test name
Test status
Simulation time 676362228 ps
CPU time 18.49 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:57 PM PDT 24
Peak memory 216824 kb
Host smart-16fd3e5a-aa7f-4de4-8a09-ac8f0e07ca1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663178353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.663178353
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3457119690
Short name T363
Test name
Test status
Simulation time 369667812 ps
CPU time 16.15 seconds
Started Jun 09 02:28:13 PM PDT 24
Finished Jun 09 02:28:30 PM PDT 24
Peak memory 222628 kb
Host smart-fe12a8b4-90f3-491c-8042-c068783b9fdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457119690 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3457119690
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.239900037
Short name T750
Test name
Test status
Simulation time 1434650191 ps
CPU time 7.07 seconds
Started Jun 09 02:29:46 PM PDT 24
Finished Jun 09 02:29:53 PM PDT 24
Peak memory 218400 kb
Host smart-eb820d2b-633a-4405-af9d-2eb8b996f0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239900037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.239900037
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3155139896
Short name T651
Test name
Test status
Simulation time 106163924 ps
CPU time 2.84 seconds
Started Jun 09 02:29:28 PM PDT 24
Finished Jun 09 02:29:31 PM PDT 24
Peak memory 208676 kb
Host smart-251bd61f-7db8-431f-851d-bd8bc728242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155139896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3155139896
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2611002029
Short name T808
Test name
Test status
Simulation time 47783722 ps
CPU time 0.86 seconds
Started Jun 09 02:28:19 PM PDT 24
Finished Jun 09 02:28:21 PM PDT 24
Peak memory 205960 kb
Host smart-e53126bb-c303-451f-98d2-68e330d14625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611002029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2611002029
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3002952021
Short name T412
Test name
Test status
Simulation time 626087001 ps
CPU time 23.82 seconds
Started Jun 09 02:28:36 PM PDT 24
Finished Jun 09 02:29:01 PM PDT 24
Peak memory 214308 kb
Host smart-e43b27b2-9af4-4992-a9b1-95e18c189ec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3002952021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3002952021
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2594680950
Short name T396
Test name
Test status
Simulation time 523698996 ps
CPU time 6.2 seconds
Started Jun 09 02:28:30 PM PDT 24
Finished Jun 09 02:28:36 PM PDT 24
Peak memory 222780 kb
Host smart-edfc53cc-2f33-4405-9905-4bd911e8b08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594680950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2594680950
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4175034622
Short name T371
Test name
Test status
Simulation time 100692677 ps
CPU time 3.5 seconds
Started Jun 09 02:28:23 PM PDT 24
Finished Jun 09 02:28:27 PM PDT 24
Peak memory 214304 kb
Host smart-7e094e26-c0a4-4fd1-b565-fe28535ca74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175034622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4175034622
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2916728234
Short name T354
Test name
Test status
Simulation time 65266851 ps
CPU time 2.36 seconds
Started Jun 09 02:28:16 PM PDT 24
Finished Jun 09 02:28:19 PM PDT 24
Peak memory 214252 kb
Host smart-12b4bdac-f3de-49df-9f1a-79d6362720bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916728234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2916728234
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.4145739020
Short name T277
Test name
Test status
Simulation time 165833228 ps
CPU time 3.86 seconds
Started Jun 09 02:28:25 PM PDT 24
Finished Jun 09 02:28:29 PM PDT 24
Peak memory 209432 kb
Host smart-dccbdcf9-8a51-4201-b5e9-bd9c7eec8ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145739020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.4145739020
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.637851011
Short name T496
Test name
Test status
Simulation time 370337803 ps
CPU time 4.35 seconds
Started Jun 09 02:28:28 PM PDT 24
Finished Jun 09 02:28:32 PM PDT 24
Peak memory 209904 kb
Host smart-43660c89-9726-4da8-9781-b9f634ae0bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637851011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.637851011
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2075308930
Short name T903
Test name
Test status
Simulation time 165094856 ps
CPU time 5.38 seconds
Started Jun 09 02:28:33 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 208020 kb
Host smart-9acaf950-3fed-459e-b9eb-a4b09bdf85e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075308930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2075308930
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3598336791
Short name T798
Test name
Test status
Simulation time 246822987 ps
CPU time 3.38 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 208408 kb
Host smart-8fb893fb-7046-4e91-8c8a-c66c748d935a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598336791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3598336791
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2434733091
Short name T581
Test name
Test status
Simulation time 64524632 ps
CPU time 3.2 seconds
Started Jun 09 02:28:27 PM PDT 24
Finished Jun 09 02:28:31 PM PDT 24
Peak memory 206968 kb
Host smart-ef373ab3-9e28-4e4b-9e3a-c49b088e801f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434733091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2434733091
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.751327005
Short name T468
Test name
Test status
Simulation time 823500223 ps
CPU time 6.2 seconds
Started Jun 09 02:29:29 PM PDT 24
Finished Jun 09 02:29:35 PM PDT 24
Peak memory 207788 kb
Host smart-ca5f097e-edee-49ef-acd0-74af6b987444
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751327005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.751327005
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.552572956
Short name T579
Test name
Test status
Simulation time 108539661 ps
CPU time 2.45 seconds
Started Jun 09 02:28:34 PM PDT 24
Finished Jun 09 02:28:37 PM PDT 24
Peak memory 214416 kb
Host smart-3f887ddc-e822-4f08-b3bd-6f19328b7e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552572956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.552572956
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3713077360
Short name T878
Test name
Test status
Simulation time 199779582 ps
CPU time 2.8 seconds
Started Jun 09 02:28:25 PM PDT 24
Finished Jun 09 02:28:28 PM PDT 24
Peak memory 206888 kb
Host smart-3a5983c2-4ce5-40ba-ae38-1d8af925d79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713077360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3713077360
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3876848989
Short name T246
Test name
Test status
Simulation time 52562021 ps
CPU time 3.16 seconds
Started Jun 09 02:29:28 PM PDT 24
Finished Jun 09 02:29:32 PM PDT 24
Peak memory 206520 kb
Host smart-37233d9d-1e75-40ab-a637-84fa96f6e42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876848989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3876848989
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.19616199
Short name T600
Test name
Test status
Simulation time 127437872 ps
CPU time 2.53 seconds
Started Jun 09 02:28:21 PM PDT 24
Finished Jun 09 02:28:24 PM PDT 24
Peak memory 210352 kb
Host smart-02737720-b75d-4491-8ddd-70cdbc14a8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19616199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.19616199
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2490697186
Short name T797
Test name
Test status
Simulation time 11260440 ps
CPU time 0.9 seconds
Started Jun 09 02:28:41 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 205968 kb
Host smart-a838ad68-6928-456d-b6a0-36cd5564a417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490697186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2490697186
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3296476697
Short name T907
Test name
Test status
Simulation time 397756799 ps
CPU time 2.85 seconds
Started Jun 09 02:28:22 PM PDT 24
Finished Jun 09 02:28:25 PM PDT 24
Peak memory 210324 kb
Host smart-89532451-0362-4ebf-b565-920fb3254c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296476697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3296476697
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.415713409
Short name T688
Test name
Test status
Simulation time 22163682 ps
CPU time 1.81 seconds
Started Jun 09 02:28:36 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 214348 kb
Host smart-4391136e-b5aa-4227-90c8-651058926844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415713409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.415713409
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.471568277
Short name T98
Test name
Test status
Simulation time 367068149 ps
CPU time 4.44 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 219188 kb
Host smart-b95a2056-4163-4d8d-80ca-86e0662cc74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471568277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.471568277
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.228450391
Short name T249
Test name
Test status
Simulation time 135957765 ps
CPU time 2.41 seconds
Started Jun 09 02:28:27 PM PDT 24
Finished Jun 09 02:28:29 PM PDT 24
Peak memory 222444 kb
Host smart-d9c813f6-0c44-4b25-9b22-ebb9df9d1ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228450391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.228450391
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1287309229
Short name T113
Test name
Test status
Simulation time 91341111 ps
CPU time 3.99 seconds
Started Jun 09 02:28:20 PM PDT 24
Finished Jun 09 02:28:24 PM PDT 24
Peak memory 210076 kb
Host smart-bb8db80a-0e45-4000-9c15-3764afcde75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287309229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1287309229
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.240110488
Short name T685
Test name
Test status
Simulation time 105723212 ps
CPU time 3.68 seconds
Started Jun 09 02:28:25 PM PDT 24
Finished Jun 09 02:28:29 PM PDT 24
Peak memory 214324 kb
Host smart-dee757df-e112-4c1f-92ff-a6ff6b4c3ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240110488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.240110488
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1077229279
Short name T771
Test name
Test status
Simulation time 30411336 ps
CPU time 2.22 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 206932 kb
Host smart-fd342da0-3db8-4ba0-9095-35716fe4a07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077229279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1077229279
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2275846149
Short name T455
Test name
Test status
Simulation time 205510378 ps
CPU time 5.67 seconds
Started Jun 09 02:28:22 PM PDT 24
Finished Jun 09 02:28:28 PM PDT 24
Peak memory 207956 kb
Host smart-582a3352-9b73-405b-9bc7-7f23a2903d05
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275846149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2275846149
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2772812178
Short name T465
Test name
Test status
Simulation time 1689453491 ps
CPU time 21.24 seconds
Started Jun 09 02:28:22 PM PDT 24
Finished Jun 09 02:28:44 PM PDT 24
Peak memory 208304 kb
Host smart-8ff2e53a-e29e-48e3-afd8-8519190fb5fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772812178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2772812178
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2050670172
Short name T430
Test name
Test status
Simulation time 75393404 ps
CPU time 2.92 seconds
Started Jun 09 02:28:31 PM PDT 24
Finished Jun 09 02:28:34 PM PDT 24
Peak memory 206800 kb
Host smart-1b869571-f41e-4638-8d7e-7492057b89f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050670172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2050670172
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.605525465
Short name T135
Test name
Test status
Simulation time 421486921 ps
CPU time 4.49 seconds
Started Jun 09 02:28:34 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 214352 kb
Host smart-20b106f4-8f42-44b8-baad-446249732d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605525465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.605525465
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1066373523
Short name T401
Test name
Test status
Simulation time 171345510 ps
CPU time 4.15 seconds
Started Jun 09 02:28:19 PM PDT 24
Finished Jun 09 02:28:23 PM PDT 24
Peak memory 206904 kb
Host smart-82ab911d-b94d-41a6-96cb-460512e0910e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066373523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1066373523
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.296585257
Short name T69
Test name
Test status
Simulation time 626803564 ps
CPU time 25.29 seconds
Started Jun 09 02:28:36 PM PDT 24
Finished Jun 09 02:29:02 PM PDT 24
Peak memory 221040 kb
Host smart-0874f459-9110-4b07-a227-d5e9f3f7c242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296585257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.296585257
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.35840962
Short name T679
Test name
Test status
Simulation time 226914646 ps
CPU time 9.47 seconds
Started Jun 09 02:28:19 PM PDT 24
Finished Jun 09 02:28:29 PM PDT 24
Peak memory 222528 kb
Host smart-a3d73c67-937a-4efc-9e90-2042aa3d172b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35840962 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.35840962
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1763858754
Short name T618
Test name
Test status
Simulation time 510983963 ps
CPU time 7.33 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:47 PM PDT 24
Peak memory 208988 kb
Host smart-2e54f21f-6db4-49df-b816-c34e939c898f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763858754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1763858754
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.4078145509
Short name T512
Test name
Test status
Simulation time 64770335 ps
CPU time 1.39 seconds
Started Jun 09 02:28:20 PM PDT 24
Finished Jun 09 02:28:22 PM PDT 24
Peak memory 210048 kb
Host smart-87a218ff-d42a-41c7-8c1a-8343de47fd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078145509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4078145509
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2419103883
Short name T787
Test name
Test status
Simulation time 24624902 ps
CPU time 0.68 seconds
Started Jun 09 02:26:36 PM PDT 24
Finished Jun 09 02:26:37 PM PDT 24
Peak memory 205972 kb
Host smart-d22e0530-a444-4a21-aaeb-984ee02141ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419103883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2419103883
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.190419937
Short name T154
Test name
Test status
Simulation time 116742056 ps
CPU time 2.57 seconds
Started Jun 09 02:26:36 PM PDT 24
Finished Jun 09 02:26:39 PM PDT 24
Peak memory 215388 kb
Host smart-cf36b2b2-2e25-4183-9cb6-6fc8752235a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190419937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.190419937
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1051136556
Short name T632
Test name
Test status
Simulation time 685788637 ps
CPU time 6.74 seconds
Started Jun 09 02:26:35 PM PDT 24
Finished Jun 09 02:26:42 PM PDT 24
Peak memory 208768 kb
Host smart-221e2ce2-bac7-4205-8428-5ab3f1d62583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051136556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1051136556
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2110316716
Short name T541
Test name
Test status
Simulation time 174360285 ps
CPU time 3.43 seconds
Started Jun 09 02:26:39 PM PDT 24
Finished Jun 09 02:26:43 PM PDT 24
Peak memory 208156 kb
Host smart-4c646cdb-4fc1-4fd1-ade3-eaf6c8e33e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110316716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2110316716
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3487480309
Short name T197
Test name
Test status
Simulation time 457779540 ps
CPU time 5.03 seconds
Started Jun 09 02:26:33 PM PDT 24
Finished Jun 09 02:26:39 PM PDT 24
Peak memory 208952 kb
Host smart-820daf9c-b946-4ac6-b6fb-fc59155726e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487480309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3487480309
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2587505641
Short name T136
Test name
Test status
Simulation time 157914837 ps
CPU time 2.39 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:26:37 PM PDT 24
Peak memory 206784 kb
Host smart-cdc89724-db1e-48eb-9d05-8e57de179eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587505641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2587505641
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3095645446
Short name T906
Test name
Test status
Simulation time 73166467 ps
CPU time 2.83 seconds
Started Jun 09 02:26:39 PM PDT 24
Finished Jun 09 02:26:43 PM PDT 24
Peak memory 208764 kb
Host smart-84046204-127c-4764-addb-25b099eebf9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095645446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3095645446
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2234491060
Short name T696
Test name
Test status
Simulation time 72699557 ps
CPU time 3.4 seconds
Started Jun 09 02:26:31 PM PDT 24
Finished Jun 09 02:26:35 PM PDT 24
Peak memory 208700 kb
Host smart-37dfdb36-2f37-42bf-989f-0c74f7d3f3d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234491060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2234491060
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.512704949
Short name T810
Test name
Test status
Simulation time 166524782 ps
CPU time 3.28 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:26:38 PM PDT 24
Peak memory 206960 kb
Host smart-a4911bde-d956-493b-a453-f8ca5ea8a05f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512704949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.512704949
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.505247861
Short name T683
Test name
Test status
Simulation time 39742242 ps
CPU time 1.92 seconds
Started Jun 09 02:26:33 PM PDT 24
Finished Jun 09 02:26:35 PM PDT 24
Peak memory 215728 kb
Host smart-45439320-d5ee-4c78-ac80-9617e4a4e0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505247861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.505247861
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1046080250
Short name T765
Test name
Test status
Simulation time 162022721 ps
CPU time 3.67 seconds
Started Jun 09 02:26:49 PM PDT 24
Finished Jun 09 02:26:53 PM PDT 24
Peak memory 208668 kb
Host smart-ebc26b2f-a4b4-48e2-bdb4-aa8174818db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046080250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1046080250
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3046795958
Short name T669
Test name
Test status
Simulation time 180457522 ps
CPU time 3.02 seconds
Started Jun 09 02:26:32 PM PDT 24
Finished Jun 09 02:26:36 PM PDT 24
Peak memory 208616 kb
Host smart-63a71573-11d3-4b78-90e5-056641986809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046795958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3046795958
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2220444931
Short name T26
Test name
Test status
Simulation time 54653703 ps
CPU time 3.19 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:26:38 PM PDT 24
Peak memory 207396 kb
Host smart-213d2b48-6b69-4e36-abd1-0350431d6ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220444931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2220444931
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2790965708
Short name T740
Test name
Test status
Simulation time 529294503 ps
CPU time 3.05 seconds
Started Jun 09 02:26:40 PM PDT 24
Finished Jun 09 02:26:43 PM PDT 24
Peak memory 210040 kb
Host smart-c9e9bcf1-3edd-4b6b-8f24-09e41de000df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790965708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2790965708
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1405163675
Short name T678
Test name
Test status
Simulation time 19659137 ps
CPU time 1 seconds
Started Jun 09 02:28:26 PM PDT 24
Finished Jun 09 02:28:32 PM PDT 24
Peak memory 206228 kb
Host smart-47245fee-538c-4e7b-a6b5-50148f081d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405163675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1405163675
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.580683562
Short name T304
Test name
Test status
Simulation time 174334105 ps
CPU time 3.95 seconds
Started Jun 09 02:28:17 PM PDT 24
Finished Jun 09 02:28:21 PM PDT 24
Peak memory 215460 kb
Host smart-be231ed6-f2c4-4fee-844a-34e18c893875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580683562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.580683562
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2664398333
Short name T25
Test name
Test status
Simulation time 416853586 ps
CPU time 2.9 seconds
Started Jun 09 02:28:30 PM PDT 24
Finished Jun 09 02:28:33 PM PDT 24
Peak memory 208276 kb
Host smart-52fc7cdc-1688-490a-a328-1c8b47626509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664398333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2664398333
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.215150347
Short name T225
Test name
Test status
Simulation time 46819960 ps
CPU time 2.3 seconds
Started Jun 09 02:28:22 PM PDT 24
Finished Jun 09 02:28:29 PM PDT 24
Peak memory 209352 kb
Host smart-7938b296-66d4-4674-85ed-5ae67d8cb0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215150347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.215150347
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3681643769
Short name T270
Test name
Test status
Simulation time 37882562 ps
CPU time 2.25 seconds
Started Jun 09 02:28:30 PM PDT 24
Finished Jun 09 02:28:32 PM PDT 24
Peak memory 214360 kb
Host smart-e5480399-751f-4a64-b6b3-adb8baa7e322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681643769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3681643769
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3256943557
Short name T253
Test name
Test status
Simulation time 1625849539 ps
CPU time 6.58 seconds
Started Jun 09 02:28:19 PM PDT 24
Finished Jun 09 02:28:25 PM PDT 24
Peak memory 214600 kb
Host smart-316e29ac-a3e2-470e-975b-c13464dcbcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256943557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3256943557
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2019554132
Short name T216
Test name
Test status
Simulation time 281438136 ps
CPU time 4.26 seconds
Started Jun 09 02:28:24 PM PDT 24
Finished Jun 09 02:28:28 PM PDT 24
Peak memory 220360 kb
Host smart-3934be16-6ccc-470f-a1b2-69b2c61e9f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019554132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2019554132
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2791903277
Short name T594
Test name
Test status
Simulation time 190320060 ps
CPU time 7.94 seconds
Started Jun 09 02:28:31 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 214284 kb
Host smart-742aaaea-d0d9-426e-8d3f-4d4333fc45cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791903277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2791903277
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2603122947
Short name T229
Test name
Test status
Simulation time 115469186 ps
CPU time 3.19 seconds
Started Jun 09 02:28:34 PM PDT 24
Finished Jun 09 02:28:38 PM PDT 24
Peak memory 208376 kb
Host smart-2fc2e498-d24e-4256-9838-75248031aa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603122947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2603122947
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2449251040
Short name T247
Test name
Test status
Simulation time 2910241790 ps
CPU time 28.9 seconds
Started Jun 09 02:28:32 PM PDT 24
Finished Jun 09 02:29:01 PM PDT 24
Peak memory 208432 kb
Host smart-041c851a-66d0-4df3-bbbe-57222ea6cfc6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449251040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2449251040
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3538877450
Short name T336
Test name
Test status
Simulation time 198847436 ps
CPU time 7.24 seconds
Started Jun 09 02:28:31 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 208932 kb
Host smart-e8cd3c35-1200-487d-9e0c-094ac67af792
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538877450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3538877450
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1220750370
Short name T881
Test name
Test status
Simulation time 204077924 ps
CPU time 2.82 seconds
Started Jun 09 02:28:36 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 208636 kb
Host smart-32526711-8165-4e92-89b1-acf93dfd06cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220750370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1220750370
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3511548942
Short name T201
Test name
Test status
Simulation time 189725003 ps
CPU time 6.19 seconds
Started Jun 09 02:28:20 PM PDT 24
Finished Jun 09 02:28:26 PM PDT 24
Peak memory 216180 kb
Host smart-fcab1da7-e70a-4d64-b992-00f7197199a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511548942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3511548942
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3484599209
Short name T772
Test name
Test status
Simulation time 2890180598 ps
CPU time 18.01 seconds
Started Jun 09 02:28:27 PM PDT 24
Finished Jun 09 02:28:45 PM PDT 24
Peak memory 208780 kb
Host smart-f34e2d15-be60-4eda-947f-8c97d554f750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484599209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3484599209
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1038602993
Short name T118
Test name
Test status
Simulation time 694619198 ps
CPU time 8.13 seconds
Started Jun 09 02:28:21 PM PDT 24
Finished Jun 09 02:28:29 PM PDT 24
Peak memory 219972 kb
Host smart-cbabf1fa-224f-4b51-9e2a-fb08281a11e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038602993 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1038602993
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.4139647857
Short name T335
Test name
Test status
Simulation time 1493963938 ps
CPU time 6.02 seconds
Started Jun 09 02:28:19 PM PDT 24
Finished Jun 09 02:28:26 PM PDT 24
Peak memory 210296 kb
Host smart-22d624f8-6ee6-4e35-959b-a3f13c78c20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139647857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.4139647857
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.445892653
Short name T905
Test name
Test status
Simulation time 181993362 ps
CPU time 2.22 seconds
Started Jun 09 02:28:20 PM PDT 24
Finished Jun 09 02:28:22 PM PDT 24
Peak memory 209992 kb
Host smart-5a4bc42f-d091-4159-9e5c-318a7690c975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445892653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.445892653
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.4222624692
Short name T650
Test name
Test status
Simulation time 9703486 ps
CPU time 0.75 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:00 PM PDT 24
Peak memory 205972 kb
Host smart-5d0ff5cf-5c1d-4c1f-a7dd-bc354ef65bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222624692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4222624692
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1545301372
Short name T275
Test name
Test status
Simulation time 413316266 ps
CPU time 20.89 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:29:01 PM PDT 24
Peak memory 214280 kb
Host smart-9647eee1-4287-4b38-a660-9f36dd732291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545301372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1545301372
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1350148453
Short name T656
Test name
Test status
Simulation time 154298654 ps
CPU time 4.39 seconds
Started Jun 09 02:28:20 PM PDT 24
Finished Jun 09 02:28:25 PM PDT 24
Peak memory 209236 kb
Host smart-4c7979de-ae4c-4525-8a6d-e2b33b7c879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350148453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1350148453
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.126692996
Short name T78
Test name
Test status
Simulation time 138563910 ps
CPU time 3.19 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 218516 kb
Host smart-a86fd024-abab-4bf9-b432-118755a854f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126692996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.126692996
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1694762610
Short name T472
Test name
Test status
Simulation time 149539819 ps
CPU time 6.25 seconds
Started Jun 09 02:28:36 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 214364 kb
Host smart-a5432866-2292-4bab-87cc-f214f22e0d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694762610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1694762610
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3314209741
Short name T836
Test name
Test status
Simulation time 156813709 ps
CPU time 3.67 seconds
Started Jun 09 02:28:29 PM PDT 24
Finished Jun 09 02:28:33 PM PDT 24
Peak memory 222452 kb
Host smart-e4e8ec4d-30fd-49a6-b39b-083ea5f24e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314209741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3314209741
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1637902314
Short name T856
Test name
Test status
Simulation time 150274125 ps
CPU time 4.49 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 215768 kb
Host smart-72616a5e-a305-4bf4-b8ec-10788ea68cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637902314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1637902314
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.752049007
Short name T134
Test name
Test status
Simulation time 822149105 ps
CPU time 6.69 seconds
Started Jun 09 02:28:34 PM PDT 24
Finished Jun 09 02:28:41 PM PDT 24
Peak memory 214300 kb
Host smart-55f6c5f0-bf8f-444a-bfc8-ce7946798a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752049007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.752049007
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3882959888
Short name T434
Test name
Test status
Simulation time 275083441 ps
CPU time 3.38 seconds
Started Jun 09 02:28:22 PM PDT 24
Finished Jun 09 02:28:26 PM PDT 24
Peak memory 208788 kb
Host smart-bb28fab2-7b5e-4b96-b2f8-67f65284d661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882959888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3882959888
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1840666383
Short name T477
Test name
Test status
Simulation time 6777352986 ps
CPU time 18.19 seconds
Started Jun 09 02:28:18 PM PDT 24
Finished Jun 09 02:28:36 PM PDT 24
Peak memory 208336 kb
Host smart-d5d7cd2a-6070-46cb-a62e-883b9a99aadc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840666383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1840666383
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1264079480
Short name T761
Test name
Test status
Simulation time 195468511 ps
CPU time 3.04 seconds
Started Jun 09 02:28:36 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 206976 kb
Host smart-294bf970-518e-4651-9446-ce2152c09f63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264079480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1264079480
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.349200610
Short name T445
Test name
Test status
Simulation time 37817010 ps
CPU time 2.41 seconds
Started Jun 09 02:28:20 PM PDT 24
Finished Jun 09 02:28:33 PM PDT 24
Peak memory 208736 kb
Host smart-d4fb2346-221c-4547-b0ad-ce075b1e36bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349200610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.349200610
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.348889149
Short name T204
Test name
Test status
Simulation time 206433723 ps
CPU time 2.36 seconds
Started Jun 09 02:28:20 PM PDT 24
Finished Jun 09 02:28:22 PM PDT 24
Peak memory 210004 kb
Host smart-f166510a-a95f-41a5-b979-252a4e2dfbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348889149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.348889149
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4163991179
Short name T497
Test name
Test status
Simulation time 9496548196 ps
CPU time 15.17 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:28:56 PM PDT 24
Peak memory 208196 kb
Host smart-3cfd5397-78ca-4b11-8517-006235b4f722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163991179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4163991179
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1475553408
Short name T194
Test name
Test status
Simulation time 1149712342 ps
CPU time 38.78 seconds
Started Jun 09 02:28:52 PM PDT 24
Finished Jun 09 02:29:31 PM PDT 24
Peak memory 222484 kb
Host smart-7ed991a0-ddb9-41f3-903b-5c1448a0a5db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475553408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1475553408
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2024213636
Short name T192
Test name
Test status
Simulation time 503049653 ps
CPU time 8.31 seconds
Started Jun 09 02:28:21 PM PDT 24
Finished Jun 09 02:28:30 PM PDT 24
Peak memory 222632 kb
Host smart-f68b88b6-abb5-4092-be30-125c540cdf53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024213636 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2024213636
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2466295420
Short name T612
Test name
Test status
Simulation time 539482403 ps
CPU time 3.98 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 209488 kb
Host smart-b1ebe963-c192-4e00-a734-1898c58b374e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466295420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2466295420
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.815381569
Short name T169
Test name
Test status
Simulation time 357029196 ps
CPU time 3.1 seconds
Started Jun 09 02:28:23 PM PDT 24
Finished Jun 09 02:28:27 PM PDT 24
Peak memory 210452 kb
Host smart-b93eb784-8fd9-40cb-b25b-1034d09f94e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815381569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.815381569
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2078624080
Short name T111
Test name
Test status
Simulation time 41164489 ps
CPU time 0.74 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:50 PM PDT 24
Peak memory 205940 kb
Host smart-9cf81d2e-82c2-42cf-8dfd-3a521dbf9a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078624080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2078624080
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1866335960
Short name T603
Test name
Test status
Simulation time 66097518 ps
CPU time 3.24 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 214572 kb
Host smart-710cb4f9-981f-4cf5-bfa9-097d9c8d37a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866335960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1866335960
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2635770042
Short name T266
Test name
Test status
Simulation time 384140941 ps
CPU time 1.75 seconds
Started Jun 09 02:28:49 PM PDT 24
Finished Jun 09 02:28:51 PM PDT 24
Peak memory 209244 kb
Host smart-513025f6-48db-4bf4-825f-efe4c5b2068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635770042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2635770042
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2864673667
Short name T820
Test name
Test status
Simulation time 100744292 ps
CPU time 1.85 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:28:37 PM PDT 24
Peak memory 214348 kb
Host smart-d5c51d51-07ca-4a22-ac47-cd26b54deab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864673667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2864673667
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.385304969
Short name T725
Test name
Test status
Simulation time 175907005 ps
CPU time 4.23 seconds
Started Jun 09 02:28:29 PM PDT 24
Finished Jun 09 02:28:33 PM PDT 24
Peak memory 214244 kb
Host smart-0ca77d8c-d650-44a0-b498-78421326d3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385304969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.385304969
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3061939729
Short name T56
Test name
Test status
Simulation time 170113884 ps
CPU time 4 seconds
Started Jun 09 02:28:21 PM PDT 24
Finished Jun 09 02:28:26 PM PDT 24
Peak memory 220360 kb
Host smart-7bbdea1e-f5a1-4047-8035-dbc754d13928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061939729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3061939729
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2484991138
Short name T574
Test name
Test status
Simulation time 326024761 ps
CPU time 4.14 seconds
Started Jun 09 02:28:45 PM PDT 24
Finished Jun 09 02:28:50 PM PDT 24
Peak memory 207968 kb
Host smart-c3921a82-96f7-4f7e-b635-bf102062d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484991138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2484991138
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3532307688
Short name T592
Test name
Test status
Simulation time 264241016 ps
CPU time 4.72 seconds
Started Jun 09 02:28:33 PM PDT 24
Finished Jun 09 02:28:38 PM PDT 24
Peak memory 206988 kb
Host smart-d840d1d8-1b39-49c7-9a22-b7126dd199a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532307688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3532307688
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.45342692
Short name T505
Test name
Test status
Simulation time 222500018 ps
CPU time 6.78 seconds
Started Jun 09 02:28:29 PM PDT 24
Finished Jun 09 02:28:36 PM PDT 24
Peak memory 209032 kb
Host smart-6265a47c-1279-4856-9cb9-d4e2799c99fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45342692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.45342692
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1666464571
Short name T475
Test name
Test status
Simulation time 65991135 ps
CPU time 3.32 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:41 PM PDT 24
Peak memory 208900 kb
Host smart-b65701e3-7dd2-40b3-b255-551ea2d6e799
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666464571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1666464571
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3808848080
Short name T694
Test name
Test status
Simulation time 89976586 ps
CPU time 3.02 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 208516 kb
Host smart-8e54ca61-db14-45be-8998-59ac50c2e502
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808848080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3808848080
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4247921337
Short name T507
Test name
Test status
Simulation time 74088495 ps
CPU time 1.55 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:41 PM PDT 24
Peak memory 208112 kb
Host smart-2c3366a1-4615-42d5-a10b-95aeca0e502a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247921337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4247921337
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3389912001
Short name T464
Test name
Test status
Simulation time 684800799 ps
CPU time 6.35 seconds
Started Jun 09 02:28:24 PM PDT 24
Finished Jun 09 02:28:30 PM PDT 24
Peak memory 207060 kb
Host smart-705ca2ba-1122-4ba0-a6da-46722c7d45d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389912001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3389912001
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1196725223
Short name T344
Test name
Test status
Simulation time 1137262845 ps
CPU time 15.7 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:53 PM PDT 24
Peak memory 222428 kb
Host smart-ba5014d5-8cfe-47de-99a7-4488c2da2223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196725223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1196725223
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.51061831
Short name T133
Test name
Test status
Simulation time 1008971909 ps
CPU time 11.7 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:52 PM PDT 24
Peak memory 219344 kb
Host smart-a4b385dd-9f97-4f98-9359-fca00a2af2d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51061831 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.51061831
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3857726853
Short name T904
Test name
Test status
Simulation time 64292630 ps
CPU time 4.19 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 214340 kb
Host smart-9fcfeb5d-b177-450b-b5a1-818ff9081834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857726853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3857726853
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1556071249
Short name T387
Test name
Test status
Simulation time 39900644 ps
CPU time 2.18 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 209536 kb
Host smart-0a23b5a1-3bbb-4750-aaeb-4d0833a9ec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556071249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1556071249
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2030855608
Short name T563
Test name
Test status
Simulation time 40222794 ps
CPU time 0.77 seconds
Started Jun 09 02:28:34 PM PDT 24
Finished Jun 09 02:28:35 PM PDT 24
Peak memory 205972 kb
Host smart-21740c2c-a37a-4457-963d-6eba2f8a5942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030855608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2030855608
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.747332908
Short name T209
Test name
Test status
Simulation time 59526915 ps
CPU time 2.4 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 220220 kb
Host smart-c437d40c-9470-4f72-a69b-f8e21ab02c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747332908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.747332908
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.172038463
Short name T537
Test name
Test status
Simulation time 83119335 ps
CPU time 3.42 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 207808 kb
Host smart-9dbc22e6-ffc4-4e85-99af-fb1cc7ad3e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172038463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.172038463
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3778399960
Short name T773
Test name
Test status
Simulation time 320047026 ps
CPU time 5.18 seconds
Started Jun 09 02:28:34 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 214368 kb
Host smart-3314b0eb-14ca-45a8-92e1-53296f48b9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778399960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3778399960
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.4140094699
Short name T310
Test name
Test status
Simulation time 457178127 ps
CPU time 3.42 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 214272 kb
Host smart-42b08799-6ebb-4abd-94ec-b04925fa26da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140094699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.4140094699
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3150430504
Short name T155
Test name
Test status
Simulation time 105171597 ps
CPU time 4.94 seconds
Started Jun 09 02:28:41 PM PDT 24
Finished Jun 09 02:28:46 PM PDT 24
Peak memory 220080 kb
Host smart-5296cd8b-3cf4-4e8e-ab7e-202d6b770ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150430504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3150430504
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2466457632
Short name T560
Test name
Test status
Simulation time 9962450599 ps
CPU time 75.42 seconds
Started Jun 09 02:28:33 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 218604 kb
Host smart-112d6d56-71a1-430f-b303-e0cba4217956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466457632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2466457632
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1642890293
Short name T585
Test name
Test status
Simulation time 541858274 ps
CPU time 5.06 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 208632 kb
Host smart-efa113fe-9305-4ce2-8e22-f7c664d963ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642890293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1642890293
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4121691076
Short name T769
Test name
Test status
Simulation time 514655229 ps
CPU time 2.67 seconds
Started Jun 09 02:28:42 PM PDT 24
Finished Jun 09 02:28:46 PM PDT 24
Peak memory 207448 kb
Host smart-5dd0f8c7-e978-4507-8451-a8e86dfc871d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121691076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4121691076
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2238899057
Short name T145
Test name
Test status
Simulation time 24526365 ps
CPU time 1.99 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 208844 kb
Host smart-4be5e3bc-c02e-4316-afa3-d70cba346a3b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238899057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2238899057
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1340251714
Short name T807
Test name
Test status
Simulation time 86131982 ps
CPU time 2.99 seconds
Started Jun 09 02:28:36 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 207988 kb
Host smart-05088fda-6930-4136-a3e9-ae035dab6ca9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340251714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1340251714
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1102700841
Short name T876
Test name
Test status
Simulation time 73018557 ps
CPU time 3.57 seconds
Started Jun 09 02:28:44 PM PDT 24
Finished Jun 09 02:28:48 PM PDT 24
Peak memory 209644 kb
Host smart-e2ed20ea-a84c-4b9c-aced-0889f435c383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102700841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1102700841
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.416724734
Short name T699
Test name
Test status
Simulation time 3898121815 ps
CPU time 9.03 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:49 PM PDT 24
Peak memory 206908 kb
Host smart-e60111bb-9eff-4881-9c62-86adb09c499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416724734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.416724734
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2338138712
Short name T131
Test name
Test status
Simulation time 277339871 ps
CPU time 12.72 seconds
Started Jun 09 02:28:36 PM PDT 24
Finished Jun 09 02:28:49 PM PDT 24
Peak memory 222928 kb
Host smart-b7a3f433-3ad5-4cdd-b9de-b633ead44c1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338138712 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2338138712
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2197088213
Short name T303
Test name
Test status
Simulation time 176918702 ps
CPU time 4.07 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 209220 kb
Host smart-b261d82f-304c-40e0-948e-0c813156d8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197088213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2197088213
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2442563825
Short name T405
Test name
Test status
Simulation time 161102446 ps
CPU time 5.76 seconds
Started Jun 09 02:28:24 PM PDT 24
Finished Jun 09 02:28:30 PM PDT 24
Peak memory 210412 kb
Host smart-49014ecc-f6f4-4ccc-8bba-526adcf7d8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442563825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2442563825
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2910657129
Short name T513
Test name
Test status
Simulation time 32188728 ps
CPU time 0.88 seconds
Started Jun 09 02:28:31 PM PDT 24
Finished Jun 09 02:28:32 PM PDT 24
Peak memory 205980 kb
Host smart-a3565ed4-9cf4-4b92-9963-b43eb936cd41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910657129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2910657129
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1527340768
Short name T425
Test name
Test status
Simulation time 166737133 ps
CPU time 3.34 seconds
Started Jun 09 02:28:41 PM PDT 24
Finished Jun 09 02:28:44 PM PDT 24
Peak memory 215092 kb
Host smart-7e1c84b6-0f1c-43c6-8dae-f793ae6f3b68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1527340768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1527340768
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3702611898
Short name T27
Test name
Test status
Simulation time 210888318 ps
CPU time 2.93 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 220404 kb
Host smart-ab2f7a72-1fb6-4ed8-ac1d-6baba7f89170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702611898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3702611898
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3442993926
Short name T586
Test name
Test status
Simulation time 290096158 ps
CPU time 3.92 seconds
Started Jun 09 02:28:47 PM PDT 24
Finished Jun 09 02:28:51 PM PDT 24
Peak memory 209044 kb
Host smart-1d2ff2bc-c913-4a42-956e-106d710ee782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442993926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3442993926
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.4177562423
Short name T317
Test name
Test status
Simulation time 514293171 ps
CPU time 4.93 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:28:40 PM PDT 24
Peak memory 214340 kb
Host smart-ef9af246-72b7-457c-83e8-531987b03d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177562423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.4177562423
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1961617032
Short name T693
Test name
Test status
Simulation time 213287096 ps
CPU time 4.58 seconds
Started Jun 09 02:28:41 PM PDT 24
Finished Jun 09 02:28:46 PM PDT 24
Peak memory 208692 kb
Host smart-33615b85-89f9-4528-a3a0-e5c1301e9962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961617032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1961617032
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2438827744
Short name T590
Test name
Test status
Simulation time 338758611 ps
CPU time 3.38 seconds
Started Jun 09 02:28:35 PM PDT 24
Finished Jun 09 02:28:39 PM PDT 24
Peak memory 208600 kb
Host smart-b98486f0-244e-49a6-95a1-62724cb8c573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438827744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2438827744
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2524974373
Short name T801
Test name
Test status
Simulation time 90971108 ps
CPU time 2.57 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 207076 kb
Host smart-2f7d26da-789d-430a-b91c-c62bb5fe5f5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524974373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2524974373
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.176076020
Short name T542
Test name
Test status
Simulation time 680817989 ps
CPU time 7.49 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:46 PM PDT 24
Peak memory 208648 kb
Host smart-e89e36ac-2448-41f5-b78e-5d638a0a228d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176076020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.176076020
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3756485378
Short name T516
Test name
Test status
Simulation time 399756352 ps
CPU time 5.57 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:45 PM PDT 24
Peak memory 208860 kb
Host smart-cec8ad0c-ebde-4f9f-96fb-39cf28f2a9a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756485378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3756485378
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.302892006
Short name T293
Test name
Test status
Simulation time 96815668 ps
CPU time 3.66 seconds
Started Jun 09 02:28:41 PM PDT 24
Finished Jun 09 02:28:45 PM PDT 24
Peak memory 214316 kb
Host smart-69d03b8e-5e3d-414c-b66d-a1127a507763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302892006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.302892006
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2090048467
Short name T462
Test name
Test status
Simulation time 94887586 ps
CPU time 3.52 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 208132 kb
Host smart-f9a607db-d6d2-40f9-a0ef-3d729e956f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090048467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2090048467
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3831493109
Short name T300
Test name
Test status
Simulation time 1888348785 ps
CPU time 35.07 seconds
Started Jun 09 02:28:44 PM PDT 24
Finished Jun 09 02:29:20 PM PDT 24
Peak memory 216972 kb
Host smart-35f0b839-2d1b-464a-bf49-b412935b3d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831493109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3831493109
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1939389526
Short name T343
Test name
Test status
Simulation time 986214546 ps
CPU time 20.51 seconds
Started Jun 09 02:28:43 PM PDT 24
Finished Jun 09 02:29:04 PM PDT 24
Peak memory 222644 kb
Host smart-a94b9c6b-9dff-473a-9f6f-63f74e971cda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939389526 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1939389526
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.594810499
Short name T554
Test name
Test status
Simulation time 126028418 ps
CPU time 5.56 seconds
Started Jun 09 02:28:37 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 210016 kb
Host smart-cd9b00e2-955c-4803-83a7-ad045370f641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594810499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.594810499
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.691187494
Short name T385
Test name
Test status
Simulation time 1589051195 ps
CPU time 8.35 seconds
Started Jun 09 02:28:44 PM PDT 24
Finished Jun 09 02:28:53 PM PDT 24
Peak memory 210496 kb
Host smart-0078a94f-d9d4-46a7-b89d-27497bb9cd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691187494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.691187494
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3636433813
Short name T440
Test name
Test status
Simulation time 59984909 ps
CPU time 0.97 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:49 PM PDT 24
Peak memory 206120 kb
Host smart-3dd5986e-03cb-4356-bbf4-dbc656937339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636433813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3636433813
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2067188736
Short name T106
Test name
Test status
Simulation time 30219815 ps
CPU time 2.52 seconds
Started Jun 09 02:28:49 PM PDT 24
Finished Jun 09 02:28:52 PM PDT 24
Peak memory 214320 kb
Host smart-d0e7c72e-8298-4bed-869e-e3866503ede5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067188736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2067188736
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3937118936
Short name T495
Test name
Test status
Simulation time 118542845 ps
CPU time 1.98 seconds
Started Jun 09 02:28:46 PM PDT 24
Finished Jun 09 02:28:48 PM PDT 24
Peak memory 209356 kb
Host smart-ec2984fb-8aa7-4d19-9fb9-4ed71c7c5eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937118936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3937118936
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1451284836
Short name T470
Test name
Test status
Simulation time 153009868 ps
CPU time 1.56 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 207224 kb
Host smart-5a4e555f-326f-4e1f-afaf-0e6fb1be785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451284836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1451284836
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2388203944
Short name T788
Test name
Test status
Simulation time 505752838 ps
CPU time 3.42 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 209332 kb
Host smart-12f3df0a-431a-40ca-822c-1c720492c870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388203944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2388203944
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2046545132
Short name T312
Test name
Test status
Simulation time 149076752 ps
CPU time 2.17 seconds
Started Jun 09 02:28:50 PM PDT 24
Finished Jun 09 02:28:52 PM PDT 24
Peak memory 214180 kb
Host smart-9874f1c1-82b6-4f8e-ac91-e5722ccacbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046545132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2046545132
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1946122204
Short name T602
Test name
Test status
Simulation time 284975458 ps
CPU time 3.78 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:44 PM PDT 24
Peak memory 209692 kb
Host smart-dd6bef06-3670-4cea-aae2-25b8734b5daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946122204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1946122204
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2394071858
Short name T675
Test name
Test status
Simulation time 2790133686 ps
CPU time 7.37 seconds
Started Jun 09 02:28:30 PM PDT 24
Finished Jun 09 02:28:38 PM PDT 24
Peak memory 214616 kb
Host smart-5b849a27-855f-4f48-ac9d-c776b89e9a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394071858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2394071858
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.754470352
Short name T713
Test name
Test status
Simulation time 171300855 ps
CPU time 4.81 seconds
Started Jun 09 02:28:42 PM PDT 24
Finished Jun 09 02:28:47 PM PDT 24
Peak memory 206836 kb
Host smart-9db2f9a0-4e0d-4cd4-bb29-9ec1afdada6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754470352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.754470352
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1386285583
Short name T272
Test name
Test status
Simulation time 89226354 ps
CPU time 2.16 seconds
Started Jun 09 02:28:50 PM PDT 24
Finished Jun 09 02:28:52 PM PDT 24
Peak memory 208512 kb
Host smart-ee51a9c6-1f90-4e5e-aaa6-9f115be0b242
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386285583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1386285583
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1542067083
Short name T460
Test name
Test status
Simulation time 63095466 ps
CPU time 2.64 seconds
Started Jun 09 02:28:43 PM PDT 24
Finished Jun 09 02:28:52 PM PDT 24
Peak memory 206944 kb
Host smart-fad2244d-38d3-4505-ac7a-cc0a6959c2a3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542067083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1542067083
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.914432590
Short name T83
Test name
Test status
Simulation time 116000861 ps
CPU time 4.82 seconds
Started Jun 09 02:28:41 PM PDT 24
Finished Jun 09 02:28:46 PM PDT 24
Peak memory 208992 kb
Host smart-4be901d3-5ff6-48c4-b184-638037cfae14
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914432590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.914432590
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1291392149
Short name T451
Test name
Test status
Simulation time 41439295 ps
CPU time 1.93 seconds
Started Jun 09 02:28:46 PM PDT 24
Finished Jun 09 02:28:48 PM PDT 24
Peak memory 214340 kb
Host smart-5488a193-4aea-4726-b453-6c68abfe38b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291392149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1291392149
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2990266681
Short name T441
Test name
Test status
Simulation time 106208014 ps
CPU time 1.98 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 206104 kb
Host smart-28489135-db34-476b-8993-27d556091049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990266681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2990266681
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.965453882
Short name T850
Test name
Test status
Simulation time 281394029 ps
CPU time 9.16 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:58 PM PDT 24
Peak memory 216932 kb
Host smart-5c31ea90-91ca-43d9-a903-b9b4d9d3b2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965453882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.965453882
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1789312974
Short name T190
Test name
Test status
Simulation time 6125998593 ps
CPU time 13.23 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:28:54 PM PDT 24
Peak memory 221328 kb
Host smart-3f816793-93ca-4a34-ba50-0ced6bcb8876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789312974 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1789312974
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2533105440
Short name T681
Test name
Test status
Simulation time 116431044 ps
CPU time 3.27 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 207716 kb
Host smart-415f4d1d-c9c7-4159-b754-0a1f235c6c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533105440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2533105440
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2000544772
Short name T35
Test name
Test status
Simulation time 199421799 ps
CPU time 2.56 seconds
Started Jun 09 02:28:42 PM PDT 24
Finished Jun 09 02:28:45 PM PDT 24
Peak memory 209880 kb
Host smart-a360c45d-99b0-4cad-8f63-3d29520b42ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000544772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2000544772
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1844946909
Short name T833
Test name
Test status
Simulation time 52810603 ps
CPU time 0.79 seconds
Started Jun 09 02:28:46 PM PDT 24
Finished Jun 09 02:28:47 PM PDT 24
Peak memory 205924 kb
Host smart-b35ab0a6-d0d5-4b18-8cdb-e9e36b3244a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844946909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1844946909
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1891692731
Short name T315
Test name
Test status
Simulation time 61149431 ps
CPU time 4 seconds
Started Jun 09 02:28:44 PM PDT 24
Finished Jun 09 02:28:49 PM PDT 24
Peak memory 215108 kb
Host smart-e6caa2a7-b357-4e7d-b6fc-a3c64f6b30c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1891692731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1891692731
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3201174382
Short name T800
Test name
Test status
Simulation time 218564422 ps
CPU time 2.68 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 208888 kb
Host smart-0cadfd7d-0a48-4cb9-b414-4d5d0afa93c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201174382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3201174382
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2717644640
Short name T320
Test name
Test status
Simulation time 7942240169 ps
CPU time 44.11 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:29:45 PM PDT 24
Peak memory 214440 kb
Host smart-4b2ca98f-8aca-4b4c-a111-ae081aa50f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717644640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2717644640
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.192281095
Short name T743
Test name
Test status
Simulation time 400788986 ps
CPU time 4.07 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 220320 kb
Host smart-7236ff4a-6c1e-49e0-8aa3-c9a7254c971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192281095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.192281095
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.815039458
Short name T710
Test name
Test status
Simulation time 4670919511 ps
CPU time 31.92 seconds
Started Jun 09 02:28:49 PM PDT 24
Finished Jun 09 02:29:21 PM PDT 24
Peak memory 208604 kb
Host smart-1a051687-a186-423f-8a9c-e2cf46e10bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815039458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.815039458
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.177852220
Short name T739
Test name
Test status
Simulation time 120454844 ps
CPU time 2.4 seconds
Started Jun 09 02:28:51 PM PDT 24
Finished Jun 09 02:28:54 PM PDT 24
Peak memory 208368 kb
Host smart-5e93ddb0-eb07-4d36-8a10-7a0ae815ba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177852220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.177852220
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.613763009
Short name T399
Test name
Test status
Simulation time 327432651 ps
CPU time 4.58 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:53 PM PDT 24
Peak memory 207988 kb
Host smart-bb446e2b-5b6b-4ca6-b4e7-706064715b99
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613763009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.613763009
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1591742586
Short name T559
Test name
Test status
Simulation time 143224968 ps
CPU time 3.62 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:53 PM PDT 24
Peak memory 207964 kb
Host smart-20fcd299-3199-417b-a52a-1a138916c24d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591742586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1591742586
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.284611243
Short name T546
Test name
Test status
Simulation time 575440897 ps
CPU time 11.49 seconds
Started Jun 09 02:28:42 PM PDT 24
Finished Jun 09 02:28:55 PM PDT 24
Peak memory 208100 kb
Host smart-51910eb7-1254-4f13-897a-ef15d7c94079
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284611243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.284611243
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.605045801
Short name T802
Test name
Test status
Simulation time 28221589 ps
CPU time 2.04 seconds
Started Jun 09 02:28:44 PM PDT 24
Finished Jun 09 02:28:47 PM PDT 24
Peak memory 215824 kb
Host smart-403c8351-301d-400d-b93a-f071216b6cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605045801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.605045801
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.503452987
Short name T534
Test name
Test status
Simulation time 1499886914 ps
CPU time 27.45 seconds
Started Jun 09 02:28:51 PM PDT 24
Finished Jun 09 02:29:19 PM PDT 24
Peak memory 208444 kb
Host smart-139dca5a-8396-459d-99ca-254262deff39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503452987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.503452987
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2271843993
Short name T210
Test name
Test status
Simulation time 11945378253 ps
CPU time 70.23 seconds
Started Jun 09 02:28:49 PM PDT 24
Finished Jun 09 02:29:59 PM PDT 24
Peak memory 221064 kb
Host smart-feae86a7-ea12-4095-a742-16e7b1ac0005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271843993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2271843993
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.617979409
Short name T784
Test name
Test status
Simulation time 1160084204 ps
CPU time 7.89 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:48 PM PDT 24
Peak memory 208716 kb
Host smart-930c49bd-cd89-4d97-b0fa-8b62d8280b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617979409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.617979409
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3027797946
Short name T533
Test name
Test status
Simulation time 300594427 ps
CPU time 3.37 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 210620 kb
Host smart-bb3c2c60-3996-4139-9b85-0e32119ff801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027797946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3027797946
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.4146237309
Short name T429
Test name
Test status
Simulation time 10747304 ps
CPU time 0.72 seconds
Started Jun 09 02:28:41 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 205944 kb
Host smart-4b78dbd9-206b-4e4a-8214-35af87d63b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146237309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4146237309
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1110531769
Short name T442
Test name
Test status
Simulation time 90490587 ps
CPU time 3.78 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 222684 kb
Host smart-9cfb158d-48ec-4a2f-807d-c267243dc741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110531769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1110531769
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3809928649
Short name T894
Test name
Test status
Simulation time 1185945583 ps
CPU time 6.6 seconds
Started Jun 09 02:28:47 PM PDT 24
Finished Jun 09 02:28:54 PM PDT 24
Peak memory 214392 kb
Host smart-a176abf9-9b7a-47b9-b852-37398c871c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809928649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3809928649
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1894645447
Short name T515
Test name
Test status
Simulation time 27400126 ps
CPU time 1.74 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:50 PM PDT 24
Peak memory 214388 kb
Host smart-40eaa158-5202-4258-9b63-4c2b0a6b7c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894645447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1894645447
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3462224300
Short name T845
Test name
Test status
Simulation time 316581858 ps
CPU time 3.2 seconds
Started Jun 09 02:28:55 PM PDT 24
Finished Jun 09 02:28:58 PM PDT 24
Peak memory 211436 kb
Host smart-454d752f-ce42-423a-9856-d6b0cf92990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462224300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3462224300
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.154066094
Short name T892
Test name
Test status
Simulation time 197166164 ps
CPU time 5.69 seconds
Started Jun 09 02:28:43 PM PDT 24
Finished Jun 09 02:28:49 PM PDT 24
Peak memory 215792 kb
Host smart-ddad8399-0fd5-43be-8a3b-ae808ab7cd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154066094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.154066094
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1857584635
Short name T236
Test name
Test status
Simulation time 567944957 ps
CPU time 14.97 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:53 PM PDT 24
Peak memory 209856 kb
Host smart-2a9c12b6-3d6d-42e5-b0ae-ccfc2b316d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857584635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1857584635
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3885433308
Short name T731
Test name
Test status
Simulation time 188086238 ps
CPU time 5.48 seconds
Started Jun 09 02:28:42 PM PDT 24
Finished Jun 09 02:28:48 PM PDT 24
Peak memory 208648 kb
Host smart-cab3230b-8c25-478d-acca-0e6f7a24d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885433308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3885433308
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.999739364
Short name T853
Test name
Test status
Simulation time 318201143 ps
CPU time 4.46 seconds
Started Jun 09 02:28:49 PM PDT 24
Finished Jun 09 02:28:54 PM PDT 24
Peak memory 208484 kb
Host smart-c47e50a5-6e0c-4b6b-9835-35c19d913e57
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999739364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.999739364
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.4123330482
Short name T690
Test name
Test status
Simulation time 469111285 ps
CPU time 5.6 seconds
Started Jun 09 02:28:43 PM PDT 24
Finished Jun 09 02:28:49 PM PDT 24
Peak memory 208992 kb
Host smart-b5d82a31-86b7-4b79-a31d-b4732d6b627a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123330482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.4123330482
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1064110751
Short name T446
Test name
Test status
Simulation time 206946067 ps
CPU time 3.01 seconds
Started Jun 09 02:28:51 PM PDT 24
Finished Jun 09 02:28:55 PM PDT 24
Peak memory 206848 kb
Host smart-4c2efe12-8921-41b6-9372-7060289cdd22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064110751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1064110751
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.576787229
Short name T735
Test name
Test status
Simulation time 95904039 ps
CPU time 1.97 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 208200 kb
Host smart-e5b2b9ed-bbd9-4799-8981-ca9ed75b6972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576787229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.576787229
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3147323205
Short name T503
Test name
Test status
Simulation time 617468737 ps
CPU time 12.25 seconds
Started Jun 09 02:28:41 PM PDT 24
Finished Jun 09 02:28:54 PM PDT 24
Peak memory 208036 kb
Host smart-c9d4137d-96fe-4782-b9a4-553f3a4d7982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147323205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3147323205
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3053229322
Short name T745
Test name
Test status
Simulation time 1846033224 ps
CPU time 67.14 seconds
Started Jun 09 02:28:46 PM PDT 24
Finished Jun 09 02:29:54 PM PDT 24
Peak memory 217328 kb
Host smart-d19b7a51-be6d-4f89-af5c-62527d604383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053229322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3053229322
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3578090509
Short name T638
Test name
Test status
Simulation time 500782606 ps
CPU time 18.71 seconds
Started Jun 09 02:28:44 PM PDT 24
Finished Jun 09 02:29:03 PM PDT 24
Peak memory 222612 kb
Host smart-499c6933-8a38-4c37-967f-f6f9e6ee46f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578090509 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3578090509
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2221880742
Short name T902
Test name
Test status
Simulation time 237254835 ps
CPU time 5.34 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:28:46 PM PDT 24
Peak memory 209920 kb
Host smart-eedac0f4-2a4a-4715-bf3d-019894173cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221880742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2221880742
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2891137031
Short name T883
Test name
Test status
Simulation time 975356738 ps
CPU time 8.57 seconds
Started Jun 09 02:28:52 PM PDT 24
Finished Jun 09 02:29:01 PM PDT 24
Peak memory 211032 kb
Host smart-8a42aaaa-ca68-4b56-95aa-c532d3b3c429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891137031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2891137031
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3029018703
Short name T577
Test name
Test status
Simulation time 17187632 ps
CPU time 0.72 seconds
Started Jun 09 02:28:51 PM PDT 24
Finished Jun 09 02:28:53 PM PDT 24
Peak memory 205924 kb
Host smart-b01a2619-d148-4243-ba80-1700cc641d1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029018703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3029018703
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1182819938
Short name T555
Test name
Test status
Simulation time 36141767 ps
CPU time 2.08 seconds
Started Jun 09 02:29:00 PM PDT 24
Finished Jun 09 02:29:02 PM PDT 24
Peak memory 207816 kb
Host smart-d33ae518-7058-42f9-9b27-37c804595e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182819938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1182819938
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1485077035
Short name T489
Test name
Test status
Simulation time 39379138 ps
CPU time 1.62 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:51 PM PDT 24
Peak memory 214344 kb
Host smart-5353c827-ecfa-42ed-9bb0-fcf91a5b1a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485077035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1485077035
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1555161975
Short name T287
Test name
Test status
Simulation time 48231419 ps
CPU time 1.98 seconds
Started Jun 09 02:28:52 PM PDT 24
Finished Jun 09 02:28:54 PM PDT 24
Peak memory 214344 kb
Host smart-26e78fcd-83a9-4e0a-9396-02d137dface0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555161975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1555161975
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.157540890
Short name T353
Test name
Test status
Simulation time 68070614 ps
CPU time 2.22 seconds
Started Jun 09 02:28:50 PM PDT 24
Finished Jun 09 02:28:52 PM PDT 24
Peak memory 214240 kb
Host smart-d2797aa1-5840-4fbe-b27a-e680b77e1a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157540890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.157540890
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2202163620
Short name T341
Test name
Test status
Simulation time 251671133 ps
CPU time 3.47 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:52 PM PDT 24
Peak memory 214340 kb
Host smart-085f7ff9-b1f9-468c-897b-f7b927f1ec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202163620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2202163620
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1557474932
Short name T804
Test name
Test status
Simulation time 549721704 ps
CPU time 3.38 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:28:44 PM PDT 24
Peak memory 218312 kb
Host smart-20800a54-7b8c-40d3-b8d7-cefc6d1e0991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557474932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1557474932
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.950352699
Short name T598
Test name
Test status
Simulation time 104626025 ps
CPU time 2.77 seconds
Started Jun 09 02:28:52 PM PDT 24
Finished Jun 09 02:28:55 PM PDT 24
Peak memory 206944 kb
Host smart-889980eb-f1af-4beb-9851-3f6f7646afb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950352699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.950352699
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1237848732
Short name T87
Test name
Test status
Simulation time 134895109 ps
CPU time 2.46 seconds
Started Jun 09 02:28:45 PM PDT 24
Finished Jun 09 02:28:48 PM PDT 24
Peak memory 206964 kb
Host smart-4915d265-74d8-44cf-a553-f3f37237e260
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237848732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1237848732
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1245204649
Short name T911
Test name
Test status
Simulation time 235563797 ps
CPU time 3.33 seconds
Started Jun 09 02:28:50 PM PDT 24
Finished Jun 09 02:28:54 PM PDT 24
Peak memory 207032 kb
Host smart-ed9a7888-e468-4a6f-aa29-e988bb77d94f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245204649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1245204649
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1892620972
Short name T777
Test name
Test status
Simulation time 3007092069 ps
CPU time 20.72 seconds
Started Jun 09 02:28:51 PM PDT 24
Finished Jun 09 02:29:12 PM PDT 24
Peak memory 208280 kb
Host smart-9785bda1-f636-43ff-a1e2-3ff6c159c8c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892620972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1892620972
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3576864228
Short name T719
Test name
Test status
Simulation time 41570472 ps
CPU time 2.25 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 208132 kb
Host smart-31906bec-80ff-4785-baf3-ab337b97520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576864228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3576864228
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3348507421
Short name T697
Test name
Test status
Simulation time 184945678 ps
CPU time 2.75 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:28:43 PM PDT 24
Peak memory 207136 kb
Host smart-ed531a53-4d37-4c50-ab16-e95ddb16e790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348507421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3348507421
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2829893706
Short name T148
Test name
Test status
Simulation time 1233965495 ps
CPU time 20.41 seconds
Started Jun 09 02:28:52 PM PDT 24
Finished Jun 09 02:29:13 PM PDT 24
Peak memory 221368 kb
Host smart-b5fdfb71-8564-4fb4-b907-2a1225a64ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829893706 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2829893706
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.231983115
Short name T360
Test name
Test status
Simulation time 441148359 ps
CPU time 11.13 seconds
Started Jun 09 02:28:54 PM PDT 24
Finished Jun 09 02:29:06 PM PDT 24
Peak memory 209828 kb
Host smart-902d5d45-1d50-4953-a4f8-0234372ecac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231983115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.231983115
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.4150944796
Short name T34
Test name
Test status
Simulation time 66612262 ps
CPU time 2.82 seconds
Started Jun 09 02:28:48 PM PDT 24
Finished Jun 09 02:28:52 PM PDT 24
Peak memory 210208 kb
Host smart-9245126e-3f8c-4926-8b92-d6832c30c9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150944796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.4150944796
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.86082997
Short name T437
Test name
Test status
Simulation time 25219572 ps
CPU time 0.88 seconds
Started Jun 09 02:28:49 PM PDT 24
Finished Jun 09 02:28:50 PM PDT 24
Peak memory 205904 kb
Host smart-4e899ab1-71d1-4fa4-bc1c-04e9b400ea5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86082997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.86082997
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3157170861
Short name T359
Test name
Test status
Simulation time 1617317813 ps
CPU time 88.27 seconds
Started Jun 09 02:28:52 PM PDT 24
Finished Jun 09 02:30:21 PM PDT 24
Peak memory 215716 kb
Host smart-be810b3c-2980-4263-bc1e-0ff2fa396d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157170861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3157170861
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1824253729
Short name T471
Test name
Test status
Simulation time 248212474 ps
CPU time 3.82 seconds
Started Jun 09 02:28:45 PM PDT 24
Finished Jun 09 02:28:49 PM PDT 24
Peak memory 221112 kb
Host smart-51d6d04b-2901-44a0-b94a-38bf86a1a500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824253729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1824253729
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.4051070714
Short name T813
Test name
Test status
Simulation time 173303340 ps
CPU time 2.3 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 207724 kb
Host smart-05fea2c3-03f9-4717-8d6d-00ef8ad22446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051070714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.4051070714
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.547749234
Short name T762
Test name
Test status
Simulation time 619708828 ps
CPU time 14.64 seconds
Started Jun 09 02:28:59 PM PDT 24
Finished Jun 09 02:29:14 PM PDT 24
Peak memory 222476 kb
Host smart-407877b5-b983-45dd-8fe9-7858b22e3552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547749234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.547749234
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.688484496
Short name T217
Test name
Test status
Simulation time 120963163 ps
CPU time 2.86 seconds
Started Jun 09 02:28:38 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 210044 kb
Host smart-29813d43-3b59-45c1-b64c-5e1f0c7c7302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688484496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.688484496
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1584177472
Short name T223
Test name
Test status
Simulation time 188297435 ps
CPU time 6.59 seconds
Started Jun 09 02:28:51 PM PDT 24
Finished Jun 09 02:28:58 PM PDT 24
Peak memory 207752 kb
Host smart-d814aefb-582b-4416-b2f3-7cb9d29fb83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584177472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1584177472
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1182286759
Short name T296
Test name
Test status
Simulation time 47738057 ps
CPU time 2.09 seconds
Started Jun 09 02:28:54 PM PDT 24
Finished Jun 09 02:28:56 PM PDT 24
Peak memory 208768 kb
Host smart-a40717ea-9fae-4281-8046-f6870ae00567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182286759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1182286759
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.730419711
Short name T870
Test name
Test status
Simulation time 228890486 ps
CPU time 3.05 seconds
Started Jun 09 02:28:46 PM PDT 24
Finished Jun 09 02:28:50 PM PDT 24
Peak memory 208652 kb
Host smart-c5e49794-cb6e-4f55-982d-ae53600532c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730419711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.730419711
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1025594952
Short name T573
Test name
Test status
Simulation time 45156167 ps
CPU time 2.88 seconds
Started Jun 09 02:28:52 PM PDT 24
Finished Jun 09 02:28:56 PM PDT 24
Peak memory 208964 kb
Host smart-75599518-d14d-491a-b3e7-8033c543af30
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025594952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1025594952
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2162840238
Short name T779
Test name
Test status
Simulation time 116984592 ps
CPU time 4.06 seconds
Started Jun 09 02:28:39 PM PDT 24
Finished Jun 09 02:28:44 PM PDT 24
Peak memory 208404 kb
Host smart-5272dc97-5ccc-4db6-86a2-7e588d3b306f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162840238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2162840238
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2312506835
Short name T855
Test name
Test status
Simulation time 109884679 ps
CPU time 2.86 seconds
Started Jun 09 02:29:06 PM PDT 24
Finished Jun 09 02:29:09 PM PDT 24
Peak memory 207320 kb
Host smart-857d0520-d7d8-4f56-aa39-f9e3489bd6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312506835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2312506835
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2578051361
Short name T562
Test name
Test status
Simulation time 24121760 ps
CPU time 1.8 seconds
Started Jun 09 02:28:40 PM PDT 24
Finished Jun 09 02:28:42 PM PDT 24
Peak memory 207228 kb
Host smart-0fae38fb-e8f5-41c4-9b20-9d79803667ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578051361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2578051361
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3535565904
Short name T242
Test name
Test status
Simulation time 80363335 ps
CPU time 2.86 seconds
Started Jun 09 02:28:44 PM PDT 24
Finished Jun 09 02:28:47 PM PDT 24
Peak memory 208068 kb
Host smart-556fa9be-9282-470c-8a3a-1593b503835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535565904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3535565904
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4212168777
Short name T901
Test name
Test status
Simulation time 54743563 ps
CPU time 0.92 seconds
Started Jun 09 02:26:40 PM PDT 24
Finished Jun 09 02:26:41 PM PDT 24
Peak memory 206096 kb
Host smart-cc98dc8a-5773-4229-9f14-8d0135f4c360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212168777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4212168777
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.920830599
Short name T397
Test name
Test status
Simulation time 266797895 ps
CPU time 3.56 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:41 PM PDT 24
Peak memory 208904 kb
Host smart-cfb8c218-6fd4-4984-9fc7-e4795721571c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920830599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.920830599
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3567623593
Short name T346
Test name
Test status
Simulation time 644948247 ps
CPU time 3.88 seconds
Started Jun 09 02:26:42 PM PDT 24
Finished Jun 09 02:26:47 PM PDT 24
Peak memory 214352 kb
Host smart-4dc96bcf-8a68-42e5-8507-232a4efcab5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567623593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3567623593
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.413204202
Short name T319
Test name
Test status
Simulation time 66086075 ps
CPU time 3.35 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:40 PM PDT 24
Peak memory 222532 kb
Host smart-549dd02a-9668-4498-8200-dccab77475cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413204202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.413204202
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2877017325
Short name T183
Test name
Test status
Simulation time 94642394 ps
CPU time 2.19 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:39 PM PDT 24
Peak memory 215724 kb
Host smart-c4ebb324-e36e-472a-a576-70a795da1aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877017325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2877017325
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3962156471
Short name T200
Test name
Test status
Simulation time 504013512 ps
CPU time 5.63 seconds
Started Jun 09 02:26:39 PM PDT 24
Finished Jun 09 02:26:44 PM PDT 24
Peak memory 207408 kb
Host smart-0d46a39c-e075-4e1f-b48c-7a5eb806a013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962156471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3962156471
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3228263709
Short name T519
Test name
Test status
Simulation time 10141688799 ps
CPU time 54.55 seconds
Started Jun 09 02:26:40 PM PDT 24
Finished Jun 09 02:27:35 PM PDT 24
Peak memory 208700 kb
Host smart-d3ef4f9f-8864-42f6-b2c0-c9b7f1793972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228263709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3228263709
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3657415765
Short name T569
Test name
Test status
Simulation time 74033261 ps
CPU time 3.14 seconds
Started Jun 09 02:26:39 PM PDT 24
Finished Jun 09 02:26:43 PM PDT 24
Peak memory 206964 kb
Host smart-5b0d4c9d-7e24-445c-9c69-22aba9aff3e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657415765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3657415765
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2890502438
Short name T450
Test name
Test status
Simulation time 109867211 ps
CPU time 2.8 seconds
Started Jun 09 02:26:39 PM PDT 24
Finished Jun 09 02:26:42 PM PDT 24
Peak memory 206996 kb
Host smart-780e7afb-3e12-4e76-96ed-6cf9ecf3633b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890502438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2890502438
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1972198005
Short name T611
Test name
Test status
Simulation time 26626273 ps
CPU time 2.06 seconds
Started Jun 09 02:26:38 PM PDT 24
Finished Jun 09 02:26:40 PM PDT 24
Peak memory 208860 kb
Host smart-6ccac3da-9923-4583-866c-beee93b031ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972198005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1972198005
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.690107345
Short name T205
Test name
Test status
Simulation time 4092655726 ps
CPU time 26.78 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:27:04 PM PDT 24
Peak memory 210512 kb
Host smart-1c03984b-7765-4478-ab8a-8aad4dfc4ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690107345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.690107345
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.762081048
Short name T827
Test name
Test status
Simulation time 1281794034 ps
CPU time 4.06 seconds
Started Jun 09 02:26:34 PM PDT 24
Finished Jun 09 02:26:38 PM PDT 24
Peak memory 208372 kb
Host smart-17b0ab84-28cb-42b7-9233-8ee2c23b1c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762081048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.762081048
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3934811856
Short name T734
Test name
Test status
Simulation time 211621593 ps
CPU time 6.58 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:44 PM PDT 24
Peak memory 208504 kb
Host smart-aca18dde-04e6-4a9c-bb84-eaa101ac0b41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934811856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3934811856
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3203933747
Short name T873
Test name
Test status
Simulation time 153051421 ps
CPU time 4.91 seconds
Started Jun 09 02:26:36 PM PDT 24
Finished Jun 09 02:26:42 PM PDT 24
Peak memory 207216 kb
Host smart-d52cd512-4ee6-4a19-aaa1-ddd7f27cec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203933747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3203933747
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2907817596
Short name T99
Test name
Test status
Simulation time 273386025 ps
CPU time 2.83 seconds
Started Jun 09 02:26:36 PM PDT 24
Finished Jun 09 02:26:39 PM PDT 24
Peak memory 209880 kb
Host smart-f93cf4c8-98f0-4da6-9996-45f9f213d462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907817596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2907817596
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3346950619
Short name T583
Test name
Test status
Simulation time 36380684 ps
CPU time 0.86 seconds
Started Jun 09 02:26:43 PM PDT 24
Finished Jun 09 02:26:44 PM PDT 24
Peak memory 205972 kb
Host smart-c4358e8a-9bbc-42cf-9dc4-865bdb1aaeba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346950619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3346950619
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.248192989
Short name T280
Test name
Test status
Simulation time 245681950 ps
CPU time 4.33 seconds
Started Jun 09 02:26:43 PM PDT 24
Finished Jun 09 02:26:48 PM PDT 24
Peak memory 215648 kb
Host smart-ce55f32e-65e6-48ef-80b9-b7f0bc81c146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248192989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.248192989
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1057936123
Short name T756
Test name
Test status
Simulation time 48136699 ps
CPU time 2.42 seconds
Started Jun 09 02:26:45 PM PDT 24
Finished Jun 09 02:26:47 PM PDT 24
Peak memory 222684 kb
Host smart-195ccb1c-9676-4268-9882-f4fdf638ba93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057936123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1057936123
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2745178799
Short name T548
Test name
Test status
Simulation time 249450957 ps
CPU time 3.63 seconds
Started Jun 09 02:26:51 PM PDT 24
Finished Jun 09 02:26:55 PM PDT 24
Peak memory 209368 kb
Host smart-10e8cff8-fcdb-4ff3-9263-604cbaa4695c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745178799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2745178799
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2119694127
Short name T380
Test name
Test status
Simulation time 366436027 ps
CPU time 4.35 seconds
Started Jun 09 02:26:46 PM PDT 24
Finished Jun 09 02:26:51 PM PDT 24
Peak memory 209692 kb
Host smart-b2b33d9e-a643-4f31-9e46-f72f7e3018ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119694127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2119694127
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2741714980
Short name T644
Test name
Test status
Simulation time 78553190 ps
CPU time 3.92 seconds
Started Jun 09 02:26:49 PM PDT 24
Finished Jun 09 02:26:53 PM PDT 24
Peak memory 214332 kb
Host smart-b8eb73c6-9cd6-4986-8815-b642174a41bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741714980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2741714980
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.695458518
Short name T70
Test name
Test status
Simulation time 6084637358 ps
CPU time 32.49 seconds
Started Jun 09 02:26:49 PM PDT 24
Finished Jun 09 02:27:22 PM PDT 24
Peak memory 222640 kb
Host smart-826cf92a-9558-46b3-884e-5892480ad0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695458518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.695458518
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.44533959
Short name T196
Test name
Test status
Simulation time 113094788 ps
CPU time 5.15 seconds
Started Jun 09 02:26:54 PM PDT 24
Finished Jun 09 02:26:59 PM PDT 24
Peak memory 209784 kb
Host smart-c8d68f8c-43de-4bbb-8457-875085efa097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44533959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.44533959
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3943292703
Short name T635
Test name
Test status
Simulation time 175352326 ps
CPU time 4.09 seconds
Started Jun 09 02:26:39 PM PDT 24
Finished Jun 09 02:26:44 PM PDT 24
Peak memory 207988 kb
Host smart-23f7bdbf-2c31-46ce-8807-d8f59554b383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943292703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3943292703
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1395258900
Short name T677
Test name
Test status
Simulation time 337818106 ps
CPU time 3.06 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:40 PM PDT 24
Peak memory 206876 kb
Host smart-2c9374e7-1097-410e-8dd3-4f25d5afc34d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395258900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1395258900
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1101287577
Short name T619
Test name
Test status
Simulation time 176357528 ps
CPU time 2.95 seconds
Started Jun 09 02:26:40 PM PDT 24
Finished Jun 09 02:26:43 PM PDT 24
Peak memory 206724 kb
Host smart-822ff2b8-a4ef-4c4b-820e-24159c3eb009
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101287577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1101287577
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2036461853
Short name T509
Test name
Test status
Simulation time 169022902 ps
CPU time 3.92 seconds
Started Jun 09 02:26:39 PM PDT 24
Finished Jun 09 02:26:44 PM PDT 24
Peak memory 208872 kb
Host smart-72b603c4-b388-408a-a594-ad0bff28048e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036461853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2036461853
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1304510282
Short name T844
Test name
Test status
Simulation time 135435729 ps
CPU time 2.34 seconds
Started Jun 09 02:26:48 PM PDT 24
Finished Jun 09 02:26:51 PM PDT 24
Peak memory 208044 kb
Host smart-1226f498-95e1-4805-9966-aff0ec62fd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304510282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1304510282
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2152087614
Short name T502
Test name
Test status
Simulation time 326545554 ps
CPU time 3.2 seconds
Started Jun 09 02:26:37 PM PDT 24
Finished Jun 09 02:26:40 PM PDT 24
Peak memory 208644 kb
Host smart-1f9e87f7-c349-4cfb-858f-260e8ca00a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152087614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2152087614
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.660529181
Short name T357
Test name
Test status
Simulation time 167629014 ps
CPU time 4.05 seconds
Started Jun 09 02:26:47 PM PDT 24
Finished Jun 09 02:26:51 PM PDT 24
Peak memory 218368 kb
Host smart-4fd5d309-8857-4e05-b174-8ddec6b7e28d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660529181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.660529181
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.901924464
Short name T741
Test name
Test status
Simulation time 118581983 ps
CPU time 3.04 seconds
Started Jun 09 02:26:56 PM PDT 24
Finished Jun 09 02:26:59 PM PDT 24
Peak memory 207504 kb
Host smart-f125de31-c5ae-4ce6-b7c5-fb834259d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901924464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.901924464
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2044587199
Short name T754
Test name
Test status
Simulation time 49950827 ps
CPU time 2.44 seconds
Started Jun 09 02:26:56 PM PDT 24
Finished Jun 09 02:26:59 PM PDT 24
Peak memory 209640 kb
Host smart-3b4862a1-6499-42df-9671-50214c5ade7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044587199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2044587199
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2544927873
Short name T642
Test name
Test status
Simulation time 15610669 ps
CPU time 0.77 seconds
Started Jun 09 02:27:56 PM PDT 24
Finished Jun 09 02:27:57 PM PDT 24
Peak memory 204984 kb
Host smart-1695e583-35a8-4aac-af8d-b4c69337ef1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544927873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2544927873
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3112750919
Short name T857
Test name
Test status
Simulation time 397210364 ps
CPU time 4.8 seconds
Started Jun 09 02:26:46 PM PDT 24
Finished Jun 09 02:26:51 PM PDT 24
Peak memory 221624 kb
Host smart-50bda46c-333f-4ca7-8fd5-841f164e5694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112750919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3112750919
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1419743220
Short name T687
Test name
Test status
Simulation time 482356078 ps
CPU time 4.01 seconds
Started Jun 09 02:26:53 PM PDT 24
Finished Jun 09 02:26:57 PM PDT 24
Peak memory 218328 kb
Host smart-ea6187b2-6e60-471d-97bc-0c01e445587b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419743220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1419743220
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2660625287
Short name T803
Test name
Test status
Simulation time 167773565 ps
CPU time 6.52 seconds
Started Jun 09 02:28:13 PM PDT 24
Finished Jun 09 02:28:20 PM PDT 24
Peak memory 222364 kb
Host smart-270ada0e-ebdf-4e27-8e55-a01b9092786e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660625287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2660625287
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2388144278
Short name T404
Test name
Test status
Simulation time 870976165 ps
CPU time 4.34 seconds
Started Jun 09 02:26:48 PM PDT 24
Finished Jun 09 02:26:52 PM PDT 24
Peak memory 215008 kb
Host smart-556c6f58-4e32-438b-816c-05e2123373fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388144278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2388144278
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1961931530
Short name T88
Test name
Test status
Simulation time 155449214 ps
CPU time 4.54 seconds
Started Jun 09 02:26:43 PM PDT 24
Finished Jun 09 02:26:47 PM PDT 24
Peak memory 214356 kb
Host smart-49595eff-78ab-4838-8a98-3039bec3f730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961931530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1961931530
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1623251692
Short name T668
Test name
Test status
Simulation time 35614108 ps
CPU time 2.29 seconds
Started Jun 09 02:26:44 PM PDT 24
Finished Jun 09 02:26:47 PM PDT 24
Peak memory 206836 kb
Host smart-57e32820-ac9d-41eb-8e98-0683b6abcf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623251692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1623251692
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2233193310
Short name T778
Test name
Test status
Simulation time 109632786 ps
CPU time 4.34 seconds
Started Jun 09 02:26:47 PM PDT 24
Finished Jun 09 02:26:51 PM PDT 24
Peak memory 209056 kb
Host smart-57c205aa-d2e0-4602-9da8-88b691e718e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233193310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2233193310
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1608124152
Short name T368
Test name
Test status
Simulation time 315378647 ps
CPU time 3.92 seconds
Started Jun 09 02:26:42 PM PDT 24
Finished Jun 09 02:26:47 PM PDT 24
Peak memory 206916 kb
Host smart-ffa3be58-fb3f-4da0-9b72-9752e13fd4af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608124152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1608124152
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.4267714808
Short name T867
Test name
Test status
Simulation time 268633025 ps
CPU time 3.31 seconds
Started Jun 09 02:26:49 PM PDT 24
Finished Jun 09 02:26:53 PM PDT 24
Peak memory 208660 kb
Host smart-2bb8c661-5ff0-4ebe-ac05-1af2868be311
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267714808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.4267714808
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.110193325
Short name T692
Test name
Test status
Simulation time 19524443 ps
CPU time 1.57 seconds
Started Jun 09 02:26:51 PM PDT 24
Finished Jun 09 02:26:53 PM PDT 24
Peak memory 209480 kb
Host smart-0d4c6db1-591b-415d-a032-cfa5b168de14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110193325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.110193325
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1994094175
Short name T522
Test name
Test status
Simulation time 3525492345 ps
CPU time 25.23 seconds
Started Jun 09 02:26:49 PM PDT 24
Finished Jun 09 02:27:14 PM PDT 24
Peak memory 208036 kb
Host smart-e646e69d-410a-4bd5-bf23-bacf1b5563cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994094175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1994094175
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2443633264
Short name T321
Test name
Test status
Simulation time 2287224122 ps
CPU time 23.56 seconds
Started Jun 09 02:26:51 PM PDT 24
Finished Jun 09 02:27:15 PM PDT 24
Peak memory 216360 kb
Host smart-5d09cc2d-52bb-4188-bc4e-f85e048c7ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443633264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2443633264
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2689172588
Short name T263
Test name
Test status
Simulation time 233784807 ps
CPU time 4.01 seconds
Started Jun 09 02:26:53 PM PDT 24
Finished Jun 09 02:26:57 PM PDT 24
Peak memory 209652 kb
Host smart-40f21901-f0bb-4d46-8793-07c956af1c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689172588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2689172588
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1775402865
Short name T195
Test name
Test status
Simulation time 183518002 ps
CPU time 3.33 seconds
Started Jun 09 02:28:13 PM PDT 24
Finished Jun 09 02:28:16 PM PDT 24
Peak memory 210832 kb
Host smart-0c0624d0-6693-45c5-9057-8113f46fe52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775402865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1775402865
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3057492448
Short name T614
Test name
Test status
Simulation time 48789449 ps
CPU time 0.73 seconds
Started Jun 09 02:26:55 PM PDT 24
Finished Jun 09 02:26:56 PM PDT 24
Peak memory 205952 kb
Host smart-235ca04c-1337-4211-b0c8-e8171501a72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057492448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3057492448
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.256082972
Short name T222
Test name
Test status
Simulation time 235407635 ps
CPU time 8.32 seconds
Started Jun 09 02:26:55 PM PDT 24
Finished Jun 09 02:27:03 PM PDT 24
Peak memory 215636 kb
Host smart-ef06f41b-7fca-4f67-ab27-27e1605e3e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256082972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.256082972
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2288842274
Short name T50
Test name
Test status
Simulation time 109861778 ps
CPU time 2.84 seconds
Started Jun 09 02:26:53 PM PDT 24
Finished Jun 09 02:26:56 PM PDT 24
Peak memory 207852 kb
Host smart-954ce493-9a27-4388-8d9b-72e650e55652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288842274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2288842274
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2371051571
Short name T365
Test name
Test status
Simulation time 53184611 ps
CPU time 3.34 seconds
Started Jun 09 02:26:49 PM PDT 24
Finished Jun 09 02:26:53 PM PDT 24
Peak memory 222448 kb
Host smart-720a434a-9b5e-4f9a-9f25-62116dd532c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371051571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2371051571
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.150483238
Short name T532
Test name
Test status
Simulation time 68783809 ps
CPU time 2.55 seconds
Started Jun 09 02:28:13 PM PDT 24
Finished Jun 09 02:28:16 PM PDT 24
Peak memory 222288 kb
Host smart-dedd9365-8e51-402b-a8d2-b81075216d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150483238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.150483238
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2725003345
Short name T481
Test name
Test status
Simulation time 89732255 ps
CPU time 3.85 seconds
Started Jun 09 02:28:13 PM PDT 24
Finished Jun 09 02:28:22 PM PDT 24
Peak memory 209060 kb
Host smart-2ad53234-a277-422d-a893-bc171bad4d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725003345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2725003345
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.223974837
Short name T641
Test name
Test status
Simulation time 239649885 ps
CPU time 9.19 seconds
Started Jun 09 02:26:55 PM PDT 24
Finished Jun 09 02:27:04 PM PDT 24
Peak memory 214312 kb
Host smart-a28385ad-11a4-4fb7-8fc2-450880d7c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223974837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.223974837
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3777521213
Short name T322
Test name
Test status
Simulation time 387824095 ps
CPU time 3.01 seconds
Started Jun 09 02:26:52 PM PDT 24
Finished Jun 09 02:26:55 PM PDT 24
Peak memory 206872 kb
Host smart-7e4fb28c-019d-47f5-bec0-4828aa909b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777521213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3777521213
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2707531544
Short name T670
Test name
Test status
Simulation time 100712366 ps
CPU time 3.2 seconds
Started Jun 09 02:26:53 PM PDT 24
Finished Jun 09 02:26:56 PM PDT 24
Peak memory 206928 kb
Host smart-ae36bd23-19f7-40fe-9407-85826cc2f749
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707531544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2707531544
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2851261070
Short name T880
Test name
Test status
Simulation time 289628021 ps
CPU time 4.36 seconds
Started Jun 09 02:26:45 PM PDT 24
Finished Jun 09 02:26:50 PM PDT 24
Peak memory 208992 kb
Host smart-2e7705e9-ea83-41e6-aeb1-c908e5e77e45
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851261070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2851261070
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1213475000
Short name T138
Test name
Test status
Simulation time 318154549 ps
CPU time 2.38 seconds
Started Jun 09 02:26:51 PM PDT 24
Finished Jun 09 02:26:54 PM PDT 24
Peak memory 206808 kb
Host smart-76dc11de-604d-457e-869f-49c2a8065ecd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213475000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1213475000
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1250902567
Short name T151
Test name
Test status
Simulation time 106070625 ps
CPU time 2.83 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 208680 kb
Host smart-e56555fa-55eb-4abe-b6ff-e7d075270b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250902567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1250902567
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.4177250555
Short name T852
Test name
Test status
Simulation time 2221848664 ps
CPU time 9.4 seconds
Started Jun 09 02:26:55 PM PDT 24
Finished Jun 09 02:27:05 PM PDT 24
Peak memory 208404 kb
Host smart-819adac2-c80b-48f9-b1ba-0c27f842057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177250555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.4177250555
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2699087024
Short name T184
Test name
Test status
Simulation time 625349890 ps
CPU time 9.65 seconds
Started Jun 09 02:26:59 PM PDT 24
Finished Jun 09 02:27:09 PM PDT 24
Peak memory 214444 kb
Host smart-2260a5ed-482a-4821-8ae5-f2d27aa0c85f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699087024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2699087024
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.500651940
Short name T130
Test name
Test status
Simulation time 232450888 ps
CPU time 14.12 seconds
Started Jun 09 02:26:55 PM PDT 24
Finished Jun 09 02:27:10 PM PDT 24
Peak memory 222564 kb
Host smart-0c7cbeb7-f022-4123-b515-42e5647349f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500651940 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.500651940
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3067013142
Short name T349
Test name
Test status
Simulation time 1380213943 ps
CPU time 11.26 seconds
Started Jun 09 02:28:13 PM PDT 24
Finished Jun 09 02:28:24 PM PDT 24
Peak memory 208164 kb
Host smart-348cb288-d393-4949-abfd-12b3b4a52018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067013142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3067013142
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1450305417
Short name T392
Test name
Test status
Simulation time 67090693 ps
CPU time 2.55 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 210092 kb
Host smart-cda038ea-a205-4a78-9189-679f6c45c217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450305417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1450305417
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2402943929
Short name T747
Test name
Test status
Simulation time 13887873 ps
CPU time 0.73 seconds
Started Jun 09 02:26:57 PM PDT 24
Finished Jun 09 02:26:58 PM PDT 24
Peak memory 205940 kb
Host smart-2b3bd586-bd73-4e34-bf69-7a0732f3ea5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402943929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2402943929
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.4264852558
Short name T32
Test name
Test status
Simulation time 357780146 ps
CPU time 3.93 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:19 PM PDT 24
Peak memory 213944 kb
Host smart-8ce96640-b006-4d93-8ee1-1424e0e6ab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264852558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.4264852558
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3858131698
Short name T75
Test name
Test status
Simulation time 192561627 ps
CPU time 2.56 seconds
Started Jun 09 02:28:12 PM PDT 24
Finished Jun 09 02:28:15 PM PDT 24
Peak memory 209016 kb
Host smart-af7dc816-fe98-493a-9d1f-952c5b0b9da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858131698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3858131698
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2847256348
Short name T95
Test name
Test status
Simulation time 310897988 ps
CPU time 5.94 seconds
Started Jun 09 02:26:57 PM PDT 24
Finished Jun 09 02:27:03 PM PDT 24
Peak memory 214344 kb
Host smart-a95c2840-a10a-4384-9102-185021fd722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847256348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2847256348
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3783654284
Short name T51
Test name
Test status
Simulation time 957799316 ps
CPU time 4.32 seconds
Started Jun 09 02:26:59 PM PDT 24
Finished Jun 09 02:27:03 PM PDT 24
Peak memory 215168 kb
Host smart-39c870c5-1983-42d6-841e-f05771af6d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783654284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3783654284
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2132079408
Short name T64
Test name
Test status
Simulation time 228898276 ps
CPU time 5.21 seconds
Started Jun 09 02:26:59 PM PDT 24
Finished Jun 09 02:27:04 PM PDT 24
Peak memory 222028 kb
Host smart-8f1043ab-28bd-4ad7-b88c-b6cfe963df06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132079408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2132079408
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3737912121
Short name T326
Test name
Test status
Simulation time 111075310 ps
CPU time 4.89 seconds
Started Jun 09 02:26:52 PM PDT 24
Finished Jun 09 02:26:58 PM PDT 24
Peak memory 208540 kb
Host smart-6353f885-a044-48b7-b6e7-b3c0f79134b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737912121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3737912121
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1300694258
Short name T838
Test name
Test status
Simulation time 47220873 ps
CPU time 2.52 seconds
Started Jun 09 02:26:53 PM PDT 24
Finished Jun 09 02:26:56 PM PDT 24
Peak memory 206928 kb
Host smart-8e3bb0eb-bb82-4964-ba76-e87ba61315bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300694258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1300694258
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1358466780
Short name T12
Test name
Test status
Simulation time 38802918 ps
CPU time 2.13 seconds
Started Jun 09 02:26:52 PM PDT 24
Finished Jun 09 02:26:54 PM PDT 24
Peak memory 208764 kb
Host smart-3ea8dbff-f5ce-460d-aaec-b4d723555b15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358466780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1358466780
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3389401724
Short name T474
Test name
Test status
Simulation time 63327914 ps
CPU time 2.44 seconds
Started Jun 09 02:26:49 PM PDT 24
Finished Jun 09 02:26:52 PM PDT 24
Peak memory 207584 kb
Host smart-21008efc-3688-42a9-8684-e1d56262762b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389401724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3389401724
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3356885442
Short name T744
Test name
Test status
Simulation time 240249446 ps
CPU time 2.87 seconds
Started Jun 09 02:26:54 PM PDT 24
Finished Jun 09 02:26:57 PM PDT 24
Peak memory 208176 kb
Host smart-1b286326-e810-4010-8881-f82a82c48ab0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356885442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3356885442
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2491248915
Short name T834
Test name
Test status
Simulation time 87162210 ps
CPU time 2.52 seconds
Started Jun 09 02:28:15 PM PDT 24
Finished Jun 09 02:28:18 PM PDT 24
Peak memory 215444 kb
Host smart-0a108e2d-45ce-48e0-8230-8afb8fdd9030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491248915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2491248915
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2813781806
Short name T435
Test name
Test status
Simulation time 37534231 ps
CPU time 2.52 seconds
Started Jun 09 02:26:52 PM PDT 24
Finished Jun 09 02:26:55 PM PDT 24
Peak memory 208752 kb
Host smart-c97d3ae0-dddc-443d-8fc1-0360c68fac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813781806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2813781806
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1622956629
Short name T815
Test name
Test status
Simulation time 157279094 ps
CPU time 8.22 seconds
Started Jun 09 02:27:06 PM PDT 24
Finished Jun 09 02:27:14 PM PDT 24
Peak memory 215812 kb
Host smart-dc3da3f7-b831-4651-afca-fb3d9db0278b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622956629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1622956629
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2448316367
Short name T186
Test name
Test status
Simulation time 522341654 ps
CPU time 19.17 seconds
Started Jun 09 02:27:04 PM PDT 24
Finished Jun 09 02:27:24 PM PDT 24
Peak memory 220020 kb
Host smart-dc92dd79-3c39-450e-bd6d-7502d908e4f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448316367 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2448316367
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2646019050
Short name T285
Test name
Test status
Simulation time 193525832 ps
CPU time 5.82 seconds
Started Jun 09 02:26:56 PM PDT 24
Finished Jun 09 02:27:02 PM PDT 24
Peak memory 218368 kb
Host smart-2541cbf5-3536-473f-bcb5-4d7e21bad94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646019050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2646019050
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1848081747
Short name T774
Test name
Test status
Simulation time 34864873 ps
CPU time 1.47 seconds
Started Jun 09 02:27:02 PM PDT 24
Finished Jun 09 02:27:04 PM PDT 24
Peak memory 209896 kb
Host smart-d8c73d74-8581-49d4-bc77-85c51eef2cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848081747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1848081747
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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