Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5004

1

T1

9

T3

5

T11

11

auto[1]

552

1

T3

1

T11

1

T16

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5004

1

T1

9

T3

5

T11

11

auto[1]

552

1

T3

1

T11

1

T16

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5018

1

T1

6

T3

6

T11

12

auto[1]

538

1

T1

3

T5

2

T6

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5018

1

T1

6

T3

6

T11

12

auto[1]

538

1

T1

3

T5

2

T6

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	489	1			T3	1		T13	1		T5	1
auto[OpGenId]	1166	1			T3	1		T13	1		T5	8
auto[OpGenSwOut]	1180	1			T3	2		T13	2		T14	1
auto[OpGenHwOut]	2658	1			T1	9		T3	2		T11	12
auto[OpDisable]	63	1			T46	2		T66	1		T67	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	489	1			T3	1		T13	1		T5	1
auto[OpGenId]	1166	1			T3	1		T13	1		T5	8
auto[OpGenSwOut]	1180	1			T3	2		T13	2		T14	1
auto[OpGenHwOut]	2658	1			T1	9		T3	2		T11	12
auto[OpDisable]	63	1			T46	2		T66	1		T67	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5009

1

T1

9

T3

5

T11

12

auto[1]

547

1

T3

1

T5

4

T6

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5009

1

T1

9

T3

5

T11

12

auto[1]

547

1

T3

1

T5

4

T6

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5248

1

T1

9

T3

6

T11

12

auto[1]

308

1

T122

7

T127

12

T128

5

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1862	1			T1	2		T3	3		T11	1
auto[1]	740	1			T3	1		T11	3		T16	1
auto[2]	703	1			T1	1		T13	1		T16	1
auto[3]	760	1			T1	2		T11	2		T13	1
auto[4]	376	1			T1	2		T11	2		T13	1
auto[5]	396	1			T1	1		T11	2		T14	1
auto[6]	345	1			T1	1		T11	1		T16	1
auto[7]	374	1			T3	2		T11	1		T13	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1491	1			T1	4		T3	2		T11	6
clear_one[1]	740	1			T3	1		T11	3		T16	1
clear_one[2]	703	1			T1	1		T13	1		T16	1
clear_one[3]	760	1			T1	2		T11	2		T13	1
clear_none	1862	1			T1	2		T3	3		T11	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1070	1			T1	1		T3	1		T11	4
auto[StInit]	691	1			T1	1		T3	1		T11	1
auto[StCreatorRootKey]	603	1			T1	1		T3	1		T11	1
auto[StOwnerIntKey]	549	1			T1	1		T3	1		T11	1
auto[StOwnerKey]	467	1			T1	1		T11	1		T16	1
auto[StDisabled]	1882	1			T1	4		T3	2		T11	4
auto[StInvalid]	294	1			T13	5		T34	4		T48	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1070	1			T1	1		T3	1		T11	4
auto[StInit]	691	1			T1	1		T3	1		T11	1
auto[StCreatorRootKey]	603	1			T1	1		T3	1		T11	1
auto[StOwnerIntKey]	549	1			T1	1		T3	1		T11	1
auto[StOwnerKey]	467	1			T1	1		T11	1		T16	1
auto[StDisabled]	1882	1			T1	4		T3	2		T11	4
auto[StInvalid]	294	1			T13	5		T34	4		T48	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	6
[auto[2] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	6
[auto[2] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	24
[auto[2] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	6

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T217	1		T218	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	153	1			T5	1		T24	1		T6	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	166	1			T5	3		T6	2		T34	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	289	1			T1	1		T3	1		T11	1
auto[0]	auto[StInit]	auto[OpAdvance]	62	1			T5	1		T46	1		T192	1
auto[0]	auto[StInit]	auto[OpGenId]	96	1			T5	1		T6	2		T46	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	89	1			T6	1		T46	2		T219	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	190	1			T5	1		T76	1		T77	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	25	1			T195	1		T63	1		T60	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	40	1			T46	1		T7	1		T127	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	45	1			T3	1		T78	1		T182	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	84	1			T6	1		T76	1		T46	2
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T112	1		T220	1		T221	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	31	1			T222	1		T178	1		T70	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	31	1			T6	1		T46	1		T191	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T1	1		T5	1		T6	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	15	1			T78	1		T63	1		T45	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	25	1			T46	1		T44	2		T223	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T68	1		T61	1		T63	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T7	1		T120	1		T224	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	31	1			T3	1		T46	1		T21	1
auto[0]	auto[StDisabled]	auto[OpGenId]	53	1			T66	1		T192	1		T44	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	48	1			T46	1		T195	1		T223	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	170	1			T16	1		T46	1		T117	2
auto[0]	auto[StDisabled]	auto[OpDisable]	20	1			T46	2		T59	1		T60	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	18	1			T225	1		T226	1		T227	1
auto[0]	auto[StInvalid]	auto[OpGenId]	18	1			T13	1		T34	1		T48	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	26	1			T49	1		T124	1		T82	2
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	18	1			T124	1		T79	1		T228	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T229	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	21	1			T7	1		T48	1		T230	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	27	1			T5	2		T47	1		T225	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	44	1			T11	1		T62	1		T59	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T178	1		T231	1		T232	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T59	1		T233	1		T234	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	11	1			T3	1		T5	1		T46	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	23	1			T117	1		T235	1		T236	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T55	1		T214	1		T237	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T192	1		T202	1		T238	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	20	1			T44	1		T120	1		T61	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	60	1			T34	1		T7	1		T123	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T127	1		T63	1		T239	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T46	2		T68	1		T59	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T46	1		T186	1		T127	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	46	1			T5	1		T240	1		T22	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T241	1		T179	1		T242	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	10	1			T200	1		T243	1		T244	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T127	2		T217	1		T245	2
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	52	1			T11	1		T117	1		T182	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	27	1			T44	1		T129	2		T50	1
auto[1]	auto[StDisabled]	auto[OpGenId]	55	1			T62	1		T44	1		T246	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	54	1			T5	1		T7	1		T68	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	151	1			T11	1		T16	1		T5	1
auto[1]	auto[StDisabled]	auto[OpDisable]	8	1			T247	1		T202	1		T73	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	10	1			T226	1		T248	1		T249	1
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T250	1		T251	1		T252	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T48	1		T82	1		T248	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T82	1		T251	1		T226	1
auto[2]	auto[StReset]	auto[OpGenId]	17	1			T5	1		T46	1		T47	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	27	1			T105	1		T253	1		T247	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	49	1			T117	1		T184	1		T235	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T199	1		T254	1		T255	1
auto[2]	auto[StInit]	auto[OpGenId]	11	1			T7	1		T61	1		T202	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T241	1		T100	1		T233	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	19	1			T198	1		T7	1		T123	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T77	1		T92	1		T22	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T178	1		T256	1		T199	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T196	1		T44	1		T69	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T184	1		T197	1		T125	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T46	1		T60	1		T257	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T46	1		T194	1		T170	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T258	1		T253	1		T247	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T117	1		T184	1		T259	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T219	1		T122	1		T203	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T46	1		T260	1		T194	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T5	1		T7	1		T60	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T6	1		T198	1		T44	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	29	1			T121	1		T122	1		T261	1
auto[2]	auto[StDisabled]	auto[OpGenId]	60	1			T5	1		T92	1		T192	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T5	1		T6	1		T46	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T1	1		T16	1		T6	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T67	1		T202	1		T199	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T49	1		T262	1		T263	1
auto[2]	auto[StInvalid]	auto[OpGenId]	16	1			T251	1		T228	1		T227	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T13	1		T228	1		T264	2
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T34	1		T48	1		T250	1
auto[3]	auto[StReset]	auto[OpGenId]	15	1			T5	1		T68	1		T83	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	25	1			T5	1		T34	1		T7	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	54	1			T11	1		T5	1		T117	1
auto[3]	auto[StInit]	auto[OpAdvance]	8	1			T46	1		T252	1		T203	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T247	1		T170	1		T265	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T186	1		T63	1		T266	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	16	1			T16	1		T184	1		T60	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T199	1		T72	1		T267	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T44	1		T68	1		T265	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T63	1		T60	1		T268	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T240	1		T269	1		T224	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T128	1		T111	1		T270	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	23	1			T6	1		T21	1		T128	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T5	1		T247	1		T113	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	58	1			T11	1		T219	1		T197	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T261	1		T128	1		T271	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	23	1			T92	1		T191	1		T63	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T63	1		T105	1		T175	2
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T125	1		T68	1		T272	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	34	1			T44	1		T121	1		T63	1
auto[3]	auto[StDisabled]	auto[OpGenId]	69	1			T5	3		T46	1		T196	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T7	2		T193	2		T273	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	148	1			T1	2		T6	3		T76	1
auto[3]	auto[StDisabled]	auto[OpDisable]	7	1			T66	1		T202	1		T274	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T250	2		T226	1		T275	1
auto[3]	auto[StInvalid]	auto[OpGenId]	14	1			T276	1		T277	1		T278	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T83	1		T93	2		T279	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T13	1		T250	1		T251	1
auto[4]	auto[StReset]	auto[OpGenId]	11	1			T46	1		T251	1		T51	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	13	1			T45	1		T178	1		T280	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	23	1			T11	1		T34	1		T46	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T120	1		T281	2		-	-
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T6	1		T282	1		T283	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	11	1			T178	1		T175	2		T265	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	13	1			T11	1		T247	1		T175	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T284	1		T285	1		T286	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T6	1		T60	1		T199	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T287	1		T288	1		T289	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T1	1		T44	1		T246	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T290	1		T218	1		T291	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T223	1		T105	1		T60	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T192	1		T260	1		T292	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T123	1		T293	1		T294	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T111	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T186	1		T199	1		T218	3
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T295	1		T231	1		T100	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T1	1		T235	1		T296	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	13	1			T63	1		T297	1		T100	1
auto[4]	auto[StDisabled]	auto[OpGenId]	35	1			T46	3		T111	1		T178	2
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	34	1			T5	1		T46	1		T188	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T46	1		T196	1		T197	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T298	1		T165	1		T299	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T263	1		T300	1		T301	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T124	1		T82	1		T302	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T13	1		T34	1		T55	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T303	1		-	-		-	-
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T250	1		T304	1		T265	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	12	1			T14	1		T46	1		T305	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	25	1			T21	1		T306	1		T307	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T306	1		T308	1		T208	1
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T105	1		T233	1		T309	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T5	1		T75	1		T310	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	17	1			T1	1		T189	1		T269	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T306	1		T311	1		T312	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T178	1		T202	1		T73	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T5	1		T238	1		T200	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T46	1		T202	1		T313	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T63	1		T52	1		T314	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T68	1		T199	1		T265	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T188	1		T196	1		T199	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T198	1		T315	1		T296	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T21	1		T243	1		T312	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T258	1		T247	1		T316	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T88	1		T200	1		T234	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T16	1		T76	1		T46	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	15	1			T63	1		T271	2		T317	1
auto[5]	auto[StDisabled]	auto[OpGenId]	30	1			T78	1		T46	1		T44	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	38	1			T188	1		T47	1		T190	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T11	2		T16	1		T5	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T202	1		T179	1		T318	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T124	1		T319	1		T303	1
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T320	1		T321	1		T322	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T323	1		T324	1		T325	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T49	1		T124	1		T252	1
auto[6]	auto[StReset]	auto[OpGenId]	7	1			T225	1		T247	1		T199	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	5	1			T37	1		T238	1		T326	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	19	1			T5	2		T51	2		T88	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T199	1		T327	1		T328	1
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T178	1		T73	1		T329	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T238	1		T330	1		T179	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	12	1			T293	1		T178	1		T331	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T332	1		T281	1		T328	2
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T63	1		T112	1		T333	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T6	1		T334	1		T23	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T16	1		T272	1		T247	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T178	1		T317	1		T326	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T78	1		T44	1		T63	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T5	1		T63	1		T37	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T45	1		T335	1		T336	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T139	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	9	1			T189	1		T63	2		T129	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T337	1		T86	1		T338	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	11	1			T7	1		T307	1		T294	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	13	1			T195	1		T60	1		T247	1
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T6	1		T46	1		T126	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T46	2		T129	1		T178	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	94	1			T1	1		T11	1		T76	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T339	1		T340	1		T341	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	5	1			T251	1		T342	1		T343	3
auto[6]	auto[StInvalid]	auto[OpGenId]	9	1			T82	1		T83	2		T279	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T48	1		T344	1		T345	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T34	1		T346	1		-	-
auto[7]	auto[StReset]	auto[OpGenId]	18	1			T34	1		T7	1		T60	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	4	1			T178	1		T180	1		T347	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	32	1			T5	1		T46	1		T117	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T241	1		T339	1		T348	1
auto[7]	auto[StInit]	auto[OpGenId]	8	1			T200	1		T316	1		T312	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	10	1			T46	1		T113	1		T71	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	9	1			T34	1		T47	1		T349	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T265	1		T243	1		T211	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T46	1		T122	1		T337	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T273	1		T214	1		T350	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T11	1		T6	1		T117	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T170	1		T351	1		T286	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T3	1		T46	1		T352	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T202	1		T241	1		T350	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T16	1		T92	1		T50	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T92	1		T353	1		T354	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T170	1		T238	1		T72	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T5	1		T46	1		T62	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T355	1		T293	1		T356	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	15	1			T78	1		T127	1		T336	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T357	1		T178	1		T175	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T5	1		T92	1		T223	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T3	1		T6	1		T7	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T114	1		T358	1		T359	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T13	1		T278	2		T360	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T319	2		T361	1		T325	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T83	1		T248	1		T362	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T49	1		T124	1		T83	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1491

1

T1

4

T3

2

T11

6

clear_one[1]

auto[0]

auto[0]

auto[0]

426

1

T3

1

T11

3

T16

1

clear_one[1]

auto[0]

auto[0]

auto[1]

145

1

T5

2

T34

1

T117

1

clear_one[1]

auto[0]

auto[1]

auto[0]

135

1

T78

1

T46

2

T186

1

clear_one[1]

auto[0]

auto[1]

auto[1]

34

1

T44

1

T282

1

T247

3

clear_one[2]

auto[0]

auto[0]

auto[0]

423

1

T1

1

T13

1

T5

3

clear_one[2]

auto[0]

auto[0]

auto[1]

115

1

T5

1

T6

1

T76

1

clear_one[2]

auto[1]

auto[0]

auto[0]

128

1

T16

1

T46

2

T240

1

clear_one[2]

auto[1]

auto[0]

auto[1]

37

1

T46

1

T120

1

T121

1

clear_one[3]

auto[0]

auto[0]

auto[0]

456

1

T11

1

T13

1

T16

1

clear_one[3]

auto[0]

auto[1]

auto[0]

131

1

T1

2

T5

2

T6

3

clear_one[3]

auto[1]

auto[0]

auto[0]

136

1

T11

1

T240

1

T66

1

clear_one[3]

auto[1]

auto[1]

auto[0]

37

1

T46

1

T258

1

T247

1

clear_none

auto[0]

auto[0]

auto[0]

1376

1

T1

1

T3

2

T11

1

clear_none

auto[0]

auto[0]

auto[1]

114

1

T5

1

T6

1

T76

2

clear_none

auto[0]

auto[1]

auto[0]

119

1

T1

1

T46

2

T198

1

clear_none

auto[0]

auto[1]

auto[1]

39

1

T46

1

T191

1

T195

1

clear_none

auto[1]

auto[0]

auto[0]

125

1

T16

1

T190

1

T66

2

clear_none

auto[1]

auto[0]

auto[1]

46

1

T3

1

T6

1

T7

2

clear_none

auto[1]

auto[1]

auto[0]

26

1

T46

2

T44

1

T60

1

clear_none

auto[1]

auto[1]

auto[1]

17

1

T195

1

T363

1

T364

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1401	1			T1	4		T3	2		T11	6
clear_all	auto[1]	90	1			T127	1		T129	5		T365	2
clear_one[1]	auto[0]	677	1			T3	1		T11	3		T16	1
clear_one[1]	auto[1]	63	1			T127	7		T129	4		T170	1
clear_one[2]	auto[0]	669	1			T1	1		T13	1		T16	1
clear_one[2]	auto[1]	34	1			T122	4		T220	1		T241	3
clear_one[3]	auto[0]	709	1			T1	2		T11	2		T13	1
clear_one[3]	auto[1]	51	1			T128	3		T366	3		T170	6
clear_none	auto[0]	1792	1			T1	2		T3	3		T11	1
clear_none	auto[1]	70	1			T122	3		T127	4		T128	2