Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11403

1

T1

7

T2

4

T3

13

auto[Attestation]

7730

1

T1

3

T2

3

T3

8

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2738	1			T2	1		T3	3		T4	1
auto[Aes]	3555	1			T2	2		T3	6		T4	3
auto[Kmac]	3269	1			T1	10		T3	2		T4	1
auto[Otbn]	3578	1			T2	1		T3	4		T15	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7858	1			T1	8		T2	3		T3	8
auto[OpGenId]	5993	1			T2	3		T3	6		T4	4
auto[OpGenSwOut]	6055	1			T2	4		T3	6		T4	2
auto[OpGenHwOut]	7085	1			T1	10		T3	9		T4	3
auto[OpDisable]	135	1			T5	2		T46	5		T47	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10967

1

T1

8

T2

6

T3

9

auto[OpDoneFail]

16159

1

T1

10

T2

4

T3

20

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6511	1			T1	3		T2	1		T3	7
auto[StInit]	3720	1			T1	2		T2	5		T3	2
auto[StCreatorRootKey]	3293	1			T1	2		T2	1		T3	2
auto[StOwnerIntKey]	2876	1			T1	2		T2	3		T3	5
auto[StOwnerKey]	2538	1			T1	2		T3	1		T11	2
auto[StDisabled]	8188	1			T1	7		T3	12		T11	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	285	1			T5	3		T77	1		T34	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	95	1			T15	1		T46	1		T182	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	95	1			T5	2		T6	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	85	1			T2	1		T3	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T5	2		T46	1		T188	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	239	1			T5	1		T46	8		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	353	1			T14	1		T5	3		T32	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T5	1		T6	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	87	1			T3	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	68	1			T3	1		T5	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	58	1			T5	1		T46	2		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	228	1			T3	1		T5	3		T32	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	320	1			T3	1		T14	1		T5	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	97	1			T5	1		T6	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T5	1		T46	2		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T5	1		T34	1		T182	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	75	1			T5	1		T190	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	215	1			T15	1		T32	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	343	1			T5	4		T33	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	103	1			T5	1		T25	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	92	1			T5	1		T6	1		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	76	1			T6	2		T92	1		T188	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	76	1			T5	1		T46	6		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	228	1			T5	2		T6	2		T46	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	68	1			T5	1		T46	3		T92	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	86	1			T5	3		T6	2		T46	6
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T46	1		T92	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	67	1			T6	1		T46	1		T188	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	76	1			T5	1		T46	1		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	217	1			T15	1		T46	4		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	97	1			T5	6		T6	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	105	1			T2	2		T3	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	82	1			T5	1		T32	1		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	64	1			T15	1		T34	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T5	1		T46	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	222	1			T15	1		T5	2		T46	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	79	1			T5	4		T34	2		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	98	1			T7	2		T44	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	82	1			T6	1		T35	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T5	1		T46	1		T186	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	64	1			T46	2		T191	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	193	1			T5	4		T32	1		T46	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	86	1			T5	1		T46	4		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	104	1			T2	1		T32	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	92	1			T5	2		T6	1		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	82	1			T5	1		T44	1		T120	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	68	1			T15	1		T5	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	238	1			T5	3		T78	1		T46	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	298	1			T14	1		T5	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	93	1			T5	1		T77	2		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	89	1			T5	1		T116	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	61	1			T5	1		T193	1		T194	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T6	1		T192	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	169	1			T5	1		T46	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	519	1			T3	1		T11	10		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	144	1			T4	1		T16	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	125	1			T11	1		T16	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	112	1			T11	1		T46	3		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	84	1			T5	1		T46	2		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	267	1			T11	3		T16	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	364	1			T1	2		T3	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	109	1			T1	1		T46	1		T92	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	123	1			T6	2		T116	1		T46	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	116	1			T1	1		T46	1		T92	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	87	1			T5	1		T46	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	304	1			T1	3		T5	2		T46	11
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	507	1			T33	1		T6	1		T46	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	113	1			T6	1		T46	1		T117	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T5	1		T34	1		T191	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T5	1		T6	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T6	1		T76	1		T117	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	312	1			T3	3		T5	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T5	3		T6	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	102	1			T34	1		T46	2		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T4	1		T6	2		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	71	1			T5	2		T34	1		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	43	1			T6	1		T46	1		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	166	1			T3	2		T5	2		T46	6
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	65	1			T5	2		T34	1		T46	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	119	1			T11	1		T6	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	120	1			T6	2		T77	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	82	1			T16	1		T62	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	92	1			T11	1		T16	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	290	1			T3	1		T11	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	58	1			T5	3		T34	1		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	92	1			T4	1		T33	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T1	1		T78	1		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T5	1		T46	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	81	1			T1	1		T6	1		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	262	1			T1	1		T6	4		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	58	1			T5	1		T34	1		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	117	1			T33	2		T76	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	133	1			T5	2		T6	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T5	1		T6	2		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	81	1			T92	1		T182	1		T184	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	284	1			T3	1		T5	1		T6	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	211	1			T2	1		T5	7		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	642	1			T3	1		T15	1		T5	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	203	1			T3	2		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	700	1			T3	1		T14	1		T5	7
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	219	1			T5	3		T34	1		T46	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	652	1			T3	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	223	1			T5	2		T6	3		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	695	1			T5	7		T33	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	215	1			T5	1		T6	1		T46	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	387	1			T15	1		T5	4		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	191	1			T15	1		T5	2		T32	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	442	1			T2	2		T3	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	216	1			T5	1		T6	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	389	1			T5	8		T32	1		T34	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	228	1			T15	1		T5	4		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	442	1			T2	1		T5	4		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	184	1			T5	2		T6	1		T116	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	582	1			T14	1		T5	3		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	297	1			T11	2		T16	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	954	1			T3	1		T4	1		T11	13
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	307	1			T1	1		T5	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	796	1			T1	6		T3	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T5	2		T6	2		T76	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	944	1			T3	3		T5	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	174	1			T4	1		T5	2		T6	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	343	1			T3	2		T5	5		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	283	1			T11	1		T16	2		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	485	1			T3	1		T11	2		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	262	1			T1	2		T5	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	428	1			T1	1		T4	1		T5	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	297	1			T5	1		T6	3		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	476	1			T3	1		T5	4		T33	2