Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33337

1

T1

21

T2

12

T3

32

auto[1]

264

1

T122

9

T127

10

T128

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33344	1			T1	21		T2	12		T3	32
auto[134217728:268435455]	13	1			T127	2		T364	1		T365	1
auto[268435456:402653183]	6	1			T127	1		T220	1		T170	1
auto[402653184:536870911]	12	1			T122	1		T281	1		T245	1
auto[536870912:671088639]	8	1			T128	1		T271	1		T241	1
auto[671088640:805306367]	5	1			T231	1		T385	1		T384	1
auto[805306368:939524095]	7	1			T122	1		T220	1		T170	1
auto[939524096:1073741823]	9	1			T122	1		T128	1		T366	1
auto[1073741824:1207959551]	7	1			T127	1		T241	1		T245	2
auto[1207959552:1342177279]	6	1			T122	1		T364	1		T220	1
auto[1342177280:1476395007]	9	1			T297	1		T231	1		T404	1
auto[1476395008:1610612735]	8	1			T366	1		T175	1		T231	1
auto[1610612736:1744830463]	2	1			T127	1		T338	1		-	-
auto[1744830464:1879048191]	8	1			T122	1		T128	1		T404	1
auto[1879048192:2013265919]	11	1			T122	1		T127	2		T128	1
auto[2013265920:2147483647]	7	1			T231	1		T217	1		T405	1
auto[2147483648:2281701375]	12	1			T127	1		T365	1		T170	1
auto[2281701376:2415919103]	12	1			T271	3		T231	1		T217	2
auto[2415919104:2550136831]	10	1			T241	1		T297	1		T245	2
auto[2550136832:2684354559]	6	1			T170	2		T271	1		T297	1
auto[2684354560:2818572287]	16	1			T127	1		T128	1		T365	1
auto[2818572288:2952790015]	8	1			T129	1		T220	1		T366	1
auto[2952790016:3087007743]	7	1			T271	2		T217	1		T404	1
auto[3087007744:3221225471]	8	1			T129	1		T175	1		T308	1
auto[3221225472:3355443199]	3	1			T364	1		T241	1		T406	1
auto[3355443200:3489660927]	11	1			T127	1		T365	1		T175	1
auto[3489660928:3623878655]	8	1			T122	2		T364	1		T170	1
auto[3623878656:3758096383]	6	1			T364	1		T271	1		T217	1
auto[3758096384:3892314111]	12	1			T364	1		T220	1		T231	1
auto[3892314112:4026531839]	9	1			T122	1		T175	1		T308	1
auto[4026531840:4160749567]	5	1			T365	1		T366	1		T285	1
auto[4160749568:4294967295]	6	1			T129	1		T364	1		T384	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33337	1			T1	21		T2	12		T3	32
auto[0:134217727]	auto[1]	7	1			T128	2		T271	1		T385	1
auto[134217728:268435455]	auto[1]	13	1			T127	2		T364	1		T365	1
auto[268435456:402653183]	auto[1]	6	1			T127	1		T220	1		T170	1
auto[402653184:536870911]	auto[1]	12	1			T122	1		T281	1		T245	1
auto[536870912:671088639]	auto[1]	8	1			T128	1		T271	1		T241	1
auto[671088640:805306367]	auto[1]	5	1			T231	1		T385	1		T384	1
auto[805306368:939524095]	auto[1]	7	1			T122	1		T220	1		T170	1
auto[939524096:1073741823]	auto[1]	9	1			T122	1		T128	1		T366	1
auto[1073741824:1207959551]	auto[1]	7	1			T127	1		T241	1		T245	2
auto[1207959552:1342177279]	auto[1]	6	1			T122	1		T364	1		T220	1
auto[1342177280:1476395007]	auto[1]	9	1			T297	1		T231	1		T404	1
auto[1476395008:1610612735]	auto[1]	8	1			T366	1		T175	1		T231	1
auto[1610612736:1744830463]	auto[1]	2	1			T127	1		T338	1		-	-
auto[1744830464:1879048191]	auto[1]	8	1			T122	1		T128	1		T404	1
auto[1879048192:2013265919]	auto[1]	11	1			T122	1		T127	2		T128	1
auto[2013265920:2147483647]	auto[1]	7	1			T231	1		T217	1		T405	1
auto[2147483648:2281701375]	auto[1]	12	1			T127	1		T365	1		T170	1
auto[2281701376:2415919103]	auto[1]	12	1			T271	3		T231	1		T217	2
auto[2415919104:2550136831]	auto[1]	10	1			T241	1		T297	1		T245	2
auto[2550136832:2684354559]	auto[1]	6	1			T170	2		T271	1		T297	1
auto[2684354560:2818572287]	auto[1]	16	1			T127	1		T128	1		T365	1
auto[2818572288:2952790015]	auto[1]	8	1			T129	1		T220	1		T366	1
auto[2952790016:3087007743]	auto[1]	7	1			T271	2		T217	1		T404	1
auto[3087007744:3221225471]	auto[1]	8	1			T129	1		T175	1		T308	1
auto[3221225472:3355443199]	auto[1]	3	1			T364	1		T241	1		T406	1
auto[3355443200:3489660927]	auto[1]	11	1			T127	1		T365	1		T175	1
auto[3489660928:3623878655]	auto[1]	8	1			T122	2		T364	1		T170	1
auto[3623878656:3758096383]	auto[1]	6	1			T364	1		T271	1		T217	1
auto[3758096384:3892314111]	auto[1]	12	1			T364	1		T220	1		T231	1
auto[3892314112:4026531839]	auto[1]	9	1			T122	1		T175	1		T308	1
auto[4026531840:4160749567]	auto[1]	5	1			T365	1		T366	1		T285	1
auto[4160749568:4294967295]	auto[1]	6	1			T129	1		T364	1		T384	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1573

1

T2

3

T3

4

T4

5

auto[1]

1879

1

T3

2

T4

2

T13

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T14	1		T5	1		T6	1
auto[134217728:268435455]	114	1			T14	1		T78	1		T46	2
auto[268435456:402653183]	107	1			T13	1		T5	2		T34	1
auto[402653184:536870911]	103	1			T4	1		T14	1		T5	2
auto[536870912:671088639]	111	1			T4	2		T5	4		T34	1
auto[671088640:805306367]	108	1			T4	1		T5	1		T186	1
auto[805306368:939524095]	140	1			T3	1		T5	1		T116	1
auto[939524096:1073741823]	96	1			T3	1		T13	1		T46	3
auto[1073741824:1207959551]	97	1			T14	1		T5	1		T77	1
auto[1207959552:1342177279]	97	1			T14	1		T46	1		T191	1
auto[1342177280:1476395007]	97	1			T6	1		T46	4		T92	1
auto[1476395008:1610612735]	102	1			T5	1		T6	1		T46	2
auto[1610612736:1744830463]	128	1			T34	1		T46	1		T182	1
auto[1744830464:1879048191]	109	1			T3	2		T5	1		T6	1
auto[1879048192:2013265919]	96	1			T13	1		T182	1		T192	1
auto[2013265920:2147483647]	84	1			T4	1		T14	1		T5	1
auto[2147483648:2281701375]	115	1			T4	1		T5	2		T6	1
auto[2281701376:2415919103]	97	1			T5	1		T46	2		T44	4
auto[2415919104:2550136831]	112	1			T6	1		T34	2		T46	2
auto[2550136832:2684354559]	120	1			T5	3		T34	1		T46	2
auto[2684354560:2818572287]	112	1			T3	2		T14	1		T5	1
auto[2818572288:2952790015]	121	1			T2	1		T46	3		T186	1
auto[2952790016:3087007743]	115	1			T24	1		T46	2		T92	1
auto[3087007744:3221225471]	109	1			T5	2		T92	1		T182	1
auto[3221225472:3355443199]	99	1			T5	2		T189	1		T7	1
auto[3355443200:3489660927]	96	1			T4	1		T13	1		T5	1
auto[3489660928:3623878655]	116	1			T14	1		T5	1		T46	2
auto[3623878656:3758096383]	108	1			T46	1		T188	1		T47	1
auto[3758096384:3892314111]	109	1			T13	2		T14	1		T6	1
auto[3892314112:4026531839]	107	1			T78	1		T62	1		T219	1
auto[4026531840:4160749567]	103	1			T2	1		T5	1		T34	1
auto[4160749568:4294967295]	109	1			T2	1		T5	3		T24	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T46	1		T182	1		T260	1
auto[0:134217727]	auto[1]	61	1			T14	1		T5	1		T6	1
auto[134217728:268435455]	auto[0]	44	1			T225	1		T128	1		T60	1
auto[134217728:268435455]	auto[1]	70	1			T14	1		T78	1		T46	2
auto[268435456:402653183]	auto[0]	45	1			T5	1		T34	1		T46	1
auto[268435456:402653183]	auto[1]	62	1			T13	1		T5	1		T46	1
auto[402653184:536870911]	auto[0]	50	1			T4	1		T14	1		T5	1
auto[402653184:536870911]	auto[1]	53	1			T5	1		T6	2		T120	1
auto[536870912:671088639]	auto[0]	52	1			T4	1		T5	3		T46	2
auto[536870912:671088639]	auto[1]	59	1			T4	1		T5	1		T34	1
auto[671088640:805306367]	auto[0]	55	1			T4	1		T186	1		T21	1
auto[671088640:805306367]	auto[1]	53	1			T5	1		T191	1		T195	1
auto[805306368:939524095]	auto[0]	72	1			T3	1		T116	1		T46	1
auto[805306368:939524095]	auto[1]	68	1			T5	1		T46	1		T21	1
auto[939524096:1073741823]	auto[0]	53	1			T3	1		T46	2		T63	3
auto[939524096:1073741823]	auto[1]	43	1			T13	1		T46	1		T182	1
auto[1073741824:1207959551]	auto[0]	45	1			T14	1		T77	1		T46	2
auto[1073741824:1207959551]	auto[1]	52	1			T5	1		T46	1		T67	1
auto[1207959552:1342177279]	auto[0]	45	1			T14	1		T46	1		T191	1
auto[1207959552:1342177279]	auto[1]	52	1			T48	1		T53	1		T120	1
auto[1342177280:1476395007]	auto[0]	49	1			T6	1		T46	2		T195	1
auto[1342177280:1476395007]	auto[1]	48	1			T46	2		T92	1		T7	1
auto[1476395008:1610612735]	auto[0]	44	1			T5	1		T7	1		T44	1
auto[1476395008:1610612735]	auto[1]	58	1			T6	1		T46	2		T219	1
auto[1610612736:1744830463]	auto[0]	58	1			T34	1		T7	1		T48	1
auto[1610612736:1744830463]	auto[1]	70	1			T46	1		T182	1		T62	1
auto[1744830464:1879048191]	auto[0]	46	1			T3	2		T6	1		T44	1
auto[1744830464:1879048191]	auto[1]	63	1			T5	1		T46	2		T189	1
auto[1879048192:2013265919]	auto[0]	37	1			T49	1		T68	1		T260	1
auto[1879048192:2013265919]	auto[1]	59	1			T13	1		T182	1		T192	1
auto[2013265920:2147483647]	auto[0]	33	1			T14	1		T5	1		T407	1
auto[2013265920:2147483647]	auto[1]	51	1			T4	1		T6	1		T305	1
auto[2147483648:2281701375]	auto[0]	52	1			T4	1		T5	2		T46	1
auto[2147483648:2281701375]	auto[1]	63	1			T6	1		T116	1		T7	1
auto[2281701376:2415919103]	auto[0]	48	1			T5	1		T44	1		T121	1
auto[2281701376:2415919103]	auto[1]	49	1			T46	2		T44	3		T63	2
auto[2415919104:2550136831]	auto[0]	47	1			T6	1		T34	1		T46	1
auto[2415919104:2550136831]	auto[1]	65	1			T34	1		T46	1		T92	1
auto[2550136832:2684354559]	auto[0]	54	1			T5	2		T46	2		T189	1
auto[2550136832:2684354559]	auto[1]	66	1			T5	1		T34	1		T189	1
auto[2684354560:2818572287]	auto[0]	45	1			T5	1		T6	1		T46	1
auto[2684354560:2818572287]	auto[1]	67	1			T3	2		T14	1		T6	1
auto[2818572288:2952790015]	auto[0]	56	1			T2	1		T7	1		T49	1
auto[2818572288:2952790015]	auto[1]	65	1			T46	3		T186	1		T122	1
auto[2952790016:3087007743]	auto[0]	58	1			T24	1		T46	1		T189	1
auto[2952790016:3087007743]	auto[1]	57	1			T46	1		T92	1		T305	1
auto[3087007744:3221225471]	auto[0]	49	1			T5	2		T44	1		T126	1
auto[3087007744:3221225471]	auto[1]	60	1			T92	1		T182	1		T7	1
auto[3221225472:3355443199]	auto[0]	42	1			T5	1		T189	1		T124	1
auto[3221225472:3355443199]	auto[1]	57	1			T5	1		T7	1		T55	1
auto[3355443200:3489660927]	auto[0]	51	1			T4	1		T13	1		T53	1
auto[3355443200:3489660927]	auto[1]	45	1			T5	1		T46	1		T195	1
auto[3489660928:3623878655]	auto[0]	54	1			T46	2		T192	1		T44	1
auto[3489660928:3623878655]	auto[1]	62	1			T14	1		T5	1		T305	1
auto[3623878656:3758096383]	auto[0]	45	1			T188	1		T44	2		T59	1
auto[3623878656:3758096383]	auto[1]	63	1			T46	1		T47	1		T287	1
auto[3758096384:3892314111]	auto[0]	45	1			T14	1		T46	1		T7	2
auto[3758096384:3892314111]	auto[1]	64	1			T13	2		T6	1		T62	1
auto[3892314112:4026531839]	auto[0]	39	1			T219	1		T44	1		T63	1
auto[3892314112:4026531839]	auto[1]	68	1			T78	1		T62	1		T192	1
auto[4026531840:4160749567]	auto[0]	57	1			T2	1		T34	1		T46	1
auto[4026531840:4160749567]	auto[1]	46	1			T5	1		T92	1		T48	1
auto[4160749568:4294967295]	auto[0]	49	1			T2	1		T5	2		T24	1
auto[4160749568:4294967295]	auto[1]	60	1			T5	1		T46	3		T192	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1571

1

T2

2

T3

4

T4

5

auto[1]

1881

1

T2

1

T3

2

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T14	1		T46	1		T7	1
auto[134217728:268435455]	96	1			T4	1		T5	1		T6	1
auto[268435456:402653183]	106	1			T46	1		T186	1		T62	1
auto[402653184:536870911]	104	1			T3	1		T14	2		T34	1
auto[536870912:671088639]	114	1			T5	1		T34	1		T46	2
auto[671088640:805306367]	109	1			T3	1		T4	1		T5	1
auto[805306368:939524095]	98	1			T3	1		T14	1		T5	1
auto[939524096:1073741823]	117	1			T2	1		T4	1		T5	2
auto[1073741824:1207959551]	101	1			T14	1		T5	1		T46	2
auto[1207959552:1342177279]	109	1			T2	1		T4	1		T5	1
auto[1342177280:1476395007]	92	1			T5	1		T92	1		T188	1
auto[1476395008:1610612735]	100	1			T3	1		T5	2		T6	1
auto[1610612736:1744830463]	110	1			T46	1		T53	1		T192	1
auto[1744830464:1879048191]	106	1			T5	1		T78	1		T46	2
auto[1879048192:2013265919]	103	1			T5	2		T6	3		T34	1
auto[2013265920:2147483647]	123	1			T13	1		T5	3		T34	1
auto[2147483648:2281701375]	125	1			T14	1		T5	3		T6	2
auto[2281701376:2415919103]	103	1			T5	1		T46	1		T182	1
auto[2415919104:2550136831]	105	1			T13	1		T5	1		T24	1
auto[2550136832:2684354559]	116	1			T46	2		T92	1		T55	1
auto[2684354560:2818572287]	124	1			T4	1		T13	3		T5	1
auto[2818572288:2952790015]	117	1			T4	1		T5	3		T6	1
auto[2952790016:3087007743]	112	1			T5	1		T6	1		T46	2
auto[3087007744:3221225471]	103	1			T5	1		T46	1		T182	1
auto[3221225472:3355443199]	117	1			T14	1		T5	2		T46	1
auto[3355443200:3489660927]	104	1			T7	2		T55	1		T44	2
auto[3489660928:3623878655]	102	1			T3	1		T34	2		T46	2
auto[3623878656:3758096383]	99	1			T4	1		T5	1		T46	1
auto[3758096384:3892314111]	106	1			T2	1		T14	1		T6	1
auto[3892314112:4026531839]	109	1			T24	1		T6	1		T116	1
auto[4026531840:4160749567]	109	1			T13	1		T14	1		T5	1
auto[4160749568:4294967295]	105	1			T3	1		T46	2		T7	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T14	1		T260	1		T105	1
auto[0:134217727]	auto[1]	64	1			T46	1		T7	1		T44	1
auto[134217728:268435455]	auto[0]	49	1			T5	1		T48	1		T55	1
auto[134217728:268435455]	auto[1]	47	1			T4	1		T6	1		T46	1
auto[268435456:402653183]	auto[0]	47	1			T46	1		T186	1		T21	1
auto[268435456:402653183]	auto[1]	59	1			T62	1		T120	1		T67	1
auto[402653184:536870911]	auto[0]	49	1			T14	1		T46	1		T21	1
auto[402653184:536870911]	auto[1]	55	1			T3	1		T14	1		T34	1
auto[536870912:671088639]	auto[0]	49	1			T5	1		T34	1		T46	1
auto[536870912:671088639]	auto[1]	65	1			T46	1		T219	1		T122	1
auto[671088640:805306367]	auto[0]	49	1			T3	1		T4	1		T5	1
auto[671088640:805306367]	auto[1]	60	1			T62	1		T48	1		T63	2
auto[805306368:939524095]	auto[0]	42	1			T92	1		T305	1		T48	1
auto[805306368:939524095]	auto[1]	56	1			T3	1		T14	1		T5	1
auto[939524096:1073741823]	auto[0]	55	1			T2	1		T4	1		T5	2
auto[939524096:1073741823]	auto[1]	62	1			T6	1		T46	1		T92	1
auto[1073741824:1207959551]	auto[0]	45	1			T14	1		T5	1		T46	1
auto[1073741824:1207959551]	auto[1]	56	1			T46	1		T21	1		T48	1
auto[1207959552:1342177279]	auto[0]	54	1			T2	1		T4	1		T5	1
auto[1207959552:1342177279]	auto[1]	55	1			T46	1		T48	1		T53	1
auto[1342177280:1476395007]	auto[0]	36	1			T92	1		T188	1		T178	1
auto[1342177280:1476395007]	auto[1]	56	1			T5	1		T189	1		T7	1
auto[1476395008:1610612735]	auto[0]	40	1			T3	1		T5	1		T6	1
auto[1476395008:1610612735]	auto[1]	60	1			T5	1		T78	1		T46	1
auto[1610612736:1744830463]	auto[0]	54	1			T53	1		T407	1		T63	1
auto[1610612736:1744830463]	auto[1]	56	1			T46	1		T192	1		T82	1
auto[1744830464:1879048191]	auto[0]	47	1			T46	1		T49	1		T225	1
auto[1744830464:1879048191]	auto[1]	59	1			T5	1		T78	1		T46	1
auto[1879048192:2013265919]	auto[0]	52	1			T5	2		T6	2		T34	1
auto[1879048192:2013265919]	auto[1]	51	1			T6	1		T186	1		T188	1
auto[2013265920:2147483647]	auto[0]	61	1			T5	2		T34	1		T46	1
auto[2013265920:2147483647]	auto[1]	62	1			T13	1		T5	1		T92	1
auto[2147483648:2281701375]	auto[0]	63	1			T14	1		T5	2		T6	1
auto[2147483648:2281701375]	auto[1]	62	1			T5	1		T6	1		T77	1
auto[2281701376:2415919103]	auto[0]	50	1			T5	1		T189	1		T191	1
auto[2281701376:2415919103]	auto[1]	53	1			T46	1		T182	1		T305	1
auto[2415919104:2550136831]	auto[0]	45	1			T44	1		T260	1		T225	1
auto[2415919104:2550136831]	auto[1]	60	1			T13	1		T5	1		T24	1
auto[2550136832:2684354559]	auto[0]	61	1			T46	1		T260	1		T61	1
auto[2550136832:2684354559]	auto[1]	55	1			T46	1		T92	1		T55	1
auto[2684354560:2818572287]	auto[0]	52	1			T4	1		T13	1		T5	1
auto[2684354560:2818572287]	auto[1]	72	1			T13	2		T116	1		T46	3
auto[2818572288:2952790015]	auto[0]	52	1			T5	2		T46	2		T182	1
auto[2818572288:2952790015]	auto[1]	65	1			T4	1		T5	1		T6	1
auto[2952790016:3087007743]	auto[0]	48	1			T5	1		T44	1		T68	1
auto[2952790016:3087007743]	auto[1]	64	1			T6	1		T46	2		T92	1
auto[3087007744:3221225471]	auto[0]	49	1			T5	1		T46	1		T182	1
auto[3087007744:3221225471]	auto[1]	54	1			T189	1		T191	1		T260	1
auto[3221225472:3355443199]	auto[0]	52	1			T5	1		T189	1		T49	1
auto[3221225472:3355443199]	auto[1]	65	1			T14	1		T5	1		T46	1
auto[3355443200:3489660927]	auto[0]	52	1			T7	2		T55	1		T44	1
auto[3355443200:3489660927]	auto[1]	52	1			T44	1		T363	1		T261	1
auto[3489660928:3623878655]	auto[0]	43	1			T3	1		T34	2		T46	1
auto[3489660928:3623878655]	auto[1]	59	1			T46	1		T44	1		T126	1
auto[3623878656:3758096383]	auto[0]	49	1			T4	1		T46	1		T305	1
auto[3623878656:3758096383]	auto[1]	50	1			T5	1		T219	1		T69	1
auto[3758096384:3892314111]	auto[0]	43	1			T14	1		T225	1		T63	1
auto[3758096384:3892314111]	auto[1]	63	1			T2	1		T6	1		T59	1
auto[3892314112:4026531839]	auto[0]	47	1			T24	1		T116	1		T44	1
auto[3892314112:4026531839]	auto[1]	62	1			T6	1		T46	2		T48	1
auto[4026531840:4160749567]	auto[0]	47	1			T46	1		T7	1		T44	1
auto[4026531840:4160749567]	auto[1]	62	1			T13	1		T14	1		T5	1
auto[4160749568:4294967295]	auto[0]	45	1			T3	1		T46	2		T7	1
auto[4160749568:4294967295]	auto[1]	60	1			T68	1		T225	1		T59	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1550

1

T2

2

T3

4

T4

6

auto[1]

1901

1

T2

1

T3

2

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T5	1		T6	1		T46	3
auto[134217728:268435455]	104	1			T14	1		T5	2		T24	1
auto[268435456:402653183]	107	1			T13	1		T14	1		T34	1
auto[402653184:536870911]	122	1			T13	1		T5	1		T46	4
auto[536870912:671088639]	113	1			T4	1		T14	1		T5	5
auto[671088640:805306367]	100	1			T2	1		T5	1		T46	1
auto[805306368:939524095]	116	1			T4	1		T5	1		T6	2
auto[939524096:1073741823]	121	1			T3	1		T5	1		T46	2
auto[1073741824:1207959551]	112	1			T5	2		T34	1		T186	1
auto[1207959552:1342177279]	106	1			T5	1		T46	1		T92	1
auto[1342177280:1476395007]	100	1			T2	1		T14	1		T46	2
auto[1476395008:1610612735]	112	1			T2	1		T6	1		T34	1
auto[1610612736:1744830463]	129	1			T13	1		T5	1		T6	1
auto[1744830464:1879048191]	110	1			T5	2		T46	1		T189	1
auto[1879048192:2013265919]	116	1			T14	1		T6	1		T78	1
auto[2013265920:2147483647]	100	1			T14	1		T5	1		T6	1
auto[2147483648:2281701375]	136	1			T13	1		T5	2		T6	1
auto[2281701376:2415919103]	101	1			T3	1		T13	1		T46	1
auto[2415919104:2550136831]	113	1			T4	1		T13	1		T5	3
auto[2550136832:2684354559]	112	1			T5	1		T46	2		T92	1
auto[2684354560:2818572287]	109	1			T46	4		T188	1		T305	2
auto[2818572288:2952790015]	110	1			T14	1		T78	1		T34	1
auto[2952790016:3087007743]	111	1			T46	2		T92	1		T44	1
auto[3087007744:3221225471]	99	1			T3	1		T6	1		T34	1
auto[3221225472:3355443199]	105	1			T5	1		T6	1		T46	1
auto[3355443200:3489660927]	96	1			T46	2		T7	1		T48	1
auto[3489660928:3623878655]	89	1			T3	1		T5	1		T46	1
auto[3623878656:3758096383]	106	1			T3	2		T4	1		T5	2
auto[3758096384:3892314111]	85	1			T5	1		T6	1		T34	1
auto[3892314112:4026531839]	93	1			T4	1		T182	1		T305	1
auto[4026531840:4160749567]	106	1			T4	1		T46	1		T7	1
auto[4160749568:4294967295]	108	1			T4	1		T14	2		T5	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T6	1		T46	2		T49	1
auto[0:134217727]	auto[1]	51	1			T5	1		T46	1		T47	1
auto[134217728:268435455]	auto[0]	50	1			T5	1		T24	1		T46	1
auto[134217728:268435455]	auto[1]	54	1			T14	1		T5	1		T46	1
auto[268435456:402653183]	auto[0]	52	1			T14	1		T34	1		T46	1
auto[268435456:402653183]	auto[1]	55	1			T13	1		T46	3		T189	1
auto[402653184:536870911]	auto[0]	58	1			T13	1		T46	4		T192	1
auto[402653184:536870911]	auto[1]	64	1			T5	1		T62	1		T7	1
auto[536870912:671088639]	auto[0]	50	1			T4	1		T14	1		T5	5
auto[536870912:671088639]	auto[1]	63	1			T192	1		T55	1		T261	1
auto[671088640:805306367]	auto[0]	34	1			T407	1		T59	1		T63	1
auto[671088640:805306367]	auto[1]	66	1			T2	1		T5	1		T46	1
auto[805306368:939524095]	auto[0]	56	1			T4	1		T6	1		T7	1
auto[805306368:939524095]	auto[1]	60	1			T5	1		T6	1		T46	2
auto[939524096:1073741823]	auto[0]	51	1			T3	1		T5	1		T46	1
auto[939524096:1073741823]	auto[1]	70	1			T46	1		T92	1		T47	1
auto[1073741824:1207959551]	auto[0]	51	1			T5	1		T60	2		T220	1
auto[1073741824:1207959551]	auto[1]	61	1			T5	1		T34	1		T186	1
auto[1207959552:1342177279]	auto[0]	45	1			T189	1		T44	1		T124	1
auto[1207959552:1342177279]	auto[1]	61	1			T5	1		T46	1		T92	1
auto[1342177280:1476395007]	auto[0]	42	1			T2	1		T14	1		T191	1
auto[1342177280:1476395007]	auto[1]	58	1			T46	2		T182	1		T62	1
auto[1476395008:1610612735]	auto[0]	54	1			T2	1		T34	1		T46	2
auto[1476395008:1610612735]	auto[1]	58	1			T6	1		T46	1		T92	1
auto[1610612736:1744830463]	auto[0]	53	1			T5	1		T225	1		T178	2
auto[1610612736:1744830463]	auto[1]	76	1			T13	1		T6	1		T189	1
auto[1744830464:1879048191]	auto[0]	50	1			T5	2		T189	1		T7	1
auto[1744830464:1879048191]	auto[1]	60	1			T46	1		T21	1		T44	1
auto[1879048192:2013265919]	auto[0]	47	1			T116	1		T7	1		T44	1
auto[1879048192:2013265919]	auto[1]	69	1			T14	1		T6	1		T78	1
auto[2013265920:2147483647]	auto[0]	48	1			T14	1		T5	1		T250	1
auto[2013265920:2147483647]	auto[1]	52	1			T6	1		T192	2		T44	1
auto[2147483648:2281701375]	auto[0]	51	1			T77	1		T63	2		T60	1
auto[2147483648:2281701375]	auto[1]	85	1			T13	1		T5	2		T6	1
auto[2281701376:2415919103]	auto[0]	47	1			T46	1		T182	1		T44	1
auto[2281701376:2415919103]	auto[1]	54	1			T3	1		T13	1		T182	1
auto[2415919104:2550136831]	auto[0]	53	1			T4	1		T5	2		T46	1
auto[2415919104:2550136831]	auto[1]	60	1			T13	1		T5	1		T46	2
auto[2550136832:2684354559]	auto[0]	53	1			T5	1		T46	1		T44	1
auto[2550136832:2684354559]	auto[1]	59	1			T46	1		T92	1		T62	1
auto[2684354560:2818572287]	auto[0]	37	1			T305	1		T55	1		T49	1
auto[2684354560:2818572287]	auto[1]	72	1			T46	4		T188	1		T305	1
auto[2818572288:2952790015]	auto[0]	53	1			T55	1		T44	1		T59	1
auto[2818572288:2952790015]	auto[1]	57	1			T14	1		T78	1		T34	1
auto[2952790016:3087007743]	auto[0]	57	1			T92	1		T124	1		T260	1
auto[2952790016:3087007743]	auto[1]	54	1			T46	2		T44	1		T120	1
auto[3087007744:3221225471]	auto[0]	50	1			T3	1		T34	1		T46	1
auto[3087007744:3221225471]	auto[1]	49	1			T6	1		T46	1		T189	1
auto[3221225472:3355443199]	auto[0]	47	1			T5	1		T44	1		T124	1
auto[3221225472:3355443199]	auto[1]	58	1			T6	1		T46	1		T126	1
auto[3355443200:3489660927]	auto[0]	53	1			T44	1		T121	1		T250	1
auto[3355443200:3489660927]	auto[1]	43	1			T46	2		T7	1		T48	1
auto[3489660928:3623878655]	auto[0]	41	1			T3	1		T5	1		T46	1
auto[3489660928:3623878655]	auto[1]	48	1			T219	1		T53	1		T67	1
auto[3623878656:3758096383]	auto[0]	45	1			T3	1		T4	1		T5	1
auto[3623878656:3758096383]	auto[1]	61	1			T3	1		T5	1		T24	1
auto[3758096384:3892314111]	auto[0]	40	1			T5	1		T34	1		T7	1
auto[3758096384:3892314111]	auto[1]	45	1			T6	1		T46	1		T7	1
auto[3892314112:4026531839]	auto[0]	37	1			T21	1		T60	1		T50	2
auto[3892314112:4026531839]	auto[1]	56	1			T4	1		T182	1		T305	1
auto[4026531840:4160749567]	auto[0]	45	1			T4	1		T46	1		T192	1
auto[4026531840:4160749567]	auto[1]	61	1			T7	1		T82	1		T250	1
auto[4160749568:4294967295]	auto[0]	47	1			T4	1		T14	1		T5	2
auto[4160749568:4294967295]	auto[1]	61	1			T14	1		T46	1		T53	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1572

1

T2

2

T3

4

T4

6

auto[1]

1879

1

T2

1

T3

2

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T5	1		T78	1		T46	2
auto[134217728:268435455]	87	1			T46	1		T182	1		T62	1
auto[268435456:402653183]	104	1			T5	2		T46	1		T48	1
auto[402653184:536870911]	128	1			T5	3		T6	1		T46	3
auto[536870912:671088639]	95	1			T2	1		T4	1		T5	2
auto[671088640:805306367]	112	1			T13	1		T5	2		T6	2
auto[805306368:939524095]	119	1			T13	1		T5	2		T24	1
auto[939524096:1073741823]	89	1			T5	3		T6	1		T116	1
auto[1073741824:1207959551]	118	1			T14	1		T5	1		T78	1
auto[1207959552:1342177279]	101	1			T4	1		T13	1		T6	1
auto[1342177280:1476395007]	114	1			T46	2		T7	1		T44	1
auto[1476395008:1610612735]	107	1			T34	1		T62	1		T124	1
auto[1610612736:1744830463]	116	1			T14	1		T5	2		T46	2
auto[1744830464:1879048191]	112	1			T3	2		T14	1		T5	1
auto[1879048192:2013265919]	113	1			T3	1		T4	1		T6	1
auto[2013265920:2147483647]	92	1			T7	1		T192	1		T44	2
auto[2147483648:2281701375]	104	1			T14	1		T5	1		T6	2
auto[2281701376:2415919103]	96	1			T3	1		T4	1		T14	1
auto[2415919104:2550136831]	104	1			T2	1		T5	2		T67	1
auto[2550136832:2684354559]	108	1			T4	1		T5	1		T34	1
auto[2684354560:2818572287]	125	1			T14	1		T46	3		T92	1
auto[2818572288:2952790015]	107	1			T6	1		T46	1		T305	1
auto[2952790016:3087007743]	108	1			T3	1		T5	1		T6	1
auto[3087007744:3221225471]	115	1			T5	1		T6	1		T34	1
auto[3221225472:3355443199]	107	1			T2	1		T5	2		T34	1
auto[3355443200:3489660927]	114	1			T4	1		T14	1		T24	1
auto[3489660928:3623878655]	101	1			T13	1		T5	2		T46	2
auto[3623878656:3758096383]	111	1			T5	2		T6	1		T219	1
auto[3758096384:3892314111]	96	1			T14	1		T77	1		T46	1
auto[3892314112:4026531839]	101	1			T3	1		T46	2		T62	1
auto[4026531840:4160749567]	123	1			T4	1		T14	1		T5	1
auto[4160749568:4294967295]	124	1			T13	2		T34	1		T46	3