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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3005 1 T2 1 T3 6 T4 2
auto[1] 306 1 T122 8 T127 16 T128 5


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 126 1 T14 1 T5 2 T6 1
auto[134217728:268435455] 105 1 T2 1 T77 1 T182 1
auto[268435456:402653183] 119 1 T5 1 T34 1 T46 2
auto[402653184:536870911] 114 1 T5 3 T34 1 T186 1
auto[536870912:671088639] 92 1 T13 1 T14 1 T5 1
auto[671088640:805306367] 105 1 T13 3 T5 1 T46 2
auto[805306368:939524095] 95 1 T13 1 T5 1 T46 1
auto[939524096:1073741823] 116 1 T3 2 T46 1 T182 1
auto[1073741824:1207959551] 113 1 T4 1 T5 1 T34 1
auto[1207959552:1342177279] 103 1 T21 1 T59 2 T63 1
auto[1342177280:1476395007] 97 1 T5 2 T46 2 T189 1
auto[1476395008:1610612735] 107 1 T5 2 T219 1 T48 3
auto[1610612736:1744830463] 111 1 T6 1 T46 3 T188 2
auto[1744830464:1879048191] 92 1 T46 1 T120 1 T122 1
auto[1879048192:2013265919] 102 1 T34 1 T92 2 T189 1
auto[2013265920:2147483647] 90 1 T5 1 T78 1 T46 2
auto[2147483648:2281701375] 116 1 T46 1 T92 2 T7 1
auto[2281701376:2415919103] 113 1 T5 1 T305 1 T7 1
auto[2415919104:2550136831] 97 1 T5 1 T34 1 T47 1
auto[2550136832:2684354559] 107 1 T13 1 T24 1 T46 2
auto[2684354560:2818572287] 105 1 T46 4 T92 1 T7 1
auto[2818572288:2952790015] 99 1 T3 1 T4 1 T5 1
auto[2952790016:3087007743] 92 1 T78 1 T21 1 T44 1
auto[3087007744:3221225471] 93 1 T5 1 T46 4 T182 1
auto[3221225472:3355443199] 96 1 T6 1 T34 1 T46 4
auto[3355443200:3489660927] 104 1 T5 1 T6 1 T46 1
auto[3489660928:3623878655] 107 1 T3 1 T5 1 T116 2
auto[3623878656:3758096383] 107 1 T3 1 T6 1 T46 2
auto[3758096384:3892314111] 90 1 T6 1 T46 1 T92 1
auto[3892314112:4026531839] 102 1 T14 1 T189 1 T120 1
auto[4026531840:4160749567] 101 1 T5 1 T6 1 T46 3
auto[4160749568:4294967295] 95 1 T3 1 T5 1 T6 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 110 1 T14 1 T5 2 T6 1
auto[0:134217727] auto[1] 16 1 T127 2 T271 1 T231 2
auto[134217728:268435455] auto[0] 94 1 T2 1 T77 1 T182 1
auto[134217728:268435455] auto[1] 11 1 T127 1 T220 1 T170 1
auto[268435456:402653183] auto[0] 108 1 T5 1 T34 1 T46 2
auto[268435456:402653183] auto[1] 11 1 T127 1 T364 2 T220 1
auto[402653184:536870911] auto[0] 108 1 T5 3 T34 1 T186 1
auto[402653184:536870911] auto[1] 6 1 T122 1 T127 1 T231 1
auto[536870912:671088639] auto[0] 82 1 T13 1 T14 1 T5 1
auto[536870912:671088639] auto[1] 10 1 T271 1 T231 1 T217 1
auto[671088640:805306367] auto[0] 98 1 T13 3 T5 1 T46 2
auto[671088640:805306367] auto[1] 7 1 T122 1 T128 2 T220 1
auto[805306368:939524095] auto[0] 91 1 T13 1 T5 1 T46 1
auto[805306368:939524095] auto[1] 4 1 T220 1 T271 1 T415 1
auto[939524096:1073741823] auto[0] 109 1 T3 2 T46 1 T182 1
auto[939524096:1073741823] auto[1] 7 1 T127 1 T128 1 T383 1
auto[1073741824:1207959551] auto[0] 102 1 T4 1 T5 1 T34 1
auto[1073741824:1207959551] auto[1] 11 1 T122 1 T127 1 T129 1
auto[1207959552:1342177279] auto[0] 85 1 T21 1 T59 2 T63 1
auto[1207959552:1342177279] auto[1] 18 1 T364 1 T365 1 T170 3
auto[1342177280:1476395007] auto[0] 89 1 T5 2 T46 2 T189 1
auto[1342177280:1476395007] auto[1] 8 1 T127 1 T128 1 T129 1
auto[1476395008:1610612735] auto[0] 98 1 T5 2 T219 1 T48 3
auto[1476395008:1610612735] auto[1] 9 1 T220 1 T404 1 T245 1
auto[1610612736:1744830463] auto[0] 98 1 T6 1 T46 3 T188 2
auto[1610612736:1744830463] auto[1] 13 1 T128 1 T365 1 T241 1
auto[1744830464:1879048191] auto[0] 82 1 T46 1 T120 1 T194 1
auto[1744830464:1879048191] auto[1] 10 1 T122 1 T127 2 T404 1
auto[1879048192:2013265919] auto[0] 95 1 T34 1 T92 2 T189 1
auto[1879048192:2013265919] auto[1] 7 1 T297 1 T242 1 T416 1
auto[2013265920:2147483647] auto[0] 80 1 T5 1 T78 1 T46 2
auto[2013265920:2147483647] auto[1] 10 1 T127 1 T365 1 T170 1
auto[2147483648:2281701375] auto[0] 108 1 T46 1 T92 2 T7 1
auto[2147483648:2281701375] auto[1] 8 1 T175 1 T271 1 T242 1
auto[2281701376:2415919103] auto[0] 108 1 T5 1 T305 1 T7 1
auto[2281701376:2415919103] auto[1] 5 1 T365 1 T415 1 T417 1
auto[2415919104:2550136831] auto[0] 88 1 T5 1 T34 1 T47 1
auto[2415919104:2550136831] auto[1] 9 1 T127 1 T220 2 T297 1
auto[2550136832:2684354559] auto[0] 96 1 T13 1 T24 1 T46 2
auto[2550136832:2684354559] auto[1] 11 1 T122 1 T365 2 T170 2
auto[2684354560:2818572287] auto[0] 96 1 T46 4 T92 1 T7 1
auto[2684354560:2818572287] auto[1] 9 1 T365 1 T170 1 T271 1
auto[2818572288:2952790015] auto[0] 92 1 T3 1 T4 1 T5 1
auto[2818572288:2952790015] auto[1] 7 1 T220 1 T170 1 T241 1
auto[2952790016:3087007743] auto[0] 81 1 T78 1 T21 1 T44 1
auto[2952790016:3087007743] auto[1] 11 1 T122 1 T127 1 T365 1
auto[3087007744:3221225471] auto[0] 84 1 T5 1 T46 4 T182 1
auto[3087007744:3221225471] auto[1] 9 1 T122 1 T175 2 T242 1
auto[3221225472:3355443199] auto[0] 86 1 T6 1 T34 1 T46 4
auto[3221225472:3355443199] auto[1] 10 1 T127 1 T271 1 T297 1
auto[3355443200:3489660927] auto[0] 92 1 T5 1 T6 1 T46 1
auto[3355443200:3489660927] auto[1] 12 1 T122 1 T220 1 T231 1
auto[3489660928:3623878655] auto[0] 98 1 T3 1 T5 1 T116 2
auto[3489660928:3623878655] auto[1] 9 1 T170 3 T175 1 T245 1
auto[3623878656:3758096383] auto[0] 93 1 T3 1 T6 1 T46 2
auto[3623878656:3758096383] auto[1] 14 1 T127 1 T364 1 T175 1
auto[3758096384:3892314111] auto[0] 83 1 T6 1 T46 1 T92 1
auto[3758096384:3892314111] auto[1] 7 1 T242 1 T353 2 T312 1
auto[3892314112:4026531839] auto[0] 91 1 T14 1 T189 1 T120 1
auto[3892314112:4026531839] auto[1] 11 1 T364 1 T366 1 T404 1
auto[4026531840:4160749567] auto[0] 94 1 T5 1 T6 1 T46 3
auto[4026531840:4160749567] auto[1] 7 1 T365 1 T245 1 T285 1
auto[4160749568:4294967295] auto[0] 86 1 T3 1 T5 1 T6 2
auto[4160749568:4294967295] auto[1] 9 1 T127 1 T384 1 T353 1

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