dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3006 1 T2 1 T3 6 T4 2
auto[1] 273 1 T122 9 T127 14 T128 5


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 108 1 T13 1 T78 1 T46 2
auto[134217728:268435455] 112 1 T34 1 T46 2 T7 1
auto[268435456:402653183] 99 1 T5 2 T46 1 T305 1
auto[402653184:536870911] 100 1 T5 1 T46 3 T182 1
auto[536870912:671088639] 106 1 T13 1 T34 1 T46 2
auto[671088640:805306367] 105 1 T7 1 T53 1 T195 1
auto[805306368:939524095] 101 1 T2 1 T5 2 T34 1
auto[939524096:1073741823] 106 1 T4 1 T13 1 T5 1
auto[1073741824:1207959551] 102 1 T46 1 T182 1 T189 1
auto[1207959552:1342177279] 105 1 T3 1 T14 1 T46 1
auto[1342177280:1476395007] 111 1 T13 1 T46 1 T219 1
auto[1476395008:1610612735] 100 1 T6 1 T92 1 T7 1
auto[1610612736:1744830463] 85 1 T46 1 T410 1 T128 2
auto[1744830464:1879048191] 95 1 T5 1 T116 1 T189 1
auto[1879048192:2013265919] 122 1 T5 3 T34 1 T46 1
auto[2013265920:2147483647] 107 1 T4 1 T5 1 T46 4
auto[2147483648:2281701375] 110 1 T3 2 T5 1 T77 1
auto[2281701376:2415919103] 98 1 T5 1 T6 1 T46 1
auto[2415919104:2550136831] 102 1 T116 1 T92 1 T182 1
auto[2550136832:2684354559] 108 1 T46 5 T188 1 T48 2
auto[2684354560:2818572287] 91 1 T13 1 T14 1 T5 1
auto[2818572288:2952790015] 92 1 T5 1 T6 1 T34 1
auto[2952790016:3087007743] 100 1 T46 2 T186 1 T188 1
auto[3087007744:3221225471] 103 1 T24 1 T6 2 T189 1
auto[3221225472:3355443199] 121 1 T3 2 T6 1 T46 2
auto[3355443200:3489660927] 101 1 T3 1 T13 1 T5 3
auto[3489660928:3623878655] 86 1 T5 1 T46 2 T7 1
auto[3623878656:3758096383] 104 1 T5 1 T46 2 T92 1
auto[3758096384:3892314111] 99 1 T5 1 T6 1 T78 1
auto[3892314112:4026531839] 110 1 T5 1 T6 2 T46 3
auto[4026531840:4160749567] 100 1 T46 2 T7 2 T48 1
auto[4160749568:4294967295] 90 1 T14 1 T5 1 T34 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 100 1 T13 1 T78 1 T46 2
auto[0:134217727] auto[1] 8 1 T127 1 T220 1 T170 1
auto[134217728:268435455] auto[0] 101 1 T34 1 T46 2 T7 1
auto[134217728:268435455] auto[1] 11 1 T122 1 T127 1 T271 1
auto[268435456:402653183] auto[0] 91 1 T5 2 T46 1 T305 1
auto[268435456:402653183] auto[1] 8 1 T364 1 T365 2 T297 1
auto[402653184:536870911] auto[0] 92 1 T5 1 T46 3 T182 1
auto[402653184:536870911] auto[1] 8 1 T220 1 T231 1 T405 1
auto[536870912:671088639] auto[0] 98 1 T13 1 T34 1 T46 2
auto[536870912:671088639] auto[1] 8 1 T122 1 T127 1 T129 1
auto[671088640:805306367] auto[0] 97 1 T7 1 T53 1 T195 1
auto[671088640:805306367] auto[1] 8 1 T365 1 T366 1 T242 1
auto[805306368:939524095] auto[0] 93 1 T2 1 T5 2 T34 1
auto[805306368:939524095] auto[1] 8 1 T271 1 T231 1 T281 1
auto[939524096:1073741823] auto[0] 97 1 T4 1 T13 1 T5 1
auto[939524096:1073741823] auto[1] 9 1 T127 2 T175 1 T245 1
auto[1073741824:1207959551] auto[0] 95 1 T46 1 T182 1 T189 1
auto[1073741824:1207959551] auto[1] 7 1 T128 1 T366 1 T297 1
auto[1207959552:1342177279] auto[0] 99 1 T3 1 T14 1 T46 1
auto[1207959552:1342177279] auto[1] 6 1 T220 1 T383 2 T406 1
auto[1342177280:1476395007] auto[0] 102 1 T13 1 T46 1 T219 1
auto[1342177280:1476395007] auto[1] 9 1 T129 1 T241 1 T404 2
auto[1476395008:1610612735] auto[0] 91 1 T6 1 T92 1 T7 1
auto[1476395008:1610612735] auto[1] 9 1 T241 1 T297 1 T404 1
auto[1610612736:1744830463] auto[0] 77 1 T46 1 T410 1 T111 1
auto[1610612736:1744830463] auto[1] 8 1 T128 2 T297 1 T285 1
auto[1744830464:1879048191] auto[0] 91 1 T5 1 T116 1 T189 1
auto[1744830464:1879048191] auto[1] 4 1 T365 1 T231 1 T404 1
auto[1879048192:2013265919] auto[0] 111 1 T5 3 T34 1 T46 1
auto[1879048192:2013265919] auto[1] 11 1 T365 2 T271 1 T217 1
auto[2013265920:2147483647] auto[0] 95 1 T4 1 T5 1 T46 4
auto[2013265920:2147483647] auto[1] 12 1 T127 1 T129 1 T231 1
auto[2147483648:2281701375] auto[0] 103 1 T3 2 T5 1 T77 1
auto[2147483648:2281701375] auto[1] 7 1 T122 1 T175 1 T285 1
auto[2281701376:2415919103] auto[0] 89 1 T5 1 T6 1 T46 1
auto[2281701376:2415919103] auto[1] 9 1 T129 1 T170 1 T297 1
auto[2415919104:2550136831] auto[0] 95 1 T116 1 T92 1 T182 1
auto[2415919104:2550136831] auto[1] 7 1 T122 1 T297 1 T242 1
auto[2550136832:2684354559] auto[0] 96 1 T46 5 T188 1 T48 2
auto[2550136832:2684354559] auto[1] 12 1 T128 1 T220 1 T175 1
auto[2684354560:2818572287] auto[0] 76 1 T13 1 T14 1 T5 1
auto[2684354560:2818572287] auto[1] 15 1 T122 1 T127 2 T129 2
auto[2818572288:2952790015] auto[0] 83 1 T5 1 T6 1 T34 1
auto[2818572288:2952790015] auto[1] 9 1 T122 1 T231 1 T404 1
auto[2952790016:3087007743] auto[0] 90 1 T46 2 T186 1 T188 1
auto[2952790016:3087007743] auto[1] 10 1 T122 1 T127 2 T220 1
auto[3087007744:3221225471] auto[0] 100 1 T24 1 T6 2 T189 1
auto[3087007744:3221225471] auto[1] 3 1 T129 1 T281 1 T411 1
auto[3221225472:3355443199] auto[0] 114 1 T3 2 T6 1 T46 2
auto[3221225472:3355443199] auto[1] 7 1 T220 1 T175 1 T217 1
auto[3355443200:3489660927] auto[0] 96 1 T3 1 T13 1 T5 3
auto[3355443200:3489660927] auto[1] 5 1 T127 2 T382 1 T218 1
auto[3489660928:3623878655] auto[0] 74 1 T5 1 T46 2 T7 1
auto[3489660928:3623878655] auto[1] 12 1 T122 1 T127 1 T220 1
auto[3623878656:3758096383] auto[0] 96 1 T5 1 T46 2 T92 1
auto[3623878656:3758096383] auto[1] 8 1 T128 1 T365 2 T242 1
auto[3758096384:3892314111] auto[0] 90 1 T5 1 T6 1 T78 1
auto[3758096384:3892314111] auto[1] 9 1 T170 1 T231 2 T381 1
auto[3892314112:4026531839] auto[0] 104 1 T5 1 T6 2 T46 3
auto[3892314112:4026531839] auto[1] 6 1 T122 1 T382 1 T412 2
auto[4026531840:4160749567] auto[0] 91 1 T46 2 T7 2 T48 1
auto[4026531840:4160749567] auto[1] 9 1 T366 1 T170 1 T271 1
auto[4160749568:4294967295] auto[0] 79 1 T14 1 T5 1 T34 1
auto[4160749568:4294967295] auto[1] 11 1 T127 1 T297 1 T231 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%